mt8192-resets.h revision 1.1.1.1 
1/*	$NetBSD: mt8192-resets.h,v 1.1.1.1 2026/01/18 05:21:54 skrll Exp $	*/
2
3/* SPDX-License-Identifier: GPL-2.0 */
4/*
5 * Copyright (c) 2020 MediaTek Inc.
6 * Author: Yong Liang <yong.liang@mediatek.com>
7 */
8
9#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
10#define _DT_BINDINGS_RESET_CONTROLLER_MT8192
11
12/* TOPRGU resets */
13#define MT8192_TOPRGU_MM_SW_RST					1
14#define MT8192_TOPRGU_MFG_SW_RST				2
15#define MT8192_TOPRGU_VENC_SW_RST				3
16#define MT8192_TOPRGU_VDEC_SW_RST				4
17#define MT8192_TOPRGU_IMG_SW_RST				5
18#define MT8192_TOPRGU_MD_SW_RST					7
19#define MT8192_TOPRGU_CONN_SW_RST				9
20#define MT8192_TOPRGU_CONN_MCU_SW_RST			12
21#define MT8192_TOPRGU_IPU0_SW_RST				14
22#define MT8192_TOPRGU_IPU1_SW_RST				15
23#define MT8192_TOPRGU_AUDIO_SW_RST				17
24#define MT8192_TOPRGU_CAMSYS_SW_RST				18
25#define MT8192_TOPRGU_MJC_SW_RST				19
26#define MT8192_TOPRGU_C2K_S2_SW_RST				20
27#define MT8192_TOPRGU_C2K_SW_RST				21
28#define MT8192_TOPRGU_PERI_SW_RST				22
29#define MT8192_TOPRGU_PERI_AO_SW_RST			23
30
31#define MT8192_TOPRGU_SW_RST_NUM				23
32
33/* MMSYS resets */
34#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0			15
35
36/* INFRA resets */
37#define MT8192_INFRA_RST0_THERM_CTRL_SWRST		0
38#define MT8192_INFRA_RST2_PEXTP_PHY_SWRST		1
39#define MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST	2
40#define MT8192_INFRA_RST4_PCIE_TOP_SWRST		3
41#define MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST	4
42
43#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
44