qcom,gcc-mdm9615.h revision 1.1.1.1 
1/*	$NetBSD: qcom,gcc-mdm9615.h,v 1.1.1.1 2017/06/15 20:14:23 jmcneill Exp $	*/
2
3/*
4 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
5 * Copyright (c) BayLibre, SAS.
6 * Author : Neil Armstrong <narmstrong@baylibre.com>
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License for more details.
16 */
17
18#ifndef _DT_BINDINGS_RESET_GCC_MDM9615_H
19#define _DT_BINDINGS_RESET_GCC_MDM9615_H
20
21#define SFAB_MSS_Q6_SW_RESET				0
22#define SFAB_MSS_Q6_FW_RESET				1
23#define QDSS_STM_RESET					2
24#define AFAB_SMPSS_S_RESET				3
25#define AFAB_SMPSS_M1_RESET				4
26#define AFAB_SMPSS_M0_RESET				5
27#define AFAB_EBI1_CH0_RESET				6
28#define AFAB_EBI1_CH1_RESET				7
29#define SFAB_ADM0_M0_RESET				8
30#define SFAB_ADM0_M1_RESET				9
31#define SFAB_ADM0_M2_RESET				10
32#define ADM0_C2_RESET					11
33#define ADM0_C1_RESET					12
34#define ADM0_C0_RESET					13
35#define ADM0_PBUS_RESET					14
36#define ADM0_RESET					15
37#define QDSS_CLKS_SW_RESET				16
38#define QDSS_POR_RESET					17
39#define QDSS_TSCTR_RESET				18
40#define QDSS_HRESET_RESET				19
41#define QDSS_AXI_RESET					20
42#define QDSS_DBG_RESET					21
43#define PCIE_A_RESET					22
44#define PCIE_AUX_RESET					23
45#define PCIE_H_RESET					24
46#define SFAB_PCIE_M_RESET				25
47#define SFAB_PCIE_S_RESET				26
48#define SFAB_MSS_M_RESET				27
49#define SFAB_USB3_M_RESET				28
50#define SFAB_RIVA_M_RESET				29
51#define SFAB_LPASS_RESET				30
52#define SFAB_AFAB_M_RESET				31
53#define AFAB_SFAB_M0_RESET				32
54#define AFAB_SFAB_M1_RESET				33
55#define SFAB_SATA_S_RESET				34
56#define SFAB_DFAB_M_RESET				35
57#define DFAB_SFAB_M_RESET				36
58#define DFAB_SWAY0_RESET				37
59#define DFAB_SWAY1_RESET				38
60#define DFAB_ARB0_RESET					39
61#define DFAB_ARB1_RESET					40
62#define PPSS_PROC_RESET					41
63#define PPSS_RESET					42
64#define DMA_BAM_RESET					43
65#define SPS_TIC_H_RESET					44
66#define SLIMBUS_H_RESET					45
67#define SFAB_CFPB_M_RESET				46
68#define SFAB_CFPB_S_RESET				47
69#define TSIF_H_RESET					48
70#define CE1_H_RESET					49
71#define CE1_CORE_RESET					50
72#define CE1_SLEEP_RESET					51
73#define CE2_H_RESET					52
74#define CE2_CORE_RESET					53
75#define SFAB_SFPB_M_RESET				54
76#define SFAB_SFPB_S_RESET				55
77#define RPM_PROC_RESET					56
78#define PMIC_SSBI2_RESET				57
79#define SDC1_RESET					58
80#define SDC2_RESET					59
81#define SDC3_RESET					60
82#define SDC4_RESET					61
83#define SDC5_RESET					62
84#define DFAB_A2_RESET					63
85#define USB_HS1_RESET					64
86#define USB_HSIC_RESET					65
87#define USB_FS1_XCVR_RESET				66
88#define USB_FS1_RESET					67
89#define USB_FS2_XCVR_RESET				68
90#define USB_FS2_RESET					69
91#define GSBI1_RESET					70
92#define GSBI2_RESET					71
93#define GSBI3_RESET					72
94#define GSBI4_RESET					73
95#define GSBI5_RESET					74
96#define GSBI6_RESET					75
97#define GSBI7_RESET					76
98#define GSBI8_RESET					77
99#define GSBI9_RESET					78
100#define GSBI10_RESET					79
101#define GSBI11_RESET					80
102#define GSBI12_RESET					81
103#define SPDM_RESET					82
104#define TLMM_H_RESET					83
105#define SFAB_MSS_S_RESET				84
106#define MSS_SLP_RESET					85
107#define MSS_Q6SW_JTAG_RESET				86
108#define MSS_Q6FW_JTAG_RESET				87
109#define MSS_RESET					88
110#define SATA_H_RESET					89
111#define SATA_RXOOB_RESE					90
112#define SATA_PMALIVE_RESET				91
113#define SATA_SFAB_M_RESET				92
114#define TSSC_RESET					93
115#define PDM_RESET					94
116#define MPM_H_RESET					95
117#define MPM_RESET					96
118#define SFAB_SMPSS_S_RESET				97
119#define PRNG_RESET					98
120#define RIVA_RESET					99
121#define USB_HS3_RESET					100
122#define USB_HS4_RESET					101
123#define CE3_RESET					102
124#define PCIE_EXT_PCI_RESET				103
125#define PCIE_PHY_RESET					104
126#define PCIE_PCI_RESET					105
127#define PCIE_POR_RESET					106
128#define PCIE_HCLK_RESET					107
129#define PCIE_ACLK_RESET					108
130#define CE3_H_RESET					109
131#define SFAB_CE3_M_RESET				110
132#define SFAB_CE3_S_RESET				111
133#define SATA_RESET					112
134#define CE3_SLEEP_RESET					113
135#define GSS_SLP_RESET					114
136#define GSS_RESET					115
137
138#endif
139