qcom,gcc-ipq806x.h revision 1.1.1.1.6.2
1 /* $NetBSD: qcom,gcc-ipq806x.h,v 1.1.1.1.6.2 2017/08/28 17:53:04 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #ifndef _DT_BINDINGS_RESET_IPQ_806X_H 17 #define _DT_BINDINGS_RESET_IPQ_806X_H 18 19 #define QDSS_STM_RESET 0 20 #define AFAB_SMPSS_S_RESET 1 21 #define AFAB_SMPSS_M1_RESET 2 22 #define AFAB_SMPSS_M0_RESET 3 23 #define AFAB_EBI1_CH0_RESET 4 24 #define AFAB_EBI1_CH1_RESET 5 25 #define SFAB_ADM0_M0_RESET 6 26 #define SFAB_ADM0_M1_RESET 7 27 #define SFAB_ADM0_M2_RESET 8 28 #define ADM0_C2_RESET 9 29 #define ADM0_C1_RESET 10 30 #define ADM0_C0_RESET 11 31 #define ADM0_PBUS_RESET 12 32 #define ADM0_RESET 13 33 #define QDSS_CLKS_SW_RESET 14 34 #define QDSS_POR_RESET 15 35 #define QDSS_TSCTR_RESET 16 36 #define QDSS_HRESET_RESET 17 37 #define QDSS_AXI_RESET 18 38 #define QDSS_DBG_RESET 19 39 #define SFAB_PCIE_M_RESET 20 40 #define SFAB_PCIE_S_RESET 21 41 #define PCIE_EXT_RESET 22 42 #define PCIE_PHY_RESET 23 43 #define PCIE_PCI_RESET 24 44 #define PCIE_POR_RESET 25 45 #define PCIE_HCLK_RESET 26 46 #define PCIE_ACLK_RESET 27 47 #define SFAB_LPASS_RESET 28 48 #define SFAB_AFAB_M_RESET 29 49 #define AFAB_SFAB_M0_RESET 30 50 #define AFAB_SFAB_M1_RESET 31 51 #define SFAB_SATA_S_RESET 32 52 #define SFAB_DFAB_M_RESET 33 53 #define DFAB_SFAB_M_RESET 34 54 #define DFAB_SWAY0_RESET 35 55 #define DFAB_SWAY1_RESET 36 56 #define DFAB_ARB0_RESET 37 57 #define DFAB_ARB1_RESET 38 58 #define PPSS_PROC_RESET 39 59 #define PPSS_RESET 40 60 #define DMA_BAM_RESET 41 61 #define SPS_TIC_H_RESET 42 62 #define SFAB_CFPB_M_RESET 43 63 #define SFAB_CFPB_S_RESET 44 64 #define TSIF_H_RESET 45 65 #define CE1_H_RESET 46 66 #define CE1_CORE_RESET 47 67 #define CE1_SLEEP_RESET 48 68 #define CE2_H_RESET 49 69 #define CE2_CORE_RESET 50 70 #define SFAB_SFPB_M_RESET 51 71 #define SFAB_SFPB_S_RESET 52 72 #define RPM_PROC_RESET 53 73 #define PMIC_SSBI2_RESET 54 74 #define SDC1_RESET 55 75 #define SDC2_RESET 56 76 #define SDC3_RESET 57 77 #define SDC4_RESET 58 78 #define USB_HS1_RESET 59 79 #define USB_HSIC_RESET 60 80 #define USB_FS1_XCVR_RESET 61 81 #define USB_FS1_RESET 62 82 #define GSBI1_RESET 63 83 #define GSBI2_RESET 64 84 #define GSBI3_RESET 65 85 #define GSBI4_RESET 66 86 #define GSBI5_RESET 67 87 #define GSBI6_RESET 68 88 #define GSBI7_RESET 69 89 #define SPDM_RESET 70 90 #define SEC_CTRL_RESET 71 91 #define TLMM_H_RESET 72 92 #define SFAB_SATA_M_RESET 73 93 #define SATA_RESET 74 94 #define TSSC_RESET 75 95 #define PDM_RESET 76 96 #define MPM_H_RESET 77 97 #define MPM_RESET 78 98 #define SFAB_SMPSS_S_RESET 79 99 #define PRNG_RESET 80 100 #define SFAB_CE3_M_RESET 81 101 #define SFAB_CE3_S_RESET 82 102 #define CE3_SLEEP_RESET 83 103 #define PCIE_1_M_RESET 84 104 #define PCIE_1_S_RESET 85 105 #define PCIE_1_EXT_RESET 86 106 #define PCIE_1_PHY_RESET 87 107 #define PCIE_1_PCI_RESET 88 108 #define PCIE_1_POR_RESET 89 109 #define PCIE_1_HCLK_RESET 90 110 #define PCIE_1_ACLK_RESET 91 111 #define PCIE_2_M_RESET 92 112 #define PCIE_2_S_RESET 93 113 #define PCIE_2_EXT_RESET 94 114 #define PCIE_2_PHY_RESET 95 115 #define PCIE_2_PCI_RESET 96 116 #define PCIE_2_POR_RESET 97 117 #define PCIE_2_HCLK_RESET 98 118 #define PCIE_2_ACLK_RESET 99 119 #define SFAB_USB30_S_RESET 100 120 #define SFAB_USB30_M_RESET 101 121 #define USB30_0_PORT2_HS_PHY_RESET 102 122 #define USB30_0_MASTER_RESET 103 123 #define USB30_0_SLEEP_RESET 104 124 #define USB30_0_UTMI_PHY_RESET 105 125 #define USB30_0_POWERON_RESET 106 126 #define USB30_0_PHY_RESET 107 127 #define USB30_1_MASTER_RESET 108 128 #define USB30_1_SLEEP_RESET 109 129 #define USB30_1_UTMI_PHY_RESET 110 130 #define USB30_1_POWERON_RESET 111 131 #define USB30_1_PHY_RESET 112 132 #define NSSFB0_RESET 113 133 #define NSSFB1_RESET 114 134 #define UBI32_CORE1_CLKRST_CLAMP_RESET 115 135 #define UBI32_CORE1_CLAMP_RESET 116 136 #define UBI32_CORE1_AHB_RESET 117 137 #define UBI32_CORE1_AXI_RESET 118 138 #define UBI32_CORE2_CLKRST_CLAMP_RESET 119 139 #define UBI32_CORE2_CLAMP_RESET 120 140 #define UBI32_CORE2_AHB_RESET 121 141 #define UBI32_CORE2_AXI_RESET 122 142 #define GMAC_CORE1_RESET 123 143 #define GMAC_CORE2_RESET 124 144 #define GMAC_CORE3_RESET 125 145 #define GMAC_CORE4_RESET 126 146 #define GMAC_AHB_RESET 127 147 #define NSS_CH0_RST_RX_CLK_N_RESET 128 148 #define NSS_CH0_RST_TX_CLK_N_RESET 129 149 #define NSS_CH0_RST_RX_125M_N_RESET 130 150 #define NSS_CH0_HW_RST_RX_125M_N_RESET 131 151 #define NSS_CH0_RST_TX_125M_N_RESET 132 152 #define NSS_CH1_RST_RX_CLK_N_RESET 133 153 #define NSS_CH1_RST_TX_CLK_N_RESET 134 154 #define NSS_CH1_RST_RX_125M_N_RESET 135 155 #define NSS_CH1_HW_RST_RX_125M_N_RESET 136 156 #define NSS_CH1_RST_TX_125M_N_RESET 137 157 #define NSS_CH2_RST_RX_CLK_N_RESET 138 158 #define NSS_CH2_RST_TX_CLK_N_RESET 139 159 #define NSS_CH2_RST_RX_125M_N_RESET 140 160 #define NSS_CH2_HW_RST_RX_125M_N_RESET 141 161 #define NSS_CH2_RST_TX_125M_N_RESET 142 162 #define NSS_CH3_RST_RX_CLK_N_RESET 143 163 #define NSS_CH3_RST_TX_CLK_N_RESET 144 164 #define NSS_CH3_RST_RX_125M_N_RESET 145 165 #define NSS_CH3_HW_RST_RX_125M_N_RESET 146 166 #define NSS_CH3_RST_TX_125M_N_RESET 147 167 #define NSS_RST_RX_250M_125M_N_RESET 148 168 #define NSS_RST_TX_250M_125M_N_RESET 149 169 #define NSS_QSGMII_TXPI_RST_N_RESET 150 170 #define NSS_QSGMII_CDR_RST_N_RESET 151 171 #define NSS_SGMII2_CDR_RST_N_RESET 152 172 #define NSS_SGMII3_CDR_RST_N_RESET 153 173 #define NSS_CAL_PRBS_RST_N_RESET 154 174 #define NSS_LCKDT_RST_N_RESET 155 175 #define NSS_SRDS_N_RESET 156 176 177 #endif 178
Indexes created Tue Oct 14 21:09:58 GMT 2025