1 1.1 jmcneill /* $NetBSD: qcom,gcc-msm8960.h,v 1.1.1.2 2020/01/03 14:33:06 skrll Exp $ */ 2 1.1 jmcneill 3 1.1.1.2 skrll /* SPDX-License-Identifier: GPL-2.0-only */ 4 1.1 jmcneill /* 5 1.1 jmcneill * Copyright (c) 2013, The Linux Foundation. All rights reserved. 6 1.1 jmcneill */ 7 1.1 jmcneill 8 1.1 jmcneill #ifndef _DT_BINDINGS_RESET_MSM_GCC_8960_H 9 1.1 jmcneill #define _DT_BINDINGS_RESET_MSM_GCC_8960_H 10 1.1 jmcneill 11 1.1 jmcneill #define SFAB_MSS_Q6_SW_RESET 0 12 1.1 jmcneill #define SFAB_MSS_Q6_FW_RESET 1 13 1.1 jmcneill #define QDSS_STM_RESET 2 14 1.1 jmcneill #define AFAB_SMPSS_S_RESET 3 15 1.1 jmcneill #define AFAB_SMPSS_M1_RESET 4 16 1.1 jmcneill #define AFAB_SMPSS_M0_RESET 5 17 1.1 jmcneill #define AFAB_EBI1_CH0_RESET 6 18 1.1 jmcneill #define AFAB_EBI1_CH1_RESET 7 19 1.1 jmcneill #define SFAB_ADM0_M0_RESET 8 20 1.1 jmcneill #define SFAB_ADM0_M1_RESET 9 21 1.1 jmcneill #define SFAB_ADM0_M2_RESET 10 22 1.1 jmcneill #define ADM0_C2_RESET 11 23 1.1 jmcneill #define ADM0_C1_RESET 12 24 1.1 jmcneill #define ADM0_C0_RESET 13 25 1.1 jmcneill #define ADM0_PBUS_RESET 14 26 1.1 jmcneill #define ADM0_RESET 15 27 1.1 jmcneill #define QDSS_CLKS_SW_RESET 16 28 1.1 jmcneill #define QDSS_POR_RESET 17 29 1.1 jmcneill #define QDSS_TSCTR_RESET 18 30 1.1 jmcneill #define QDSS_HRESET_RESET 19 31 1.1 jmcneill #define QDSS_AXI_RESET 20 32 1.1 jmcneill #define QDSS_DBG_RESET 21 33 1.1 jmcneill #define PCIE_A_RESET 22 34 1.1 jmcneill #define PCIE_AUX_RESET 23 35 1.1 jmcneill #define PCIE_H_RESET 24 36 1.1 jmcneill #define SFAB_PCIE_M_RESET 25 37 1.1 jmcneill #define SFAB_PCIE_S_RESET 26 38 1.1 jmcneill #define SFAB_MSS_M_RESET 27 39 1.1 jmcneill #define SFAB_USB3_M_RESET 28 40 1.1 jmcneill #define SFAB_RIVA_M_RESET 29 41 1.1 jmcneill #define SFAB_LPASS_RESET 30 42 1.1 jmcneill #define SFAB_AFAB_M_RESET 31 43 1.1 jmcneill #define AFAB_SFAB_M0_RESET 32 44 1.1 jmcneill #define AFAB_SFAB_M1_RESET 33 45 1.1 jmcneill #define SFAB_SATA_S_RESET 34 46 1.1 jmcneill #define SFAB_DFAB_M_RESET 35 47 1.1 jmcneill #define DFAB_SFAB_M_RESET 36 48 1.1 jmcneill #define DFAB_SWAY0_RESET 37 49 1.1 jmcneill #define DFAB_SWAY1_RESET 38 50 1.1 jmcneill #define DFAB_ARB0_RESET 39 51 1.1 jmcneill #define DFAB_ARB1_RESET 40 52 1.1 jmcneill #define PPSS_PROC_RESET 41 53 1.1 jmcneill #define PPSS_RESET 42 54 1.1 jmcneill #define DMA_BAM_RESET 43 55 1.1 jmcneill #define SPS_TIC_H_RESET 44 56 1.1 jmcneill #define SLIMBUS_H_RESET 45 57 1.1 jmcneill #define SFAB_CFPB_M_RESET 46 58 1.1 jmcneill #define SFAB_CFPB_S_RESET 47 59 1.1 jmcneill #define TSIF_H_RESET 48 60 1.1 jmcneill #define CE1_H_RESET 49 61 1.1 jmcneill #define CE1_CORE_RESET 50 62 1.1 jmcneill #define CE1_SLEEP_RESET 51 63 1.1 jmcneill #define CE2_H_RESET 52 64 1.1 jmcneill #define CE2_CORE_RESET 53 65 1.1 jmcneill #define SFAB_SFPB_M_RESET 54 66 1.1 jmcneill #define SFAB_SFPB_S_RESET 55 67 1.1 jmcneill #define RPM_PROC_RESET 56 68 1.1 jmcneill #define PMIC_SSBI2_RESET 57 69 1.1 jmcneill #define SDC1_RESET 58 70 1.1 jmcneill #define SDC2_RESET 59 71 1.1 jmcneill #define SDC3_RESET 60 72 1.1 jmcneill #define SDC4_RESET 61 73 1.1 jmcneill #define SDC5_RESET 62 74 1.1 jmcneill #define DFAB_A2_RESET 63 75 1.1 jmcneill #define USB_HS1_RESET 64 76 1.1 jmcneill #define USB_HSIC_RESET 65 77 1.1 jmcneill #define USB_FS1_XCVR_RESET 66 78 1.1 jmcneill #define USB_FS1_RESET 67 79 1.1 jmcneill #define USB_FS2_XCVR_RESET 68 80 1.1 jmcneill #define USB_FS2_RESET 69 81 1.1 jmcneill #define GSBI1_RESET 70 82 1.1 jmcneill #define GSBI2_RESET 71 83 1.1 jmcneill #define GSBI3_RESET 72 84 1.1 jmcneill #define GSBI4_RESET 73 85 1.1 jmcneill #define GSBI5_RESET 74 86 1.1 jmcneill #define GSBI6_RESET 75 87 1.1 jmcneill #define GSBI7_RESET 76 88 1.1 jmcneill #define GSBI8_RESET 77 89 1.1 jmcneill #define GSBI9_RESET 78 90 1.1 jmcneill #define GSBI10_RESET 79 91 1.1 jmcneill #define GSBI11_RESET 80 92 1.1 jmcneill #define GSBI12_RESET 81 93 1.1 jmcneill #define SPDM_RESET 82 94 1.1 jmcneill #define TLMM_H_RESET 83 95 1.1 jmcneill #define SFAB_MSS_S_RESET 84 96 1.1 jmcneill #define MSS_SLP_RESET 85 97 1.1 jmcneill #define MSS_Q6SW_JTAG_RESET 86 98 1.1 jmcneill #define MSS_Q6FW_JTAG_RESET 87 99 1.1 jmcneill #define MSS_RESET 88 100 1.1 jmcneill #define SATA_H_RESET 89 101 1.1 jmcneill #define SATA_RXOOB_RESE 90 102 1.1 jmcneill #define SATA_PMALIVE_RESET 91 103 1.1 jmcneill #define SATA_SFAB_M_RESET 92 104 1.1 jmcneill #define TSSC_RESET 93 105 1.1 jmcneill #define PDM_RESET 94 106 1.1 jmcneill #define MPM_H_RESET 95 107 1.1 jmcneill #define MPM_RESET 96 108 1.1 jmcneill #define SFAB_SMPSS_S_RESET 97 109 1.1 jmcneill #define PRNG_RESET 98 110 1.1 jmcneill #define RIVA_RESET 99 111 1.1 jmcneill #define USB_HS3_RESET 100 112 1.1 jmcneill #define USB_HS4_RESET 101 113 1.1 jmcneill #define CE3_RESET 102 114 1.1 jmcneill #define PCIE_EXT_PCI_RESET 103 115 1.1 jmcneill #define PCIE_PHY_RESET 104 116 1.1 jmcneill #define PCIE_PCI_RESET 105 117 1.1 jmcneill #define PCIE_POR_RESET 106 118 1.1 jmcneill #define PCIE_HCLK_RESET 107 119 1.1 jmcneill #define PCIE_ACLK_RESET 108 120 1.1 jmcneill #define CE3_H_RESET 109 121 1.1 jmcneill #define SFAB_CE3_M_RESET 110 122 1.1 jmcneill #define SFAB_CE3_S_RESET 111 123 1.1 jmcneill #define SATA_RESET 112 124 1.1 jmcneill #define CE3_SLEEP_RESET 113 125 1.1 jmcneill #define GSS_SLP_RESET 114 126 1.1 jmcneill #define GSS_RESET 115 127 1.1 jmcneill 128 1.1 jmcneill #endif 129