11.1Sskrll/*	$NetBSD: qcom,ipq9574-gcc.h,v 1.1.1.1 2026/01/18 05:21:55 skrll Exp $	*/
21.1Sskrll
31.1Sskrll/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
41.1Sskrll/*
51.1Sskrll * Copyright (c) 2018-2023, The Linux Foundation. All rights reserved.
61.1Sskrll */
71.1Sskrll
81.1Sskrll#ifndef _DT_BINDINGS_RESET_IPQ_GCC_9574_H
91.1Sskrll#define _DT_BINDINGS_RESET_IPQ_GCC_9574_H
101.1Sskrll
111.1Sskrll#define GCC_ADSS_BCR						0
121.1Sskrll#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR			1
131.1Sskrll#define GCC_BLSP1_BCR						2
141.1Sskrll#define GCC_BLSP1_QUP1_BCR					3
151.1Sskrll#define GCC_BLSP1_QUP2_BCR					4
161.1Sskrll#define GCC_BLSP1_QUP3_BCR					5
171.1Sskrll#define GCC_BLSP1_QUP4_BCR					6
181.1Sskrll#define GCC_BLSP1_QUP5_BCR					7
191.1Sskrll#define GCC_BLSP1_QUP6_BCR					8
201.1Sskrll#define GCC_BLSP1_UART1_BCR					9
211.1Sskrll#define GCC_BLSP1_UART2_BCR					10
221.1Sskrll#define GCC_BLSP1_UART3_BCR					11
231.1Sskrll#define GCC_BLSP1_UART4_BCR					12
241.1Sskrll#define GCC_BLSP1_UART5_BCR					13
251.1Sskrll#define GCC_BLSP1_UART6_BCR					14
261.1Sskrll#define GCC_BOOT_ROM_BCR					15
271.1Sskrll#define GCC_MDIO_BCR						16
281.1Sskrll#define GCC_NSS_BCR						17
291.1Sskrll#define GCC_NSS_TBU_BCR						18
301.1Sskrll#define GCC_PCIE0_BCR						19
311.1Sskrll#define GCC_PCIE0_LINK_DOWN_BCR					20
321.1Sskrll#define GCC_PCIE0_PHY_BCR					21
331.1Sskrll#define GCC_PCIE0PHY_PHY_BCR					22
341.1Sskrll#define GCC_PCIE1_BCR						23
351.1Sskrll#define GCC_PCIE1_LINK_DOWN_BCR					24
361.1Sskrll#define GCC_PCIE1_PHY_BCR					25
371.1Sskrll#define GCC_PCIE1PHY_PHY_BCR					26
381.1Sskrll#define GCC_PCIE2_BCR						27
391.1Sskrll#define GCC_PCIE2_LINK_DOWN_BCR					28
401.1Sskrll#define GCC_PCIE2_PHY_BCR					29
411.1Sskrll#define GCC_PCIE2PHY_PHY_BCR					30
421.1Sskrll#define GCC_PCIE3_BCR						31
431.1Sskrll#define GCC_PCIE3_LINK_DOWN_BCR					32
441.1Sskrll#define GCC_PCIE3_PHY_BCR					33
451.1Sskrll#define GCC_PCIE3PHY_PHY_BCR					34
461.1Sskrll#define GCC_PRNG_BCR						35
471.1Sskrll#define GCC_QUSB2_0_PHY_BCR					36
481.1Sskrll#define GCC_SDCC_BCR						37
491.1Sskrll#define GCC_TLMM_BCR						38
501.1Sskrll#define GCC_UNIPHY0_BCR						39
511.1Sskrll#define GCC_UNIPHY1_BCR						40
521.1Sskrll#define GCC_UNIPHY2_BCR						41
531.1Sskrll#define GCC_USB0_PHY_BCR					42
541.1Sskrll#define GCC_USB3PHY_0_PHY_BCR					43
551.1Sskrll#define GCC_USB_BCR						44
561.1Sskrll#define GCC_ANOC0_TBU_BCR					45
571.1Sskrll#define GCC_ANOC1_TBU_BCR					46
581.1Sskrll#define GCC_ANOC_BCR						47
591.1Sskrll#define GCC_APSS_TCU_BCR					48
601.1Sskrll#define GCC_CMN_BLK_BCR						49
611.1Sskrll#define GCC_CMN_BLK_AHB_ARES					50
621.1Sskrll#define GCC_CMN_BLK_SYS_ARES					51
631.1Sskrll#define GCC_CMN_BLK_APU_ARES					52
641.1Sskrll#define GCC_DCC_BCR						53
651.1Sskrll#define GCC_DDRSS_BCR						54
661.1Sskrll#define GCC_IMEM_BCR						55
671.1Sskrll#define GCC_LPASS_BCR						56
681.1Sskrll#define GCC_MPM_BCR						57
691.1Sskrll#define GCC_MSG_RAM_BCR						58
701.1Sskrll#define GCC_NSSNOC_MEMNOC_1_ARES				59
711.1Sskrll#define GCC_NSSNOC_PCNOC_1_ARES					60
721.1Sskrll#define GCC_NSSNOC_SNOC_1_ARES					61
731.1Sskrll#define GCC_NSSNOC_XO_DCD_ARES					62
741.1Sskrll#define GCC_NSSNOC_TS_ARES					63
751.1Sskrll#define GCC_NSSCC_ARES						64
761.1Sskrll#define GCC_NSSNOC_NSSCC_ARES					65
771.1Sskrll#define GCC_NSSNOC_ATB_ARES					66
781.1Sskrll#define GCC_NSSNOC_MEMNOC_ARES					67
791.1Sskrll#define GCC_NSSNOC_QOSGEN_REF_ARES				68
801.1Sskrll#define GCC_NSSNOC_SNOC_ARES					69
811.1Sskrll#define GCC_NSSNOC_TIMEOUT_REF_ARES				70
821.1Sskrll#define GCC_NSS_CFG_ARES					71
831.1Sskrll#define GCC_UBI0_DBG_ARES					72
841.1Sskrll#define GCC_PCIE0_AHB_ARES					73
851.1Sskrll#define GCC_PCIE0_AUX_ARES					74
861.1Sskrll#define GCC_PCIE0_AXI_M_ARES					75
871.1Sskrll#define GCC_PCIE0_AXI_M_STICKY_ARES				76
881.1Sskrll#define GCC_PCIE0_AXI_S_ARES					77
891.1Sskrll#define GCC_PCIE0_AXI_S_STICKY_ARES				78
901.1Sskrll#define GCC_PCIE0_CORE_STICKY_ARES				79
911.1Sskrll#define GCC_PCIE0_PIPE_ARES					80
921.1Sskrll#define GCC_PCIE1_AHB_ARES					81
931.1Sskrll#define GCC_PCIE1_AUX_ARES					82
941.1Sskrll#define GCC_PCIE1_AXI_M_ARES					83
951.1Sskrll#define GCC_PCIE1_AXI_M_STICKY_ARES				84
961.1Sskrll#define GCC_PCIE1_AXI_S_ARES					85
971.1Sskrll#define GCC_PCIE1_AXI_S_STICKY_ARES				86
981.1Sskrll#define GCC_PCIE1_CORE_STICKY_ARES				87
991.1Sskrll#define GCC_PCIE1_PIPE_ARES					88
1001.1Sskrll#define GCC_PCIE2_AHB_ARES					89
1011.1Sskrll#define GCC_PCIE2_AUX_ARES					90
1021.1Sskrll#define GCC_PCIE2_AXI_M_ARES					91
1031.1Sskrll#define GCC_PCIE2_AXI_M_STICKY_ARES				92
1041.1Sskrll#define GCC_PCIE2_AXI_S_ARES					93
1051.1Sskrll#define GCC_PCIE2_AXI_S_STICKY_ARES				94
1061.1Sskrll#define GCC_PCIE2_CORE_STICKY_ARES				95
1071.1Sskrll#define GCC_PCIE2_PIPE_ARES					96
1081.1Sskrll#define GCC_PCIE3_AHB_ARES					97
1091.1Sskrll#define GCC_PCIE3_AUX_ARES					98
1101.1Sskrll#define GCC_PCIE3_AXI_M_ARES					99
1111.1Sskrll#define GCC_PCIE3_AXI_M_STICKY_ARES				100
1121.1Sskrll#define GCC_PCIE3_AXI_S_ARES					101
1131.1Sskrll#define GCC_PCIE3_AXI_S_STICKY_ARES				102
1141.1Sskrll#define GCC_PCIE3_CORE_STICKY_ARES				103
1151.1Sskrll#define GCC_PCIE3_PIPE_ARES					104
1161.1Sskrll#define GCC_PCNOC_BCR						105
1171.1Sskrll#define GCC_PCNOC_BUS_TIMEOUT0_BCR				106
1181.1Sskrll#define GCC_PCNOC_BUS_TIMEOUT1_BCR				107
1191.1Sskrll#define GCC_PCNOC_BUS_TIMEOUT2_BCR				108
1201.1Sskrll#define GCC_PCNOC_BUS_TIMEOUT3_BCR				109
1211.1Sskrll#define GCC_PCNOC_BUS_TIMEOUT4_BCR				110
1221.1Sskrll#define GCC_PCNOC_BUS_TIMEOUT5_BCR				111
1231.1Sskrll#define GCC_PCNOC_BUS_TIMEOUT6_BCR				112
1241.1Sskrll#define GCC_PCNOC_BUS_TIMEOUT7_BCR				113
1251.1Sskrll#define GCC_PCNOC_BUS_TIMEOUT8_BCR				114
1261.1Sskrll#define GCC_PCNOC_BUS_TIMEOUT9_BCR				115
1271.1Sskrll#define GCC_PCNOC_TBU_BCR					116
1281.1Sskrll#define GCC_Q6SS_DBG_ARES					117
1291.1Sskrll#define GCC_Q6_AHB_ARES						118
1301.1Sskrll#define GCC_Q6_AHB_S_ARES					119
1311.1Sskrll#define GCC_Q6_AXIM2_ARES					120
1321.1Sskrll#define GCC_Q6_AXIM_ARES					121
1331.1Sskrll#define GCC_QDSS_BCR						122
1341.1Sskrll#define GCC_QPIC_BCR						123
1351.1Sskrll#define GCC_QPIC_AHB_ARES					124
1361.1Sskrll#define GCC_QPIC_ARES						125
1371.1Sskrll#define GCC_RBCPR_BCR						126
1381.1Sskrll#define GCC_RBCPR_MX_BCR					127
1391.1Sskrll#define GCC_SEC_CTRL_BCR					128
1401.1Sskrll#define GCC_SMMU_CFG_BCR					129
1411.1Sskrll#define GCC_SNOC_BCR						130
1421.1Sskrll#define GCC_SPDM_BCR						131
1431.1Sskrll#define GCC_TME_BCR						132
1441.1Sskrll#define GCC_UNIPHY0_SYS_RESET					133
1451.1Sskrll#define GCC_UNIPHY0_AHB_RESET					134
1461.1Sskrll#define GCC_UNIPHY0_XPCS_RESET					135
1471.1Sskrll#define GCC_UNIPHY1_SYS_RESET					136
1481.1Sskrll#define GCC_UNIPHY1_AHB_RESET					137
1491.1Sskrll#define GCC_UNIPHY1_XPCS_RESET					138
1501.1Sskrll#define GCC_UNIPHY2_SYS_RESET					139
1511.1Sskrll#define GCC_UNIPHY2_AHB_RESET					140
1521.1Sskrll#define GCC_UNIPHY2_XPCS_RESET					141
1531.1Sskrll#define GCC_USB_MISC_RESET					142
1541.1Sskrll#define GCC_WCSSAON_RESET					143
1551.1Sskrll#define GCC_WCSS_ACMT_ARES					144
1561.1Sskrll#define GCC_WCSS_AHB_S_ARES					145
1571.1Sskrll#define GCC_WCSS_AXI_M_ARES					146
1581.1Sskrll#define GCC_WCSS_BCR						147
1591.1Sskrll#define GCC_WCSS_DBG_ARES					148
1601.1Sskrll#define GCC_WCSS_DBG_BDG_ARES					149
1611.1Sskrll#define GCC_WCSS_ECAHB_ARES					150
1621.1Sskrll#define GCC_WCSS_Q6_BCR						151
1631.1Sskrll#define GCC_WCSS_Q6_TBU_BCR					152
1641.1Sskrll#define GCC_TCSR_BCR						153
1651.1Sskrll#define GCC_CRYPTO_BCR						154
1661.1Sskrll
1671.1Sskrll#endif
168