11.1Sjmcneill/* $NetBSD: realtek,rtd1195.h,v 1.1.1.1 2021/11/07 16:49:57 jmcneill Exp $ */ 21.1Sjmcneill 31.1Sjmcneill/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ 41.1Sjmcneill/* 51.1Sjmcneill * Realtek RTD1195 reset controllers 61.1Sjmcneill * 71.1Sjmcneill * Copyright (c) 2017 Andreas Färber 81.1Sjmcneill */ 91.1Sjmcneill#ifndef DT_BINDINGS_RESET_RTD1195_H 101.1Sjmcneill#define DT_BINDINGS_RESET_RTD1195_H 111.1Sjmcneill 121.1Sjmcneill/* soft reset 1 */ 131.1Sjmcneill#define RTD1195_RSTN_MISC 0 141.1Sjmcneill#define RTD1195_RSTN_RNG 1 151.1Sjmcneill#define RTD1195_RSTN_USB3_POW 2 161.1Sjmcneill#define RTD1195_RSTN_GSPI 3 171.1Sjmcneill#define RTD1195_RSTN_USB3_P0_MDIO 4 181.1Sjmcneill#define RTD1195_RSTN_VE_H265 5 191.1Sjmcneill#define RTD1195_RSTN_USB 6 201.1Sjmcneill#define RTD1195_RSTN_USB_PHY0 8 211.1Sjmcneill#define RTD1195_RSTN_USB_PHY1 9 221.1Sjmcneill#define RTD1195_RSTN_HDMIRX 11 231.1Sjmcneill#define RTD1195_RSTN_HDMI 12 241.1Sjmcneill#define RTD1195_RSTN_ETN 14 251.1Sjmcneill#define RTD1195_RSTN_AIO 15 261.1Sjmcneill#define RTD1195_RSTN_GPU 16 271.1Sjmcneill#define RTD1195_RSTN_VE_H264 17 281.1Sjmcneill#define RTD1195_RSTN_VE_JPEG 18 291.1Sjmcneill#define RTD1195_RSTN_TVE 19 301.1Sjmcneill#define RTD1195_RSTN_VO 20 311.1Sjmcneill#define RTD1195_RSTN_LVDS 21 321.1Sjmcneill#define RTD1195_RSTN_SE 22 331.1Sjmcneill#define RTD1195_RSTN_DCU 23 341.1Sjmcneill#define RTD1195_RSTN_DC_PHY 24 351.1Sjmcneill#define RTD1195_RSTN_CP 25 361.1Sjmcneill#define RTD1195_RSTN_MD 26 371.1Sjmcneill#define RTD1195_RSTN_TP 27 381.1Sjmcneill#define RTD1195_RSTN_AE 28 391.1Sjmcneill#define RTD1195_RSTN_NF 29 401.1Sjmcneill#define RTD1195_RSTN_MIPI 30 411.1Sjmcneill 421.1Sjmcneill/* soft reset 2 */ 431.1Sjmcneill#define RTD1195_RSTN_ACPU 0 441.1Sjmcneill#define RTD1195_RSTN_VCPU 1 451.1Sjmcneill#define RTD1195_RSTN_PCR 9 461.1Sjmcneill#define RTD1195_RSTN_CR 10 471.1Sjmcneill#define RTD1195_RSTN_EMMC 11 481.1Sjmcneill#define RTD1195_RSTN_SDIO 12 491.1Sjmcneill#define RTD1195_RSTN_I2C_5 18 501.1Sjmcneill#define RTD1195_RSTN_RTC 20 511.1Sjmcneill#define RTD1195_RSTN_I2C_4 23 521.1Sjmcneill#define RTD1195_RSTN_I2C_3 24 531.1Sjmcneill#define RTD1195_RSTN_I2C_2 25 541.1Sjmcneill#define RTD1195_RSTN_I2C_1 26 551.1Sjmcneill#define RTD1195_RSTN_UR1 28 561.1Sjmcneill 571.1Sjmcneill/* soft reset 3 */ 581.1Sjmcneill#define RTD1195_RSTN_SB2 0 591.1Sjmcneill 601.1Sjmcneill/* iso soft reset */ 611.1Sjmcneill#define RTD1195_ISO_RSTN_VFD 0 621.1Sjmcneill#define RTD1195_ISO_RSTN_IR 1 631.1Sjmcneill#define RTD1195_ISO_RSTN_CEC0 2 641.1Sjmcneill#define RTD1195_ISO_RSTN_CEC1 3 651.1Sjmcneill#define RTD1195_ISO_RSTN_DP 4 661.1Sjmcneill#define RTD1195_ISO_RSTN_CBUSTX 5 671.1Sjmcneill#define RTD1195_ISO_RSTN_CBUSRX 6 681.1Sjmcneill#define RTD1195_ISO_RSTN_EFUSE 7 691.1Sjmcneill#define RTD1195_ISO_RSTN_UR0 8 701.1Sjmcneill#define RTD1195_ISO_RSTN_GMAC 9 711.1Sjmcneill#define RTD1195_ISO_RSTN_GPHY 10 721.1Sjmcneill#define RTD1195_ISO_RSTN_I2C_0 11 731.1Sjmcneill#define RTD1195_ISO_RSTN_I2C_6 12 741.1Sjmcneill#define RTD1195_ISO_RSTN_CBUS 13 751.1Sjmcneill 761.1Sjmcneill#endif 77