tegra186-reset.h revision 1.1.1.1.8.2
1 /* $NetBSD: tegra186-reset.h,v 1.1.1.1.8.2 2017/12/03 11:38:40 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef _ABI_MACH_T186_RESET_T186_H_ 20 #define _ABI_MACH_T186_RESET_T186_H_ 21 22 23 #define TEGRA186_RESET_ACTMON 0 24 #define TEGRA186_RESET_AFI 1 25 #define TEGRA186_RESET_CEC 2 26 #define TEGRA186_RESET_CSITE 3 27 #define TEGRA186_RESET_DP2 4 28 #define TEGRA186_RESET_DPAUX 5 29 #define TEGRA186_RESET_DSI 6 30 #define TEGRA186_RESET_DSIB 7 31 #define TEGRA186_RESET_DTV 8 32 #define TEGRA186_RESET_DVFS 9 33 #define TEGRA186_RESET_ENTROPY 10 34 #define TEGRA186_RESET_EXTPERIPH1 11 35 #define TEGRA186_RESET_EXTPERIPH2 12 36 #define TEGRA186_RESET_EXTPERIPH3 13 37 #define TEGRA186_RESET_GPU 14 38 #define TEGRA186_RESET_HDA 15 39 #define TEGRA186_RESET_HDA2CODEC_2X 16 40 #define TEGRA186_RESET_HDA2HDMICODEC 17 41 #define TEGRA186_RESET_HOST1X 18 42 #define TEGRA186_RESET_I2C1 19 43 #define TEGRA186_RESET_I2C2 20 44 #define TEGRA186_RESET_I2C3 21 45 #define TEGRA186_RESET_I2C4 22 46 #define TEGRA186_RESET_I2C5 23 47 #define TEGRA186_RESET_I2C6 24 48 #define TEGRA186_RESET_ISP 25 49 #define TEGRA186_RESET_KFUSE 26 50 #define TEGRA186_RESET_LA 27 51 #define TEGRA186_RESET_MIPI_CAL 28 52 #define TEGRA186_RESET_PCIE 29 53 #define TEGRA186_RESET_PCIEXCLK 30 54 #define TEGRA186_RESET_SATA 31 55 #define TEGRA186_RESET_SATACOLD 32 56 #define TEGRA186_RESET_SDMMC1 33 57 #define TEGRA186_RESET_SDMMC2 34 58 #define TEGRA186_RESET_SDMMC3 35 59 #define TEGRA186_RESET_SDMMC4 36 60 #define TEGRA186_RESET_SE 37 61 #define TEGRA186_RESET_SOC_THERM 38 62 #define TEGRA186_RESET_SOR0 39 63 #define TEGRA186_RESET_SPI1 40 64 #define TEGRA186_RESET_SPI2 41 65 #define TEGRA186_RESET_SPI3 42 66 #define TEGRA186_RESET_SPI4 43 67 #define TEGRA186_RESET_TMR 44 68 #define TEGRA186_RESET_TRIG_SYS 45 69 #define TEGRA186_RESET_TSEC 46 70 #define TEGRA186_RESET_UARTA 47 71 #define TEGRA186_RESET_UARTB 48 72 #define TEGRA186_RESET_UARTC 49 73 #define TEGRA186_RESET_UARTD 50 74 #define TEGRA186_RESET_VI 51 75 #define TEGRA186_RESET_VIC 52 76 #define TEGRA186_RESET_XUSB_DEV 53 77 #define TEGRA186_RESET_XUSB_HOST 54 78 #define TEGRA186_RESET_XUSB_PADCTL 55 79 #define TEGRA186_RESET_XUSB_SS 56 80 #define TEGRA186_RESET_AON_APB 57 81 #define TEGRA186_RESET_AXI_CBB 58 82 #define TEGRA186_RESET_BPMP_APB 59 83 #define TEGRA186_RESET_CAN1 60 84 #define TEGRA186_RESET_CAN2 61 85 #define TEGRA186_RESET_DMIC5 62 86 #define TEGRA186_RESET_DSIC 63 87 #define TEGRA186_RESET_DSID 64 88 #define TEGRA186_RESET_EMC_EMC 65 89 #define TEGRA186_RESET_EMC_MEM 66 90 #define TEGRA186_RESET_EMCSB_EMC 67 91 #define TEGRA186_RESET_EMCSB_MEM 68 92 #define TEGRA186_RESET_EQOS 69 93 #define TEGRA186_RESET_GPCDMA 70 94 #define TEGRA186_RESET_GPIO_CTL0 71 95 #define TEGRA186_RESET_GPIO_CTL1 72 96 #define TEGRA186_RESET_GPIO_CTL2 73 97 #define TEGRA186_RESET_GPIO_CTL3 74 98 #define TEGRA186_RESET_GPIO_CTL4 75 99 #define TEGRA186_RESET_GPIO_CTL5 76 100 #define TEGRA186_RESET_I2C10 77 101 #define TEGRA186_RESET_I2C12 78 102 #define TEGRA186_RESET_I2C13 79 103 #define TEGRA186_RESET_I2C14 80 104 #define TEGRA186_RESET_I2C7 81 105 #define TEGRA186_RESET_I2C8 82 106 #define TEGRA186_RESET_I2C9 83 107 #define TEGRA186_RESET_JTAG2AXI 84 108 #define TEGRA186_RESET_MPHY_IOBIST 85 109 #define TEGRA186_RESET_MPHY_L0_RX 86 110 #define TEGRA186_RESET_MPHY_L0_TX 87 111 #define TEGRA186_RESET_NVCSI 88 112 #define TEGRA186_RESET_NVDISPLAY0_HEAD0 89 113 #define TEGRA186_RESET_NVDISPLAY0_HEAD1 90 114 #define TEGRA186_RESET_NVDISPLAY0_HEAD2 91 115 #define TEGRA186_RESET_NVDISPLAY0_MISC 92 116 #define TEGRA186_RESET_NVDISPLAY0_WGRP0 93 117 #define TEGRA186_RESET_NVDISPLAY0_WGRP1 94 118 #define TEGRA186_RESET_NVDISPLAY0_WGRP2 95 119 #define TEGRA186_RESET_NVDISPLAY0_WGRP3 96 120 #define TEGRA186_RESET_NVDISPLAY0_WGRP4 97 121 #define TEGRA186_RESET_NVDISPLAY0_WGRP5 98 122 #define TEGRA186_RESET_PWM1 99 123 #define TEGRA186_RESET_PWM2 100 124 #define TEGRA186_RESET_PWM3 101 125 #define TEGRA186_RESET_PWM4 102 126 #define TEGRA186_RESET_PWM5 103 127 #define TEGRA186_RESET_PWM6 104 128 #define TEGRA186_RESET_PWM7 105 129 #define TEGRA186_RESET_PWM8 106 130 #define TEGRA186_RESET_SCE_APB 107 131 #define TEGRA186_RESET_SOR1 108 132 #define TEGRA186_RESET_TACH 109 133 #define TEGRA186_RESET_TSC 110 134 #define TEGRA186_RESET_UARTF 111 135 #define TEGRA186_RESET_UARTG 112 136 #define TEGRA186_RESET_UFSHC 113 137 #define TEGRA186_RESET_UFSHC_AXI_M 114 138 #define TEGRA186_RESET_UPHY 115 139 #define TEGRA186_RESET_ADSP 116 140 #define TEGRA186_RESET_ADSPDBG 117 141 #define TEGRA186_RESET_ADSPINTF 118 142 #define TEGRA186_RESET_ADSPNEON 119 143 #define TEGRA186_RESET_ADSPPERIPH 120 144 #define TEGRA186_RESET_ADSPSCU 121 145 #define TEGRA186_RESET_ADSPWDT 122 146 #define TEGRA186_RESET_APE 123 147 #define TEGRA186_RESET_DPAUX1 124 148 #define TEGRA186_RESET_NVDEC 125 149 #define TEGRA186_RESET_NVENC 126 150 #define TEGRA186_RESET_NVJPG 127 151 #define TEGRA186_RESET_PEX_USB_UPHY 128 152 #define TEGRA186_RESET_QSPI 129 153 #define TEGRA186_RESET_TSECB 130 154 #define TEGRA186_RESET_VI_I2C 131 155 #define TEGRA186_RESET_UARTE 132 156 #define TEGRA186_RESET_TOP_GTE 133 157 #define TEGRA186_RESET_SHSP 134 158 #define TEGRA186_RESET_PEX_USB_UPHY_L5 135 159 #define TEGRA186_RESET_PEX_USB_UPHY_L4 136 160 #define TEGRA186_RESET_PEX_USB_UPHY_L3 137 161 #define TEGRA186_RESET_PEX_USB_UPHY_L2 138 162 #define TEGRA186_RESET_PEX_USB_UPHY_L1 139 163 #define TEGRA186_RESET_PEX_USB_UPHY_L0 140 164 #define TEGRA186_RESET_PEX_USB_UPHY_PLL1 141 165 #define TEGRA186_RESET_PEX_USB_UPHY_PLL0 142 166 #define TEGRA186_RESET_TSCTNVI 143 167 #define TEGRA186_RESET_EXTPERIPH4 144 168 #define TEGRA186_RESET_DSIPADCTL 145 169 #define TEGRA186_RESET_AUD_MCLK 146 170 #define TEGRA186_RESET_MPHY_CLK_CTL 147 171 #define TEGRA186_RESET_MPHY_L1_RX 148 172 #define TEGRA186_RESET_MPHY_L1_TX 149 173 #define TEGRA186_RESET_UFSHC_LP 150 174 #define TEGRA186_RESET_BPMP_NIC 151 175 #define TEGRA186_RESET_BPMP_NSYSPORESET 152 176 #define TEGRA186_RESET_BPMP_NRESET 153 177 #define TEGRA186_RESET_BPMP_DBGRESETN 154 178 #define TEGRA186_RESET_BPMP_PRESETDBGN 155 179 #define TEGRA186_RESET_BPMP_PM 156 180 #define TEGRA186_RESET_BPMP_CVC 157 181 #define TEGRA186_RESET_BPMP_DMA 158 182 #define TEGRA186_RESET_BPMP_HSP 159 183 #define TEGRA186_RESET_TSCTNBPMP 160 184 #define TEGRA186_RESET_BPMP_TKE 161 185 #define TEGRA186_RESET_BPMP_GTE 162 186 #define TEGRA186_RESET_BPMP_PM_ACTMON 163 187 #define TEGRA186_RESET_AON_NIC 164 188 #define TEGRA186_RESET_AON_NSYSPORESET 165 189 #define TEGRA186_RESET_AON_NRESET 166 190 #define TEGRA186_RESET_AON_DBGRESETN 167 191 #define TEGRA186_RESET_AON_PRESETDBGN 168 192 #define TEGRA186_RESET_AON_ACTMON 169 193 #define TEGRA186_RESET_AOPM 170 194 #define TEGRA186_RESET_AOVC 171 195 #define TEGRA186_RESET_AON_DMA 172 196 #define TEGRA186_RESET_AON_GPIO 173 197 #define TEGRA186_RESET_AON_HSP 174 198 #define TEGRA186_RESET_TSCTNAON 175 199 #define TEGRA186_RESET_AON_TKE 176 200 #define TEGRA186_RESET_AON_GTE 177 201 #define TEGRA186_RESET_SCE_NIC 178 202 #define TEGRA186_RESET_SCE_NSYSPORESET 179 203 #define TEGRA186_RESET_SCE_NRESET 180 204 #define TEGRA186_RESET_SCE_DBGRESETN 181 205 #define TEGRA186_RESET_SCE_PRESETDBGN 182 206 #define TEGRA186_RESET_SCE_ACTMON 183 207 #define TEGRA186_RESET_SCE_PM 184 208 #define TEGRA186_RESET_SCE_DMA 185 209 #define TEGRA186_RESET_SCE_HSP 186 210 #define TEGRA186_RESET_TSCTNSCE 187 211 #define TEGRA186_RESET_SCE_TKE 188 212 #define TEGRA186_RESET_SCE_GTE 189 213 #define TEGRA186_RESET_SCE_CFG 190 214 #define TEGRA186_RESET_ADSP_ALL 191 215 /** @brief controls the power up/down sequence of UFSHC PSW partition. Controls LP_PWR_READY, LP_ISOL_EN, and LP_RESET_N signals */ 216 #define TEGRA186_RESET_UFSHC_LP_SEQ 192 217 #define TEGRA186_RESET_SIZE 193 218 219 #endif 220
Indexes created Sat Oct 25 00:10:07 GMT 2025