11.1Sskrll/*	$NetBSD: cs35l45.h,v 1.1.1.1 2026/01/18 05:21:56 skrll Exp $	*/
21.1Sskrll
31.1Sskrll/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
41.1Sskrll/*
51.1Sskrll * cs35l45.h -- CS35L45 ALSA SoC audio driver DT bindings header
61.1Sskrll *
71.1Sskrll * Copyright 2022 Cirrus Logic, Inc.
81.1Sskrll */
91.1Sskrll
101.1Sskrll#ifndef DT_CS35L45_H
111.1Sskrll#define DT_CS35L45_H
121.1Sskrll
131.1Sskrll/*
141.1Sskrll * cirrus,asp-sdout-hiz-ctrl
151.1Sskrll *
161.1Sskrll * TX_HIZ_UNUSED:   TX pin high-impedance during unused slots.
171.1Sskrll * TX_HIZ_DISABLED: TX pin high-impedance when all channels disabled.
181.1Sskrll */
191.1Sskrll#define CS35L45_ASP_TX_HIZ_UNUSED	0x1
201.1Sskrll#define CS35L45_ASP_TX_HIZ_DISABLED	0x2
211.1Sskrll
221.1Sskrll/*
231.1Sskrll * Optional GPIOX Sub-nodes:
241.1Sskrll *  The cs35l45 node can have up to three "cirrus,gpio-ctrlX" ('X' = [1,2,3])
251.1Sskrll *  sub-nodes for configuring the GPIO pins.
261.1Sskrll *
271.1Sskrll * - gpio-dir : GPIO pin direction. Valid only when 'gpio-ctrl'
281.1Sskrll *   is 1.
291.1Sskrll *    0 = Output
301.1Sskrll *    1 = Input (Default)
311.1Sskrll *
321.1Sskrll * - gpio-lvl : GPIO level. Valid only when 'gpio-ctrl' is 1 and 'gpio-dir' is 0.
331.1Sskrll *
341.1Sskrll *    0 = Low (Default)
351.1Sskrll *    1 = High
361.1Sskrll *
371.1Sskrll * - gpio-op-cfg : GPIO output configuration. Valid only when 'gpio-ctrl' is 1
381.1Sskrll *   and 'gpio-dir' is 0.
391.1Sskrll *
401.1Sskrll *    0 = CMOS (Default)
411.1Sskrll *    1 = Open Drain
421.1Sskrll *
431.1Sskrll * - gpio-pol : GPIO output polarity select. Valid only when 'gpio-ctrl' is 1
441.1Sskrll *   and 'gpio-dir' is 0.
451.1Sskrll *
461.1Sskrll *    0 = Non-inverted, Active High (Default)
471.1Sskrll *    1 = Inverted, Active Low
481.1Sskrll *
491.1Sskrll * - gpio-invert : Defines the polarity of the GPIO pin if configured
501.1Sskrll *   as input.
511.1Sskrll *
521.1Sskrll *    0 = Not inverted (Default)
531.1Sskrll *    1 = Inverted
541.1Sskrll *
551.1Sskrll * - gpio-ctrl : Defines the function of the GPIO pin.
561.1Sskrll *
571.1Sskrll * GPIO1:
581.1Sskrll *   0 = High impedance input (Default)
591.1Sskrll *   1 = Pin acts as a GPIO, direction controlled by 'gpio-dir'
601.1Sskrll *   2 = Pin acts as MDSYNC, direction controlled by MDSYNC
611.1Sskrll *   3-7 = Reserved
621.1Sskrll *
631.1Sskrll * GPIO2:
641.1Sskrll *   0 = High impedance input (Default)
651.1Sskrll *   1 = Pin acts as a GPIO, direction controlled by 'gpio-dir'
661.1Sskrll *   2 = Pin acts as open drain INT
671.1Sskrll *   3 = Reserved
681.1Sskrll *   4 = Pin acts as push-pull output INT. Active low.
691.1Sskrll *   5 = Pin acts as push-pull output INT. Active high.
701.1Sskrll *   6,7 = Reserved
711.1Sskrll *
721.1Sskrll * GPIO3:
731.1Sskrll *   0 = High impedance input (Default)
741.1Sskrll *   1 = Pin acts as a GPIO, direction controlled by 'gpio-dir'
751.1Sskrll *   2-7 = Reserved
761.1Sskrll */
771.1Sskrll#define CS35L45_NUM_GPIOS	0x3
781.1Sskrll
791.1Sskrll#endif /* DT_CS35L45_H */
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