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      1  1.1  alc /*
      2  1.1  alc  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
      3  1.1  alc  * Copyright (c) 2002-2008 Atheros Communications, Inc.
      4  1.1  alc  *
      5  1.1  alc  * Permission to use, copy, modify, and/or distribute this software for any
      6  1.1  alc  * purpose with or without fee is hereby granted, provided that the above
      7  1.1  alc  * copyright notice and this permission notice appear in all copies.
      8  1.1  alc  *
      9  1.1  alc  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
     10  1.1  alc  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
     11  1.1  alc  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
     12  1.1  alc  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
     13  1.1  alc  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
     14  1.1  alc  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
     15  1.1  alc  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
     16  1.1  alc  *
     17  1.1  alc  * $Id: ah_decode.h,v 1.1.1.1 2008/12/11 04:46:23 alc Exp $
     18  1.1  alc  */
     19  1.1  alc #ifndef _ATH_AH_DECODE_H_
     20  1.1  alc #define _ATH_AH_DECODE_H_
     21  1.1  alc /*
     22  1.1  alc  * Register tracing support.
     23  1.1  alc  *
     24  1.1  alc  * Setting hw.ath.hal.alq=1 enables tracing of all register reads and
     25  1.1  alc  * writes to the file /tmp/ath_hal.log.  The file format is a simple
     26  1.1  alc  * fixed-size array of records.  When done logging set hw.ath.hal.alq=0
     27  1.1  alc  * and then decode the file with the arcode program (that is part of the
     28  1.1  alc  * HAL).  If you start+stop tracing the data will be appended to an
     29  1.1  alc  * existing file.
     30  1.1  alc  */
     31  1.1  alc struct athregrec {
     32  1.1  alc 	uint32_t	op	: 8,
     33  1.1  alc 			reg	: 24;
     34  1.1  alc 	uint32_t	val;
     35  1.1  alc };
     36  1.1  alc 
     37  1.1  alc enum {
     38  1.1  alc 	OP_READ		= 0,		/* register read */
     39  1.1  alc 	OP_WRITE	= 1,		/* register write */
     40  1.1  alc 	OP_DEVICE	= 2,		/* device identification */
     41  1.1  alc 	OP_MARK		= 3,		/* application marker */
     42  1.1  alc };
     43  1.1  alc 
     44  1.1  alc enum {
     45  1.1  alc 	AH_MARK_RESET,			/* ar*Reset entry, bChannelChange */
     46  1.1  alc 	AH_MARK_RESET_LINE,		/* ar*_reset.c, line %d */
     47  1.1  alc 	AH_MARK_RESET_DONE,		/* ar*Reset exit, error code */
     48  1.1  alc 	AH_MARK_CHIPRESET,		/* ar*ChipReset, channel num */
     49  1.1  alc 	AH_MARK_PERCAL,			/* ar*PerCalibration, channel num */
     50  1.1  alc 	AH_MARK_SETCHANNEL,		/* ar*SetChannel, channel num */
     51  1.1  alc 	AH_MARK_ANI_RESET,		/* ar*AniReset, opmode */
     52  1.1  alc 	AH_MARK_ANI_POLL,		/* ar*AniReset, listen time */
     53  1.1  alc 	AH_MARK_ANI_CONTROL,		/* ar*AniReset, cmd */
     54  1.1  alc };
     55  1.1  alc #endif /* _ATH_AH_DECODE_H_ */
     56