ah_desc.h revision 1.2.2.2
1 1.2.2.2 mjf /* 2 1.2.2.2 mjf * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 1.2.2.2 mjf * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 1.2.2.2 mjf * 5 1.2.2.2 mjf * Permission to use, copy, modify, and/or distribute this software for any 6 1.2.2.2 mjf * purpose with or without fee is hereby granted, provided that the above 7 1.2.2.2 mjf * copyright notice and this permission notice appear in all copies. 8 1.2.2.2 mjf * 9 1.2.2.2 mjf * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 1.2.2.2 mjf * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 1.2.2.2 mjf * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 1.2.2.2 mjf * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 1.2.2.2 mjf * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 1.2.2.2 mjf * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 1.2.2.2 mjf * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 1.2.2.2 mjf * 17 1.2.2.2 mjf * $Id: ah_desc.h,v 1.2.2.2 2009/01/17 13:29:11 mjf Exp $ 18 1.2.2.2 mjf */ 19 1.2.2.2 mjf 20 1.2.2.2 mjf #ifndef _DEV_ATH_DESC_H 21 1.2.2.2 mjf #define _DEV_ATH_DESC_H 22 1.2.2.2 mjf 23 1.2.2.2 mjf #include "opt_ah.h" /* NB: required for AH_SUPPORT_AR5416 */ 24 1.2.2.2 mjf 25 1.2.2.2 mjf /* 26 1.2.2.2 mjf * Transmit descriptor status. This structure is filled 27 1.2.2.2 mjf * in only after the tx descriptor process method finds a 28 1.2.2.2 mjf * ``done'' descriptor; at which point it returns something 29 1.2.2.2 mjf * other than HAL_EINPROGRESS. 30 1.2.2.2 mjf * 31 1.2.2.2 mjf * Note that ts_antenna may not be valid for all h/w. It 32 1.2.2.2 mjf * should be used only if non-zero. 33 1.2.2.2 mjf */ 34 1.2.2.2 mjf struct ath_tx_status { 35 1.2.2.2 mjf uint16_t ts_seqnum; /* h/w assigned sequence number */ 36 1.2.2.2 mjf uint16_t ts_tstamp; /* h/w assigned timestamp */ 37 1.2.2.2 mjf uint8_t ts_status; /* frame status, 0 => xmit ok */ 38 1.2.2.2 mjf uint8_t ts_rate; /* h/w transmit rate index */ 39 1.2.2.2 mjf #define HAL_TXSTAT_ALTRATE 0x80 /* alternate xmit rate used */ 40 1.2.2.2 mjf int8_t ts_rssi; /* tx ack RSSI */ 41 1.2.2.2 mjf uint8_t ts_shortretry; /* # short retries */ 42 1.2.2.2 mjf uint8_t ts_longretry; /* # long retries */ 43 1.2.2.2 mjf uint8_t ts_virtcol; /* virtual collision count */ 44 1.2.2.2 mjf uint8_t ts_antenna; /* antenna information */ 45 1.2.2.2 mjf uint8_t ts_finaltsi; /* final transmit series index */ 46 1.2.2.2 mjf #ifdef AH_SUPPORT_AR5416 47 1.2.2.2 mjf /* 802.11n status */ 48 1.2.2.2 mjf uint8_t ts_flags; /* misc flags */ 49 1.2.2.2 mjf int8_t ts_rssi_ctl[3]; /* tx ack RSSI [ctl, chain 0-2] */ 50 1.2.2.2 mjf int8_t ts_rssi_ext[3]; /* tx ack RSSI [ext, chain 0-2] */ 51 1.2.2.2 mjf /* #define ts_rssi ts_rssi_combined */ 52 1.2.2.2 mjf uint32_t ts_ba_low; /* blockack bitmap low */ 53 1.2.2.2 mjf uint32_t ts_ba_high; /* blockack bitmap high */ 54 1.2.2.2 mjf uint32_t ts_evm0; /* evm bytes */ 55 1.2.2.2 mjf uint32_t ts_evm1; 56 1.2.2.2 mjf uint32_t ts_evm2; 57 1.2.2.2 mjf #endif /* AH_SUPPORT_AR5416 */ 58 1.2.2.2 mjf }; 59 1.2.2.2 mjf 60 1.2.2.2 mjf /* bits found in ts_status */ 61 1.2.2.2 mjf #define HAL_TXERR_XRETRY 0x01 /* excessive retries */ 62 1.2.2.2 mjf #define HAL_TXERR_FILT 0x02 /* blocked by tx filtering */ 63 1.2.2.2 mjf #define HAL_TXERR_FIFO 0x04 /* fifo underrun */ 64 1.2.2.2 mjf #define HAL_TXERR_XTXOP 0x08 /* txop exceeded */ 65 1.2.2.2 mjf #define HAL_TXERR_TIMER_EXPIRED 0x10 /* Tx timer expired */ 66 1.2.2.2 mjf 67 1.2.2.2 mjf /* bits found in ts_flags */ 68 1.2.2.2 mjf #define HAL_TX_BA 0x01 /* Block Ack seen */ 69 1.2.2.2 mjf #define HAL_TX_AGGR 0x02 /* Aggregate */ 70 1.2.2.2 mjf #define HAL_TX_DESC_CFG_ERR 0x10 /* Error in 20/40 desc config */ 71 1.2.2.2 mjf #define HAL_TX_DATA_UNDERRUN 0x20 /* Tx buffer underrun */ 72 1.2.2.2 mjf #define HAL_TX_DELIM_UNDERRUN 0x40 /* Tx delimiter underrun */ 73 1.2.2.2 mjf 74 1.2.2.2 mjf /* 75 1.2.2.2 mjf * Receive descriptor status. This structure is filled 76 1.2.2.2 mjf * in only after the rx descriptor process method finds a 77 1.2.2.2 mjf * ``done'' descriptor; at which point it returns something 78 1.2.2.2 mjf * other than HAL_EINPROGRESS. 79 1.2.2.2 mjf * 80 1.2.2.2 mjf * If rx_status is zero, then the frame was received ok; 81 1.2.2.2 mjf * otherwise the error information is indicated and rs_phyerr 82 1.2.2.2 mjf * contains a phy error code if HAL_RXERR_PHY is set. In general 83 1.2.2.2 mjf * the frame contents is undefined when an error occurred thought 84 1.2.2.2 mjf * for some errors (e.g. a decryption error), it may be meaningful. 85 1.2.2.2 mjf * 86 1.2.2.2 mjf * Note that the receive timestamp is expanded using the TSF to 87 1.2.2.2 mjf * at least 15 bits (regardless of what the h/w provides directly). 88 1.2.2.2 mjf * Newer hardware supports a full 32-bits; use HAL_CAP_32TSTAMP to 89 1.2.2.2 mjf * find out if the hardware is capable. 90 1.2.2.2 mjf * 91 1.2.2.2 mjf * rx_rssi is in units of dbm above the noise floor. This value 92 1.2.2.2 mjf * is measured during the preamble and PLCP; i.e. with the initial 93 1.2.2.2 mjf * 4us of detection. The noise floor is typically a consistent 94 1.2.2.2 mjf * -96dBm absolute power in a 20MHz channel. 95 1.2.2.2 mjf */ 96 1.2.2.2 mjf struct ath_rx_status { 97 1.2.2.2 mjf uint16_t rs_datalen; /* rx frame length */ 98 1.2.2.2 mjf uint8_t rs_status; /* rx status, 0 => recv ok */ 99 1.2.2.2 mjf uint8_t rs_phyerr; /* phy error code */ 100 1.2.2.2 mjf int8_t rs_rssi; /* rx frame RSSI (combined for 11n) */ 101 1.2.2.2 mjf uint8_t rs_keyix; /* key cache index */ 102 1.2.2.2 mjf uint8_t rs_rate; /* h/w receive rate index */ 103 1.2.2.2 mjf uint8_t rs_more; /* more descriptors follow */ 104 1.2.2.2 mjf uint32_t rs_tstamp; /* h/w assigned timestamp */ 105 1.2.2.2 mjf uint32_t rs_antenna; /* antenna information */ 106 1.2.2.2 mjf #ifdef AH_SUPPORT_AR5416 107 1.2.2.2 mjf /* 802.11n status */ 108 1.2.2.2 mjf int8_t rs_rssi_ctl[3]; /* rx frame RSSI [ctl, chain 0-2] */ 109 1.2.2.2 mjf int8_t rs_rssi_ext[3]; /* rx frame RSSI [ext, chain 0-2] */ 110 1.2.2.2 mjf uint8_t rs_isaggr; /* is part of the aggregate */ 111 1.2.2.2 mjf uint8_t rs_moreaggr; /* more frames in aggr to follow */ 112 1.2.2.2 mjf uint8_t rs_num_delims; /* number of delims in aggr */ 113 1.2.2.2 mjf uint8_t rs_flags; /* misc flags */ 114 1.2.2.2 mjf uint32_t rs_evm0; /* evm bytes */ 115 1.2.2.2 mjf uint32_t rs_evm1; 116 1.2.2.2 mjf uint32_t rs_evm2; 117 1.2.2.2 mjf #endif /* AH_SUPPORT_AR5416 */ 118 1.2.2.2 mjf }; 119 1.2.2.2 mjf 120 1.2.2.2 mjf /* bits found in rs_status */ 121 1.2.2.2 mjf #define HAL_RXERR_CRC 0x01 /* CRC error on frame */ 122 1.2.2.2 mjf #define HAL_RXERR_PHY 0x02 /* PHY error, rs_phyerr is valid */ 123 1.2.2.2 mjf #define HAL_RXERR_FIFO 0x04 /* fifo overrun */ 124 1.2.2.2 mjf #define HAL_RXERR_DECRYPT 0x08 /* non-Michael decrypt error */ 125 1.2.2.2 mjf #define HAL_RXERR_MIC 0x10 /* Michael MIC decrypt error */ 126 1.2.2.2 mjf 127 1.2.2.2 mjf /* bits found in rs_flags */ 128 1.2.2.2 mjf #define HAL_RX_MORE 0x01 /* more descriptors follow */ 129 1.2.2.2 mjf #define HAL_RX_MORE_AGGR 0x02 /* more frames in aggr */ 130 1.2.2.2 mjf #define HAL_RX_GI 0x04 /* full gi */ 131 1.2.2.2 mjf #define HAL_RX_2040 0x08 /* 40 Mhz */ 132 1.2.2.2 mjf #define HAL_RX_DELIM_CRC_PRE 0x10 /* crc error in delimiter pre */ 133 1.2.2.2 mjf #define HAL_RX_DELIM_CRC_POST 0x20 /* crc error in delim after */ 134 1.2.2.2 mjf #define HAL_RX_DECRYPT_BUSY 0x40 /* decrypt was too slow */ 135 1.2.2.2 mjf #define HAL_RX_HI_RX_CHAIN 0x80 /* SM power save: hi Rx chain control */ 136 1.2.2.2 mjf 137 1.2.2.2 mjf enum { 138 1.2.2.2 mjf HAL_PHYERR_UNDERRUN = 0, /* Transmit underrun */ 139 1.2.2.2 mjf HAL_PHYERR_TIMING = 1, /* Timing error */ 140 1.2.2.2 mjf HAL_PHYERR_PARITY = 2, /* Illegal parity */ 141 1.2.2.2 mjf HAL_PHYERR_RATE = 3, /* Illegal rate */ 142 1.2.2.2 mjf HAL_PHYERR_LENGTH = 4, /* Illegal length */ 143 1.2.2.2 mjf HAL_PHYERR_RADAR = 5, /* Radar detect */ 144 1.2.2.2 mjf HAL_PHYERR_SERVICE = 6, /* Illegal service */ 145 1.2.2.2 mjf HAL_PHYERR_TOR = 7, /* Transmit override receive */ 146 1.2.2.2 mjf /* NB: these are specific to the 5212 */ 147 1.2.2.2 mjf HAL_PHYERR_OFDM_TIMING = 17, /* */ 148 1.2.2.2 mjf HAL_PHYERR_OFDM_SIGNAL_PARITY = 18, /* */ 149 1.2.2.2 mjf HAL_PHYERR_OFDM_RATE_ILLEGAL = 19, /* */ 150 1.2.2.2 mjf HAL_PHYERR_OFDM_LENGTH_ILLEGAL = 20, /* */ 151 1.2.2.2 mjf HAL_PHYERR_OFDM_POWER_DROP = 21, /* */ 152 1.2.2.2 mjf HAL_PHYERR_OFDM_SERVICE = 22, /* */ 153 1.2.2.2 mjf HAL_PHYERR_OFDM_RESTART = 23, /* */ 154 1.2.2.2 mjf HAL_PHYERR_CCK_TIMING = 25, /* */ 155 1.2.2.2 mjf HAL_PHYERR_CCK_HEADER_CRC = 26, /* */ 156 1.2.2.2 mjf HAL_PHYERR_CCK_RATE_ILLEGAL = 27, /* */ 157 1.2.2.2 mjf HAL_PHYERR_CCK_SERVICE = 30, /* */ 158 1.2.2.2 mjf HAL_PHYERR_CCK_RESTART = 31, /* */ 159 1.2.2.2 mjf }; 160 1.2.2.2 mjf 161 1.2.2.2 mjf /* value found in rs_keyix to mark invalid entries */ 162 1.2.2.2 mjf #define HAL_RXKEYIX_INVALID ((uint8_t) -1) 163 1.2.2.2 mjf /* value used to specify no encryption key for xmit */ 164 1.2.2.2 mjf #define HAL_TXKEYIX_INVALID ((u_int) -1) 165 1.2.2.2 mjf 166 1.2.2.2 mjf /* XXX rs_antenna definitions */ 167 1.2.2.2 mjf 168 1.2.2.2 mjf /* 169 1.2.2.2 mjf * Definitions for the software frame/packet descriptors used by 170 1.2.2.2 mjf * the Atheros HAL. This definition obscures hardware-specific 171 1.2.2.2 mjf * details from the driver. Drivers are expected to fillin the 172 1.2.2.2 mjf * portions of a descriptor that are not opaque then use HAL calls 173 1.2.2.2 mjf * to complete the work. Status for completed frames is returned 174 1.2.2.2 mjf * in a device-independent format. 175 1.2.2.2 mjf */ 176 1.2.2.2 mjf #ifdef AH_SUPPORT_AR5416 177 1.2.2.2 mjf #define HAL_DESC_HW_SIZE 20 178 1.2.2.2 mjf #else 179 1.2.2.2 mjf #define HAL_DESC_HW_SIZE 4 180 1.2.2.2 mjf #endif /* AH_SUPPORT_AR5416 */ 181 1.2.2.2 mjf 182 1.2.2.2 mjf struct ath_desc { 183 1.2.2.2 mjf /* 184 1.2.2.2 mjf * The following definitions are passed directly 185 1.2.2.2 mjf * the hardware and managed by the HAL. Drivers 186 1.2.2.2 mjf * should not touch those elements marked opaque. 187 1.2.2.2 mjf */ 188 1.2.2.2 mjf uint32_t ds_link; /* phys address of next descriptor */ 189 1.2.2.2 mjf uint32_t ds_data; /* phys address of data buffer */ 190 1.2.2.2 mjf uint32_t ds_ctl0; /* opaque DMA control 0 */ 191 1.2.2.2 mjf uint32_t ds_ctl1; /* opaque DMA control 1 */ 192 1.2.2.2 mjf uint32_t ds_hw[HAL_DESC_HW_SIZE]; /* opaque h/w region */ 193 1.2.2.2 mjf union { 194 1.2.2.2 mjf struct ath_tx_status tx;/* xmit status */ 195 1.2.2.2 mjf struct ath_rx_status rx;/* recv status */ 196 1.2.2.2 mjf } ds_us; 197 1.2.2.2 mjf }; 198 1.2.2.2 mjf 199 1.2.2.2 mjf #define ds_txstat ds_us.tx 200 1.2.2.2 mjf #define ds_rxstat ds_us.rx 201 1.2.2.2 mjf 202 1.2.2.2 mjf /* flags passed to tx descriptor setup methods */ 203 1.2.2.2 mjf #define HAL_TXDESC_CLRDMASK 0x0001 /* clear destination filter mask */ 204 1.2.2.2 mjf #define HAL_TXDESC_NOACK 0x0002 /* don't wait for ACK */ 205 1.2.2.2 mjf #define HAL_TXDESC_RTSENA 0x0004 /* enable RTS */ 206 1.2.2.2 mjf #define HAL_TXDESC_CTSENA 0x0008 /* enable CTS */ 207 1.2.2.2 mjf #define HAL_TXDESC_INTREQ 0x0010 /* enable per-descriptor interrupt */ 208 1.2.2.2 mjf #define HAL_TXDESC_VEOL 0x0020 /* mark virtual EOL */ 209 1.2.2.2 mjf /* NB: this only affects frame, not any RTS/CTS */ 210 1.2.2.2 mjf #define HAL_TXDESC_DURENA 0x0040 /* enable h/w write of duration field */ 211 1.2.2.2 mjf #define HAL_TXDESC_EXT_ONLY 0x0080 /* send on ext channel only (11n) */ 212 1.2.2.2 mjf #define HAL_TXDESC_EXT_AND_CTL 0x0100 /* send on ext + ctl channels (11n) */ 213 1.2.2.2 mjf #define HAL_TXDESC_VMF 0x0200 /* virtual more frag */ 214 1.2.2.2 mjf 215 1.2.2.2 mjf /* flags passed to rx descriptor setup methods */ 216 1.2.2.2 mjf #define HAL_RXDESC_INTREQ 0x0020 /* enable per-descriptor interrupt */ 217 1.2.2.2 mjf #endif /* _DEV_ATH_DESC_H */ 218
Indexes created Fri Oct 31 11:10:07 GMT 2025