ah_internal.h revision 1.5
1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $Id: ah_internal.h,v 1.5 2011/02/20 11:21:02 jmcneill Exp $ 18 */ 19 #ifndef _ATH_AH_INTERAL_H_ 20 #define _ATH_AH_INTERAL_H_ 21 /* 22 * Atheros Device Hardware Access Layer (HAL). 23 * 24 * Internal definitions. 25 */ 26 #define AH_NULL 0 27 #define AH_MIN(a,b) ((a)<(b)?(a):(b)) 28 #define AH_MAX(a,b) ((a)>(b)?(a):(b)) 29 30 #ifndef NBBY 31 #define NBBY 8 /* number of bits/byte */ 32 #endif 33 34 #ifndef roundup 35 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ 36 #endif 37 #ifndef howmany 38 #define howmany(x, y) (((x)+((y)-1))/(y)) 39 #endif 40 41 #ifndef offsetof 42 #define offsetof(type, field) ((size_t)(&((type *)0)->field)) 43 #endif 44 45 /* 46 * Remove const in a way that keeps the compiler happy. 47 * This works for gcc but may require other magic for 48 * other compilers (not sure where this should reside). 49 * Note that uintptr_t is C99. 50 */ 51 #ifndef __DECONST 52 #define __DECONST(type, var) ((type)(unsigned long)(const void *)(var)) 53 #endif 54 55 typedef struct { 56 uint16_t start; /* first register */ 57 uint16_t end; /* ending register or zero */ 58 } HAL_REGRANGE; 59 60 /* 61 * Transmit power scale factor. 62 * 63 * NB: This is not public because we want to discourage the use of 64 * scaling; folks should use the tx power limit interface. 65 */ 66 typedef enum { 67 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ 68 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */ 69 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */ 70 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */ 71 HAL_TP_SCALE_MIN = 4, /* min, but still on */ 72 } HAL_TP_SCALE; 73 74 typedef enum { 75 HAL_CAP_RADAR = 0, /* Radar capability */ 76 HAL_CAP_AR = 1, /* AR capability */ 77 } HAL_PHYDIAG_CAPS; 78 79 /* 80 * Each chip or class of chips registers to offer support. 81 */ 82 struct ath_hal_chip { 83 const char *name; 84 const char *(*probe)(uint16_t vendorid, uint16_t devid); 85 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC, 86 HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *error); 87 }; 88 #ifndef AH_CHIP 89 #define AH_CHIP(_name, _probe, _attach) \ 90 static struct ath_hal_chip name##_chip = { \ 91 .name = #_name, \ 92 .probe = _probe, \ 93 .attach = _attach \ 94 }; \ 95 OS_DATA_SET(ah_chips, name##_chip) 96 #endif 97 98 /* 99 * Each RF backend registers to offer support; this is mostly 100 * used by multi-chip 5212 solutions. Single-chip solutions 101 * have a fixed idea about which RF to use. 102 */ 103 struct ath_hal_rf { 104 const char *name; 105 HAL_BOOL (*probe)(struct ath_hal *ah); 106 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode); 107 }; 108 #ifndef AH_RF 109 #define AH_RF(_name, _probe, _attach) \ 110 static struct ath_hal_rf _name##_rf = { \ 111 .name = __STRING(_name), \ 112 .probe = _probe, \ 113 .attach = _attach \ 114 }; \ 115 OS_DATA_SET(ah_rfs, _name##_rf) 116 #endif 117 118 struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode); 119 120 /* 121 * Internal form of a HAL_CHANNEL. Note that the structure 122 * must be defined such that you can cast references to a 123 * HAL_CHANNEL so don't shuffle the first two members. 124 */ 125 typedef struct { 126 uint32_t channelFlags; 127 uint16_t channel; /* NB: must be first for casting */ 128 uint8_t privFlags; 129 int8_t maxRegTxPower; 130 int8_t maxTxPower; 131 int8_t minTxPower; /* as above... */ 132 133 HAL_BOOL bssSendHere; 134 uint8_t gainI; 135 HAL_BOOL iqCalValid; 136 uint8_t calValid; /* bitmask of cal types */ 137 int8_t iCoff; 138 int8_t qCoff; 139 int16_t rawNoiseFloor; 140 int16_t noiseFloorAdjust; 141 int8_t antennaMax; 142 uint32_t regDmnFlags; /* Flags for channel use in reg */ 143 uint32_t conformanceTestLimit; /* conformance test limit from reg domain */ 144 uint16_t mainSpur; /* cached spur value for this cahnnel */ 145 } HAL_CHANNEL_INTERNAL; 146 147 typedef struct { 148 uint32_t halChanSpreadSupport : 1, 149 halSleepAfterBeaconBroken : 1, 150 halCompressSupport : 1, 151 halBurstSupport : 1, 152 halFastFramesSupport : 1, 153 halChapTuningSupport : 1, 154 halTurboGSupport : 1, 155 halTurboPrimeSupport : 1, 156 halMicAesCcmSupport : 1, 157 halMicCkipSupport : 1, 158 halMicTkipSupport : 1, 159 halTkipMicTxRxKeySupport : 1, 160 halCipherAesCcmSupport : 1, 161 halCipherCkipSupport : 1, 162 halCipherTkipSupport : 1, 163 halPSPollBroken : 1, 164 halVEOLSupport : 1, 165 halBssIdMaskSupport : 1, 166 halMcastKeySrchSupport : 1, 167 halTsfAddSupport : 1, 168 halChanHalfRate : 1, 169 halChanQuarterRate : 1, 170 halHTSupport : 1, 171 halRfSilentSupport : 1, 172 halHwPhyCounterSupport : 1, 173 halWowSupport : 1, 174 halWowMatchPatternExact : 1, 175 halAutoSleepSupport : 1, 176 halFastCCSupport : 1, 177 halBtCoexSupport : 1; 178 uint32_t halRxStbcSupport : 1, 179 halTxStbcSupport : 1, 180 halGTTSupport : 1, 181 halCSTSupport : 1, 182 halRifsRxSupport : 1, 183 halRifsTxSupport : 1, 184 halExtChanDfsSupport : 1, 185 halForcePpmSupport : 1, 186 halEnhancedPmSupport : 1, 187 halMbssidAggrSupport : 1; 188 uint32_t halWirelessModes; 189 uint16_t halTotalQueues; 190 uint16_t halKeyCacheSize; 191 uint16_t halLow5GhzChan, halHigh5GhzChan; 192 uint16_t halLow2GhzChan, halHigh2GhzChan; 193 int halTstampPrecision; 194 int halRtsAggrLimit; 195 uint8_t halTxChainMask; 196 uint8_t halRxChainMask; 197 uint8_t halNumGpioPins; 198 uint8_t halNumAntCfg2GHz; 199 uint8_t halNumAntCfg5GHz; 200 } HAL_CAPABILITIES; 201 202 /* 203 * The ``private area'' follows immediately after the ``public area'' 204 * in the data structure returned by ath_hal_attach. Private data are 205 * used by device-independent code such as the regulatory domain support. 206 * In general, code within the HAL should never depend on data in the 207 * public area. Instead any public data needed internally should be 208 * shadowed here. 209 * 210 * When declaring a device-specific ath_hal data structure this structure 211 * is assumed to at the front; e.g. 212 * 213 * struct ath_hal_5212 { 214 * struct ath_hal_private ah_priv; 215 * ... 216 * }; 217 * 218 * It might be better to manage the method pointers in this structure 219 * using an indirect pointer to a read-only data structure but this would 220 * disallow class-style method overriding. 221 */ 222 struct ath_hal_private { 223 struct ath_hal h; /* public area */ 224 225 /* NB: all methods go first to simplify initialization */ 226 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*, 227 uint16_t channelFlags, 228 uint16_t *lowChannel, uint16_t *highChannel); 229 u_int (*ah_getWirelessModes)(struct ath_hal*); 230 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off, 231 uint16_t *data); 232 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off, 233 uint16_t data); 234 HAL_BOOL (*ah_gpioCfgOutput)(struct ath_hal *, uint32_t gpio); 235 HAL_BOOL (*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 236 uint32_t (*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 237 HAL_BOOL (*ah_gpioSet)(struct ath_hal *, 238 uint32_t gpio, uint32_t val); 239 void (*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 240 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *, 241 HAL_CHANNEL *, uint32_t); 242 int16_t (*ah_getNfAdjust)(struct ath_hal *, 243 const HAL_CHANNEL_INTERNAL*); 244 void (*ah_getNoiseFloor)(struct ath_hal *, 245 int16_t nfarray[]); 246 247 void *ah_eeprom; /* opaque EEPROM state */ 248 uint16_t ah_eeversion; /* EEPROM version */ 249 void (*ah_eepromDetach)(struct ath_hal *); 250 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *); 251 HAL_BOOL (*ah_eepromSet)(struct ath_hal *, int, int); 252 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL); 253 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request, 254 const void *args, uint32_t argsize, 255 void **result, uint32_t *resultsize); 256 257 /* 258 * Device revision information. 259 */ 260 uint16_t ah_devid; /* PCI device ID */ 261 uint16_t ah_subvendorid; /* PCI subvendor ID */ 262 uint32_t ah_macVersion; /* MAC version id */ 263 uint16_t ah_macRev; /* MAC revision */ 264 uint16_t ah_phyRev; /* PHY revision */ 265 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 266 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 267 uint8_t ah_ispcie; /* PCIE, special treatment */ 268 269 270 HAL_OPMODE ah_opmode; /* operating mode from reset */ 271 HAL_CAPABILITIES ah_caps; /* device capabilities */ 272 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */ 273 int16_t ah_powerLimit; /* tx power cap */ 274 uint16_t ah_maxPowerLevel; /* calculated max tx power */ 275 u_int ah_tpScale; /* tx power scale factor */ 276 uint32_t ah_11nCompat; /* 11n compat controls */ 277 278 /* 279 * State for regulatory domain handling. 280 */ 281 HAL_REG_DOMAIN ah_currentRD; /* Current regulatory domain */ 282 HAL_CTRY_CODE ah_countryCode; /* current country code */ 283 HAL_CHANNEL_INTERNAL ah_channels[256]; /* calculated channel list */ 284 u_int ah_nchan; /* valid channels in list */ 285 HAL_CHANNEL_INTERNAL *ah_curchan; /* current channel */ 286 287 uint8_t ah_coverageClass; /* coverage class */ 288 HAL_BOOL ah_regdomainUpdate; /* regdomain is updated? */ 289 /* 290 * RF Silent handling; setup according to the EEPROM. 291 */ 292 uint16_t ah_rfsilent; /* GPIO pin + polarity */ 293 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */ 294 /* 295 * Diagnostic support for discriminating HIUERR reports. 296 */ 297 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */ 298 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */ 299 }; 300 301 #define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) 302 303 #define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \ 304 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc) 305 #define ath_hal_getWirelessModes(_ah) \ 306 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah) 307 #define ath_hal_eepromRead(_ah, _off, _data) \ 308 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data) 309 #define ath_hal_eepromWrite(_ah, _off, _data) \ 310 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data) 311 #define ath_hal_gpioCfgOutput(_ah, _gpio) \ 312 AH_PRIVATE(_ah)->ah_gpioCfgOutput(_ah, _gpio) 313 #define ath_hal_gpioCfgInput(_ah, _gpio) \ 314 AH_PRIVATE(_ah)->ah_gpioCfgInput(_ah, _gpio) 315 #define ath_hal_gpioGet(_ah, _gpio) \ 316 AH_PRIVATE(_ah)->ah_gpioGet(_ah, _gpio) 317 #define ath_hal_gpioSet(_ah, _gpio, _val) \ 318 AH_PRIVATE(_ah)->ah_gpioGet(_ah, _gpio, _val) 319 #define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \ 320 AH_PRIVATE(_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel) 321 #define ath_hal_getpowerlimits(_ah, _chans, _nchan) \ 322 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chans, _nchan) 323 #define ath_hal_getNfAdjust(_ah, _c) \ 324 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) 325 #define ath_hal_getNoiseFloor(_ah, _nfArray) \ 326 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) 327 #define ath_hal_configPCIE(_ah, _reset) \ 328 (_ah)->ah_configPCIE(_ah, _reset) 329 #define ath_hal_disablePCIE(_ah) \ 330 (_ah)->ah_disablePCIE(_ah) 331 332 #define ath_hal_eepromDetach(_ah) \ 333 do { \ 334 if (AH_PRIVATE(_ah)->ah_eepromDetach != NULL) \ 335 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \ 336 } while (/*CONSTCOND*/0) 337 #define ath_hal_eepromGet(_ah, _param, _val) \ 338 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val) 339 #define ath_hal_eepromSet(_ah, _param, _val) \ 340 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val) 341 #define ath_hal_eepromGetFlag(_ah, _param) \ 342 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK) 343 #define ath_hal_getSpurChan(_ah, _ix, _is2G) \ 344 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G) 345 #define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \ 346 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) 347 348 #if !defined(_NET_IF_IEEE80211_H_) && !defined(_NET80211__IEEE80211_H_) 349 /* 350 * Stuff that would naturally come from _ieee80211.h 351 */ 352 #define IEEE80211_ADDR_LEN 6 353 354 #define IEEE80211_WEP_KEYLEN 5 /* 40bit */ 355 #define IEEE80211_WEP_IVLEN 3 /* 24bit */ 356 #define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ 357 #define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ 358 359 #define IEEE80211_CRC_LEN 4 360 361 #define IEEE80211_MTU 1500 362 #define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ 363 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) 364 365 enum { 366 IEEE80211_T_DS, /* direct sequence spread spectrum */ 367 IEEE80211_T_FH, /* frequency hopping */ 368 IEEE80211_T_OFDM, /* frequency division multiplexing */ 369 IEEE80211_T_TURBO, /* high rate DS */ 370 IEEE80211_T_HT, /* HT - full GI */ 371 }; 372 #define IEEE80211_T_CCK IEEE80211_T_DS /* more common nomenclatur */ 373 #endif /* _NET_IF_IEEE80211_H_ */ 374 375 /* NB: these are defined privately until XR support is announced */ 376 enum { 377 ATHEROS_T_XR = IEEE80211_T_HT+1, /* extended range */ 378 }; 379 380 #define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 381 382 #define INIT_AIFS 2 383 #define INIT_CWMIN 15 384 #define INIT_CWMIN_11B 31 385 #define INIT_CWMAX 1023 386 #define INIT_SH_RETRY 10 387 #define INIT_LG_RETRY 10 388 #define INIT_SSH_RETRY 32 389 #define INIT_SLG_RETRY 32 390 391 typedef struct { 392 uint32_t tqi_ver; /* HAL TXQ verson */ 393 HAL_TX_QUEUE tqi_type; /* hw queue type*/ 394 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */ 395 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */ 396 uint32_t tqi_priority; 397 uint32_t tqi_aifs; /* aifs */ 398 uint32_t tqi_cwmin; /* cwMin */ 399 uint32_t tqi_cwmax; /* cwMax */ 400 uint16_t tqi_shretry; /* frame short retry limit */ 401 uint16_t tqi_lgretry; /* frame long retry limit */ 402 uint32_t tqi_cbrPeriod; 403 uint32_t tqi_cbrOverflowLimit; 404 uint32_t tqi_burstTime; 405 uint32_t tqi_readyTime; 406 uint32_t tqi_physCompBuf; 407 uint32_t tqi_intFlags; /* flags for internal use */ 408 } HAL_TX_QUEUE_INFO; 409 410 extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah, 411 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo); 412 extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah, 413 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi); 414 415 typedef enum { 416 HAL_ANI_PRESENT, /* is ANI support present */ 417 HAL_ANI_NOISE_IMMUNITY_LEVEL, /* set level */ 418 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, /* enable/disable */ 419 HAL_ANI_CCK_WEAK_SIGNAL_THR, /* enable/disable */ 420 HAL_ANI_FIRSTEP_LEVEL, /* set level */ 421 HAL_ANI_SPUR_IMMUNITY_LEVEL, /* set level */ 422 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 423 HAL_ANI_PHYERR_RESET, /* reset phy error stats */ 424 } HAL_ANI_CMD; 425 426 #define HAL_SPUR_VAL_MASK 0x3FFF 427 #define HAL_SPUR_CHAN_WIDTH 87 428 #define HAL_BIN_WIDTH_BASE_100HZ 3125 429 #define HAL_BIN_WIDTH_TURBO_100HZ 6250 430 #define HAL_MAX_BINS_ALLOWED 28 431 432 /* 433 * A = 5GHZ|OFDM 434 * T = 5GHZ|OFDM|TURBO 435 * 436 * IS_CHAN_A(T) will return TRUE. This is probably 437 * not the default behavior we want. We should migrate to a better mask -- 438 * perhaps CHANNEL_ALL. 439 * 440 * For now, IS_CHAN_G() masks itself with CHANNEL_108G. 441 * 442 */ 443 444 #define IS_CHAN_A(_c) (((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) 445 #define IS_CHAN_B(_c) (((_c)->channelFlags & CHANNEL_B) == CHANNEL_B) 446 #define IS_CHAN_G(_c) (((_c)->channelFlags & (CHANNEL_108G|CHANNEL_G)) == CHANNEL_G) 447 #define IS_CHAN_108G(_c)(((_c)->channelFlags & CHANNEL_108G) == CHANNEL_108G) 448 #define IS_CHAN_T(_c) (((_c)->channelFlags & CHANNEL_T) == CHANNEL_T) 449 #define IS_CHAN_PUREG(_c) \ 450 (((_c)->channelFlags & CHANNEL_PUREG) == CHANNEL_PUREG) 451 452 #define IS_CHAN_TURBO(_c) (((_c)->channelFlags & CHANNEL_TURBO) != 0) 453 #define IS_CHAN_CCK(_c) (((_c)->channelFlags & CHANNEL_CCK) != 0) 454 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) 455 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) 456 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) 457 #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0) 458 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) 459 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) 460 461 #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 462 463 #define CHANNEL_HT40 (CHANNEL_HT40PLUS | CHANNEL_HT40MINUS) 464 #define CHANNEL_HT (CHANNEL_HT20 | CHANNEL_HT40) 465 #define IS_CHAN_HT(_c) (((_c)->channelFlags & CHANNEL_HT) != 0) 466 #define IS_CHAN_HT20(_c) (((_c)->channelFlags & CHANNEL_HT) == CHANNEL_HT20) 467 #define IS_CHAN_HT40(_c) (((_c)->channelFlags & CHANNEL_HT40) != 0) 468 469 /* 470 * Deduce if the host cpu has big- or litt-endian byte order. 471 */ 472 static __inline__ int 473 isBigEndian(void) 474 { 475 union { 476 int32_t i; 477 char c[4]; 478 } u; 479 u.i = 1; 480 return (u.c[0] == 0); 481 } 482 483 /* unalligned little endian access */ 484 #define LE_READ_2(p) \ 485 ((uint16_t) \ 486 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8))) 487 #define LE_READ_4(p) \ 488 ((uint32_t) \ 489 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\ 490 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24))) 491 492 /* 493 * Register manipulation macros that expect bit field defines 494 * to follow the convention that an _S suffix is appended for 495 * a shift count, while the field mask has no suffix. 496 */ 497 #define SM(_v, _f) (((_v) << _f##_S) & (_f)) 498 #define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 499 #define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ 500 OS_REG_WRITE(_a, _r, \ 501 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) 502 #define OS_REG_SET_BIT(_a, _r, _f) \ 503 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f)) 504 #define OS_REG_CLR_BIT(_a, _r, _f) \ 505 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f)) 506 507 /* 508 * Regulatory domain support. 509 */ 510 511 /* 512 * Return the max allowed antenna gain based on the current 513 * regulatory domain. 514 */ 515 extern u_int ath_hal_getantennareduction(struct ath_hal *, 516 HAL_CHANNEL *, u_int twiceGain); 517 /* 518 * Return the test group for the specific channel based on 519 * the current regulator domain. 520 */ 521 extern u_int ath_hal_getctl(struct ath_hal *, HAL_CHANNEL *); 522 /* 523 * Return whether or not a noise floor check is required 524 * based on the current regulatory domain for the specified 525 * channel. 526 */ 527 extern HAL_BOOL ath_hal_getnfcheckrequired(struct ath_hal *, HAL_CHANNEL *); 528 529 /* 530 * Map a public channel definition to the corresponding 531 * internal data structure. This implicitly specifies 532 * whether or not the specified channel is ok to use 533 * based on the current regulatory domain constraints. 534 */ 535 extern HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *, 536 const HAL_CHANNEL *); 537 538 /* system-configurable parameters */ 539 extern int ath_hal_dma_beacon_response_time; /* in TU's */ 540 extern int ath_hal_sw_beacon_response_time; /* in TU's */ 541 extern int ath_hal_additional_swba_backoff; /* in TU's */ 542 543 /* wait for the register contents to have the specified value */ 544 extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg, 545 uint32_t mask, uint32_t val); 546 547 /* return the first n bits in val reversed */ 548 extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n); 549 550 /* printf interfaces */ 551 extern void ath_hal_printf(struct ath_hal *, const char*, ...) 552 __printflike(2,3); 553 extern void ath_hal_vprintf(struct ath_hal *, const char*, va_list) 554 __printflike(2, 0); 555 extern const char* ath_hal_ether_sprintf(const uint8_t *mac); 556 557 /* allocate and free memory */ 558 extern void *ath_hal_malloc(size_t); 559 extern void ath_hal_free(void *); 560 561 /* common debugging interfaces */ 562 #ifdef AH_DEBUG 563 #include "ah_debug.h" 564 extern int ath_hal_debug; 565 extern void HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...) 566 __printflike(3,4); 567 #else 568 #define HALDEBUG(_ah, __m, _fmt, ...) 569 #endif /* AH_DEBUG */ 570 571 /* 572 * Register logging definitions shared with ardecode. 573 */ 574 #include "ah_decode.h" 575 576 /* 577 * Common assertion interface. Note: it is a bad idea to generate 578 * an assertion failure for any recoverable event. Instead catch 579 * the violation and, if possible, fix it up or recover from it; either 580 * with an error return value or a diagnostic messages. System software 581 * does not panic unless the situation is hopeless. 582 */ 583 #ifdef AH_ASSERT 584 extern void ath_hal_assert_failed(const char* filename, 585 int lineno, const char* msg); 586 587 #define HALASSERT(_x) do { \ 588 if (!(_x)) { \ 589 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \ 590 } \ 591 } while (0) 592 #else 593 #define HALASSERT(_x) 594 #endif /* AH_ASSERT */ 595 596 /* 597 * Return the h/w frequency for a channel. This may be 598 * different from ic_freq if this is a GSM device that 599 * takes 2.4GHz frequencies and down-converts them. 600 */ 601 static OS_INLINE uint16_t 602 ath_hal_gethwchannel(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c) 603 { 604 return ath_hal_checkchannel(ah, (const HAL_CHANNEL *)c)->channel; 605 } 606 607 /* 608 * Convert between microseconds and core system clocks. 609 */ 610 extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs); 611 extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks); 612 613 /* 614 * Generic get/set capability support. Each chip overrides 615 * this routine to support chip-specific capabilities. 616 */ 617 extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, 618 HAL_CAPABILITY_TYPE type, uint32_t capability, 619 uint32_t *result); 620 extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, 621 HAL_CAPABILITY_TYPE type, uint32_t capability, 622 uint32_t setting, HAL_STATUS *status); 623 624 /* 625 * Diagnostic interface. This is an open-ended interface that 626 * is opaque to applications. Diagnostic programs use this to 627 * retrieve internal data structures, etc. There is no guarantee 628 * that calling conventions for calls other than HAL_DIAG_REVS 629 * are stable between HAL releases; a diagnostic application must 630 * use the HAL revision information to deal with ABI/API differences. 631 * 632 * NB: do not renumber these, certain codes are publicly used. 633 */ 634 enum { 635 HAL_DIAG_REVS = 0, /* MAC/PHY/Radio revs */ 636 HAL_DIAG_EEPROM = 1, /* EEPROM contents */ 637 HAL_DIAG_EEPROM_EXP_11A = 2, /* EEPROM 5112 power exp for 11a */ 638 HAL_DIAG_EEPROM_EXP_11B = 3, /* EEPROM 5112 power exp for 11b */ 639 HAL_DIAG_EEPROM_EXP_11G = 4, /* EEPROM 5112 power exp for 11g */ 640 HAL_DIAG_ANI_CURRENT = 5, /* ANI current channel state */ 641 HAL_DIAG_ANI_OFDM = 6, /* ANI OFDM timing error stats */ 642 HAL_DIAG_ANI_CCK = 7, /* ANI CCK timing error stats */ 643 HAL_DIAG_ANI_STATS = 8, /* ANI statistics */ 644 HAL_DIAG_RFGAIN = 9, /* RfGain GAIN_VALUES */ 645 HAL_DIAG_RFGAIN_CURSTEP = 10, /* RfGain GAIN_OPTIMIZATION_STEP */ 646 HAL_DIAG_PCDAC = 11, /* PCDAC table */ 647 HAL_DIAG_TXRATES = 12, /* Transmit rate table */ 648 HAL_DIAG_REGS = 13, /* Registers */ 649 HAL_DIAG_ANI_CMD = 14, /* ANI issue command (XXX do not change!) */ 650 HAL_DIAG_SETKEY = 15, /* Set keycache backdoor */ 651 HAL_DIAG_RESETKEY = 16, /* Reset keycache backdoor */ 652 HAL_DIAG_EEREAD = 17, /* Read EEPROM word */ 653 HAL_DIAG_EEWRITE = 18, /* Write EEPROM word */ 654 /* 19 was HAL_DIAG_TXCONT, 20-23 were for radar */ 655 HAL_DIAG_REGREAD = 24, /* Reg reads */ 656 HAL_DIAG_REGWRITE = 25, /* Reg writes */ 657 HAL_DIAG_GET_REGBASE = 26, /* Get register base */ 658 HAL_DIAG_RDWRITE = 27, /* Write regulatory domain */ 659 HAL_DIAG_RDREAD = 28, /* Get regulatory domain */ 660 HAL_DIAG_FATALERR = 29, /* Read cached interrupt state */ 661 HAL_DIAG_11NCOMPAT = 30, /* 11n compatibility tweaks */ 662 HAL_DIAG_ANI_PARAMS = 31, /* ANI noise immunity parameters */ 663 HAL_DIAG_CHECK_HANGS = 32, /* check h/w hangs */ 664 }; 665 666 enum { 667 HAL_BB_HANG_DFS = 0x0001, 668 HAL_BB_HANG_RIFS = 0x0002, 669 HAL_BB_HANG_RX_CLEAR = 0x0004, 670 HAL_BB_HANG_UNKNOWN = 0x0080, 671 672 HAL_MAC_HANG_SIG1 = 0x0100, 673 HAL_MAC_HANG_SIG2 = 0x0200, 674 HAL_MAC_HANG_UNKNOWN = 0x8000, 675 676 HAL_BB_HANGS = HAL_BB_HANG_DFS 677 | HAL_BB_HANG_RIFS 678 | HAL_BB_HANG_RX_CLEAR 679 | HAL_BB_HANG_UNKNOWN, 680 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1 681 | HAL_MAC_HANG_SIG2 682 | HAL_MAC_HANG_UNKNOWN, 683 }; 684 685 /* 686 * Device revision information. 687 */ 688 typedef struct { 689 uint16_t ah_devid; /* PCI device ID */ 690 uint16_t ah_subvendorid; /* PCI subvendor ID */ 691 uint32_t ah_macVersion; /* MAC version id */ 692 uint16_t ah_macRev; /* MAC revision */ 693 uint16_t ah_phyRev; /* PHY revision */ 694 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */ 695 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */ 696 } HAL_REVS; 697 698 /* 699 * Argument payload for HAL_DIAG_SETKEY. 700 */ 701 typedef struct { 702 HAL_KEYVAL dk_keyval; 703 uint16_t dk_keyix; /* key index */ 704 uint8_t dk_mac[IEEE80211_ADDR_LEN]; 705 int dk_xor; /* XOR key data */ 706 } HAL_DIAG_KEYVAL; 707 708 /* 709 * Argument payload for HAL_DIAG_EEWRITE. 710 */ 711 typedef struct { 712 uint16_t ee_off; /* eeprom offset */ 713 uint16_t ee_data; /* write data */ 714 } HAL_DIAG_EEVAL; 715 716 717 typedef struct { 718 u_int offset; /* reg offset */ 719 uint32_t val; /* reg value */ 720 } HAL_DIAG_REGVAL; 721 722 /* 723 * 11n compatibility tweaks. 724 */ 725 #define HAL_DIAG_11N_SERVICES 0x00000003 726 #define HAL_DIAG_11N_SERVICES_S 0 727 #define HAL_DIAG_11N_TXSTOMP 0x0000000c 728 #define HAL_DIAG_11N_TXSTOMP_S 2 729 730 typedef struct { 731 int maxNoiseImmunityLevel; /* [0..4] */ 732 int totalSizeDesired[5]; 733 int coarseHigh[5]; 734 int coarseLow[5]; 735 int firpwr[5]; 736 737 int maxSpurImmunityLevel; /* [0..7] */ 738 int cycPwrThr1[8]; 739 740 int maxFirstepLevel; /* [0..2] */ 741 int firstep[3]; 742 743 uint32_t ofdmTrigHigh; 744 uint32_t ofdmTrigLow; 745 int32_t cckTrigHigh; 746 int32_t cckTrigLow; 747 int32_t rssiThrLow; 748 int32_t rssiThrHigh; 749 750 int period; /* update listen period */ 751 } HAL_ANI_PARAMS; 752 753 extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request, 754 const void *args, uint32_t argsize, 755 void **result, uint32_t *resultsize); 756 757 /* 758 * Setup a h/w rate table for use. 759 */ 760 extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt); 761 762 /* 763 * Common routine for implementing getChanNoise api. 764 */ 765 extern int16_t ath_hal_getChanNoise(struct ath_hal *ah, HAL_CHANNEL *chan); 766 767 /* 768 * Initialization support. 769 */ 770 typedef struct { 771 const uint32_t *data; 772 int rows, cols; 773 } HAL_INI_ARRAY; 774 775 #define HAL_INI_INIT(_ia, _data, _cols) do { \ 776 (_ia)->data = (const uint32_t *)(_data); \ 777 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \ 778 (_ia)->cols = (_cols); \ 779 } while (0) 780 #define HAL_INI_VAL(_ia, _r, _c) \ 781 ((_ia)->data[((_r)*(_ia)->cols) + (_c)]) 782 783 /* 784 * OS_DELAY() does a PIO READ on the PCI bus which allows 785 * other cards' DMA reads to complete in the middle of our reset. 786 */ 787 #define DMA_YIELD(x) do { \ 788 if ((++(x) % 64) == 0) \ 789 OS_DELAY(1); \ 790 } while (0) 791 792 #define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \ 793 int r; \ 794 for (r = 0; r < N(regArray); r++) { \ 795 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \ 796 DMA_YIELD(regWr); \ 797 } \ 798 } while (0) 799 800 #define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \ 801 int r; \ 802 for (r = 0; r < N(regArray); r++) { \ 803 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \ 804 DMA_YIELD(regWr); \ 805 } \ 806 } while (0) 807 808 extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 809 int col, int regWr); 810 extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia, 811 int col); 812 extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 813 const uint32_t data[], int regWr); 814 815 #define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ 816 #endif /* _ATH_AH_INTERAL_H_ */ 817
Indexes created Fri Oct 03 02:09:57 GMT 2025