ar5210.h revision 1.2 1 1.1 alc /*
2 1.1 alc * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 1.1 alc * Copyright (c) 2002-2004 Atheros Communications, Inc.
4 1.1 alc *
5 1.1 alc * Permission to use, copy, modify, and/or distribute this software for any
6 1.1 alc * purpose with or without fee is hereby granted, provided that the above
7 1.1 alc * copyright notice and this permission notice appear in all copies.
8 1.1 alc *
9 1.1 alc * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 1.1 alc * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 1.1 alc * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 1.1 alc * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 1.1 alc * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 1.1 alc * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 1.1 alc * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 1.1 alc *
17 1.2 reinoud * $Id: ar5210.h,v 1.2 2009/05/14 09:07:49 reinoud Exp $
18 1.1 alc */
19 1.1 alc #ifndef _ATH_AR5210_H_
20 1.1 alc #define _ATH_AR5210_H_
21 1.1 alc
22 1.1 alc #define AR5210_MAGIC 0x19980124
23 1.1 alc
24 1.1 alc #if 0
25 1.1 alc /*
26 1.1 alc * RTS_ENABLE includes LONG_PKT because they essentially
27 1.1 alc * imply the same thing, and are set or not set together
28 1.1 alc * for this chip
29 1.1 alc */
30 1.1 alc #define AR5210_TXD_CTRL_A_HDR_LEN(_val) (((_val) ) & 0x0003f)
31 1.1 alc #define AR5210_TXD_CTRL_A_TX_RATE(_val) (((_val) << 6) & 0x003c0)
32 1.1 alc #define AR5210_TXD_CTRL_A_RTS_ENABLE ( 0x00c00)
33 1.1 alc #define AR5210_TXD_CTRL_A_CLEAR_DEST_MASK(_val) (((_val) << 12) & 0x01000)
34 1.1 alc #define AR5210_TXD_CTRL_A_ANT_MODE(_val) (((_val) << 13) & 0x02000)
35 1.1 alc #define AR5210_TXD_CTRL_A_PKT_TYPE(_val) (((_val) << 14) & 0x1c000)
36 1.1 alc #define AR5210_TXD_CTRL_A_INT_REQ ( 0x20000)
37 1.1 alc #define AR5210_TXD_CTRL_A_KEY_VALID ( 0x40000)
38 1.1 alc #define AR5210_TXD_CTRL_B_KEY_ID(_val) (((_val) ) & 0x0003f)
39 1.1 alc #define AR5210_TXD_CTRL_B_RTS_DURATION(_val) (((_val) << 6) & 0x7ffc0)
40 1.1 alc #endif
41 1.1 alc
42 1.1 alc #define INIT_CONFIG_STATUS 0x00000000
43 1.1 alc #define INIT_ACKTOPS 0x00000008
44 1.1 alc #define INIT_BCON_CNTRL_REG 0x00000000
45 1.1 alc #define INIT_SLOT_TIME 0x00000168
46 1.1 alc #define INIT_SLOT_TIME_TURBO 0x000001e0 /* More aggressive turbo slot timing = 6 us */
47 1.1 alc #define INIT_ACK_CTS_TIMEOUT 0x04000400
48 1.1 alc #define INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800
49 1.1 alc
50 1.1 alc #define INIT_USEC 0x27
51 1.1 alc #define INIT_USEC_TURBO 0x4f
52 1.1 alc #define INIT_USEC_32 0x1f
53 1.1 alc #define INIT_TX_LATENCY 0x36
54 1.1 alc #define INIT_RX_LATENCY 0x1D
55 1.1 alc #define INIT_TRANSMIT_LATENCY \
56 1.1 alc ((INIT_RX_LATENCY << AR_USEC_RX_LATENCY_S) | \
57 1.1 alc (INIT_TX_LATENCY << AR_USEC_TX_LATENCY_S) | \
58 1.1 alc (INIT_USEC_32 << 7) | INIT_USEC )
59 1.1 alc #define INIT_TRANSMIT_LATENCY_TURBO \
60 1.1 alc ((INIT_RX_LATENCY << AR_USEC_RX_LATENCY_S) | \
61 1.1 alc (INIT_TX_LATENCY << AR_USEC_TX_LATENCY_S) | \
62 1.1 alc (INIT_USEC_32 << 7) | INIT_USEC_TURBO)
63 1.1 alc
64 1.1 alc #define INIT_SIFS 0x230 /* = 16 us - 2 us */
65 1.1 alc #define INIT_SIFS_TURBO 0x1E0 /* More aggressive turbo SIFS timing - 8 us - 2 us */
66 1.1 alc
67 1.1 alc /*
68 1.1 alc * Various fifo fill before Tx start, in 64-byte units
69 1.1 alc * i.e. put the frame in the air while still DMAing
70 1.1 alc */
71 1.1 alc #define MIN_TX_FIFO_THRESHOLD 0x1
72 1.1 alc #define MAX_TX_FIFO_THRESHOLD ((IEEE80211_MAX_LEN / 64) + 1)
73 1.1 alc
74 1.1 alc #define INIT_NEXT_CFP_START 0xffffffff
75 1.1 alc
76 1.1 alc #define INIT_BEACON_PERIOD 0xffff
77 1.1 alc #define INIT_BEACON_EN 0 /* this should be set by AP only when it's ready */
78 1.1 alc #define INIT_BEACON_CONTROL \
79 1.1 alc ((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \
80 1.1 alc (INIT_TIM_OFFSET<<16) | INIT_BEACON_PERIOD)
81 1.1 alc
82 1.1 alc #define INIT_RSSI_THR 0x00000700 /* Missed beacon counter initialized to max value of 7 */
83 1.1 alc #define INIT_ProgIFS 0x398 /* PIFS - 2us */
84 1.1 alc #define INIT_ProgIFS_TURBO 0x3C0
85 1.1 alc #define INIT_EIFS 0xd70
86 1.1 alc #define INIT_EIFS_TURBO 0x1ae0
87 1.1 alc #define INIT_CARR_SENSE_EN 1
88 1.1 alc #define INIT_PROTO_TIME_CNTRL ( (INIT_CARR_SENSE_EN << 26) | (INIT_EIFS << 12) | \
89 1.1 alc (INIT_ProgIFS) )
90 1.1 alc #define INIT_PROTO_TIME_CNTRL_TURBO ( (INIT_CARR_SENSE_EN << 26) | (INIT_EIFS_TURBO << 12) | \
91 1.1 alc (INIT_ProgIFS_TURBO) )
92 1.1 alc
93 1.1 alc #define AR5210_MAX_RATE_POWER 60
94 1.1 alc
95 1.1 alc #undef HAL_NUM_TX_QUEUES /* from ah.h */
96 1.1 alc #define HAL_NUM_TX_QUEUES 3
97 1.1 alc
98 1.1 alc struct ath_hal_5210 {
99 1.1 alc struct ath_hal_private ah_priv; /* base definitions */
100 1.1 alc
101 1.1 alc uint8_t ah_macaddr[IEEE80211_ADDR_LEN];
102 1.1 alc /*
103 1.1 alc * Runtime state.
104 1.1 alc */
105 1.1 alc uint32_t ah_maskReg; /* shadow of IMR+IER regs */
106 1.1 alc uint32_t ah_txOkInterruptMask;
107 1.1 alc uint32_t ah_txErrInterruptMask;
108 1.1 alc uint32_t ah_txDescInterruptMask;
109 1.1 alc uint32_t ah_txEolInterruptMask;
110 1.1 alc uint32_t ah_txUrnInterruptMask;
111 1.1 alc HAL_POWER_MODE ah_powerMode;
112 1.1 alc uint8_t ah_bssid[IEEE80211_ADDR_LEN];
113 1.1 alc HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; /* beacon+cab+data */
114 1.1 alc /*
115 1.1 alc * Station mode support.
116 1.1 alc */
117 1.1 alc uint32_t ah_staId1Defaults; /* STA_ID1 default settings */
118 1.1 alc uint32_t ah_rssiThr; /* RSSI_THR settings */
119 1.1 alc
120 1.1 alc u_int ah_sifstime; /* user-specified sifs time */
121 1.1 alc u_int ah_slottime; /* user-specified slot time */
122 1.1 alc u_int ah_acktimeout; /* user-specified ack timeout */
123 1.1 alc u_int ah_ctstimeout; /* user-specified cts timeout */
124 1.1 alc };
125 1.1 alc #define AH5210(ah) ((struct ath_hal_5210 *)(ah))
126 1.1 alc
127 1.1 alc struct ath_hal;
128 1.1 alc
129 1.1 alc extern void ar5210Detach(struct ath_hal *ah);
130 1.1 alc extern HAL_BOOL ar5210Reset(struct ath_hal *, HAL_OPMODE,
131 1.1 alc HAL_CHANNEL *, HAL_BOOL bChannelChange, HAL_STATUS *);
132 1.1 alc extern void ar5210SetPCUConfig(struct ath_hal *);
133 1.1 alc extern HAL_BOOL ar5210PhyDisable(struct ath_hal *);
134 1.1 alc extern HAL_BOOL ar5210Disable(struct ath_hal *);
135 1.1 alc extern HAL_BOOL ar5210ChipReset(struct ath_hal *, HAL_CHANNEL *);
136 1.1 alc extern HAL_BOOL ar5210PerCalibration(struct ath_hal *, HAL_CHANNEL *, HAL_BOOL *);
137 1.1 alc extern HAL_BOOL ar5210PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan,
138 1.1 alc u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone);
139 1.1 alc extern HAL_BOOL ar5210ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan);
140 1.1 alc extern int16_t ar5210GetNoiseFloor(struct ath_hal *);
141 1.1 alc extern int16_t ar5210GetNfAdjust(struct ath_hal *,
142 1.1 alc const HAL_CHANNEL_INTERNAL *);
143 1.1 alc extern HAL_BOOL ar5210SetTxPowerLimit(struct ath_hal *, uint32_t limit);
144 1.1 alc extern HAL_BOOL ar5210SetTransmitPower(struct ath_hal *, HAL_CHANNEL *);
145 1.1 alc extern HAL_BOOL ar5210CalNoiseFloor(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
146 1.1 alc extern HAL_BOOL ar5210ResetDma(struct ath_hal *, HAL_OPMODE);
147 1.1 alc
148 1.1 alc extern HAL_BOOL ar5210SetTxQueueProps(struct ath_hal *ah, int q,
149 1.1 alc const HAL_TXQ_INFO *qInfo);
150 1.1 alc extern HAL_BOOL ar5210GetTxQueueProps(struct ath_hal *ah, int q,
151 1.1 alc HAL_TXQ_INFO *qInfo);
152 1.1 alc extern int ar5210SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,
153 1.1 alc const HAL_TXQ_INFO *qInfo);
154 1.1 alc extern HAL_BOOL ar5210ReleaseTxQueue(struct ath_hal *ah, u_int q);
155 1.1 alc extern HAL_BOOL ar5210ResetTxQueue(struct ath_hal *ah, u_int q);
156 1.1 alc extern uint32_t ar5210GetTxDP(struct ath_hal *, u_int);
157 1.1 alc extern HAL_BOOL ar5210SetTxDP(struct ath_hal *, u_int, uint32_t txdp);
158 1.1 alc extern HAL_BOOL ar5210UpdateTxTrigLevel(struct ath_hal *, HAL_BOOL);
159 1.1 alc extern uint32_t ar5210NumTxPending(struct ath_hal *, u_int);
160 1.1 alc extern HAL_BOOL ar5210StartTxDma(struct ath_hal *, u_int);
161 1.1 alc extern HAL_BOOL ar5210StopTxDma(struct ath_hal *, u_int);
162 1.1 alc extern HAL_BOOL ar5210SetupTxDesc(struct ath_hal *, struct ath_desc *,
163 1.1 alc u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower,
164 1.1 alc u_int txRate0, u_int txRetries0,
165 1.1 alc u_int keyIx, u_int antMode, u_int flags,
166 1.1 alc u_int rtsctsRate, u_int rtsctsDuration,
167 1.1 alc u_int compicvLen, u_int compivLen, u_int comp);
168 1.1 alc extern HAL_BOOL ar5210SetupXTxDesc(struct ath_hal *, struct ath_desc *,
169 1.1 alc u_int txRate1, u_int txRetries1,
170 1.1 alc u_int txRate2, u_int txRetries2,
171 1.1 alc u_int txRate3, u_int txRetries3);
172 1.1 alc extern HAL_BOOL ar5210FillTxDesc(struct ath_hal *, struct ath_desc *,
173 1.1 alc u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
174 1.1 alc const struct ath_desc *ds0);
175 1.1 alc extern HAL_STATUS ar5210ProcTxDesc(struct ath_hal *,
176 1.1 alc struct ath_desc *, struct ath_tx_status *);
177 1.1 alc extern void ar5210GetTxIntrQueue(struct ath_hal *ah, uint32_t *);
178 1.1 alc extern void ar5210IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *);
179 1.1 alc
180 1.1 alc extern uint32_t ar5210GetRxDP(struct ath_hal *);
181 1.1 alc extern void ar5210SetRxDP(struct ath_hal *, uint32_t rxdp);
182 1.1 alc extern void ar5210EnableReceive(struct ath_hal *);
183 1.1 alc extern HAL_BOOL ar5210StopDmaReceive(struct ath_hal *);
184 1.1 alc extern void ar5210StartPcuReceive(struct ath_hal *);
185 1.1 alc extern void ar5210StopPcuReceive(struct ath_hal *);
186 1.1 alc extern void ar5210SetMulticastFilter(struct ath_hal *,
187 1.1 alc uint32_t filter0, uint32_t filter1);
188 1.1 alc extern HAL_BOOL ar5210ClrMulticastFilterIndex(struct ath_hal *, uint32_t);
189 1.1 alc extern HAL_BOOL ar5210SetMulticastFilterIndex(struct ath_hal *, uint32_t);
190 1.1 alc extern uint32_t ar5210GetRxFilter(struct ath_hal *);
191 1.1 alc extern void ar5210SetRxFilter(struct ath_hal *, uint32_t);
192 1.1 alc extern HAL_BOOL ar5210SetupRxDesc(struct ath_hal *, struct ath_desc *,
193 1.1 alc uint32_t, u_int flags);
194 1.1 alc extern HAL_STATUS ar5210ProcRxDesc(struct ath_hal *, struct ath_desc *,
195 1.1 alc uint32_t, struct ath_desc *, uint64_t,
196 1.1 alc struct ath_rx_status *);
197 1.1 alc
198 1.1 alc extern void ar5210GetMacAddress(struct ath_hal *, uint8_t *);
199 1.1 alc extern HAL_BOOL ar5210SetMacAddress(struct ath_hal *ah, const uint8_t *);
200 1.1 alc extern void ar5210GetBssIdMask(struct ath_hal *, uint8_t *);
201 1.1 alc extern HAL_BOOL ar5210SetBssIdMask(struct ath_hal *, const uint8_t *);
202 1.1 alc extern HAL_BOOL ar5210EepromRead(struct ath_hal *, u_int off, uint16_t *data);
203 1.1 alc extern HAL_BOOL ar5210EepromWrite(struct ath_hal *, u_int off, uint16_t data);
204 1.1 alc extern HAL_BOOL ar5210SetRegulatoryDomain(struct ath_hal *,
205 1.1 alc uint16_t, HAL_STATUS *);
206 1.1 alc extern u_int ar5210GetWirelessModes(struct ath_hal *ah);
207 1.1 alc extern void ar5210EnableRfKill(struct ath_hal *);
208 1.1 alc extern HAL_BOOL ar5210GpioCfgInput(struct ath_hal *, uint32_t gpio);
209 1.1 alc extern HAL_BOOL ar5210GpioCfgOutput(struct ath_hal *, uint32_t gpio);
210 1.1 alc extern uint32_t ar5210GpioGet(struct ath_hal *, uint32_t gpio);
211 1.1 alc extern HAL_BOOL ar5210GpioSet(struct ath_hal *, uint32_t gpio, uint32_t);
212 1.1 alc extern void ar5210Gpio0SetIntr(struct ath_hal *, u_int, uint32_t ilevel);
213 1.1 alc extern void ar5210SetLedState(struct ath_hal *, HAL_LED_STATE);
214 1.1 alc extern u_int ar5210GetDefAntenna(struct ath_hal *);
215 1.1 alc extern void ar5210SetDefAntenna(struct ath_hal *, u_int);
216 1.1 alc extern HAL_ANT_SETTING ar5210GetAntennaSwitch(struct ath_hal *);
217 1.1 alc extern HAL_BOOL ar5210SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING);
218 1.1 alc extern void ar5210WriteAssocid(struct ath_hal *,
219 1.1 alc const uint8_t *bssid, uint16_t assocId);
220 1.1 alc extern uint32_t ar5210GetTsf32(struct ath_hal *);
221 1.1 alc extern uint64_t ar5210GetTsf64(struct ath_hal *);
222 1.1 alc extern void ar5210ResetTsf(struct ath_hal *);
223 1.1 alc extern uint32_t ar5210GetRandomSeed(struct ath_hal *);
224 1.1 alc extern HAL_BOOL ar5210DetectCardPresent(struct ath_hal *);
225 1.1 alc extern void ar5210UpdateMibCounters(struct ath_hal *, HAL_MIB_STATS *);
226 1.1 alc extern void ar5210EnableHwEncryption(struct ath_hal *);
227 1.1 alc extern void ar5210DisableHwEncryption(struct ath_hal *);
228 1.1 alc extern HAL_RFGAIN ar5210GetRfgain(struct ath_hal *);
229 1.1 alc extern HAL_BOOL ar5210SetSifsTime(struct ath_hal *, u_int);
230 1.1 alc extern u_int ar5210GetSifsTime(struct ath_hal *);
231 1.1 alc extern HAL_BOOL ar5210SetSlotTime(struct ath_hal *, u_int);
232 1.1 alc extern u_int ar5210GetSlotTime(struct ath_hal *);
233 1.1 alc extern HAL_BOOL ar5210SetAckTimeout(struct ath_hal *, u_int);
234 1.1 alc extern u_int ar5210GetAckTimeout(struct ath_hal *);
235 1.1 alc extern HAL_BOOL ar5210SetAckCTSRate(struct ath_hal *, u_int);
236 1.1 alc extern u_int ar5210GetAckCTSRate(struct ath_hal *);
237 1.1 alc extern HAL_BOOL ar5210SetCTSTimeout(struct ath_hal *, u_int);
238 1.1 alc extern u_int ar5210GetCTSTimeout(struct ath_hal *);
239 1.1 alc extern HAL_BOOL ar5210SetDecompMask(struct ath_hal *, uint16_t, int);
240 1.1 alc void ar5210SetCoverageClass(struct ath_hal *, uint8_t, int);
241 1.1 alc extern HAL_STATUS ar5210GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
242 1.1 alc uint32_t, uint32_t *);
243 1.1 alc extern HAL_BOOL ar5210SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
244 1.1 alc uint32_t, uint32_t, HAL_STATUS *);
245 1.1 alc extern HAL_BOOL ar5210GetDiagState(struct ath_hal *ah, int request,
246 1.1 alc const void *args, uint32_t argsize,
247 1.1 alc void **result, uint32_t *resultsize);
248 1.1 alc
249 1.1 alc extern u_int ar5210GetKeyCacheSize(struct ath_hal *);
250 1.1 alc extern HAL_BOOL ar5210IsKeyCacheEntryValid(struct ath_hal *, uint16_t);
251 1.1 alc extern HAL_BOOL ar5210ResetKeyCacheEntry(struct ath_hal *, uint16_t entry);
252 1.1 alc extern HAL_BOOL ar5210SetKeyCacheEntry(struct ath_hal *, uint16_t entry,
253 1.1 alc const HAL_KEYVAL *, const uint8_t *mac, int xorKey);
254 1.1 alc extern HAL_BOOL ar5210SetKeyCacheEntryMac(struct ath_hal *,
255 1.1 alc uint16_t, const uint8_t *);
256 1.1 alc
257 1.2 reinoud extern HAL_BOOL ar5210SetPowerMode(struct ath_hal *, HAL_POWER_MODE mode,
258 1.1 alc int setChip);
259 1.1 alc extern HAL_POWER_MODE ar5210GetPowerMode(struct ath_hal *);
260 1.1 alc
261 1.1 alc extern void ar5210SetBeaconTimers(struct ath_hal *,
262 1.1 alc const HAL_BEACON_TIMERS *);
263 1.1 alc extern void ar5210BeaconInit(struct ath_hal *, uint32_t, uint32_t);
264 1.1 alc extern void ar5210SetStaBeaconTimers(struct ath_hal *,
265 1.1 alc const HAL_BEACON_STATE *);
266 1.1 alc extern void ar5210ResetStaBeaconTimers(struct ath_hal *);
267 1.1 alc
268 1.1 alc extern HAL_BOOL ar5210IsInterruptPending(struct ath_hal *);
269 1.1 alc extern HAL_BOOL ar5210GetPendingInterrupts(struct ath_hal *, HAL_INT *);
270 1.1 alc extern HAL_INT ar5210GetInterrupts(struct ath_hal *);
271 1.1 alc extern HAL_INT ar5210SetInterrupts(struct ath_hal *, HAL_INT ints);
272 1.1 alc
273 1.1 alc extern const HAL_RATE_TABLE *ar5210GetRateTable(struct ath_hal *, u_int mode);
274 1.1 alc
275 1.1 alc extern HAL_BOOL ar5210AniControl(struct ath_hal *, HAL_ANI_CMD, int );
276 1.1 alc extern void ar5210AniPoll(struct ath_hal *, const HAL_NODE_STATS *, HAL_CHANNEL *);
277 1.1 alc extern void ar5210MibEvent(struct ath_hal *, const HAL_NODE_STATS *);
278 1.1 alc #endif /* _ATH_AR5210_H_ */
279