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      1  1.1  alc /*
      2  1.1  alc  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
      3  1.1  alc  * Copyright (c) 2002-2004 Atheros Communications, Inc.
      4  1.1  alc  *
      5  1.1  alc  * Permission to use, copy, modify, and/or distribute this software for any
      6  1.1  alc  * purpose with or without fee is hereby granted, provided that the above
      7  1.1  alc  * copyright notice and this permission notice appear in all copies.
      8  1.1  alc  *
      9  1.1  alc  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
     10  1.1  alc  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
     11  1.1  alc  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
     12  1.1  alc  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
     13  1.1  alc  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
     14  1.1  alc  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
     15  1.1  alc  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
     16  1.1  alc  *
     17  1.1  alc  * $Id: ar5210_beacon.c,v 1.1.1.1 2008/12/11 04:46:27 alc Exp $
     18  1.1  alc  */
     19  1.1  alc #include "opt_ah.h"
     20  1.1  alc 
     21  1.1  alc #include "ah.h"
     22  1.1  alc #include "ah_internal.h"
     23  1.1  alc #include "ah_desc.h"
     24  1.1  alc 
     25  1.1  alc #include "ar5210/ar5210.h"
     26  1.1  alc #include "ar5210/ar5210reg.h"
     27  1.1  alc #include "ar5210/ar5210desc.h"
     28  1.1  alc 
     29  1.1  alc /*
     30  1.1  alc  * Initialize all of the hardware registers used to send beacons.
     31  1.1  alc  */
     32  1.1  alc void
     33  1.1  alc ar5210SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt)
     34  1.1  alc {
     35  1.1  alc 
     36  1.1  alc 	OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt);
     37  1.1  alc 	OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba);
     38  1.1  alc 	OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba);
     39  1.1  alc 	OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim);
     40  1.1  alc 	/*
     41  1.1  alc 	 * Set the Beacon register after setting all timers.
     42  1.1  alc 	 */
     43  1.1  alc 	OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);
     44  1.1  alc }
     45  1.1  alc 
     46  1.1  alc /*
     47  1.1  alc  * Legacy api to Initialize all of the beacon registers.
     48  1.1  alc  */
     49  1.1  alc void
     50  1.1  alc ar5210BeaconInit(struct ath_hal *ah,
     51  1.1  alc 	uint32_t next_beacon, uint32_t beacon_period)
     52  1.1  alc {
     53  1.1  alc 	HAL_BEACON_TIMERS bt;
     54  1.1  alc 
     55  1.1  alc 	bt.bt_nexttbtt = next_beacon;
     56  1.1  alc 
     57  1.1  alc 	if (AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) {
     58  1.1  alc 		bt.bt_nextdba = (next_beacon -
     59  1.1  alc 			ath_hal_dma_beacon_response_time) << 3;	/* 1/8 TU */
     60  1.1  alc 		bt.bt_nextswba = (next_beacon -
     61  1.1  alc 			ath_hal_sw_beacon_response_time) << 3;	/* 1/8 TU */
     62  1.1  alc 		/*
     63  1.1  alc 		 * The SWBA interrupt is not used for beacons in ad hoc mode
     64  1.1  alc 		 * as we don't yet support ATIMs. So since the beacon never
     65  1.1  alc 		 * changes, the beacon descriptor is set up once and read
     66  1.1  alc 		 * into a special HW buffer, from which it will be
     67  1.1  alc 		 * automagically retrieved at each DMA Beacon Alert (DBA).
     68  1.1  alc 		 */
     69  1.1  alc 
     70  1.1  alc 		/* Set the ATIM window */
     71  1.1  alc 		bt.bt_nextatim = next_beacon + 0;	/* NB: no ATIMs */
     72  1.1  alc 	} else {
     73  1.1  alc 		bt.bt_nextdba = ~0;
     74  1.1  alc 		bt.bt_nextswba = ~0;
     75  1.1  alc 		bt.bt_nextatim = 1;
     76  1.1  alc 	}
     77  1.1  alc 	bt.bt_intval = beacon_period &
     78  1.1  alc 		(AR_BEACON_PERIOD | AR_BEACON_RESET_TSF | AR_BEACON_EN);
     79  1.1  alc 	ar5210SetBeaconTimers(ah, &bt);
     80  1.1  alc }
     81  1.1  alc 
     82  1.1  alc void
     83  1.1  alc ar5210ResetStaBeaconTimers(struct ath_hal *ah)
     84  1.1  alc {
     85  1.1  alc 	uint32_t val;
     86  1.1  alc 
     87  1.1  alc 	OS_REG_WRITE(ah, AR_TIMER0, 0);		/* no beacons */
     88  1.1  alc 	val = OS_REG_READ(ah, AR_STA_ID1);
     89  1.1  alc 	val |= AR_STA_ID1_NO_PSPOLL;		/* XXX */
     90  1.1  alc 	/* tell the h/w that the associated AP is not PCF capable */
     91  1.1  alc 	OS_REG_WRITE(ah, AR_STA_ID1,
     92  1.1  alc 		val & ~(AR_STA_ID1_DEFAULT_ANTENNA | AR_STA_ID1_PCF));
     93  1.1  alc 	OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD);
     94  1.1  alc }
     95  1.1  alc 
     96  1.1  alc /*
     97  1.1  alc  * Set all the beacon related bits on the h/w for stations
     98  1.1  alc  * i.e. initializes the corresponding h/w timers;
     99  1.1  alc  * also tells the h/w whether to anticipate PCF beacons
    100  1.1  alc  *
    101  1.1  alc  * dtim_count and cfp_count from the current beacon - their current
    102  1.1  alc  * values aren't necessarily maintained in the device struct
    103  1.1  alc  */
    104  1.1  alc void
    105  1.1  alc ar5210SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs)
    106  1.1  alc {
    107  1.1  alc 	struct ath_hal_5210 *ahp = AH5210(ah);
    108  1.1  alc 
    109  1.1  alc 	HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: setting beacon timers\n", __func__);
    110  1.1  alc 
    111  1.1  alc 	HALASSERT(bs->bs_intval != 0);
    112  1.1  alc 	/* if the AP will do PCF */
    113  1.1  alc 	if (bs->bs_cfpmaxduration != 0) {
    114  1.1  alc 		/* tell the h/w that the associated AP is PCF capable */
    115  1.1  alc 		OS_REG_WRITE(ah, AR_STA_ID1,
    116  1.1  alc 			(OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_DEFAULT_ANTENNA)
    117  1.1  alc 			| AR_STA_ID1_PCF);
    118  1.1  alc 
    119  1.1  alc 		/* set CFP_PERIOD(1.024ms) register */
    120  1.1  alc 		OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod);
    121  1.1  alc 
    122  1.1  alc 		/* set CFP_DUR(1.024ms) register to max cfp duration */
    123  1.1  alc 		OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration);
    124  1.1  alc 
    125  1.1  alc 		/* set TIMER2(128us) to anticipated time of next CFP */
    126  1.1  alc 		OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3);
    127  1.1  alc 	} else {
    128  1.1  alc 		/* tell the h/w that the associated AP is not PCF capable */
    129  1.1  alc 		OS_REG_WRITE(ah, AR_STA_ID1,
    130  1.1  alc 			OS_REG_READ(ah, AR_STA_ID1) &~ (AR_STA_ID1_DEFAULT_ANTENNA | AR_STA_ID1_PCF));
    131  1.1  alc 	}
    132  1.1  alc 
    133  1.1  alc 	/*
    134  1.1  alc 	 * Set TIMER0(1.024ms) to the anticipated time of the next beacon.
    135  1.1  alc 	 */
    136  1.1  alc 	OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt);
    137  1.1  alc 
    138  1.1  alc 	/*
    139  1.1  alc 	 * Start the beacon timers by setting the BEACON register
    140  1.1  alc 	 * to the beacon interval; also write the tim offset which
    141  1.1  alc 	 * we should know by now.  The code, in ar5211WriteAssocid,
    142  1.1  alc 	 * also sets the tim offset once the AID is known which can
    143  1.1  alc 	 * be left as such for now.
    144  1.1  alc 	 */
    145  1.1  alc 	OS_REG_WRITE(ah, AR_BEACON,
    146  1.1  alc 		(OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
    147  1.1  alc 		| SM(bs->bs_intval, AR_BEACON_PERIOD)
    148  1.1  alc 		| SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM)
    149  1.1  alc 	);
    150  1.1  alc 
    151  1.1  alc 	/*
    152  1.1  alc 	 * Configure the BMISS interrupt.  Note that we
    153  1.1  alc 	 * assume the caller blocks interrupts while enabling
    154  1.1  alc 	 * the threshold.
    155  1.1  alc 	 */
    156  1.1  alc 
    157  1.1  alc 	/*
    158  1.1  alc 	 * Interrupt works only on Crete.
    159  1.1  alc 	 */
    160  1.1  alc 	if (AH_PRIVATE(ah)->ah_macRev < AR_SREV_CRETE)
    161  1.1  alc 		return;
    162  1.1  alc 	/*
    163  1.1  alc 	 * Counter is only 3-bits.
    164  1.1  alc 	 * Count of 0 with BMISS interrupt enabled will hang the system
    165  1.1  alc 	 * with too many interrupts
    166  1.1  alc 	 */
    167  1.1  alc 	if (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_CRETE &&
    168  1.1  alc 	    (bs->bs_bmissthreshold&7) == 0) {
    169  1.1  alc #ifdef AH_DEBUG
    170  1.1  alc 		ath_hal_printf(ah, "%s: invalid beacon miss threshold %u\n",
    171  1.1  alc 			__func__, bs->bs_bmissthreshold);
    172  1.1  alc #endif
    173  1.1  alc 		return;
    174  1.1  alc 	}
    175  1.1  alc #define	BMISS_MAX	(AR_RSSI_THR_BM_THR >> AR_RSSI_THR_BM_THR_S)
    176  1.1  alc 	/*
    177  1.1  alc 	 * Configure the BMISS interrupt.  Note that we
    178  1.1  alc 	 * assume the caller blocks interrupts while enabling
    179  1.1  alc 	 * the threshold.
    180  1.1  alc 	 *
    181  1.1  alc 	 * NB: the beacon miss count field is only 3 bits which
    182  1.1  alc 	 *     is much smaller than what's found on later parts;
    183  1.1  alc 	 *     clamp overflow values as a safeguard.
    184  1.1  alc 	 */
    185  1.1  alc 	ahp->ah_rssiThr = (ahp->ah_rssiThr &~ AR_RSSI_THR_BM_THR)
    186  1.1  alc 			| SM(bs->bs_bmissthreshold > BMISS_MAX ?
    187  1.1  alc 				BMISS_MAX : bs->bs_bmissthreshold,
    188  1.1  alc 			     AR_RSSI_THR_BM_THR);
    189  1.1  alc 	OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
    190  1.1  alc #undef BMISS_MAX
    191  1.1  alc }
    192