ar5212.h revision 1.1.1.1.16.2
1 1.1.1.1.16.2 matt /* 2 1.1.1.1.16.2 matt * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 1.1.1.1.16.2 matt * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 1.1.1.1.16.2 matt * 5 1.1.1.1.16.2 matt * Permission to use, copy, modify, and/or distribute this software for any 6 1.1.1.1.16.2 matt * purpose with or without fee is hereby granted, provided that the above 7 1.1.1.1.16.2 matt * copyright notice and this permission notice appear in all copies. 8 1.1.1.1.16.2 matt * 9 1.1.1.1.16.2 matt * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 1.1.1.1.16.2 matt * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 1.1.1.1.16.2 matt * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 1.1.1.1.16.2 matt * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 1.1.1.1.16.2 matt * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 1.1.1.1.16.2 matt * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 1.1.1.1.16.2 matt * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 1.1.1.1.16.2 matt * 17 1.1.1.1.16.2 matt * $Id: ar5212.h,v 1.1.1.1.16.2 2010/04/21 00:28:09 matt Exp $ 18 1.1.1.1.16.2 matt */ 19 1.1.1.1.16.2 matt #ifndef _ATH_AR5212_H_ 20 1.1.1.1.16.2 matt #define _ATH_AR5212_H_ 21 1.1.1.1.16.2 matt 22 1.1.1.1.16.2 matt #include "ah_eeprom.h" 23 1.1.1.1.16.2 matt 24 1.1.1.1.16.2 matt #define AR5212_MAGIC 0x19541014 25 1.1.1.1.16.2 matt 26 1.1.1.1.16.2 matt /* DCU Transmit Filter macros */ 27 1.1.1.1.16.2 matt #define CALC_MMR(dcu, idx) \ 28 1.1.1.1.16.2 matt ( (4 * dcu) + (idx < 32 ? 0 : (idx < 64 ? 1 : (idx < 96 ? 2 : 3))) ) 29 1.1.1.1.16.2 matt #define TXBLK_FROM_MMR(mmr) \ 30 1.1.1.1.16.2 matt (AR_D_TXBLK_BASE + ((mmr & 0x1f) << 6) + ((mmr & 0x20) >> 3)) 31 1.1.1.1.16.2 matt #define CALC_TXBLK_ADDR(dcu, idx) (TXBLK_FROM_MMR(CALC_MMR(dcu, idx))) 32 1.1.1.1.16.2 matt #define CALC_TXBLK_VALUE(idx) (1 << (idx & 0x1f)) 33 1.1.1.1.16.2 matt 34 1.1.1.1.16.2 matt /* MAC register values */ 35 1.1.1.1.16.2 matt 36 1.1.1.1.16.2 matt #define INIT_INTERRUPT_MASK \ 37 1.1.1.1.16.2 matt ( AR_IMR_TXERR | AR_IMR_TXOK | AR_IMR_RXORN | \ 38 1.1.1.1.16.2 matt AR_IMR_RXERR | AR_IMR_RXOK | AR_IMR_TXURN | \ 39 1.1.1.1.16.2 matt AR_IMR_HIUERR ) 40 1.1.1.1.16.2 matt #define INIT_BEACON_CONTROL \ 41 1.1.1.1.16.2 matt ((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \ 42 1.1.1.1.16.2 matt (INIT_TIM_OFFSET << 16) | INIT_BEACON_PERIOD) 43 1.1.1.1.16.2 matt 44 1.1.1.1.16.2 matt #define INIT_CONFIG_STATUS 0x00000000 45 1.1.1.1.16.2 matt #define INIT_RSSI_THR 0x00000781 /* Missed beacon counter initialized to 0x7 (max is 0xff) */ 46 1.1.1.1.16.2 matt #define INIT_IQCAL_LOG_COUNT_MAX 0xF 47 1.1.1.1.16.2 matt #define INIT_BCON_CNTRL_REG 0x00000000 48 1.1.1.1.16.2 matt 49 1.1.1.1.16.2 matt #define INIT_USEC 40 50 1.1.1.1.16.2 matt #define HALF_RATE_USEC 19 /* ((40 / 2) - 1 ) */ 51 1.1.1.1.16.2 matt #define QUARTER_RATE_USEC 9 /* ((40 / 4) - 1 ) */ 52 1.1.1.1.16.2 matt 53 1.1.1.1.16.2 matt #define RX_NON_FULL_RATE_LATENCY 63 54 1.1.1.1.16.2 matt #define TX_HALF_RATE_LATENCY 108 55 1.1.1.1.16.2 matt #define TX_QUARTER_RATE_LATENCY 216 56 1.1.1.1.16.2 matt 57 1.1.1.1.16.2 matt #define IFS_SLOT_FULL_RATE 0x168 /* 9 us half, 40 MHz core clock (9*40) */ 58 1.1.1.1.16.2 matt #define IFS_SLOT_HALF_RATE 0x104 /* 13 us half, 20 MHz core clock (13*20) */ 59 1.1.1.1.16.2 matt #define IFS_SLOT_QUARTER_RATE 0xD2 /* 21 us quarter, 10 MHz core clock (21*10) */ 60 1.1.1.1.16.2 matt #define IFS_EIFS_FULL_RATE 0xE60 /* (74 + (2 * 9)) * 40MHz core clock */ 61 1.1.1.1.16.2 matt #define IFS_EIFS_HALF_RATE 0xDAC /* (149 + (2 * 13)) * 20MHz core clock */ 62 1.1.1.1.16.2 matt #define IFS_EIFS_QUARTER_RATE 0xD48 /* (298 + (2 * 21)) * 10MHz core clock */ 63 1.1.1.1.16.2 matt 64 1.1.1.1.16.2 matt #define ACK_CTS_TIMEOUT_11A 0x3E8 /* ACK timeout in 11a core clocks */ 65 1.1.1.1.16.2 matt 66 1.1.1.1.16.2 matt /* Tx frame start to tx data start delay */ 67 1.1.1.1.16.2 matt #define TX_FRAME_D_START_HALF_RATE 0xc 68 1.1.1.1.16.2 matt #define TX_FRAME_D_START_QUARTER_RATE 0xd 69 1.1.1.1.16.2 matt 70 1.1.1.1.16.2 matt /* 71 1.1.1.1.16.2 matt * Various fifo fill before Tx start, in 64-byte units 72 1.1.1.1.16.2 matt * i.e. put the frame in the air while still DMAing 73 1.1.1.1.16.2 matt */ 74 1.1.1.1.16.2 matt #define MIN_TX_FIFO_THRESHOLD 0x1 75 1.1.1.1.16.2 matt #define MAX_TX_FIFO_THRESHOLD ((IEEE80211_MAX_LEN / 64) + 1) 76 1.1.1.1.16.2 matt #define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD 77 1.1.1.1.16.2 matt 78 1.1.1.1.16.2 matt #define HAL_DECOMP_MASK_SIZE 128 /* 1 byte per key */ 79 1.1.1.1.16.2 matt 80 1.1.1.1.16.2 matt /* 81 1.1.1.1.16.2 matt * Gain support. 82 1.1.1.1.16.2 matt */ 83 1.1.1.1.16.2 matt #define NUM_CORNER_FIX_BITS 4 84 1.1.1.1.16.2 matt #define NUM_CORNER_FIX_BITS_5112 7 85 1.1.1.1.16.2 matt #define DYN_ADJ_UP_MARGIN 15 86 1.1.1.1.16.2 matt #define DYN_ADJ_LO_MARGIN 20 87 1.1.1.1.16.2 matt #define PHY_PROBE_CCK_CORRECTION 5 88 1.1.1.1.16.2 matt #define CCK_OFDM_GAIN_DELTA 15 89 1.1.1.1.16.2 matt 90 1.1.1.1.16.2 matt enum GAIN_PARAMS { 91 1.1.1.1.16.2 matt GP_TXCLIP, 92 1.1.1.1.16.2 matt GP_PD90, 93 1.1.1.1.16.2 matt GP_PD84, 94 1.1.1.1.16.2 matt GP_GSEL, 95 1.1.1.1.16.2 matt }; 96 1.1.1.1.16.2 matt 97 1.1.1.1.16.2 matt enum GAIN_PARAMS_5112 { 98 1.1.1.1.16.2 matt GP_MIXGAIN_OVR, 99 1.1.1.1.16.2 matt GP_PWD_138, 100 1.1.1.1.16.2 matt GP_PWD_137, 101 1.1.1.1.16.2 matt GP_PWD_136, 102 1.1.1.1.16.2 matt GP_PWD_132, 103 1.1.1.1.16.2 matt GP_PWD_131, 104 1.1.1.1.16.2 matt GP_PWD_130, 105 1.1.1.1.16.2 matt }; 106 1.1.1.1.16.2 matt 107 1.1.1.1.16.2 matt typedef struct _gainOptStep { 108 1.1.1.1.16.2 matt int16_t paramVal[NUM_CORNER_FIX_BITS_5112]; 109 1.1.1.1.16.2 matt int32_t stepGain; 110 1.1.1.1.16.2 matt int8_t stepName[16]; 111 1.1.1.1.16.2 matt } GAIN_OPTIMIZATION_STEP; 112 1.1.1.1.16.2 matt 113 1.1.1.1.16.2 matt typedef struct { 114 1.1.1.1.16.2 matt uint32_t numStepsInLadder; 115 1.1.1.1.16.2 matt uint32_t defaultStepNum; 116 1.1.1.1.16.2 matt GAIN_OPTIMIZATION_STEP optStep[10]; 117 1.1.1.1.16.2 matt } GAIN_OPTIMIZATION_LADDER; 118 1.1.1.1.16.2 matt 119 1.1.1.1.16.2 matt typedef struct { 120 1.1.1.1.16.2 matt uint32_t currStepNum; 121 1.1.1.1.16.2 matt uint32_t currGain; 122 1.1.1.1.16.2 matt uint32_t targetGain; 123 1.1.1.1.16.2 matt uint32_t loTrig; 124 1.1.1.1.16.2 matt uint32_t hiTrig; 125 1.1.1.1.16.2 matt uint32_t gainFCorrection; 126 1.1.1.1.16.2 matt uint32_t active; 127 1.1.1.1.16.2 matt const GAIN_OPTIMIZATION_STEP *currStep; 128 1.1.1.1.16.2 matt } GAIN_VALUES; 129 1.1.1.1.16.2 matt 130 1.1.1.1.16.2 matt /* RF HAL structures */ 131 1.1.1.1.16.2 matt typedef struct RfHalFuncs { 132 1.1.1.1.16.2 matt void *priv; /* private state */ 133 1.1.1.1.16.2 matt 134 1.1.1.1.16.2 matt void (*rfDetach)(struct ath_hal *ah); 135 1.1.1.1.16.2 matt void (*writeRegs)(struct ath_hal *, 136 1.1.1.1.16.2 matt u_int modeIndex, u_int freqIndex, int regWrites); 137 1.1.1.1.16.2 matt uint32_t *(*getRfBank)(struct ath_hal *ah, int bank); 138 1.1.1.1.16.2 matt HAL_BOOL (*setChannel)(struct ath_hal *, HAL_CHANNEL_INTERNAL *); 139 1.1.1.1.16.2 matt HAL_BOOL (*setRfRegs)(struct ath_hal *, 140 1.1.1.1.16.2 matt HAL_CHANNEL_INTERNAL *, uint16_t modesIndex, 141 1.1.1.1.16.2 matt uint16_t *rfXpdGain); 142 1.1.1.1.16.2 matt HAL_BOOL (*setPowerTable)(struct ath_hal *ah, 143 1.1.1.1.16.2 matt int16_t *minPower, int16_t *maxPower, 144 1.1.1.1.16.2 matt HAL_CHANNEL_INTERNAL *, uint16_t *rfXpdGain); 145 1.1.1.1.16.2 matt HAL_BOOL (*getChannelMaxMinPower)(struct ath_hal *ah, HAL_CHANNEL *, 146 1.1.1.1.16.2 matt int16_t *maxPow, int16_t *minPow); 147 1.1.1.1.16.2 matt int16_t (*getNfAdjust)(struct ath_hal *, const HAL_CHANNEL_INTERNAL*); 148 1.1.1.1.16.2 matt } RF_HAL_FUNCS; 149 1.1.1.1.16.2 matt 150 1.1.1.1.16.2 matt struct ar5212AniParams { 151 1.1.1.1.16.2 matt int maxNoiseImmunityLevel; /* [0..4] */ 152 1.1.1.1.16.2 matt int totalSizeDesired[5]; 153 1.1.1.1.16.2 matt int coarseHigh[5]; 154 1.1.1.1.16.2 matt int coarseLow[5]; 155 1.1.1.1.16.2 matt int firpwr[5]; 156 1.1.1.1.16.2 matt 157 1.1.1.1.16.2 matt int maxSpurImmunityLevel; /* [0..7] */ 158 1.1.1.1.16.2 matt int cycPwrThr1[8]; 159 1.1.1.1.16.2 matt 160 1.1.1.1.16.2 matt int maxFirstepLevel; /* [0..2] */ 161 1.1.1.1.16.2 matt int firstep[3]; 162 1.1.1.1.16.2 matt 163 1.1.1.1.16.2 matt uint32_t ofdmTrigHigh; 164 1.1.1.1.16.2 matt uint32_t ofdmTrigLow; 165 1.1.1.1.16.2 matt uint32_t cckTrigHigh; 166 1.1.1.1.16.2 matt uint32_t cckTrigLow; 167 1.1.1.1.16.2 matt int32_t rssiThrLow; 168 1.1.1.1.16.2 matt uint32_t rssiThrHigh; 169 1.1.1.1.16.2 matt 170 1.1.1.1.16.2 matt int period; /* update listen period */ 171 1.1.1.1.16.2 matt 172 1.1.1.1.16.2 matt /* NB: intentionally ordered so data exported to user space is first */ 173 1.1.1.1.16.2 matt uint32_t ofdmPhyErrBase; /* Base value for ofdm err counter */ 174 1.1.1.1.16.2 matt uint32_t cckPhyErrBase; /* Base value for cck err counters */ 175 1.1.1.1.16.2 matt }; 176 1.1.1.1.16.2 matt 177 1.1.1.1.16.2 matt /* 178 1.1.1.1.16.2 matt * Per-channel ANI state private to the driver. 179 1.1.1.1.16.2 matt */ 180 1.1.1.1.16.2 matt struct ar5212AniState { 181 1.1.1.1.16.2 matt uint8_t noiseImmunityLevel; 182 1.1.1.1.16.2 matt uint8_t spurImmunityLevel; 183 1.1.1.1.16.2 matt uint8_t firstepLevel; 184 1.1.1.1.16.2 matt uint8_t ofdmWeakSigDetectOff; 185 1.1.1.1.16.2 matt uint8_t cckWeakSigThreshold; 186 1.1.1.1.16.2 matt uint32_t listenTime; 187 1.1.1.1.16.2 matt 188 1.1.1.1.16.2 matt /* NB: intentionally ordered so data exported to user space is first */ 189 1.1.1.1.16.2 matt HAL_CHANNEL c; 190 1.1.1.1.16.2 matt HAL_BOOL isSetup; /* has state to do a restore */ 191 1.1.1.1.16.2 matt uint32_t txFrameCount; /* Last txFrameCount */ 192 1.1.1.1.16.2 matt uint32_t rxFrameCount; /* Last rx Frame count */ 193 1.1.1.1.16.2 matt uint32_t cycleCount; /* Last cycleCount 194 1.1.1.1.16.2 matt (to detect wrap-around) */ 195 1.1.1.1.16.2 matt uint32_t ofdmPhyErrCount;/* OFDM err count since last reset */ 196 1.1.1.1.16.2 matt uint32_t cckPhyErrCount; /* CCK err count since last reset */ 197 1.1.1.1.16.2 matt 198 1.1.1.1.16.2 matt const struct ar5212AniParams *params; 199 1.1.1.1.16.2 matt }; 200 1.1.1.1.16.2 matt 201 1.1.1.1.16.2 matt #define HAL_ANI_ENA 0x00000001 /* ANI operation enabled */ 202 1.1.1.1.16.2 matt #define HAL_RSSI_ANI_ENA 0x00000002 /* rssi-based processing ena'd*/ 203 1.1.1.1.16.2 matt 204 1.1.1.1.16.2 matt struct ar5212Stats { 205 1.1.1.1.16.2 matt uint32_t ast_ani_niup; /* ANI increased noise immunity */ 206 1.1.1.1.16.2 matt uint32_t ast_ani_nidown; /* ANI decreased noise immunity */ 207 1.1.1.1.16.2 matt uint32_t ast_ani_spurup; /* ANI increased spur immunity */ 208 1.1.1.1.16.2 matt uint32_t ast_ani_spurdown;/* ANI descreased spur immunity */ 209 1.1.1.1.16.2 matt uint32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */ 210 1.1.1.1.16.2 matt uint32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */ 211 1.1.1.1.16.2 matt uint32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */ 212 1.1.1.1.16.2 matt uint32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */ 213 1.1.1.1.16.2 matt uint32_t ast_ani_stepup; /* ANI increased first step level */ 214 1.1.1.1.16.2 matt uint32_t ast_ani_stepdown;/* ANI decreased first step level */ 215 1.1.1.1.16.2 matt uint32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */ 216 1.1.1.1.16.2 matt uint32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */ 217 1.1.1.1.16.2 matt uint32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */ 218 1.1.1.1.16.2 matt uint32_t ast_ani_lzero; /* ANI listen time forced to zero */ 219 1.1.1.1.16.2 matt uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */ 220 1.1.1.1.16.2 matt HAL_MIB_STATS ast_mibstats; /* MIB counter stats */ 221 1.1.1.1.16.2 matt HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */ 222 1.1.1.1.16.2 matt }; 223 1.1.1.1.16.2 matt 224 1.1.1.1.16.2 matt /* 225 1.1.1.1.16.2 matt * NF Cal history buffer 226 1.1.1.1.16.2 matt */ 227 1.1.1.1.16.2 matt #define AR5212_CCA_MAX_GOOD_VALUE -95 228 1.1.1.1.16.2 matt #define AR5212_CCA_MAX_HIGH_VALUE -62 229 1.1.1.1.16.2 matt #define AR5212_CCA_MIN_BAD_VALUE -125 230 1.1.1.1.16.2 matt 231 1.1.1.1.16.2 matt #define AR512_NF_CAL_HIST_MAX 5 232 1.1.1.1.16.2 matt 233 1.1.1.1.16.2 matt struct ar5212NfCalHist { 234 1.1.1.1.16.2 matt int16_t nfCalBuffer[AR512_NF_CAL_HIST_MAX]; 235 1.1.1.1.16.2 matt int16_t privNF; 236 1.1.1.1.16.2 matt uint8_t currIndex; 237 1.1.1.1.16.2 matt uint8_t first_run; 238 1.1.1.1.16.2 matt uint8_t invalidNFcount; 239 1.1.1.1.16.2 matt }; 240 1.1.1.1.16.2 matt 241 1.1.1.1.16.2 matt struct ath_hal_5212 { 242 1.1.1.1.16.2 matt struct ath_hal_private ah_priv; /* base class */ 243 1.1.1.1.16.2 matt 244 1.1.1.1.16.2 matt /* 245 1.1.1.1.16.2 matt * Per-chip common Initialization data. 246 1.1.1.1.16.2 matt * NB: RF backends have their own ini data. 247 1.1.1.1.16.2 matt */ 248 1.1.1.1.16.2 matt HAL_INI_ARRAY ah_ini_modes; 249 1.1.1.1.16.2 matt HAL_INI_ARRAY ah_ini_common; 250 1.1.1.1.16.2 matt 251 1.1.1.1.16.2 matt GAIN_VALUES ah_gainValues; 252 1.1.1.1.16.2 matt 253 1.1.1.1.16.2 matt uint8_t ah_macaddr[IEEE80211_ADDR_LEN]; 254 1.1.1.1.16.2 matt uint8_t ah_bssid[IEEE80211_ADDR_LEN]; 255 1.1.1.1.16.2 matt uint8_t ah_bssidmask[IEEE80211_ADDR_LEN]; 256 1.1.1.1.16.2 matt 257 1.1.1.1.16.2 matt /* 258 1.1.1.1.16.2 matt * Runtime state. 259 1.1.1.1.16.2 matt */ 260 1.1.1.1.16.2 matt uint32_t ah_maskReg; /* copy of AR_IMR */ 261 1.1.1.1.16.2 matt struct ar5212Stats ah_stats; /* various statistics */ 262 1.1.1.1.16.2 matt RF_HAL_FUNCS *ah_rfHal; 263 1.1.1.1.16.2 matt uint32_t ah_txDescMask; /* mask for TXDESC */ 264 1.1.1.1.16.2 matt uint32_t ah_txOkInterruptMask; 265 1.1.1.1.16.2 matt uint32_t ah_txErrInterruptMask; 266 1.1.1.1.16.2 matt uint32_t ah_txDescInterruptMask; 267 1.1.1.1.16.2 matt uint32_t ah_txEolInterruptMask; 268 1.1.1.1.16.2 matt uint32_t ah_txUrnInterruptMask; 269 1.1.1.1.16.2 matt HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; 270 1.1.1.1.16.2 matt uint32_t ah_intrTxqs; /* tx q interrupt state */ 271 1.1.1.1.16.2 matt /* decomp mask array */ 272 1.1.1.1.16.2 matt uint8_t ah_decompMask[HAL_DECOMP_MASK_SIZE]; 273 1.1.1.1.16.2 matt HAL_POWER_MODE ah_powerMode; 274 1.1.1.1.16.2 matt HAL_ANT_SETTING ah_antControl; /* antenna setting */ 275 1.1.1.1.16.2 matt HAL_BOOL ah_diversity; /* fast diversity setting */ 276 1.1.1.1.16.2 matt enum { 277 1.1.1.1.16.2 matt IQ_CAL_INACTIVE, 278 1.1.1.1.16.2 matt IQ_CAL_RUNNING, 279 1.1.1.1.16.2 matt IQ_CAL_DONE 280 1.1.1.1.16.2 matt } ah_bIQCalibration; /* IQ calibrate state */ 281 1.1.1.1.16.2 matt HAL_RFGAIN ah_rfgainState; /* RF gain calibrartion state */ 282 1.1.1.1.16.2 matt uint32_t ah_tx6PowerInHalfDbm; /* power output for 6Mb tx */ 283 1.1.1.1.16.2 matt uint32_t ah_staId1Defaults; /* STA_ID1 default settings */ 284 1.1.1.1.16.2 matt uint32_t ah_miscMode; /* MISC_MODE settings */ 285 1.1.1.1.16.2 matt uint32_t ah_rssiThr; /* RSSI_THR settings */ 286 1.1.1.1.16.2 matt HAL_BOOL ah_cwCalRequire; /* for ap51 */ 287 1.1.1.1.16.2 matt HAL_BOOL ah_tpcEnabled; /* per-packet tpc enabled */ 288 1.1.1.1.16.2 matt HAL_BOOL ah_phyPowerOn; /* PHY power state */ 289 1.1.1.1.16.2 matt HAL_BOOL ah_isHb63; /* cached HB63 check */ 290 1.1.1.1.16.2 matt uint32_t ah_macTPC; /* tpc register */ 291 1.1.1.1.16.2 matt uint32_t ah_beaconInterval; /* XXX */ 292 1.1.1.1.16.2 matt enum { 293 1.1.1.1.16.2 matt AUTO_32KHZ, /* use it if 32kHz crystal present */ 294 1.1.1.1.16.2 matt USE_32KHZ, /* do it regardless */ 295 1.1.1.1.16.2 matt DONT_USE_32KHZ, /* don't use it regardless */ 296 1.1.1.1.16.2 matt } ah_enable32kHzClock; /* whether to sleep at 32kHz */ 297 1.1.1.1.16.2 matt uint32_t ah_ofdmTxPower; 298 1.1.1.1.16.2 matt int16_t ah_txPowerIndexOffset; 299 1.1.1.1.16.2 matt /* 300 1.1.1.1.16.2 matt * Noise floor cal histogram support. 301 1.1.1.1.16.2 matt */ 302 1.1.1.1.16.2 matt struct ar5212NfCalHist ah_nfCalHist; 303 1.1.1.1.16.2 matt 304 1.1.1.1.16.2 matt u_int ah_slottime; /* user-specified slot time */ 305 1.1.1.1.16.2 matt u_int ah_acktimeout; /* user-specified ack timeout */ 306 1.1.1.1.16.2 matt u_int ah_ctstimeout; /* user-specified cts timeout */ 307 1.1.1.1.16.2 matt u_int ah_sifstime; /* user-specified sifs time */ 308 1.1.1.1.16.2 matt /* 309 1.1.1.1.16.2 matt * RF Silent handling; setup according to the EEPROM. 310 1.1.1.1.16.2 matt */ 311 1.1.1.1.16.2 matt uint32_t ah_gpioSelect; /* GPIO pin to use */ 312 1.1.1.1.16.2 matt uint32_t ah_polarity; /* polarity to disable RF */ 313 1.1.1.1.16.2 matt uint32_t ah_gpioBit; /* after init, prev value */ 314 1.1.1.1.16.2 matt /* 315 1.1.1.1.16.2 matt * ANI support. 316 1.1.1.1.16.2 matt */ 317 1.1.1.1.16.2 matt uint32_t ah_procPhyErr; /* Process Phy errs */ 318 1.1.1.1.16.2 matt HAL_BOOL ah_hasHwPhyCounters; /* Hardware has phy counters */ 319 1.1.1.1.16.2 matt struct ar5212AniParams ah_aniParams24; /* 2.4GHz parameters */ 320 1.1.1.1.16.2 matt struct ar5212AniParams ah_aniParams5; /* 5GHz parameters */ 321 1.1.1.1.16.2 matt struct ar5212AniState *ah_curani; /* cached last reference */ 322 1.1.1.1.16.2 matt struct ar5212AniState ah_ani[64]; /* per-channel state */ 323 1.1.1.1.16.2 matt 324 1.1.1.1.16.2 matt /* 325 1.1.1.1.16.2 matt * Transmit power state. Note these are maintained 326 1.1.1.1.16.2 matt * here so they can be retrieved by diagnostic tools. 327 1.1.1.1.16.2 matt */ 328 1.1.1.1.16.2 matt uint16_t *ah_pcdacTable; 329 1.1.1.1.16.2 matt u_int ah_pcdacTableSize; 330 1.1.1.1.16.2 matt uint16_t ah_ratesArray[16]; 331 1.1.1.1.16.2 matt }; 332 1.1.1.1.16.2 matt #define AH5212(_ah) ((struct ath_hal_5212 *)(_ah)) 333 1.1.1.1.16.2 matt 334 1.1.1.1.16.2 matt /* 335 1.1.1.1.16.2 matt * IS_XXXX macros test the MAC version 336 1.1.1.1.16.2 matt * IS_RADXXX macros test the radio/RF version (matching both 2G-only and 2/5G) 337 1.1.1.1.16.2 matt * 338 1.1.1.1.16.2 matt * Some single chip radios have equivalent radio/RF (e.g. 5112) 339 1.1.1.1.16.2 matt * for those use IS_RADXXX_ANY macros. 340 1.1.1.1.16.2 matt */ 341 1.1.1.1.16.2 matt #define IS_2317(ah) \ 342 1.1.1.1.16.2 matt ((AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV1) || \ 343 1.1.1.1.16.2 matt (AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV2)) 344 1.1.1.1.16.2 matt #define IS_2316(ah) \ 345 1.1.1.1.16.2 matt (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2415) 346 1.1.1.1.16.2 matt #define IS_2413(ah) \ 347 1.1.1.1.16.2 matt (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2413 || IS_2316(ah)) 348 1.1.1.1.16.2 matt #define IS_5424(ah) \ 349 1.1.1.1.16.2 matt (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5424 || \ 350 1.1.1.1.16.2 matt (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 && \ 351 1.1.1.1.16.2 matt AH_PRIVATE(ah)->ah_macRev <= AR_SREV_D2PLUS_MS)) 352 1.1.1.1.16.2 matt #define IS_5413(ah) \ 353 1.1.1.1.16.2 matt (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 || IS_5424(ah)) 354 1.1.1.1.16.2 matt #define IS_2425(ah) \ 355 1.1.1.1.16.2 matt (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) 356 1.1.1.1.16.2 matt #define IS_2417(ah) \ 357 1.1.1.1.16.2 matt ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_2417) 358 1.1.1.1.16.2 matt #define IS_HB63(ah) (AH5212(ah)->ah_isHb63 == AH_TRUE) 359 1.1.1.1.16.2 matt 360 1.1.1.1.16.2 matt #define IS_PCIE(ah) (IS_5424(ah) || IS_2425(ah)) 361 1.1.1.1.16.2 matt 362 1.1.1.1.16.2 matt #define AH_RADIO_MAJOR(ah) \ 363 1.1.1.1.16.2 matt (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) 364 1.1.1.1.16.2 matt #define AH_RADIO_MINOR(ah) \ 365 1.1.1.1.16.2 matt (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MINOR) 366 1.1.1.1.16.2 matt #define IS_RAD5111(ah) \ 367 1.1.1.1.16.2 matt (AH_RADIO_MAJOR(ah) == AR_RAD5111_SREV_MAJOR || \ 368 1.1.1.1.16.2 matt AH_RADIO_MAJOR(ah) == AR_RAD2111_SREV_MAJOR) 369 1.1.1.1.16.2 matt #define IS_RAD5112(ah) \ 370 1.1.1.1.16.2 matt (AH_RADIO_MAJOR(ah) == AR_RAD5112_SREV_MAJOR || \ 371 1.1.1.1.16.2 matt AH_RADIO_MAJOR(ah) == AR_RAD2112_SREV_MAJOR) 372 1.1.1.1.16.2 matt /* NB: does not include 5413 as Atheros' IS_5112 macro does */ 373 1.1.1.1.16.2 matt #define IS_RAD5112_ANY(ah) \ 374 1.1.1.1.16.2 matt (AR_RAD5112_SREV_MAJOR <= AH_RADIO_MAJOR(ah) && \ 375 1.1.1.1.16.2 matt AH_RADIO_MAJOR(ah) <= AR_RAD2413_SREV_MAJOR) 376 1.1.1.1.16.2 matt #define IS_RAD5112_REV1(ah) \ 377 1.1.1.1.16.2 matt (IS_RAD5112(ah) && \ 378 1.1.1.1.16.2 matt AH_RADIO_MINOR(ah) < (AR_RAD5112_SREV_2_0 & AR_RADIO_SREV_MINOR)) 379 1.1.1.1.16.2 matt #define IS_RADX112_REV2(ah) \ 380 1.1.1.1.16.2 matt (AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_0 || \ 381 1.1.1.1.16.2 matt AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_0 || \ 382 1.1.1.1.16.2 matt AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_1 || \ 383 1.1.1.1.16.2 matt AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_1) 384 1.1.1.1.16.2 matt 385 1.1.1.1.16.2 matt #define ar5212RfDetach(ah) do { \ 386 1.1.1.1.16.2 matt if (AH5212(ah)->ah_rfHal != AH_NULL) \ 387 1.1.1.1.16.2 matt AH5212(ah)->ah_rfHal->rfDetach(ah); \ 388 1.1.1.1.16.2 matt } while (0) 389 1.1.1.1.16.2 matt #define ar5212GetRfBank(ah, b) \ 390 1.1.1.1.16.2 matt AH5212(ah)->ah_rfHal->getRfBank(ah, b) 391 1.1.1.1.16.2 matt 392 1.1.1.1.16.2 matt /* 393 1.1.1.1.16.2 matt * Hack macros for Nala/San: 11b is handled 394 1.1.1.1.16.2 matt * using 11g; flip the channel flags to accomplish this. 395 1.1.1.1.16.2 matt */ 396 1.1.1.1.16.2 matt #define SAVE_CCK(_ah, _chan, _flag) do { \ 397 1.1.1.1.16.2 matt if ((IS_2425(_ah) || IS_2417(_ah)) && \ 398 1.1.1.1.16.2 matt (((_chan)->channelFlags) & CHANNEL_CCK)) { \ 399 1.1.1.1.16.2 matt (_chan)->channelFlags &= ~CHANNEL_CCK; \ 400 1.1.1.1.16.2 matt (_chan)->channelFlags |= CHANNEL_OFDM; \ 401 1.1.1.1.16.2 matt (_flag) = AH_TRUE; \ 402 1.1.1.1.16.2 matt } \ 403 1.1.1.1.16.2 matt } while (0) 404 1.1.1.1.16.2 matt #define RESTORE_CCK(_ah, _chan, _flag) do { \ 405 1.1.1.1.16.2 matt if ((IS_2425(_ah) || IS_2417(_ah)) && (_flag) == AH_TRUE) {\ 406 1.1.1.1.16.2 matt (_chan)->channelFlags &= ~CHANNEL_OFDM; \ 407 1.1.1.1.16.2 matt (_chan)->channelFlags |= CHANNEL_CCK; \ 408 1.1.1.1.16.2 matt } \ 409 1.1.1.1.16.2 matt } while (0) 410 1.1.1.1.16.2 matt 411 1.1.1.1.16.2 matt struct ath_hal; 412 1.1.1.1.16.2 matt 413 1.1.1.1.16.2 matt extern uint32_t ar5212GetRadioRev(struct ath_hal *ah); 414 1.1.1.1.16.2 matt extern void ar5212InitState(struct ath_hal_5212 *, uint16_t devid, HAL_SOFTC, 415 1.1.1.1.16.2 matt HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status); 416 1.1.1.1.16.2 matt extern void ar5212Detach(struct ath_hal *ah); 417 1.1.1.1.16.2 matt extern HAL_BOOL ar5212ChipTest(struct ath_hal *ah); 418 1.1.1.1.16.2 matt extern HAL_BOOL ar5212GetChannelEdges(struct ath_hal *ah, 419 1.1.1.1.16.2 matt uint16_t flags, uint16_t *low, uint16_t *high); 420 1.1.1.1.16.2 matt extern HAL_BOOL ar5212FillCapabilityInfo(struct ath_hal *ah); 421 1.1.1.1.16.2 matt 422 1.1.1.1.16.2 matt extern void ar5212SetBeaconTimers(struct ath_hal *ah, 423 1.1.1.1.16.2 matt const HAL_BEACON_TIMERS *); 424 1.1.1.1.16.2 matt extern void ar5212BeaconInit(struct ath_hal *ah, 425 1.1.1.1.16.2 matt uint32_t next_beacon, uint32_t beacon_period); 426 1.1.1.1.16.2 matt extern void ar5212ResetStaBeaconTimers(struct ath_hal *ah); 427 1.1.1.1.16.2 matt extern void ar5212SetStaBeaconTimers(struct ath_hal *ah, 428 1.1.1.1.16.2 matt const HAL_BEACON_STATE *); 429 1.1.1.1.16.2 matt 430 1.1.1.1.16.2 matt extern HAL_BOOL ar5212IsInterruptPending(struct ath_hal *ah); 431 1.1.1.1.16.2 matt extern HAL_BOOL ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *); 432 1.1.1.1.16.2 matt extern HAL_INT ar5212GetInterrupts(struct ath_hal *ah); 433 1.1.1.1.16.2 matt extern HAL_INT ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints); 434 1.1.1.1.16.2 matt 435 1.1.1.1.16.2 matt extern uint32_t ar5212GetKeyCacheSize(struct ath_hal *); 436 1.1.1.1.16.2 matt extern HAL_BOOL ar5212IsKeyCacheEntryValid(struct ath_hal *, uint16_t entry); 437 1.1.1.1.16.2 matt extern HAL_BOOL ar5212ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry); 438 1.1.1.1.16.2 matt extern HAL_BOOL ar5212SetKeyCacheEntryMac(struct ath_hal *, 439 1.1.1.1.16.2 matt uint16_t entry, const uint8_t *mac); 440 1.1.1.1.16.2 matt extern HAL_BOOL ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry, 441 1.1.1.1.16.2 matt const HAL_KEYVAL *k, const uint8_t *mac, int xorKey); 442 1.1.1.1.16.2 matt 443 1.1.1.1.16.2 matt extern void ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac); 444 1.1.1.1.16.2 matt extern HAL_BOOL ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *); 445 1.1.1.1.16.2 matt extern void ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mac); 446 1.1.1.1.16.2 matt extern HAL_BOOL ar5212SetBssIdMask(struct ath_hal *, const uint8_t *); 447 1.1.1.1.16.2 matt extern HAL_BOOL ar5212EepromRead(struct ath_hal *, u_int off, uint16_t *data); 448 1.1.1.1.16.2 matt extern HAL_BOOL ar5212EepromWrite(struct ath_hal *, u_int off, uint16_t data); 449 1.1.1.1.16.2 matt extern HAL_BOOL ar5212SetRegulatoryDomain(struct ath_hal *ah, 450 1.1.1.1.16.2 matt uint16_t regDomain, HAL_STATUS *stats); 451 1.1.1.1.16.2 matt extern u_int ar5212GetWirelessModes(struct ath_hal *ah); 452 1.1.1.1.16.2 matt extern void ar5212EnableRfKill(struct ath_hal *); 453 1.1.1.1.16.2 matt extern HAL_BOOL ar5212GpioCfgOutput(struct ath_hal *, uint32_t gpio); 454 1.1.1.1.16.2 matt extern HAL_BOOL ar5212GpioCfgInput(struct ath_hal *, uint32_t gpio); 455 1.1.1.1.16.2 matt extern HAL_BOOL ar5212GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val); 456 1.1.1.1.16.2 matt extern uint32_t ar5212GpioGet(struct ath_hal *ah, uint32_t gpio); 457 1.1.1.1.16.2 matt extern void ar5212GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel); 458 1.1.1.1.16.2 matt extern void ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state); 459 1.1.1.1.16.2 matt extern void ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, 460 1.1.1.1.16.2 matt uint16_t assocId); 461 1.1.1.1.16.2 matt extern uint32_t ar5212GetTsf32(struct ath_hal *ah); 462 1.1.1.1.16.2 matt extern uint64_t ar5212GetTsf64(struct ath_hal *ah); 463 1.1.1.1.16.2 matt extern void ar5212ResetTsf(struct ath_hal *ah); 464 1.1.1.1.16.2 matt extern void ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *pSet); 465 1.1.1.1.16.2 matt extern uint32_t ar5212GetRandomSeed(struct ath_hal *ah); 466 1.1.1.1.16.2 matt extern HAL_BOOL ar5212DetectCardPresent(struct ath_hal *ah); 467 1.1.1.1.16.2 matt extern void ar5212EnableMibCounters(struct ath_hal *); 468 1.1.1.1.16.2 matt extern void ar5212DisableMibCounters(struct ath_hal *); 469 1.1.1.1.16.2 matt extern void ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats); 470 1.1.1.1.16.2 matt extern HAL_BOOL ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah); 471 1.1.1.1.16.2 matt extern uint32_t ar5212GetCurRssi(struct ath_hal *ah); 472 1.1.1.1.16.2 matt extern u_int ar5212GetDefAntenna(struct ath_hal *ah); 473 1.1.1.1.16.2 matt extern void ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna); 474 1.1.1.1.16.2 matt extern HAL_ANT_SETTING ar5212GetAntennaSwitch(struct ath_hal *); 475 1.1.1.1.16.2 matt extern HAL_BOOL ar5212SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING); 476 1.1.1.1.16.2 matt extern HAL_BOOL ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah); 477 1.1.1.1.16.2 matt extern HAL_BOOL ar5212SetSifsTime(struct ath_hal *, u_int); 478 1.1.1.1.16.2 matt extern u_int ar5212GetSifsTime(struct ath_hal *); 479 1.1.1.1.16.2 matt extern HAL_BOOL ar5212SetSlotTime(struct ath_hal *, u_int); 480 1.1.1.1.16.2 matt extern u_int ar5212GetSlotTime(struct ath_hal *); 481 1.1.1.1.16.2 matt extern HAL_BOOL ar5212SetAckTimeout(struct ath_hal *, u_int); 482 1.1.1.1.16.2 matt extern u_int ar5212GetAckTimeout(struct ath_hal *); 483 1.1.1.1.16.2 matt extern HAL_BOOL ar5212SetAckCTSRate(struct ath_hal *, u_int); 484 1.1.1.1.16.2 matt extern u_int ar5212GetAckCTSRate(struct ath_hal *); 485 1.1.1.1.16.2 matt extern HAL_BOOL ar5212SetCTSTimeout(struct ath_hal *, u_int); 486 1.1.1.1.16.2 matt extern u_int ar5212GetCTSTimeout(struct ath_hal *); 487 1.1.1.1.16.2 matt extern HAL_BOOL ar5212SetDecompMask(struct ath_hal *, uint16_t, int); 488 1.1.1.1.16.2 matt void ar5212SetCoverageClass(struct ath_hal *, uint8_t, int); 489 1.1.1.1.16.2 matt extern void ar5212SetPCUConfig(struct ath_hal *); 490 1.1.1.1.16.2 matt extern HAL_BOOL ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode); 491 1.1.1.1.16.2 matt extern void ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode); 492 1.1.1.1.16.2 matt extern void ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode); 493 1.1.1.1.16.2 matt extern int16_t ar5212GetNfAdjust(struct ath_hal *, 494 1.1.1.1.16.2 matt const HAL_CHANNEL_INTERNAL *); 495 1.1.1.1.16.2 matt extern void ar5212SetCompRegs(struct ath_hal *ah); 496 1.1.1.1.16.2 matt extern HAL_STATUS ar5212GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, 497 1.1.1.1.16.2 matt uint32_t, uint32_t *); 498 1.1.1.1.16.2 matt extern HAL_BOOL ar5212SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, 499 1.1.1.1.16.2 matt uint32_t, uint32_t, HAL_STATUS *); 500 1.1.1.1.16.2 matt extern HAL_BOOL ar5212GetDiagState(struct ath_hal *ah, int request, 501 1.1.1.1.16.2 matt const void *args, uint32_t argsize, 502 1.1.1.1.16.2 matt void **result, uint32_t *resultsize); 503 1.1.1.1.16.2 matt 504 1.1.1.1.16.2 matt extern HAL_BOOL ar5212SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, 505 1.1.1.1.16.2 matt int setChip); 506 1.1.1.1.16.2 matt extern HAL_POWER_MODE ar5212GetPowerMode(struct ath_hal *ah); 507 1.1.1.1.16.2 matt extern HAL_BOOL ar5212GetPowerStatus(struct ath_hal *ah); 508 1.1.1.1.16.2 matt 509 1.1.1.1.16.2 matt extern uint32_t ar5212GetRxDP(struct ath_hal *ath); 510 1.1.1.1.16.2 matt extern void ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp); 511 1.1.1.1.16.2 matt extern void ar5212EnableReceive(struct ath_hal *ah); 512 1.1.1.1.16.2 matt extern HAL_BOOL ar5212StopDmaReceive(struct ath_hal *ah); 513 1.1.1.1.16.2 matt extern void ar5212StartPcuReceive(struct ath_hal *ah); 514 1.1.1.1.16.2 matt extern void ar5212StopPcuReceive(struct ath_hal *ah); 515 1.1.1.1.16.2 matt extern void ar5212SetMulticastFilter(struct ath_hal *ah, 516 1.1.1.1.16.2 matt uint32_t filter0, uint32_t filter1); 517 1.1.1.1.16.2 matt extern HAL_BOOL ar5212ClrMulticastFilterIndex(struct ath_hal *, uint32_t ix); 518 1.1.1.1.16.2 matt extern HAL_BOOL ar5212SetMulticastFilterIndex(struct ath_hal *, uint32_t ix); 519 1.1.1.1.16.2 matt extern uint32_t ar5212GetRxFilter(struct ath_hal *ah); 520 1.1.1.1.16.2 matt extern void ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits); 521 1.1.1.1.16.2 matt extern HAL_BOOL ar5212SetupRxDesc(struct ath_hal *, 522 1.1.1.1.16.2 matt struct ath_desc *, uint32_t size, u_int flags); 523 1.1.1.1.16.2 matt extern HAL_STATUS ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *, 524 1.1.1.1.16.2 matt uint32_t, struct ath_desc *, uint64_t, 525 1.1.1.1.16.2 matt struct ath_rx_status *); 526 1.1.1.1.16.2 matt 527 1.1.1.1.16.2 matt extern HAL_BOOL ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode, 528 1.1.1.1.16.2 matt HAL_CHANNEL *chan, HAL_BOOL bChannelChange, HAL_STATUS *status); 529 1.1.1.1.16.2 matt extern HAL_BOOL ar5212SetChannel(struct ath_hal *, HAL_CHANNEL_INTERNAL *); 530 1.1.1.1.16.2 matt extern void ar5212SetOperatingMode(struct ath_hal *ah, int opmode); 531 1.1.1.1.16.2 matt extern HAL_BOOL ar5212PhyDisable(struct ath_hal *ah); 532 1.1.1.1.16.2 matt extern HAL_BOOL ar5212Disable(struct ath_hal *ah); 533 1.1.1.1.16.2 matt extern HAL_BOOL ar5212ChipReset(struct ath_hal *ah, HAL_CHANNEL *); 534 1.1.1.1.16.2 matt extern HAL_BOOL ar5212PerCalibration(struct ath_hal *ah, HAL_CHANNEL *chan, 535 1.1.1.1.16.2 matt HAL_BOOL *isIQdone); 536 1.1.1.1.16.2 matt extern HAL_BOOL ar5212PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan, 537 1.1.1.1.16.2 matt u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone); 538 1.1.1.1.16.2 matt extern HAL_BOOL ar5212ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan); 539 1.1.1.1.16.2 matt extern int16_t ar5212GetNoiseFloor(struct ath_hal *ah); 540 1.1.1.1.16.2 matt extern void ar5212InitNfCalHistBuffer(struct ath_hal *); 541 1.1.1.1.16.2 matt extern int16_t ar5212GetNfHistMid(const int16_t calData[]); 542 1.1.1.1.16.2 matt extern void ar5212SetSpurMitigation(struct ath_hal *, HAL_CHANNEL_INTERNAL *); 543 1.1.1.1.16.2 matt extern HAL_BOOL ar5212SetAntennaSwitchInternal(struct ath_hal *ah, 544 1.1.1.1.16.2 matt HAL_ANT_SETTING settings, const HAL_CHANNEL_INTERNAL *ichan); 545 1.1.1.1.16.2 matt extern HAL_BOOL ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit); 546 1.1.1.1.16.2 matt extern HAL_BOOL ar5212GetChipPowerLimits(struct ath_hal *ah, 547 1.1.1.1.16.2 matt HAL_CHANNEL *chans, uint32_t nchans); 548 1.1.1.1.16.2 matt extern void ar5212InitializeGainValues(struct ath_hal *); 549 1.1.1.1.16.2 matt extern HAL_RFGAIN ar5212GetRfgain(struct ath_hal *ah); 550 1.1.1.1.16.2 matt extern void ar5212RequestRfgain(struct ath_hal *); 551 1.1.1.1.16.2 matt 552 1.1.1.1.16.2 matt extern HAL_BOOL ar5212UpdateTxTrigLevel(struct ath_hal *, 553 1.1.1.1.16.2 matt HAL_BOOL IncTrigLevel); 554 1.1.1.1.16.2 matt extern HAL_BOOL ar5212SetTxQueueProps(struct ath_hal *ah, int q, 555 1.1.1.1.16.2 matt const HAL_TXQ_INFO *qInfo); 556 1.1.1.1.16.2 matt extern HAL_BOOL ar5212GetTxQueueProps(struct ath_hal *ah, int q, 557 1.1.1.1.16.2 matt HAL_TXQ_INFO *qInfo); 558 1.1.1.1.16.2 matt extern int ar5212SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type, 559 1.1.1.1.16.2 matt const HAL_TXQ_INFO *qInfo); 560 1.1.1.1.16.2 matt extern HAL_BOOL ar5212ReleaseTxQueue(struct ath_hal *ah, u_int q); 561 1.1.1.1.16.2 matt extern HAL_BOOL ar5212ResetTxQueue(struct ath_hal *ah, u_int q); 562 1.1.1.1.16.2 matt extern uint32_t ar5212GetTxDP(struct ath_hal *ah, u_int q); 563 1.1.1.1.16.2 matt extern HAL_BOOL ar5212SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp); 564 1.1.1.1.16.2 matt extern HAL_BOOL ar5212StartTxDma(struct ath_hal *ah, u_int q); 565 1.1.1.1.16.2 matt extern uint32_t ar5212NumTxPending(struct ath_hal *ah, u_int q); 566 1.1.1.1.16.2 matt extern HAL_BOOL ar5212StopTxDma(struct ath_hal *ah, u_int q); 567 1.1.1.1.16.2 matt extern HAL_BOOL ar5212SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds, 568 1.1.1.1.16.2 matt u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower, 569 1.1.1.1.16.2 matt u_int txRate0, u_int txTries0, 570 1.1.1.1.16.2 matt u_int keyIx, u_int antMode, u_int flags, 571 1.1.1.1.16.2 matt u_int rtsctsRate, u_int rtsctsDuration, 572 1.1.1.1.16.2 matt u_int compicvLen, u_int compivLen, u_int comp); 573 1.1.1.1.16.2 matt extern HAL_BOOL ar5212SetupXTxDesc(struct ath_hal *, struct ath_desc *, 574 1.1.1.1.16.2 matt u_int txRate1, u_int txRetries1, 575 1.1.1.1.16.2 matt u_int txRate2, u_int txRetries2, 576 1.1.1.1.16.2 matt u_int txRate3, u_int txRetries3); 577 1.1.1.1.16.2 matt extern HAL_BOOL ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds, 578 1.1.1.1.16.2 matt u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg, 579 1.1.1.1.16.2 matt const struct ath_desc *ds0); 580 1.1.1.1.16.2 matt extern HAL_STATUS ar5212ProcTxDesc(struct ath_hal *ah, 581 1.1.1.1.16.2 matt struct ath_desc *, struct ath_tx_status *); 582 1.1.1.1.16.2 matt extern void ar5212GetTxIntrQueue(struct ath_hal *ah, uint32_t *); 583 1.1.1.1.16.2 matt extern void ar5212IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *); 584 1.1.1.1.16.2 matt 585 1.1.1.1.16.2 matt extern const HAL_RATE_TABLE *ar5212GetRateTable(struct ath_hal *, u_int mode); 586 1.1.1.1.16.2 matt 587 1.1.1.1.16.2 matt extern void ar5212AniAttach(struct ath_hal *, const struct ar5212AniParams *, 588 1.1.1.1.16.2 matt const struct ar5212AniParams *, HAL_BOOL ena); 589 1.1.1.1.16.2 matt extern void ar5212AniDetach(struct ath_hal *); 590 1.1.1.1.16.2 matt extern struct ar5212AniState *ar5212AniGetCurrentState(struct ath_hal *); 591 1.1.1.1.16.2 matt extern struct ar5212Stats *ar5212AniGetCurrentStats(struct ath_hal *); 592 1.1.1.1.16.2 matt extern HAL_BOOL ar5212AniControl(struct ath_hal *, HAL_ANI_CMD cmd, int param); 593 1.1.1.1.16.2 matt extern HAL_BOOL ar5212AniSetParams(struct ath_hal *, 594 1.1.1.1.16.2 matt const struct ar5212AniParams *, const struct ar5212AniParams *); 595 1.1.1.1.16.2 matt struct ath_rx_status; 596 1.1.1.1.16.2 matt extern void ar5212AniPhyErrReport(struct ath_hal *ah, 597 1.1.1.1.16.2 matt const struct ath_rx_status *rs); 598 1.1.1.1.16.2 matt extern void ar5212ProcessMibIntr(struct ath_hal *, const HAL_NODE_STATS *); 599 1.1.1.1.16.2 matt extern void ar5212AniPoll(struct ath_hal *, const HAL_NODE_STATS *, 600 1.1.1.1.16.2 matt HAL_CHANNEL *); 601 1.1.1.1.16.2 matt extern void ar5212AniReset(struct ath_hal *, HAL_CHANNEL_INTERNAL *, 602 1.1.1.1.16.2 matt HAL_OPMODE, int); 603 1.1.1.1.16.2 matt #endif /* _ATH_AR5212_H_ */ 604
Indexes created Thu Oct 30 16:09:53 GMT 2025