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      1  1.1  alc /*
      2  1.1  alc  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
      3  1.1  alc  * Copyright (c) 2002-2008 Atheros Communications, Inc.
      4  1.1  alc  *
      5  1.1  alc  * Permission to use, copy, modify, and/or distribute this software for any
      6  1.1  alc  * purpose with or without fee is hereby granted, provided that the above
      7  1.1  alc  * copyright notice and this permission notice appear in all copies.
      8  1.1  alc  *
      9  1.1  alc  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
     10  1.1  alc  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
     11  1.1  alc  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
     12  1.1  alc  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
     13  1.1  alc  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
     14  1.1  alc  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
     15  1.1  alc  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
     16  1.1  alc  *
     17  1.1  alc  * $Id: ar5311reg.h,v 1.1.1.1 2008/12/11 04:46:44 alc Exp $
     18  1.1  alc  */
     19  1.1  alc #ifndef _DEV_ATH_AR5311REG_H_
     20  1.1  alc #define _DEV_ATH_AR5311REG_H_
     21  1.1  alc 
     22  1.1  alc /*
     23  1.1  alc  * Definitions for the Atheros 5311 chipset.
     24  1.1  alc  */
     25  1.1  alc #define	AR5311_QDCLKGATE	0x005c	/* MAC QCU/DCU clock gating control */
     26  1.1  alc #define	AR5311_QDCLKGATE_QCU_M	0x0000FFFF /* QCU clock disable */
     27  1.1  alc #define	AR5311_QDCLKGATE_DCU_M	0x07FF0000 /* DCU clock disable */
     28  1.1  alc 
     29  1.1  alc #define	AR5311_RXCFG_DEF_RX_ANTENNA	0x00000008 /* Default Receive Antenna */
     30  1.1  alc 
     31  1.1  alc /*
     32  1.1  alc  * NOTE: MAC_5211/MAC_5311 difference
     33  1.1  alc  * On Oahu the TX latency field has increased from 6 bits to 9 bits.
     34  1.1  alc  * The RX latency field is unchanged but is shifted over 3 bits.
     35  1.1  alc  */
     36  1.1  alc #define	AR5311_USEC_TX_LAT_M	0x000FC000 /* tx latency (usec) */
     37  1.1  alc #define	AR5311_USEC_TX_LAT_S	14
     38  1.1  alc #define	AR5311_USEC_RX_LAT_M	0x03F00000 /* rx latency (usec) */
     39  1.1  alc #define	AR5311_USEC_RX_LAT_S	20
     40  1.1  alc 
     41  1.1  alc /*
     42  1.1  alc  * NOTE: MAC_5211/MAC_5311 difference
     43  1.1  alc  * On Maui2/Spirit the frame sequence number is controlled per DCU.
     44  1.1  alc  * On Oahu the frame sequence number is global across all DCUs and
     45  1.1  alc  * is controlled
     46  1.1  alc  */
     47  1.1  alc #define	AR5311_D_MISC_SEQ_NUM_CONTROL	0x01000000 /* seq num local or global */
     48  1.1  alc #define	AR5311_DIAG_USE_ECO	0x00000400	/* "super secret" enable ECO */
     49  1.1  alc 
     50  1.1  alc #endif /* _DEV_ATH_AR5311REG_H_ */
     51