ar2133.c revision 1.1.1.1.10.2
1 1.1.1.1.10.2 snj /* 2 1.1.1.1.10.2 snj * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 1.1.1.1.10.2 snj * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 1.1.1.1.10.2 snj * 5 1.1.1.1.10.2 snj * Permission to use, copy, modify, and/or distribute this software for any 6 1.1.1.1.10.2 snj * purpose with or without fee is hereby granted, provided that the above 7 1.1.1.1.10.2 snj * copyright notice and this permission notice appear in all copies. 8 1.1.1.1.10.2 snj * 9 1.1.1.1.10.2 snj * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 1.1.1.1.10.2 snj * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 1.1.1.1.10.2 snj * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 1.1.1.1.10.2 snj * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 1.1.1.1.10.2 snj * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 1.1.1.1.10.2 snj * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 1.1.1.1.10.2 snj * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 1.1.1.1.10.2 snj * 17 1.1.1.1.10.2 snj * $Id: ar2133.c,v 1.1.1.1.10.2 2009/08/07 06:43:46 snj Exp $ 18 1.1.1.1.10.2 snj */ 19 1.1.1.1.10.2 snj #include "opt_ah.h" 20 1.1.1.1.10.2 snj 21 1.1.1.1.10.2 snj #include "ah.h" 22 1.1.1.1.10.2 snj #include "ah_internal.h" 23 1.1.1.1.10.2 snj 24 1.1.1.1.10.2 snj #include "ah_eeprom_v14.h" 25 1.1.1.1.10.2 snj 26 1.1.1.1.10.2 snj #include "ar5416/ar5416.h" 27 1.1.1.1.10.2 snj #include "ar5416/ar5416reg.h" 28 1.1.1.1.10.2 snj #include "ar5416/ar5416phy.h" 29 1.1.1.1.10.2 snj 30 1.1.1.1.10.2 snj #define N(a) (sizeof(a)/sizeof(a[0])) 31 1.1.1.1.10.2 snj 32 1.1.1.1.10.2 snj struct ar2133State { 33 1.1.1.1.10.2 snj RF_HAL_FUNCS base; /* public state, must be first */ 34 1.1.1.1.10.2 snj uint16_t pcdacTable[1]; 35 1.1.1.1.10.2 snj 36 1.1.1.1.10.2 snj uint32_t *Bank0Data; 37 1.1.1.1.10.2 snj uint32_t *Bank1Data; 38 1.1.1.1.10.2 snj uint32_t *Bank2Data; 39 1.1.1.1.10.2 snj uint32_t *Bank3Data; 40 1.1.1.1.10.2 snj uint32_t *Bank6Data; 41 1.1.1.1.10.2 snj uint32_t *Bank7Data; 42 1.1.1.1.10.2 snj 43 1.1.1.1.10.2 snj /* NB: Bank*Data storage follows */ 44 1.1.1.1.10.2 snj }; 45 1.1.1.1.10.2 snj #define AR2133(ah) ((struct ar2133State *) AH5212(ah)->ah_rfHal) 46 1.1.1.1.10.2 snj 47 1.1.1.1.10.2 snj #define ar5416ModifyRfBuffer ar5212ModifyRfBuffer /*XXX*/ 48 1.1.1.1.10.2 snj 49 1.1.1.1.10.2 snj extern void ar5416ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32, 50 1.1.1.1.10.2 snj uint32_t numBits, uint32_t firstBit, uint32_t column); 51 1.1.1.1.10.2 snj HAL_BOOL ar2133GetChipPowerLimits(struct ath_hal *ah, HAL_CHANNEL 52 1.1.1.1.10.2 snj *chans, uint32_t nchans); 53 1.1.1.1.10.2 snj 54 1.1.1.1.10.2 snj static HAL_BOOL ar2133GetChannelMaxMinPower(struct ath_hal *, HAL_CHANNEL *, 55 1.1.1.1.10.2 snj int16_t *maxPow,int16_t *minPow); 56 1.1.1.1.10.2 snj int16_t ar2133GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c); 57 1.1.1.1.10.2 snj 58 1.1.1.1.10.2 snj static void 59 1.1.1.1.10.2 snj ar2133WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex, 60 1.1.1.1.10.2 snj int writes) 61 1.1.1.1.10.2 snj { 62 1.1.1.1.10.2 snj (void) ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_bb_rfgain, 63 1.1.1.1.10.2 snj freqIndex, writes); 64 1.1.1.1.10.2 snj } 65 1.1.1.1.10.2 snj 66 1.1.1.1.10.2 snj /* 67 1.1.1.1.10.2 snj * Take the MHz channel value and set the Channel value 68 1.1.1.1.10.2 snj * 69 1.1.1.1.10.2 snj * ASSUMES: Writes enabled to analog bus 70 1.1.1.1.10.2 snj */ 71 1.1.1.1.10.2 snj static HAL_BOOL 72 1.1.1.1.10.2 snj ar2133SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan) 73 1.1.1.1.10.2 snj { 74 1.1.1.1.10.2 snj uint32_t channelSel = 0; 75 1.1.1.1.10.2 snj uint32_t bModeSynth = 0; 76 1.1.1.1.10.2 snj uint32_t aModeRefSel = 0; 77 1.1.1.1.10.2 snj uint32_t reg32 = 0; 78 1.1.1.1.10.2 snj uint16_t freq; 79 1.1.1.1.10.2 snj CHAN_CENTERS centers; 80 1.1.1.1.10.2 snj 81 1.1.1.1.10.2 snj OS_MARK(ah, AH_MARK_SETCHANNEL, chan->channel); 82 1.1.1.1.10.2 snj 83 1.1.1.1.10.2 snj ar5416GetChannelCenters(ah, chan, ¢ers); 84 1.1.1.1.10.2 snj freq = centers.synth_center; 85 1.1.1.1.10.2 snj 86 1.1.1.1.10.2 snj if (freq < 4800) { 87 1.1.1.1.10.2 snj uint32_t txctl; 88 1.1.1.1.10.2 snj 89 1.1.1.1.10.2 snj if (((freq - 2192) % 5) == 0) { 90 1.1.1.1.10.2 snj channelSel = ((freq - 672) * 2 - 3040)/10; 91 1.1.1.1.10.2 snj bModeSynth = 0; 92 1.1.1.1.10.2 snj } else if (((freq - 2224) % 5) == 0) { 93 1.1.1.1.10.2 snj channelSel = ((freq - 704) * 2 - 3040) / 10; 94 1.1.1.1.10.2 snj bModeSynth = 1; 95 1.1.1.1.10.2 snj } else { 96 1.1.1.1.10.2 snj HALDEBUG(ah, HAL_DEBUG_ANY, 97 1.1.1.1.10.2 snj "%s: invalid channel %u MHz\n", __func__, freq); 98 1.1.1.1.10.2 snj return AH_FALSE; 99 1.1.1.1.10.2 snj } 100 1.1.1.1.10.2 snj 101 1.1.1.1.10.2 snj channelSel = (channelSel << 2) & 0xff; 102 1.1.1.1.10.2 snj channelSel = ath_hal_reverseBits(channelSel, 8); 103 1.1.1.1.10.2 snj 104 1.1.1.1.10.2 snj txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL); 105 1.1.1.1.10.2 snj if (freq == 2484) { 106 1.1.1.1.10.2 snj /* Enable channel spreading for channel 14 */ 107 1.1.1.1.10.2 snj OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 108 1.1.1.1.10.2 snj txctl | AR_PHY_CCK_TX_CTRL_JAPAN); 109 1.1.1.1.10.2 snj } else { 110 1.1.1.1.10.2 snj OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 111 1.1.1.1.10.2 snj txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN); 112 1.1.1.1.10.2 snj } 113 1.1.1.1.10.2 snj } else if ((freq % 20) == 0 && freq >= 5120) { 114 1.1.1.1.10.2 snj channelSel = ath_hal_reverseBits(((freq - 4800) / 20 << 2), 8); 115 1.1.1.1.10.2 snj if (AR_SREV_SOWL_10_OR_LATER(ah)) 116 1.1.1.1.10.2 snj aModeRefSel = ath_hal_reverseBits(3, 2); 117 1.1.1.1.10.2 snj else 118 1.1.1.1.10.2 snj aModeRefSel = ath_hal_reverseBits(1, 2); 119 1.1.1.1.10.2 snj } else if ((freq % 10) == 0) { 120 1.1.1.1.10.2 snj channelSel = ath_hal_reverseBits(((freq - 4800) / 10 << 1), 8); 121 1.1.1.1.10.2 snj if (AR_SREV_SOWL_10_OR_LATER(ah)) 122 1.1.1.1.10.2 snj aModeRefSel = ath_hal_reverseBits(2, 2); 123 1.1.1.1.10.2 snj else 124 1.1.1.1.10.2 snj aModeRefSel = ath_hal_reverseBits(1, 2); 125 1.1.1.1.10.2 snj } else if ((freq % 5) == 0) { 126 1.1.1.1.10.2 snj channelSel = ath_hal_reverseBits((freq - 4800) / 5, 8); 127 1.1.1.1.10.2 snj aModeRefSel = ath_hal_reverseBits(1, 2); 128 1.1.1.1.10.2 snj } else { 129 1.1.1.1.10.2 snj HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n", 130 1.1.1.1.10.2 snj __func__, freq); 131 1.1.1.1.10.2 snj return AH_FALSE; 132 1.1.1.1.10.2 snj } 133 1.1.1.1.10.2 snj 134 1.1.1.1.10.2 snj reg32 = (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) | 135 1.1.1.1.10.2 snj (1 << 5) | 0x1; 136 1.1.1.1.10.2 snj 137 1.1.1.1.10.2 snj OS_REG_WRITE(ah, AR_PHY(0x37), reg32); 138 1.1.1.1.10.2 snj 139 1.1.1.1.10.2 snj AH_PRIVATE(ah)->ah_curchan = chan; 140 1.1.1.1.10.2 snj return AH_TRUE; 141 1.1.1.1.10.2 snj 142 1.1.1.1.10.2 snj } 143 1.1.1.1.10.2 snj 144 1.1.1.1.10.2 snj /* 145 1.1.1.1.10.2 snj * Return a reference to the requested RF Bank. 146 1.1.1.1.10.2 snj */ 147 1.1.1.1.10.2 snj static uint32_t * 148 1.1.1.1.10.2 snj ar2133GetRfBank(struct ath_hal *ah, int bank) 149 1.1.1.1.10.2 snj { 150 1.1.1.1.10.2 snj struct ar2133State *priv = AR2133(ah); 151 1.1.1.1.10.2 snj 152 1.1.1.1.10.2 snj HALASSERT(priv != AH_NULL); 153 1.1.1.1.10.2 snj switch (bank) { 154 1.1.1.1.10.2 snj case 1: return priv->Bank1Data; 155 1.1.1.1.10.2 snj case 2: return priv->Bank2Data; 156 1.1.1.1.10.2 snj case 3: return priv->Bank3Data; 157 1.1.1.1.10.2 snj case 6: return priv->Bank6Data; 158 1.1.1.1.10.2 snj case 7: return priv->Bank7Data; 159 1.1.1.1.10.2 snj } 160 1.1.1.1.10.2 snj HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n", 161 1.1.1.1.10.2 snj __func__, bank); 162 1.1.1.1.10.2 snj return AH_NULL; 163 1.1.1.1.10.2 snj } 164 1.1.1.1.10.2 snj 165 1.1.1.1.10.2 snj /* 166 1.1.1.1.10.2 snj * Reads EEPROM header info from device structure and programs 167 1.1.1.1.10.2 snj * all rf registers 168 1.1.1.1.10.2 snj * 169 1.1.1.1.10.2 snj * REQUIRES: Access to the analog rf device 170 1.1.1.1.10.2 snj */ 171 1.1.1.1.10.2 snj static HAL_BOOL 172 1.1.1.1.10.2 snj ar2133SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, 173 1.1.1.1.10.2 snj uint16_t modesIndex, uint16_t *rfXpdGain) 174 1.1.1.1.10.2 snj { 175 1.1.1.1.10.2 snj struct ar2133State *priv = AR2133(ah); 176 1.1.1.1.10.2 snj int writes; 177 1.1.1.1.10.2 snj 178 1.1.1.1.10.2 snj HALASSERT(priv); 179 1.1.1.1.10.2 snj 180 1.1.1.1.10.2 snj /* Setup Bank 0 Write */ 181 1.1.1.1.10.2 snj ath_hal_ini_bank_setup(priv->Bank0Data, &AH5416(ah)->ah_ini_bank0, 1); 182 1.1.1.1.10.2 snj 183 1.1.1.1.10.2 snj /* Setup Bank 1 Write */ 184 1.1.1.1.10.2 snj ath_hal_ini_bank_setup(priv->Bank1Data, &AH5416(ah)->ah_ini_bank1, 1); 185 1.1.1.1.10.2 snj 186 1.1.1.1.10.2 snj /* Setup Bank 2 Write */ 187 1.1.1.1.10.2 snj ath_hal_ini_bank_setup(priv->Bank2Data, &AH5416(ah)->ah_ini_bank2, 1); 188 1.1.1.1.10.2 snj 189 1.1.1.1.10.2 snj /* Setup Bank 3 Write */ 190 1.1.1.1.10.2 snj ath_hal_ini_bank_setup(priv->Bank3Data, &AH5416(ah)->ah_ini_bank3, modesIndex); 191 1.1.1.1.10.2 snj 192 1.1.1.1.10.2 snj /* Setup Bank 6 Write */ 193 1.1.1.1.10.2 snj ath_hal_ini_bank_setup(priv->Bank6Data, &AH5416(ah)->ah_ini_bank6, modesIndex); 194 1.1.1.1.10.2 snj 195 1.1.1.1.10.2 snj /* Only the 5 or 2 GHz OB/DB need to be set for a mode */ 196 1.1.1.1.10.2 snj if (IS_CHAN_2GHZ(chan)) { 197 1.1.1.1.10.2 snj ar5416ModifyRfBuffer(priv->Bank6Data, 198 1.1.1.1.10.2 snj ath_hal_eepromGet(ah, AR_EEP_OB_2, AH_NULL), 3, 197, 0); 199 1.1.1.1.10.2 snj ar5416ModifyRfBuffer(priv->Bank6Data, 200 1.1.1.1.10.2 snj ath_hal_eepromGet(ah, AR_EEP_DB_2, AH_NULL), 3, 194, 0); 201 1.1.1.1.10.2 snj } else { 202 1.1.1.1.10.2 snj ar5416ModifyRfBuffer(priv->Bank6Data, 203 1.1.1.1.10.2 snj ath_hal_eepromGet(ah, AR_EEP_OB_5, AH_NULL), 3, 203, 0); 204 1.1.1.1.10.2 snj ar5416ModifyRfBuffer(priv->Bank6Data, 205 1.1.1.1.10.2 snj ath_hal_eepromGet(ah, AR_EEP_DB_5, AH_NULL), 3, 200, 0); 206 1.1.1.1.10.2 snj } 207 1.1.1.1.10.2 snj /* Setup Bank 7 Setup */ 208 1.1.1.1.10.2 snj ath_hal_ini_bank_setup(priv->Bank7Data, &AH5416(ah)->ah_ini_bank7, 1); 209 1.1.1.1.10.2 snj 210 1.1.1.1.10.2 snj /* Write Analog registers */ 211 1.1.1.1.10.2 snj writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank0, 212 1.1.1.1.10.2 snj priv->Bank0Data, 0); 213 1.1.1.1.10.2 snj writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank1, 214 1.1.1.1.10.2 snj priv->Bank1Data, writes); 215 1.1.1.1.10.2 snj writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank2, 216 1.1.1.1.10.2 snj priv->Bank2Data, writes); 217 1.1.1.1.10.2 snj writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank3, 218 1.1.1.1.10.2 snj priv->Bank3Data, writes); 219 1.1.1.1.10.2 snj writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank6, 220 1.1.1.1.10.2 snj priv->Bank6Data, writes); 221 1.1.1.1.10.2 snj (void) ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank7, 222 1.1.1.1.10.2 snj priv->Bank7Data, writes); 223 1.1.1.1.10.2 snj 224 1.1.1.1.10.2 snj return AH_TRUE; 225 1.1.1.1.10.2 snj #undef RF_BANK_SETUP 226 1.1.1.1.10.2 snj } 227 1.1.1.1.10.2 snj 228 1.1.1.1.10.2 snj /* 229 1.1.1.1.10.2 snj * Read the transmit power levels from the structures taken from EEPROM 230 1.1.1.1.10.2 snj * Interpolate read transmit power values for this channel 231 1.1.1.1.10.2 snj * Organize the transmit power values into a table for writing into the hardware 232 1.1.1.1.10.2 snj */ 233 1.1.1.1.10.2 snj 234 1.1.1.1.10.2 snj static HAL_BOOL 235 1.1.1.1.10.2 snj ar2133SetPowerTable(struct ath_hal *ah, int16_t *pPowerMin, int16_t *pPowerMax, 236 1.1.1.1.10.2 snj HAL_CHANNEL_INTERNAL *chan, uint16_t *rfXpdGain) 237 1.1.1.1.10.2 snj { 238 1.1.1.1.10.2 snj return AH_TRUE; 239 1.1.1.1.10.2 snj } 240 1.1.1.1.10.2 snj 241 1.1.1.1.10.2 snj #if 0 242 1.1.1.1.10.2 snj static int16_t 243 1.1.1.1.10.2 snj ar2133GetMinPower(struct ath_hal *ah, EXPN_DATA_PER_CHANNEL_5112 *data) 244 1.1.1.1.10.2 snj { 245 1.1.1.1.10.2 snj int i, minIndex; 246 1.1.1.1.10.2 snj int16_t minGain,minPwr,minPcdac,retVal; 247 1.1.1.1.10.2 snj 248 1.1.1.1.10.2 snj /* Assume NUM_POINTS_XPD0 > 0 */ 249 1.1.1.1.10.2 snj minGain = data->pDataPerXPD[0].xpd_gain; 250 1.1.1.1.10.2 snj for (minIndex=0,i=1; i<NUM_XPD_PER_CHANNEL; i++) { 251 1.1.1.1.10.2 snj if (data->pDataPerXPD[i].xpd_gain < minGain) { 252 1.1.1.1.10.2 snj minIndex = i; 253 1.1.1.1.10.2 snj minGain = data->pDataPerXPD[i].xpd_gain; 254 1.1.1.1.10.2 snj } 255 1.1.1.1.10.2 snj } 256 1.1.1.1.10.2 snj minPwr = data->pDataPerXPD[minIndex].pwr_t4[0]; 257 1.1.1.1.10.2 snj minPcdac = data->pDataPerXPD[minIndex].pcdac[0]; 258 1.1.1.1.10.2 snj for (i=1; i<NUM_POINTS_XPD0; i++) { 259 1.1.1.1.10.2 snj if (data->pDataPerXPD[minIndex].pwr_t4[i] < minPwr) { 260 1.1.1.1.10.2 snj minPwr = data->pDataPerXPD[minIndex].pwr_t4[i]; 261 1.1.1.1.10.2 snj minPcdac = data->pDataPerXPD[minIndex].pcdac[i]; 262 1.1.1.1.10.2 snj } 263 1.1.1.1.10.2 snj } 264 1.1.1.1.10.2 snj retVal = minPwr - (minPcdac*2); 265 1.1.1.1.10.2 snj return(retVal); 266 1.1.1.1.10.2 snj } 267 1.1.1.1.10.2 snj #endif 268 1.1.1.1.10.2 snj 269 1.1.1.1.10.2 snj static HAL_BOOL 270 1.1.1.1.10.2 snj ar2133GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan, int16_t *maxPow, 271 1.1.1.1.10.2 snj int16_t *minPow) 272 1.1.1.1.10.2 snj { 273 1.1.1.1.10.2 snj #if 0 274 1.1.1.1.10.2 snj struct ath_hal_5212 *ahp = AH5212(ah); 275 1.1.1.1.10.2 snj int numChannels=0,i,last; 276 1.1.1.1.10.2 snj int totalD, totalF,totalMin; 277 1.1.1.1.10.2 snj EXPN_DATA_PER_CHANNEL_5112 *data=AH_NULL; 278 1.1.1.1.10.2 snj EEPROM_POWER_EXPN_5112 *powerArray=AH_NULL; 279 1.1.1.1.10.2 snj 280 1.1.1.1.10.2 snj *maxPow = 0; 281 1.1.1.1.10.2 snj if (IS_CHAN_A(chan)) { 282 1.1.1.1.10.2 snj powerArray = ahp->ah_modePowerArray5112; 283 1.1.1.1.10.2 snj data = powerArray[headerInfo11A].pDataPerChannel; 284 1.1.1.1.10.2 snj numChannels = powerArray[headerInfo11A].numChannels; 285 1.1.1.1.10.2 snj } else if (IS_CHAN_G(chan) || IS_CHAN_108G(chan)) { 286 1.1.1.1.10.2 snj /* XXX - is this correct? Should we also use the same power for turbo G? */ 287 1.1.1.1.10.2 snj powerArray = ahp->ah_modePowerArray5112; 288 1.1.1.1.10.2 snj data = powerArray[headerInfo11G].pDataPerChannel; 289 1.1.1.1.10.2 snj numChannels = powerArray[headerInfo11G].numChannels; 290 1.1.1.1.10.2 snj } else if (IS_CHAN_B(chan)) { 291 1.1.1.1.10.2 snj powerArray = ahp->ah_modePowerArray5112; 292 1.1.1.1.10.2 snj data = powerArray[headerInfo11B].pDataPerChannel; 293 1.1.1.1.10.2 snj numChannels = powerArray[headerInfo11B].numChannels; 294 1.1.1.1.10.2 snj } else { 295 1.1.1.1.10.2 snj return (AH_TRUE); 296 1.1.1.1.10.2 snj } 297 1.1.1.1.10.2 snj /* Make sure the channel is in the range of the TP values 298 1.1.1.1.10.2 snj * (freq piers) 299 1.1.1.1.10.2 snj */ 300 1.1.1.1.10.2 snj if ((numChannels < 1) || 301 1.1.1.1.10.2 snj (chan->channel < data[0].channelValue) || 302 1.1.1.1.10.2 snj (chan->channel > data[numChannels-1].channelValue)) 303 1.1.1.1.10.2 snj return(AH_FALSE); 304 1.1.1.1.10.2 snj 305 1.1.1.1.10.2 snj /* Linearly interpolate the power value now */ 306 1.1.1.1.10.2 snj for (last=0,i=0; 307 1.1.1.1.10.2 snj (i<numChannels) && (chan->channel > data[i].channelValue); 308 1.1.1.1.10.2 snj last=i++); 309 1.1.1.1.10.2 snj totalD = data[i].channelValue - data[last].channelValue; 310 1.1.1.1.10.2 snj if (totalD > 0) { 311 1.1.1.1.10.2 snj totalF = data[i].maxPower_t4 - data[last].maxPower_t4; 312 1.1.1.1.10.2 snj *maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) + data[last].maxPower_t4*totalD)/totalD); 313 1.1.1.1.10.2 snj 314 1.1.1.1.10.2 snj totalMin = ar2133GetMinPower(ah,&data[i]) - ar2133GetMinPower(ah, &data[last]); 315 1.1.1.1.10.2 snj *minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) + ar2133GetMinPower(ah, &data[last])*totalD)/totalD); 316 1.1.1.1.10.2 snj return (AH_TRUE); 317 1.1.1.1.10.2 snj } else { 318 1.1.1.1.10.2 snj if (chan->channel == data[i].channelValue) { 319 1.1.1.1.10.2 snj *maxPow = data[i].maxPower_t4; 320 1.1.1.1.10.2 snj *minPow = ar2133GetMinPower(ah, &data[i]); 321 1.1.1.1.10.2 snj return(AH_TRUE); 322 1.1.1.1.10.2 snj } else 323 1.1.1.1.10.2 snj return(AH_FALSE); 324 1.1.1.1.10.2 snj } 325 1.1.1.1.10.2 snj #else 326 1.1.1.1.10.2 snj *maxPow = *minPow = 0; 327 1.1.1.1.10.2 snj return AH_FALSE; 328 1.1.1.1.10.2 snj #endif 329 1.1.1.1.10.2 snj } 330 1.1.1.1.10.2 snj 331 1.1.1.1.10.2 snj static void 332 1.1.1.1.10.2 snj ar2133GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[]) 333 1.1.1.1.10.2 snj { 334 1.1.1.1.10.2 snj struct ath_hal_5416 *ahp = AH5416(ah); 335 1.1.1.1.10.2 snj int16_t nf; 336 1.1.1.1.10.2 snj 337 1.1.1.1.10.2 snj switch (ahp->ah_rx_chainmask) { 338 1.1.1.1.10.2 snj case 0x7: 339 1.1.1.1.10.2 snj nf = MS(OS_REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR); 340 1.1.1.1.10.2 snj if (nf & 0x100) 341 1.1.1.1.10.2 snj nf = 0 - ((nf ^ 0x1ff) + 1); 342 1.1.1.1.10.2 snj HALDEBUG(ah, HAL_DEBUG_NFCAL, 343 1.1.1.1.10.2 snj "NF calibrated [ctl] [chain 2] is %d\n", nf); 344 1.1.1.1.10.2 snj nfarray[4] = nf; 345 1.1.1.1.10.2 snj 346 1.1.1.1.10.2 snj nf = MS(OS_REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR); 347 1.1.1.1.10.2 snj if (nf & 0x100) 348 1.1.1.1.10.2 snj nf = 0 - ((nf ^ 0x1ff) + 1); 349 1.1.1.1.10.2 snj HALDEBUG(ah, HAL_DEBUG_NFCAL, 350 1.1.1.1.10.2 snj "NF calibrated [ext] [chain 2] is %d\n", nf); 351 1.1.1.1.10.2 snj nfarray[5] = nf; 352 1.1.1.1.10.2 snj /* fall thru... */ 353 1.1.1.1.10.2 snj case 0x3: 354 1.1.1.1.10.2 snj case 0x5: 355 1.1.1.1.10.2 snj nf = MS(OS_REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR); 356 1.1.1.1.10.2 snj if (nf & 0x100) 357 1.1.1.1.10.2 snj nf = 0 - ((nf ^ 0x1ff) + 1); 358 1.1.1.1.10.2 snj HALDEBUG(ah, HAL_DEBUG_NFCAL, 359 1.1.1.1.10.2 snj "NF calibrated [ctl] [chain 1] is %d\n", nf); 360 1.1.1.1.10.2 snj nfarray[2] = nf; 361 1.1.1.1.10.2 snj 362 1.1.1.1.10.2 snj 363 1.1.1.1.10.2 snj nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR); 364 1.1.1.1.10.2 snj if (nf & 0x100) 365 1.1.1.1.10.2 snj nf = 0 - ((nf ^ 0x1ff) + 1); 366 1.1.1.1.10.2 snj HALDEBUG(ah, HAL_DEBUG_NFCAL, 367 1.1.1.1.10.2 snj "NF calibrated [ext] [chain 1] is %d\n", nf); 368 1.1.1.1.10.2 snj nfarray[3] = nf; 369 1.1.1.1.10.2 snj /* fall thru... */ 370 1.1.1.1.10.2 snj case 0x1: 371 1.1.1.1.10.2 snj nf = MS(OS_REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); 372 1.1.1.1.10.2 snj if (nf & 0x100) 373 1.1.1.1.10.2 snj nf = 0 - ((nf ^ 0x1ff) + 1); 374 1.1.1.1.10.2 snj HALDEBUG(ah, HAL_DEBUG_NFCAL, 375 1.1.1.1.10.2 snj "NF calibrated [ctl] [chain 0] is %d\n", nf); 376 1.1.1.1.10.2 snj nfarray[0] = nf; 377 1.1.1.1.10.2 snj 378 1.1.1.1.10.2 snj nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR); 379 1.1.1.1.10.2 snj if (nf & 0x100) 380 1.1.1.1.10.2 snj nf = 0 - ((nf ^ 0x1ff) + 1); 381 1.1.1.1.10.2 snj HALDEBUG(ah, HAL_DEBUG_NFCAL, 382 1.1.1.1.10.2 snj "NF calibrated [ext] [chain 0] is %d\n", nf); 383 1.1.1.1.10.2 snj nfarray[1] = nf; 384 1.1.1.1.10.2 snj 385 1.1.1.1.10.2 snj break; 386 1.1.1.1.10.2 snj } 387 1.1.1.1.10.2 snj } 388 1.1.1.1.10.2 snj 389 1.1.1.1.10.2 snj /* 390 1.1.1.1.10.2 snj * Adjust NF based on statistical values for 5GHz frequencies. 391 1.1.1.1.10.2 snj * Stubbed:Not used by Fowl 392 1.1.1.1.10.2 snj */ 393 1.1.1.1.10.2 snj int16_t 394 1.1.1.1.10.2 snj ar2133GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c) 395 1.1.1.1.10.2 snj { 396 1.1.1.1.10.2 snj return 0; 397 1.1.1.1.10.2 snj } 398 1.1.1.1.10.2 snj 399 1.1.1.1.10.2 snj /* 400 1.1.1.1.10.2 snj * Free memory for analog bank scratch buffers 401 1.1.1.1.10.2 snj */ 402 1.1.1.1.10.2 snj static void 403 1.1.1.1.10.2 snj ar2133RfDetach(struct ath_hal *ah) 404 1.1.1.1.10.2 snj { 405 1.1.1.1.10.2 snj struct ath_hal_5212 *ahp = AH5212(ah); 406 1.1.1.1.10.2 snj 407 1.1.1.1.10.2 snj HALASSERT(ahp->ah_rfHal != AH_NULL); 408 1.1.1.1.10.2 snj ath_hal_free(ahp->ah_rfHal); 409 1.1.1.1.10.2 snj ahp->ah_rfHal = AH_NULL; 410 1.1.1.1.10.2 snj } 411 1.1.1.1.10.2 snj 412 1.1.1.1.10.2 snj /* 413 1.1.1.1.10.2 snj * Allocate memory for analog bank scratch buffers 414 1.1.1.1.10.2 snj * Scratch Buffer will be reinitialized every reset so no need to zero now 415 1.1.1.1.10.2 snj */ 416 1.1.1.1.10.2 snj HAL_BOOL 417 1.1.1.1.10.2 snj ar2133RfAttach(struct ath_hal *ah, HAL_STATUS *status) 418 1.1.1.1.10.2 snj { 419 1.1.1.1.10.2 snj struct ath_hal_5212 *ahp = AH5212(ah); 420 1.1.1.1.10.2 snj struct ar2133State *priv; 421 1.1.1.1.10.2 snj uint32_t *bankData; 422 1.1.1.1.10.2 snj 423 1.1.1.1.10.2 snj HALASSERT(ahp->ah_rfHal == AH_NULL); 424 1.1.1.1.10.2 snj priv = ath_hal_malloc(sizeof(struct ar2133State) 425 1.1.1.1.10.2 snj + AH5416(ah)->ah_ini_bank0.rows * sizeof(uint32_t) 426 1.1.1.1.10.2 snj + AH5416(ah)->ah_ini_bank1.rows * sizeof(uint32_t) 427 1.1.1.1.10.2 snj + AH5416(ah)->ah_ini_bank2.rows * sizeof(uint32_t) 428 1.1.1.1.10.2 snj + AH5416(ah)->ah_ini_bank3.rows * sizeof(uint32_t) 429 1.1.1.1.10.2 snj + AH5416(ah)->ah_ini_bank6.rows * sizeof(uint32_t) 430 1.1.1.1.10.2 snj + AH5416(ah)->ah_ini_bank7.rows * sizeof(uint32_t) 431 1.1.1.1.10.2 snj ); 432 1.1.1.1.10.2 snj if (priv == AH_NULL) { 433 1.1.1.1.10.2 snj HALDEBUG(ah, HAL_DEBUG_ANY, 434 1.1.1.1.10.2 snj "%s: cannot allocate private state\n", __func__); 435 1.1.1.1.10.2 snj *status = HAL_ENOMEM; /* XXX */ 436 1.1.1.1.10.2 snj return AH_FALSE; 437 1.1.1.1.10.2 snj } 438 1.1.1.1.10.2 snj priv->base.rfDetach = ar2133RfDetach; 439 1.1.1.1.10.2 snj priv->base.writeRegs = ar2133WriteRegs; 440 1.1.1.1.10.2 snj priv->base.getRfBank = ar2133GetRfBank; 441 1.1.1.1.10.2 snj priv->base.setChannel = ar2133SetChannel; 442 1.1.1.1.10.2 snj priv->base.setRfRegs = ar2133SetRfRegs; 443 1.1.1.1.10.2 snj priv->base.setPowerTable = ar2133SetPowerTable; 444 1.1.1.1.10.2 snj priv->base.getChannelMaxMinPower = ar2133GetChannelMaxMinPower; 445 1.1.1.1.10.2 snj priv->base.getNfAdjust = ar2133GetNfAdjust; 446 1.1.1.1.10.2 snj 447 1.1.1.1.10.2 snj bankData = (uint32_t *) &priv[1]; 448 1.1.1.1.10.2 snj priv->Bank0Data = bankData, bankData += AH5416(ah)->ah_ini_bank0.rows; 449 1.1.1.1.10.2 snj priv->Bank1Data = bankData, bankData += AH5416(ah)->ah_ini_bank1.rows; 450 1.1.1.1.10.2 snj priv->Bank2Data = bankData, bankData += AH5416(ah)->ah_ini_bank2.rows; 451 1.1.1.1.10.2 snj priv->Bank3Data = bankData, bankData += AH5416(ah)->ah_ini_bank3.rows; 452 1.1.1.1.10.2 snj priv->Bank6Data = bankData, bankData += AH5416(ah)->ah_ini_bank6.rows; 453 1.1.1.1.10.2 snj priv->Bank7Data = bankData, bankData += AH5416(ah)->ah_ini_bank7.rows; 454 1.1.1.1.10.2 snj 455 1.1.1.1.10.2 snj ahp->ah_pcdacTable = priv->pcdacTable; 456 1.1.1.1.10.2 snj ahp->ah_pcdacTableSize = sizeof(priv->pcdacTable); 457 1.1.1.1.10.2 snj ahp->ah_rfHal = &priv->base; 458 1.1.1.1.10.2 snj /* 459 1.1.1.1.10.2 snj * Set noise floor adjust method; we arrange a 460 1.1.1.1.10.2 snj * direct call instead of thunking. 461 1.1.1.1.10.2 snj */ 462 1.1.1.1.10.2 snj AH_PRIVATE(ah)->ah_getNfAdjust = priv->base.getNfAdjust; 463 1.1.1.1.10.2 snj AH_PRIVATE(ah)->ah_getNoiseFloor = ar2133GetNoiseFloor; 464 1.1.1.1.10.2 snj 465 1.1.1.1.10.2 snj return AH_TRUE; 466 1.1.1.1.10.2 snj } 467
Indexes created Thu Oct 30 16:09:53 GMT 2025