ar5416.h revision 1.1.1.1.10.2
1 1.1.1.1.10.2 snj /* 2 1.1.1.1.10.2 snj * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 1.1.1.1.10.2 snj * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 1.1.1.1.10.2 snj * 5 1.1.1.1.10.2 snj * Permission to use, copy, modify, and/or distribute this software for any 6 1.1.1.1.10.2 snj * purpose with or without fee is hereby granted, provided that the above 7 1.1.1.1.10.2 snj * copyright notice and this permission notice appear in all copies. 8 1.1.1.1.10.2 snj * 9 1.1.1.1.10.2 snj * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 1.1.1.1.10.2 snj * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 1.1.1.1.10.2 snj * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 1.1.1.1.10.2 snj * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 1.1.1.1.10.2 snj * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 1.1.1.1.10.2 snj * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 1.1.1.1.10.2 snj * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 1.1.1.1.10.2 snj * 17 1.1.1.1.10.2 snj * $Id: ar5416.h,v 1.1.1.1.10.2 2009/08/07 06:43:46 snj Exp $ 18 1.1.1.1.10.2 snj */ 19 1.1.1.1.10.2 snj #ifndef _ATH_AR5416_H_ 20 1.1.1.1.10.2 snj #define _ATH_AR5416_H_ 21 1.1.1.1.10.2 snj 22 1.1.1.1.10.2 snj #include "ar5212/ar5212.h" 23 1.1.1.1.10.2 snj #include "ar5416_cal.h" 24 1.1.1.1.10.2 snj 25 1.1.1.1.10.2 snj #define AR5416_MAGIC 0x20065416 26 1.1.1.1.10.2 snj 27 1.1.1.1.10.2 snj enum { 28 1.1.1.1.10.2 snj HAL_RESET_POWER_ON, 29 1.1.1.1.10.2 snj HAL_RESET_WARM, 30 1.1.1.1.10.2 snj HAL_RESET_COLD, 31 1.1.1.1.10.2 snj }; 32 1.1.1.1.10.2 snj 33 1.1.1.1.10.2 snj typedef struct { 34 1.1.1.1.10.2 snj uint16_t synth_center; 35 1.1.1.1.10.2 snj uint16_t ctl_center; 36 1.1.1.1.10.2 snj uint16_t ext_center; 37 1.1.1.1.10.2 snj } CHAN_CENTERS; 38 1.1.1.1.10.2 snj 39 1.1.1.1.10.2 snj #define AR5416_DEFAULT_RXCHAINMASK 7 40 1.1.1.1.10.2 snj #define AR5416_DEFAULT_TXCHAINMASK 1 41 1.1.1.1.10.2 snj #define AR5416_MAX_RATE_POWER 63 42 1.1.1.1.10.2 snj #define AR5416_KEYTABLE_SIZE 128 43 1.1.1.1.10.2 snj 44 1.1.1.1.10.2 snj #define AR5416_CCA_MAX_GOOD_VALUE -85 45 1.1.1.1.10.2 snj #define AR5416_CCA_MAX_HIGH_VALUE -62 46 1.1.1.1.10.2 snj #define AR5416_CCA_MIN_BAD_VALUE -140 47 1.1.1.1.10.2 snj 48 1.1.1.1.10.2 snj struct ath_hal_5416 { 49 1.1.1.1.10.2 snj struct ath_hal_5212 ah_5212; 50 1.1.1.1.10.2 snj 51 1.1.1.1.10.2 snj /* NB: RF data setup at attach */ 52 1.1.1.1.10.2 snj HAL_INI_ARRAY ah_ini_bb_rfgain; 53 1.1.1.1.10.2 snj HAL_INI_ARRAY ah_ini_bank0; 54 1.1.1.1.10.2 snj HAL_INI_ARRAY ah_ini_bank1; 55 1.1.1.1.10.2 snj HAL_INI_ARRAY ah_ini_bank2; 56 1.1.1.1.10.2 snj HAL_INI_ARRAY ah_ini_bank3; 57 1.1.1.1.10.2 snj HAL_INI_ARRAY ah_ini_bank6; 58 1.1.1.1.10.2 snj HAL_INI_ARRAY ah_ini_bank7; 59 1.1.1.1.10.2 snj HAL_INI_ARRAY ah_ini_addac; 60 1.1.1.1.10.2 snj 61 1.1.1.1.10.2 snj u_int ah_globaltxtimeout; /* global tx timeout */ 62 1.1.1.1.10.2 snj int ah_hangs; /* h/w hangs state */ 63 1.1.1.1.10.2 snj uint8_t ah_keytype[AR5416_KEYTABLE_SIZE]; 64 1.1.1.1.10.2 snj /* 65 1.1.1.1.10.2 snj * Extension Channel Rx Clear State 66 1.1.1.1.10.2 snj */ 67 1.1.1.1.10.2 snj uint32_t ah_cycleCount; 68 1.1.1.1.10.2 snj uint32_t ah_ctlBusy; 69 1.1.1.1.10.2 snj uint32_t ah_extBusy; 70 1.1.1.1.10.2 snj uint32_t ah_rx_chainmask; 71 1.1.1.1.10.2 snj uint32_t ah_tx_chainmask; 72 1.1.1.1.10.2 snj 73 1.1.1.1.10.2 snj struct ar5416PerCal ah_cal; /* periodic calibration state */ 74 1.1.1.1.10.2 snj }; 75 1.1.1.1.10.2 snj #define AH5416(_ah) ((struct ath_hal_5416 *)(_ah)) 76 1.1.1.1.10.2 snj 77 1.1.1.1.10.2 snj #define IS_5416_PCI(ah) ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_VERSION_OWL_PCI) 78 1.1.1.1.10.2 snj #define IS_5416_PCIE(ah) ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_VERSION_OWL_PCIE) 79 1.1.1.1.10.2 snj #undef IS_PCIE 80 1.1.1.1.10.2 snj #define IS_PCIE(ah) (IS_5416_PCIE(ah)) 81 1.1.1.1.10.2 snj 82 1.1.1.1.10.2 snj extern HAL_BOOL ar2133RfAttach(struct ath_hal *, HAL_STATUS *); 83 1.1.1.1.10.2 snj 84 1.1.1.1.10.2 snj struct ath_hal; 85 1.1.1.1.10.2 snj 86 1.1.1.1.10.2 snj extern struct ath_hal * ar5416Attach(uint16_t devid, HAL_SOFTC sc, 87 1.1.1.1.10.2 snj HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status); 88 1.1.1.1.10.2 snj extern void ar5416InitState(struct ath_hal_5416 *, uint16_t devid, 89 1.1.1.1.10.2 snj HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh, 90 1.1.1.1.10.2 snj HAL_STATUS *status); 91 1.1.1.1.10.2 snj extern void ar5416Detach(struct ath_hal *ah); 92 1.1.1.1.10.2 snj extern HAL_BOOL ar5416FillCapabilityInfo(struct ath_hal *ah); 93 1.1.1.1.10.2 snj 94 1.1.1.1.10.2 snj #define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \ 95 1.1.1.1.10.2 snj (IS_CHAN_5GHZ(_c) && ath_hal_eepromGetFlag(ah, AR_EEP_FSTCLK_5G)) 96 1.1.1.1.10.2 snj 97 1.1.1.1.10.2 snj extern void ar5416AniAttach(struct ath_hal *, const struct ar5212AniParams *, 98 1.1.1.1.10.2 snj const struct ar5212AniParams *, HAL_BOOL ena); 99 1.1.1.1.10.2 snj extern void ar5416AniDetach(struct ath_hal *); 100 1.1.1.1.10.2 snj extern HAL_BOOL ar5416AniControl(struct ath_hal *, HAL_ANI_CMD cmd, int param); 101 1.1.1.1.10.2 snj extern HAL_BOOL ar5416AniSetParams(struct ath_hal *, 102 1.1.1.1.10.2 snj const struct ar5212AniParams *, const struct ar5212AniParams *); 103 1.1.1.1.10.2 snj extern void ar5416ProcessMibIntr(struct ath_hal *, const HAL_NODE_STATS *); 104 1.1.1.1.10.2 snj extern void ar5416AniPoll(struct ath_hal *, const HAL_NODE_STATS *, 105 1.1.1.1.10.2 snj HAL_CHANNEL *); 106 1.1.1.1.10.2 snj extern void ar5416AniReset(struct ath_hal *, HAL_CHANNEL_INTERNAL *, 107 1.1.1.1.10.2 snj HAL_OPMODE, int); 108 1.1.1.1.10.2 snj 109 1.1.1.1.10.2 snj extern void ar5416SetBeaconTimers(struct ath_hal *, const HAL_BEACON_TIMERS *); 110 1.1.1.1.10.2 snj extern void ar5416BeaconInit(struct ath_hal *ah, 111 1.1.1.1.10.2 snj uint32_t next_beacon, uint32_t beacon_period); 112 1.1.1.1.10.2 snj extern void ar5416ResetStaBeaconTimers(struct ath_hal *ah); 113 1.1.1.1.10.2 snj extern void ar5416SetStaBeaconTimers(struct ath_hal *ah, 114 1.1.1.1.10.2 snj const HAL_BEACON_STATE *); 115 1.1.1.1.10.2 snj 116 1.1.1.1.10.2 snj extern HAL_BOOL ar5416EepromRead(struct ath_hal *, u_int off, uint16_t *data); 117 1.1.1.1.10.2 snj extern HAL_BOOL ar5416EepromWrite(struct ath_hal *, u_int off, uint16_t data); 118 1.1.1.1.10.2 snj 119 1.1.1.1.10.2 snj extern HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah); 120 1.1.1.1.10.2 snj extern HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *, HAL_INT *masked); 121 1.1.1.1.10.2 snj extern HAL_INT ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints); 122 1.1.1.1.10.2 snj 123 1.1.1.1.10.2 snj extern HAL_BOOL ar5416GpioCfgOutput(struct ath_hal *, uint32_t gpio); 124 1.1.1.1.10.2 snj extern HAL_BOOL ar5416GpioCfgInput(struct ath_hal *, uint32_t gpio); 125 1.1.1.1.10.2 snj extern HAL_BOOL ar5416GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val); 126 1.1.1.1.10.2 snj extern uint32_t ar5416GpioGet(struct ath_hal *ah, uint32_t gpio); 127 1.1.1.1.10.2 snj extern void ar5416GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel); 128 1.1.1.1.10.2 snj 129 1.1.1.1.10.2 snj extern u_int ar5416GetWirelessModes(struct ath_hal *ah); 130 1.1.1.1.10.2 snj extern void ar5416SetLedState(struct ath_hal *ah, HAL_LED_STATE state); 131 1.1.1.1.10.2 snj extern void ar5416ResetTsf(struct ath_hal *ah); 132 1.1.1.1.10.2 snj extern HAL_BOOL ar5416SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING); 133 1.1.1.1.10.2 snj extern HAL_BOOL ar5416SetDecompMask(struct ath_hal *, uint16_t, int); 134 1.1.1.1.10.2 snj extern void ar5416SetCoverageClass(struct ath_hal *, uint8_t, int); 135 1.1.1.1.10.2 snj extern uint32_t ar5416Get11nExtBusy(struct ath_hal *ah); 136 1.1.1.1.10.2 snj extern void ar5416Set11nMac2040(struct ath_hal *ah, HAL_HT_MACMODE mode); 137 1.1.1.1.10.2 snj extern HAL_HT_RXCLEAR ar5416Get11nRxClear(struct ath_hal *ah); 138 1.1.1.1.10.2 snj extern void ar5416Set11nRxClear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear); 139 1.1.1.1.10.2 snj extern HAL_STATUS ar5416GetCapability(struct ath_hal *ah, 140 1.1.1.1.10.2 snj HAL_CAPABILITY_TYPE type, uint32_t capability, uint32_t *result); 141 1.1.1.1.10.2 snj extern HAL_BOOL ar5416GetDiagState(struct ath_hal *ah, int request, 142 1.1.1.1.10.2 snj const void *args, uint32_t argsize, 143 1.1.1.1.10.2 snj void **result, uint32_t *resultsize); 144 1.1.1.1.10.2 snj 145 1.1.1.1.10.2 snj extern HAL_BOOL ar5416SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, 146 1.1.1.1.10.2 snj int setChip); 147 1.1.1.1.10.2 snj extern HAL_POWER_MODE ar5416GetPowerMode(struct ath_hal *ah); 148 1.1.1.1.10.2 snj extern HAL_BOOL ar5416GetPowerStatus(struct ath_hal *ah); 149 1.1.1.1.10.2 snj 150 1.1.1.1.10.2 snj extern HAL_BOOL ar5416ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry); 151 1.1.1.1.10.2 snj extern HAL_BOOL ar5416SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry, 152 1.1.1.1.10.2 snj const HAL_KEYVAL *k, const uint8_t *mac, int xorKey); 153 1.1.1.1.10.2 snj 154 1.1.1.1.10.2 snj extern void ar5416StartPcuReceive(struct ath_hal *ah); 155 1.1.1.1.10.2 snj extern void ar5416StopPcuReceive(struct ath_hal *ah); 156 1.1.1.1.10.2 snj extern HAL_BOOL ar5416SetupRxDesc(struct ath_hal *, 157 1.1.1.1.10.2 snj struct ath_desc *, uint32_t size, u_int flags); 158 1.1.1.1.10.2 snj extern HAL_STATUS ar5416ProcRxDesc(struct ath_hal *ah, struct ath_desc *, 159 1.1.1.1.10.2 snj uint32_t, struct ath_desc *, uint64_t, 160 1.1.1.1.10.2 snj struct ath_rx_status *); 161 1.1.1.1.10.2 snj 162 1.1.1.1.10.2 snj extern HAL_BOOL ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode, 163 1.1.1.1.10.2 snj HAL_CHANNEL *chan, HAL_BOOL bChannelChange, HAL_STATUS *status); 164 1.1.1.1.10.2 snj extern HAL_BOOL ar5416PhyDisable(struct ath_hal *ah); 165 1.1.1.1.10.2 snj extern HAL_RFGAIN ar5416GetRfgain(struct ath_hal *ah); 166 1.1.1.1.10.2 snj extern HAL_BOOL ar5416Disable(struct ath_hal *ah); 167 1.1.1.1.10.2 snj extern HAL_BOOL ar5416ChipReset(struct ath_hal *ah, HAL_CHANNEL *); 168 1.1.1.1.10.2 snj extern HAL_BOOL ar5416SetResetReg(struct ath_hal *, uint32_t type); 169 1.1.1.1.10.2 snj extern HAL_BOOL ar5416SetTxPowerLimit(struct ath_hal *ah, uint32_t limit); 170 1.1.1.1.10.2 snj extern HAL_BOOL ar5416GetChipPowerLimits(struct ath_hal *ah, 171 1.1.1.1.10.2 snj HAL_CHANNEL *chans, uint32_t nchans); 172 1.1.1.1.10.2 snj extern void ar5416GetChannelCenters(struct ath_hal *, 173 1.1.1.1.10.2 snj HAL_CHANNEL_INTERNAL *chan, CHAN_CENTERS *centers); 174 1.1.1.1.10.2 snj 175 1.1.1.1.10.2 snj extern HAL_BOOL ar5416StopTxDma(struct ath_hal *ah, u_int q); 176 1.1.1.1.10.2 snj extern HAL_BOOL ar5416SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds, 177 1.1.1.1.10.2 snj u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower, 178 1.1.1.1.10.2 snj u_int txRate0, u_int txTries0, 179 1.1.1.1.10.2 snj u_int keyIx, u_int antMode, u_int flags, 180 1.1.1.1.10.2 snj u_int rtsctsRate, u_int rtsctsDuration, 181 1.1.1.1.10.2 snj u_int compicvLen, u_int compivLen, u_int comp); 182 1.1.1.1.10.2 snj extern HAL_BOOL ar5416SetupXTxDesc(struct ath_hal *, struct ath_desc *, 183 1.1.1.1.10.2 snj u_int txRate1, u_int txRetries1, 184 1.1.1.1.10.2 snj u_int txRate2, u_int txRetries2, 185 1.1.1.1.10.2 snj u_int txRate3, u_int txRetries3); 186 1.1.1.1.10.2 snj extern HAL_BOOL ar5416FillTxDesc(struct ath_hal *ah, struct ath_desc *ds, 187 1.1.1.1.10.2 snj u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg, 188 1.1.1.1.10.2 snj const struct ath_desc *ds0); 189 1.1.1.1.10.2 snj extern HAL_STATUS ar5416ProcTxDesc(struct ath_hal *ah, 190 1.1.1.1.10.2 snj struct ath_desc *, struct ath_tx_status *); 191 1.1.1.1.10.2 snj 192 1.1.1.1.10.2 snj extern const HAL_RATE_TABLE *ar5416GetRateTable(struct ath_hal *, u_int mode); 193 1.1.1.1.10.2 snj #endif /* _ATH_AR5416_H_ */ 194
Indexes created Tue Oct 28 09:09:52 GMT 2025