1 1.1 alc /* 2 1.1 alc * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 1.1 alc * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 1.1 alc * 5 1.1 alc * Permission to use, copy, modify, and/or distribute this software for any 6 1.1 alc * purpose with or without fee is hereby granted, provided that the above 7 1.1 alc * copyright notice and this permission notice appear in all copies. 8 1.1 alc * 9 1.1 alc * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 1.1 alc * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 1.1 alc * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 1.1 alc * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 1.1 alc * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 1.1 alc * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 1.1 alc * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 1.1 alc * 17 1.1 alc * $Id: ar5416_cal_adcgain.c,v 1.1.1.1 2008/12/11 04:46:48 alc Exp $ 18 1.1 alc */ 19 1.1 alc #include "opt_ah.h" 20 1.1 alc 21 1.1 alc #include "ah.h" 22 1.1 alc #include "ah_internal.h" 23 1.1 alc #include "ah_devid.h" 24 1.1 alc 25 1.1 alc #include "ar5416/ar5416.h" 26 1.1 alc #include "ar5416/ar5416reg.h" 27 1.1 alc #include "ar5416/ar5416phy.h" 28 1.1 alc 29 1.1 alc /* Adc Gain Cal aliases */ 30 1.1 alc #define totalAdcIOddPhase(i) caldata[0][i].u 31 1.1 alc #define totalAdcIEvenPhase(i) caldata[1][i].u 32 1.1 alc #define totalAdcQOddPhase(i) caldata[2][i].u 33 1.1 alc #define totalAdcQEvenPhase(i) caldata[3][i].u 34 1.1 alc 35 1.1 alc /* 36 1.1 alc * Collect data from HW to later perform ADC Gain Calibration 37 1.1 alc */ 38 1.1 alc void 39 1.1 alc ar5416AdcGainCalCollect(struct ath_hal *ah) 40 1.1 alc { 41 1.1 alc struct ar5416PerCal *cal = &AH5416(ah)->ah_cal; 42 1.1 alc int i; 43 1.1 alc 44 1.1 alc /* 45 1.1 alc * Accumulate ADC Gain cal measures for active chains 46 1.1 alc */ 47 1.1 alc for (i = 0; i < AR5416_MAX_CHAINS; i++) { 48 1.1 alc cal->totalAdcIOddPhase(i) += 49 1.1 alc OS_REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); 50 1.1 alc cal->totalAdcIEvenPhase(i) += 51 1.1 alc OS_REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); 52 1.1 alc cal->totalAdcQOddPhase(i) += 53 1.1 alc OS_REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); 54 1.1 alc cal->totalAdcQEvenPhase(i) += 55 1.1 alc OS_REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); 56 1.1 alc 57 1.1 alc HALDEBUG(ah, HAL_DEBUG_PERCAL, 58 1.1 alc "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n", 59 1.1 alc cal->calSamples, i, cal->totalAdcIOddPhase(i), 60 1.1 alc cal->totalAdcIEvenPhase(i), cal->totalAdcQOddPhase(i), 61 1.1 alc cal->totalAdcQEvenPhase(i)); 62 1.1 alc } 63 1.1 alc } 64 1.1 alc 65 1.1 alc /* 66 1.1 alc * Use HW data to do ADC Gain Calibration 67 1.1 alc */ 68 1.1 alc void 69 1.1 alc ar5416AdcGainCalibration(struct ath_hal *ah, uint8_t numChains) 70 1.1 alc { 71 1.1 alc struct ar5416PerCal *cal = &AH5416(ah)->ah_cal; 72 1.1 alc uint32_t i; 73 1.1 alc 74 1.1 alc for (i = 0; i < numChains; i++) { 75 1.1 alc uint32_t iOddMeasOffset = cal->totalAdcIOddPhase(i); 76 1.1 alc uint32_t iEvenMeasOffset = cal->totalAdcIEvenPhase(i); 77 1.1 alc uint32_t qOddMeasOffset = cal->totalAdcQOddPhase(i); 78 1.1 alc uint32_t qEvenMeasOffset = cal->totalAdcQEvenPhase(i); 79 1.1 alc 80 1.1 alc HALDEBUG(ah, HAL_DEBUG_PERCAL, 81 1.1 alc "Start ADC Gain Cal for Chain %d\n", i); 82 1.1 alc HALDEBUG(ah, HAL_DEBUG_PERCAL, 83 1.1 alc " pwr_meas_odd_i = 0x%08x\n", iOddMeasOffset); 84 1.1 alc HALDEBUG(ah, HAL_DEBUG_PERCAL, 85 1.1 alc " pwr_meas_even_i = 0x%08x\n", iEvenMeasOffset); 86 1.1 alc HALDEBUG(ah, HAL_DEBUG_PERCAL, 87 1.1 alc " pwr_meas_odd_q = 0x%08x\n", qOddMeasOffset); 88 1.1 alc HALDEBUG(ah, HAL_DEBUG_PERCAL, 89 1.1 alc " pwr_meas_even_q = 0x%08x\n", qEvenMeasOffset); 90 1.1 alc 91 1.1 alc if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) { 92 1.1 alc uint32_t iGainMismatch = 93 1.1 alc ((iEvenMeasOffset*32)/iOddMeasOffset) & 0x3f; 94 1.1 alc uint32_t qGainMismatch = 95 1.1 alc ((qOddMeasOffset*32)/qEvenMeasOffset) & 0x3f; 96 1.1 alc uint32_t val; 97 1.1 alc 98 1.1 alc HALDEBUG(ah, HAL_DEBUG_PERCAL, 99 1.1 alc " gain_mismatch_i = 0x%08x\n", 100 1.1 alc iGainMismatch); 101 1.1 alc HALDEBUG(ah, HAL_DEBUG_PERCAL, 102 1.1 alc " gain_mismatch_q = 0x%08x\n", 103 1.1 alc qGainMismatch); 104 1.1 alc 105 1.1 alc val = OS_REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); 106 1.1 alc val &= 0xfffff000; 107 1.1 alc val |= (qGainMismatch) | (iGainMismatch << 6); 108 1.1 alc OS_REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); 109 1.1 alc 110 1.1 alc HALDEBUG(ah, HAL_DEBUG_PERCAL, 111 1.1 alc "ADC Gain Cal done for Chain %d\n", i); 112 1.1 alc } 113 1.1 alc } 114 1.1 alc OS_REG_SET_BIT(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), 115 1.1 alc AR_PHY_NEW_ADC_GAIN_CORR_ENABLE); 116 1.1 alc } 117