ar5416reg.h revision 1.2
1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $Id: ar5416reg.h,v 1.2 2011/02/20 11:21:04 jmcneill Exp $ 18 */ 19 #ifndef _DEV_ATH_AR5416REG_H 20 #define _DEV_ATH_AR5416REG_H 21 22 #include "ar5212/ar5212reg.h" 23 24 /* 25 * Register added starting with the AR5416 26 */ 27 #define AR_MIRT 0x0020 /* interrupt rate threshold */ 28 #define AR_TIMT 0x0028 /* Tx Interrupt mitigation threshold */ 29 #define AR_RIMT 0x002C /* Rx Interrupt mitigation threshold */ 30 #define AR_GTXTO 0x0064 /* global transmit timeout */ 31 #define AR_GTTM 0x0068 /* global transmit timeout mode */ 32 #define AR_CST 0x006C /* carrier sense timeout */ 33 #define AR_MAC_LED 0x1f04 /* LED control */ 34 #define AR_WA 0x4004 /* PCIE work-arounds */ 35 #define AR_PCIE_PM_CTRL 0x4014 36 #define AR_AHB_MODE 0x4024 /* AHB mode for dma */ 37 #define AR_INTR_SYNC_CAUSE_CLR 0x4028 /* clear interrupt */ 38 #define AR_INTR_SYNC_CAUSE 0x4028 /* check pending interrupts */ 39 #define AR_INTR_SYNC_ENABLE 0x402c /* enable interrupts */ 40 #define AR_INTR_ASYNC_MASK 0x4030 /* asynchronous interrupt mask */ 41 #define AR_INTR_SYNC_MASK 0x4034 /* synchronous interrupt mask */ 42 #define AR_INTR_ASYNC_CAUSE 0x4038 /* check pending interrupts */ 43 #define AR_INTR_ASYNC_ENABLE 0x403c /* enable interrupts */ 44 #define AR5416_PCIE_SERDES 0x4040 45 #define AR5416_PCIE_SERDES2 0x4044 46 #define AR_GPIO_IN 0x4048 /* GPIO input register */ 47 #define AR_GPIO_INTR_OUT 0x404c /* GPIO output register */ 48 #define AR_EEPROM_STATUS_DATA 0x407c 49 #define AR_OBS 0x4080 50 #define AR_RTC_RC 0x7000 /* reset control */ 51 #define AR_RTC_PLL_CONTROL 0x7014 52 #define AR_RTC_RESET 0x7040 /* RTC reset register */ 53 #define AR_RTC_STATUS 0x7044 /* system sleep status */ 54 #define AR_RTC_SLEEP_CLK 0x7048 55 #define AR_RTC_FORCE_WAKE 0x704c /* control MAC force wake */ 56 #define AR_RTC_INTR_CAUSE 0x7050 /* RTC interrupt cause/clear */ 57 #define AR_RTC_INTR_ENABLE 0x7054 /* RTC interrupt enable */ 58 #define AR_RTC_INTR_MASK 0x7058 /* RTC interrupt mask */ 59 /* AR9280: rf long shift registers */ 60 #define AR_AN_RF2G1_CH0 0x7810 61 #define AR_AN_RF5G1_CH0 0x7818 62 #define AR_AN_RF2G1_CH1 0x7834 63 #define AR_AN_RF5G1_CH1 0x783C 64 #define AR_AN_TOP2 0x7894 65 #define AR_AN_SYNTH9 0x7868 66 #define AR9285_AN_RF2G3 0x7828 67 #define AR9285_AN_TOP3 0x786c 68 #define AR_RESET_TSF 0x8020 69 #define AR_RXFIFO_CFG 0x8114 70 #define AR_PHY_ERR_1 0x812c 71 #define AR_PHY_ERR_MASK_1 0x8130 /* mask for AR_PHY_ERR_1 */ 72 #define AR_PHY_ERR_2 0x8134 73 #define AR_PHY_ERR_MASK_2 0x8138 /* mask for AR_PHY_ERR_2 */ 74 #define AR_TSFOOR_THRESHOLD 0x813c 75 #define AR_PHY_ERR_3 0x8168 76 #define AR_PHY_ERR_MASK_3 0x816c /* mask for AR_PHY_ERR_3 */ 77 #define AR_TXOP_X 0x81ec /* txop for legacy non-qos */ 78 #define AR_TXOP_0_3 0x81f0 /* txop for various tid's */ 79 #define AR_TXOP_4_7 0x81f4 80 #define AR_TXOP_8_11 0x81f8 81 #define AR_TXOP_12_15 0x81fc 82 /* generic timers based on tsf - all uS */ 83 #define AR_NEXT_TBTT 0x8200 84 #define AR_NEXT_DBA 0x8204 85 #define AR_NEXT_SWBA 0x8208 86 #define AR_NEXT_CFP 0x8208 87 #define AR_NEXT_HCF 0x820C 88 #define AR_NEXT_TIM 0x8210 89 #define AR_NEXT_DTIM 0x8214 90 #define AR_NEXT_QUIET 0x8218 91 #define AR_NEXT_NDP 0x821C 92 #define AR5416_BEACON_PERIOD 0x8220 93 #define AR_DBA_PERIOD 0x8224 94 #define AR_SWBA_PERIOD 0x8228 95 #define AR_HCF_PERIOD 0x822C 96 #define AR_TIM_PERIOD 0x8230 97 #define AR_DTIM_PERIOD 0x8234 98 #define AR_QUIET_PERIOD 0x8238 99 #define AR_NDP_PERIOD 0x823C 100 #define AR_TIMER_MODE 0x8240 101 #define AR_SLP32_MODE 0x8244 102 #define AR_SLP32_WAKE 0x8248 103 #define AR_SLP32_INC 0x824c 104 #define AR_SLP_CNT 0x8250 /* 32kHz cycles with mac asleep */ 105 #define AR_SLP_CYCLE_CNT 0x8254 /* absolute number of 32kHz cycles */ 106 #define AR_SLP_MIB_CTRL 0x8258 107 #define AR_2040_MODE 0x8318 108 #define AR_EXTRCCNT 0x8328 /* extension channel rx clear count */ 109 #define AR_SELFGEN_MASK 0x832c /* rx and cal chain masks */ 110 #define AR_PCU_TXBUF_CTRL 0x8340 111 112 /* DMA & PCI Registers in PCI space (usable during sleep)*/ 113 #define AR_RC_AHB 0x00000001 /* AHB reset */ 114 #define AR_RC_APB 0x00000002 /* APB reset */ 115 #define AR_RC_HOSTIF 0x00000100 /* host interface reset */ 116 117 #define AR_MIRT_VAL 0x0000ffff /* in uS */ 118 #define AR_MIRT_VAL_S 16 119 120 #define AR_TIMT_LAST 0x0000ffff /* Last packet threshold */ 121 #define AR_TIMT_LAST_S 0 122 #define AR_TIMT_FIRST 0xffff0000 /* First packet threshold */ 123 #define AR_TIMT_FIRST_S 16 124 125 #define AR_RIMT_LAST 0x0000ffff /* Last packet threshold */ 126 #define AR_RIMT_LAST_S 0 127 #define AR_RIMT_FIRST 0xffff0000 /* First packet threshold */ 128 #define AR_RIMT_FIRST_S 16 129 130 #define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 131 #define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 132 #define AR_GTXTO_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 133 134 #define AR_GTTM_USEC 0x00000001 // usec strobe 135 #define AR_GTTM_IGNORE_IDLE 0x00000002 // ignore channel idle 136 #define AR_GTTM_RESET_IDLE 0x00000004 // reset counter on channel idle low 137 #define AR_GTTM_CST_USEC 0x00000008 // CST usec strobe 138 139 #define AR_CST_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 140 #define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 141 #define AR_CST_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 142 143 /* MAC tx DMA size config */ 144 #define AR_TXCFG_DMASZ_MASK 0x00000003 145 #define AR_TXCFG_DMASZ_4B 0 146 #define AR_TXCFG_DMASZ_8B 1 147 #define AR_TXCFG_DMASZ_16B 2 148 #define AR_TXCFG_DMASZ_32B 3 149 #define AR_TXCFG_DMASZ_64B 4 150 #define AR_TXCFG_DMASZ_128B 5 151 #define AR_TXCFG_DMASZ_256B 6 152 #define AR_TXCFG_DMASZ_512B 7 153 #define AR_TXCFG_ATIM_TXPOLICY 0x00000800 154 155 /* MAC rx DMA size config */ 156 #define AR_RXCFG_DMASZ_MASK 0x00000007 157 #define AR_RXCFG_DMASZ_4B 0 158 #define AR_RXCFG_DMASZ_8B 1 159 #define AR_RXCFG_DMASZ_16B 2 160 #define AR_RXCFG_DMASZ_32B 3 161 #define AR_RXCFG_DMASZ_64B 4 162 #define AR_RXCFG_DMASZ_128B 5 163 #define AR_RXCFG_DMASZ_256B 6 164 #define AR_RXCFG_DMASZ_512B 7 165 166 /* MAC Led registers */ 167 #define AR_MAC_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode */ 168 #define AR_MAC_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select */ 169 #define AR_MAC_LED_MODE 0x00000380 /* LED mode select */ 170 #define AR_MAC_LED_MODE_S 7 171 #define AR_MAC_LED_MODE_PROP 0 /* Blink prop to filtered tx/rx */ 172 #define AR_MAC_LED_MODE_RPROP 1 /* Blink prop to unfiltered tx/rx */ 173 #define AR_MAC_LED_MODE_SPLIT 2 /* Blink power for tx/net for rx */ 174 #define AR_MAC_LED_MODE_RAND 3 /* Blink randomly */ 175 #define AR_MAC_LED_MODE_POWON 5 /* Power LED on (s/w control) */ 176 #define AR_MAC_LED_MODE_NETON 6 /* Network LED on (s/w control) */ 177 #define AR_MAC_LED_ASSOC 0x00000c00 178 #define AR_MAC_LED_ASSOC_NONE 0x00000000 /* STA is not associated or trying */ 179 #define AR_MAC_LED_ASSOC_ACTIVE 0x00000400 /* STA is associated */ 180 #define AR_MAC_LED_ASSOC_PEND 0x00000800 /* STA is trying to associate */ 181 #define AR_MAC_LED_ASSOC_S 10 182 183 #define AR_WA_UNTIE_RESET_EN 0x00008000 /* ena PCI reset to POR */ 184 #define AR_WA_RESET_EN 0x00040000 /* ena AR_WA_UNTIE_RESET_EN */ 185 #define AR_WA_ANALOG_SHIFT 0x00100000 186 #define AR_WA_POR_SHORT 0x00200000 /* PCIE phy reset control */ 187 188 #define AR_WA_DEFAULT 0x0000073f 189 #define AR9280_WA_DEFAULT 0x0040073f 190 #define AR9285_WA_DEFAULT 0x004a05cb 191 192 #define AR_PCIE_PM_CTRL_ENA 0x00080000 193 194 #define AR_AHB_EXACT_WR_EN 0x00000000 /* write exact bytes */ 195 #define AR_AHB_BUF_WR_EN 0x00000001 /* buffer write upto cacheline*/ 196 #define AR_AHB_EXACT_RD_EN 0x00000000 /* read exact bytes */ 197 #define AR_AHB_CACHELINE_RD_EN 0x00000002 /* read upto end of cacheline */ 198 #define AR_AHB_PREFETCH_RD_EN 0x00000004 /* prefetch upto page boundary*/ 199 #define AR_AHB_PAGE_SIZE_1K 0x00000000 /* set page-size as 1k */ 200 #define AR_AHB_PAGE_SIZE_2K 0x00000008 /* set page-size as 2k */ 201 #define AR_AHB_PAGE_SIZE_4K 0x00000010 /* set page-size as 4k */ 202 203 /* MAC PCU Registers */ 204 #define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 /* Don't replace seq num */ 205 206 /* Extended PCU DIAG_SW control fields */ 207 #define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 /* dual chain channel info */ 208 #define AR_DIAG_RX_ABORT 0x02000000 /* abort rx */ 209 #define AR_DIAG_SATURATE_CCNT 0x04000000 /* sat. cycle cnts (no shift) */ 210 #define AR_DIAG_OBS_PT_SEL2 0x08000000 /* observation point sel */ 211 #define AR_DIAG_RXCLEAR_CTL_LOW 0x10000000 /* force rx_clear(ctl) low/busy */ 212 #define AR_DIAG_RXCLEAR_EXT_LOW 0x20000000 /* force rx_clear(ext) low/busy */ 213 214 #define AR_TXOP_X_VAL 0x000000FF 215 216 #define AR_RESET_TSF_ONCE 0x01000000 /* reset tsf once; self-clears*/ 217 218 /* Interrupts */ 219 #define AR_ISR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ 220 #define AR_ISR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ 221 #define AR_ISR_TXINTM 0x40000000 /* Tx int after mitigation */ 222 #define AR_ISR_RXINTM 0x80000000 /* Rx int after mitigation */ 223 224 #define AR_ISR_S2_CST 0x00400000 /* Carrier sense timeout */ 225 #define AR_ISR_S2_GTT 0x00800000 /* Global transmit timeout */ 226 #define AR_ISR_S2_TSFOOR 0x40000000 /* RX TSF out of range */ 227 228 #define AR_INTR_SPURIOUS 0xffffffff 229 #define AR_INTR_RTC_IRQ 0x00000001 /* rtc in shutdown state */ 230 #define AR_INTR_MAC_IRQ 0x00000002 /* pending mac interrupt */ 231 #define AR_INTR_EEP_PROT_ACCESS 0x00000004 /* eeprom protected access */ 232 #define AR_INTR_MAC_AWAKE 0x00020000 /* mac is awake */ 233 #define AR_INTR_MAC_ASLEEP 0x00040000 /* mac is asleep */ 234 235 /* Interrupt Mask Registers */ 236 #define AR_IMR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ 237 #define AR_IMR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ 238 #define AR_IMR_TXINTM 0x40000000 /* Tx int after mitigation */ 239 #define AR_IMR_RXINTM 0x80000000 /* Rx int after mitigation */ 240 241 #define AR_IMR_S2_CST 0x00400000 /* Carrier sense timeout */ 242 #define AR_IMR_S2_GTT 0x00800000 /* Global transmit timeout */ 243 244 /* synchronous interrupt signals */ 245 #define AR_INTR_SYNC_RTC_IRQ 0x00000001 246 #define AR_INTR_SYNC_MAC_IRQ 0x00000002 247 #define AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS 0x00000004 248 #define AR_INTR_SYNC_APB_TIMEOUT 0x00000008 249 #define AR_INTR_SYNC_PCI_MODE_CONFLICT 0x00000010 250 #define AR_INTR_SYNC_HOST1_FATAL 0x00000020 251 #define AR_INTR_SYNC_HOST1_PERR 0x00000040 252 #define AR_INTR_SYNC_TRCV_FIFO_PERR 0x00000080 253 #define AR_INTR_SYNC_RADM_CPL_EP 0x00000100 254 #define AR_INTR_SYNC_RADM_CPL_DLLP_ABORT 0x00000200 255 #define AR_INTR_SYNC_RADM_CPL_TLP_ABORT 0x00000400 256 #define AR_INTR_SYNC_RADM_CPL_ECRC_ERR 0x00000800 257 #define AR_INTR_SYNC_RADM_CPL_TIMEOUT 0x00001000 258 #define AR_INTR_SYNC_LOCAL_TIMEOUT 0x00002000 259 #define AR_INTR_SYNC_PM_ACCESS 0x00004000 260 #define AR_INTR_SYNC_MAC_AWAKE 0x00008000 261 #define AR_INTR_SYNC_MAC_ASLEEP 0x00010000 262 #define AR_INTR_SYNC_MAC_SLEEP_ACCESS 0x00020000 263 #define AR_INTR_SYNC_ALL 0x0003FFFF 264 265 /* default synchronous interrupt signals enabled */ 266 #define AR_INTR_SYNC_DEFAULT \ 267 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR | \ 268 AR_INTR_SYNC_RADM_CPL_EP | AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | \ 269 AR_INTR_SYNC_RADM_CPL_TLP_ABORT | AR_INTR_SYNC_RADM_CPL_ECRC_ERR | \ 270 AR_INTR_SYNC_RADM_CPL_TIMEOUT | AR_INTR_SYNC_LOCAL_TIMEOUT | \ 271 AR_INTR_SYNC_MAC_SLEEP_ACCESS) 272 273 /* RTC registers */ 274 #define AR_RTC_RC_M 0x00000003 275 #define AR_RTC_RC_MAC_WARM 0x00000001 276 #define AR_RTC_RC_MAC_COLD 0x00000002 277 #define AR_RTC_PLL_DIV 0x0000001f 278 #define AR_RTC_PLL_DIV_S 0 279 #define AR_RTC_PLL_DIV2 0x00000020 280 #define AR_RTC_PLL_REFDIV_5 0x000000c0 281 282 #define AR_RTC_SOWL_PLL_DIV 0x000003ff 283 #define AR_RTC_SOWL_PLL_DIV_S 0 284 #define AR_RTC_SOWL_PLL_REFDIV 0x00003C00 285 #define AR_RTC_SOWL_PLL_REFDIV_S 10 286 #define AR_RTC_SOWL_PLL_CLKSEL 0x0000C000 287 #define AR_RTC_SOWL_PLL_CLKSEL_S 14 288 289 #define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */ 290 291 #define AR_RTC_PM_STATUS_M 0x0000000f /* Pwr Mgmt Status */ 292 #define AR_RTC_STATUS_M 0x0000003f /* RTC Status */ 293 #define AR_RTC_STATUS_SHUTDOWN 0x00000001 294 #define AR_RTC_STATUS_ON 0x00000002 295 #define AR_RTC_STATUS_SLEEP 0x00000004 296 #define AR_RTC_STATUS_WAKEUP 0x00000008 297 #define AR_RTC_STATUS_COLDRESET 0x00000010 /* Not currently used */ 298 #define AR_RTC_STATUS_PLLCHANGE 0x00000020 /* Not currently used */ 299 300 #define AR_RTC_SLEEP_DERIVED_CLK 0x2 301 302 #define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */ 303 #define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */ 304 305 #define AR_RTC_PLL_CLKSEL 0x00000300 306 #define AR_RTC_PLL_CLKSEL_S 8 307 308 /* AR9280: rf long shift registers */ 309 #define AR_AN_RF2G1_CH0_OB 0x03800000 310 #define AR_AN_RF2G1_CH0_OB_S 23 311 #define AR_AN_RF2G1_CH0_DB 0x1C000000 312 #define AR_AN_RF2G1_CH0_DB_S 26 313 314 #define AR_AN_RF5G1_CH0_OB5 0x00070000 315 #define AR_AN_RF5G1_CH0_OB5_S 16 316 #define AR_AN_RF5G1_CH0_DB5 0x00380000 317 #define AR_AN_RF5G1_CH0_DB5_S 19 318 319 #define AR_AN_RF2G1_CH1_OB 0x03800000 320 #define AR_AN_RF2G1_CH1_OB_S 23 321 #define AR_AN_RF2G1_CH1_DB 0x1C000000 322 #define AR_AN_RF2G1_CH1_DB_S 26 323 324 #define AR_AN_RF5G1_CH1_OB5 0x00070000 325 #define AR_AN_RF5G1_CH1_OB5_S 16 326 #define AR_AN_RF5G1_CH1_DB5 0x00380000 327 #define AR_AN_RF5G1_CH1_DB5_S 19 328 329 #define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 330 #define AR_AN_TOP2_XPABIAS_LVL_S 30 331 #define AR_AN_TOP2_LOCALBIAS 0x00200000 332 #define AR_AN_TOP2_LOCALBIAS_S 21 333 #define AR_AN_TOP2_PWDCLKIND 0x00400000 334 #define AR_AN_TOP2_PWDCLKIND_S 22 335 336 #define AR_AN_SYNTH9_REFDIVA 0xf8000000 337 #define AR_AN_SYNTH9_REFDIVA_S 27 338 339 /* AR9285 Analog registers */ 340 #define AR9285_AN_RF2G3_OB_0 0x00E00000 341 #define AR9285_AN_RF2G3_OB_0_S 21 342 #define AR9285_AN_RF2G3_OB_1 0x001C0000 343 #define AR9285_AN_RF2G3_OB_1_S 18 344 #define AR9285_AN_RF2G3_OB_2 0x00038000 345 #define AR9285_AN_RF2G3_OB_2_S 15 346 #define AR9285_AN_RF2G3_OB_3 0x00007000 347 #define AR9285_AN_RF2G3_OB_3_S 12 348 #define AR9285_AN_RF2G3_OB_4 0x00000E00 349 #define AR9285_AN_RF2G3_OB_4_S 9 350 351 #define AR9285_AN_RF2G3_DB1_0 0x000001C0 352 #define AR9285_AN_RF2G3_DB1_0_S 6 353 #define AR9285_AN_RF2G3_DB1_1 0x00000038 354 #define AR9285_AN_RF2G3_DB1_1_S 3 355 #define AR9285_AN_RF2G3_DB1_2 0x00000007 356 #define AR9285_AN_RF2G3_DB1_2_S 0 357 #define AR9285_AN_RF2G4 0x782C 358 #define AR9285_AN_RF2G4_DB1_3 0xE0000000 359 #define AR9285_AN_RF2G4_DB1_3_S 29 360 #define AR9285_AN_RF2G4_DB1_4 0x1C000000 361 #define AR9285_AN_RF2G4_DB1_4_S 26 362 363 #define AR9285_AN_RF2G4_DB2_0 0x03800000 364 #define AR9285_AN_RF2G4_DB2_0_S 23 365 #define AR9285_AN_RF2G4_DB2_1 0x00700000 366 #define AR9285_AN_RF2G4_DB2_1_S 20 367 #define AR9285_AN_RF2G4_DB2_2 0x000E0000 368 #define AR9285_AN_RF2G4_DB2_2_S 17 369 #define AR9285_AN_RF2G4_DB2_3 0x0001C000 370 #define AR9285_AN_RF2G4_DB2_3_S 14 371 #define AR9285_AN_RF2G4_DB2_4 0x00003800 372 #define AR9285_AN_RF2G4_DB2_4_S 11 373 374 #define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C 375 #define AR9285_AN_TOP3_XPABIAS_LVL_S 2 376 377 /* Sleep control */ 378 #define AR5416_SLEEP1_CAB_TIMEOUT 0xFFE00000 /* Cab timeout (TU) */ 379 #define AR5416_SLEEP1_CAB_TIMEOUT_S 22 380 381 #define AR5416_SLEEP2_BEACON_TIMEOUT 0xFFE00000 /* Beacon timeout (TU)*/ 382 #define AR5416_SLEEP2_BEACON_TIMEOUT_S 22 383 384 /* Sleep Registers */ 385 #define AR_SLP32_HALFCLK_LATENCY 0x000FFFFF /* rising <-> falling edge */ 386 #define AR_SLP32_ENA 0x00100000 387 #define AR_SLP32_TSF_WRITE_STATUS 0x00200000 /* tsf update in progress */ 388 389 #define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF /* time to wake crystal */ 390 391 #define AR_SLP32_TST_INC 0x000FFFFF 392 393 #define AR_SLP_MIB_CLEAR 0x00000001 /* clear pending */ 394 #define AR_SLP_MIB_PENDING 0x00000002 /* clear counters */ 395 396 #define AR_TIMER_MODE_TBTT 0x00000001 397 #define AR_TIMER_MODE_DBA 0x00000002 398 #define AR_TIMER_MODE_SWBA 0x00000004 399 #define AR_TIMER_MODE_HCF 0x00000008 400 #define AR_TIMER_MODE_TIM 0x00000010 401 #define AR_TIMER_MODE_DTIM 0x00000020 402 #define AR_TIMER_MODE_QUIET 0x00000040 403 #define AR_TIMER_MODE_NDP 0x00000080 404 #define AR_TIMER_MODE_OVERFLOW_INDEX 0x00000700 405 #define AR_TIMER_MODE_OVERFLOW_INDEX_S 8 406 #define AR_TIMER_MODE_THRESH 0xFFFFF000 407 #define AR_TIMER_MODE_THRESH_S 12 408 409 /* PCU Misc modes */ 410 #define AR_PCU_FORCE_BSSID_MATCH 0x00000001 /* force bssid to match */ 411 #define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 /* tx/rx mic keys together */ 412 #define AR_PCU_TX_ADD_TSF 0x00000008 /* add tx_tsf + int_tsf */ 413 #define AR_PCU_CCK_SIFS_MODE 0x00000010 /* assume 11b sifs */ 414 #define AR_PCU_RX_ANT_UPDT 0x00000800 /* KC_RX_ANT_UPDATE */ 415 #define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 /* enforce txop / tbtt */ 416 #define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 /* count bmiss's when sleeping */ 417 #define AR_PCU_BUG_12306_FIX_ENA 0x00020000 /* use rx_clear to count sifs */ 418 #define AR_PCU_FORCE_QUIET_COLL 0x00040000 /* kill xmit for channel change */ 419 #define AR_PCU_TBTT_PROTECT 0x00200000 /* no xmit upto tbtt+20 uS */ 420 #define AR_PCU_CLEAR_VMF 0x01000000 /* clear vmf mode (fast cc)*/ 421 #define AR_PCU_CLEAR_BA_VALID 0x04000000 /* clear ba state */ 422 423 /* GPIO Interrupt */ 424 #define AR_INTR_GPIO 0x3FF00000 /* gpio interrupted */ 425 #define AR_INTR_GPIO_S 20 426 427 #define AR_GPIO_OUT_CTRL 0x000003FF /* 0 = out, 1 = in */ 428 #define AR_GPIO_OUT_VAL 0x000FFC00 429 #define AR_GPIO_OUT_VAL_S 10 430 #define AR_GPIO_INTR_CTRL 0x3FF00000 431 #define AR_GPIO_INTR_CTRL_S 20 432 433 #define AR_2040_JOINED_RX_CLEAR 0x00000001 /* use ctl + ext rx_clear for cca */ 434 435 #define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF 436 #define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700 437 438 /* Eeprom defines */ 439 #define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff 440 #define AR_EEPROM_STATUS_DATA_VAL_S 0 441 #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 442 #define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 443 #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 444 #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 445 446 #define AR_SREV_REVISION_OWL_10 0x08 447 #define AR_SREV_REVISION_OWL_20 0x09 448 #define AR_SREV_REVISION_OWL_22 0x0a 449 450 #define AR_RAD5133_SREV_MAJOR 0xc0 /* Fowl: 2+5G/3x3 */ 451 #define AR_RAD2133_SREV_MAJOR 0xd0 /* Fowl: 2G/3x3 */ 452 #define AR_RAD5122_SREV_MAJOR 0xe0 /* Fowl: 5G/2x2 */ 453 #define AR_RAD2122_SREV_MAJOR 0xf0 /* Fowl: 2+5G/2x2 */ 454 455 /* Test macro for owl 1.0 */ 456 #define IS_5416V1(_ah) ((_ah)->ah_macRev == AR_SREV_REVISION_OWL_10) 457 #define IS_5416V2(_ah) ((_ah)->ah_macRev >= AR_SREV_REVISION_OWL_20) 458 #define IS_5416V2_2(_ah) ((_ah)->ah_macRev == AR_SREV_REVISION_OWL_22) 459 460 /* Expanded Mac Silicon Rev (16 bits starting with Sowl) */ 461 #define AR_XSREV_ID 0xFFFFFFFF /* Chip ID */ 462 #define AR_XSREV_ID_S 0 463 #define AR_XSREV_VERSION 0xFFFC0000 /* Chip version */ 464 #define AR_XSREV_VERSION_S 18 465 #define AR_XSREV_TYPE 0x0003F000 /* Chip type */ 466 #define AR_XSREV_TYPE_S 12 467 #define AR_XSREV_TYPE_CHAIN 0x00001000 /* Chain Mode (1:3 chains, 468 * 0:2 chains) */ 469 #define AR_XSREV_TYPE_HOST_MODE 0x00002000 /* Host Mode (1:PCI, 0:PCIe) */ 470 #define AR_XSREV_REVISION 0x00000F00 471 #define AR_XSREV_REVISION_S 8 472 473 #define AR_XSREV_VERSION_OWL_PCI 0x0D 474 #define AR_XSREV_VERSION_OWL_PCIE 0x0C 475 #define AR_XSREV_REVISION_OWL_10 0 /* Owl 1.0 */ 476 #define AR_XSREV_REVISION_OWL_20 1 /* Owl 2.0/2.1 */ 477 #define AR_XSREV_REVISION_OWL_22 2 /* Owl 2.2 */ 478 #define AR_XSREV_VERSION_SOWL 0x40 479 #define AR_XSREV_REVISION_SOWL_10 0 /* Sowl 1.0 */ 480 #define AR_XSREV_REVISION_SOWL_11 1 /* Sowl 1.1 */ 481 #define AR_XSREV_VERSION_MERLIN 0x80 /* Merlin Version */ 482 #define AR_XSREV_REVISION_MERLIN_10 0 /* Merlin 1.0 */ 483 #define AR_XSREV_REVISION_MERLIN_20 1 /* Merlin 2.0 */ 484 #define AR_XSREV_REVISION_MERLIN_21 2 /* Merlin 2.1 */ 485 #define AR_XSREV_VERSION_KITE 0xC0 /* Kite Version */ 486 #define AR_XSREV_REVISION_KITE_10 0 /* Kite 1.0 */ 487 488 #define AR_SREV_OWL_20_OR_LATER(_ah) \ 489 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL || \ 490 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_OWL_20) 491 #define AR_SREV_OWL_22_OR_LATER(_ah) \ 492 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL || \ 493 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_OWL_22) 494 495 #define AR_SREV_SOWL(_ah) \ 496 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_SOWL) 497 #define AR_SREV_SOWL_10_OR_LATER(_ah) \ 498 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL) 499 #define AR_SREV_SOWL_11(_ah) \ 500 (AR_SREV_SOWL(_ah) && \ 501 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_SOWL_11) 502 503 #define AR_SREV_MERLIN(_ah) \ 504 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_MERLIN) 505 #define AR_SREV_MERLIN_10_OR_LATER(_ah) \ 506 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_MERLIN) 507 #define AR_SREV_MERLIN_20(_ah) \ 508 (AR_SREV_MERLIN(_ah) && \ 509 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20) 510 #define AR_SREV_MERLIN_20_OR_LATER(_ah) \ 511 (AR_SREV_MERLIN_20(_ah) || \ 512 AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_MERLIN) 513 514 #define AR_SREV_KITE(_ah) \ 515 (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KITE) 516 #define AR_SREV_KITE_10_OR_LATER(_ah) \ 517 (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KITE) 518 #endif /* _DEV_ATH_AR5416REG_H */ 519
Indexes created Tue Oct 21 15:09:54 GMT 2025