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ar5416reg.h revision 1.3
      1 /*
      2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
      3  * Copyright (c) 2002-2008 Atheros Communications, Inc.
      4  *
      5  * Permission to use, copy, modify, and/or distribute this software for any
      6  * purpose with or without fee is hereby granted, provided that the above
      7  * copyright notice and this permission notice appear in all copies.
      8  *
      9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
     10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
     11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
     12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
     13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
     14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
     15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
     16  *
     17  * $Id: ar5416reg.h,v 1.3 2011/02/21 11:06:38 cegger Exp $
     18  */
     19 #ifndef _DEV_ATH_AR5416REG_H
     20 #define	_DEV_ATH_AR5416REG_H
     21 
     22 #include "ar5212/ar5212reg.h"
     23 
     24 /*
     25  * Register added starting with the AR5416
     26  */
     27 #define	AR_MIRT			0x0020	/* interrupt rate threshold */
     28 #define	AR_TIMT			0x0028	/* Tx Interrupt mitigation threshold */
     29 #define	AR_RIMT			0x002C	/* Rx Interrupt mitigation threshold */
     30 #define	AR_GTXTO		0x0064	/* global transmit timeout */
     31 #define	AR_GTTM			0x0068	/* global transmit timeout mode */
     32 #define	AR_CST			0x006C	/* carrier sense timeout */
     33 #define	AR_MAC_LED		0x1f04	/* LED control */
     34 #define AR_WA                   0x4004  /* PCIE work-arounds */
     35 #define AR_PCIE_PM_CTRL         0x4014
     36 #define	AR_AHB_MODE		0x4024	/* AHB mode for dma */
     37 #define	AR_INTR_SYNC_CAUSE_CLR	0x4028	/* clear interrupt */
     38 #define	AR_INTR_SYNC_CAUSE	0x4028	/* check pending interrupts */
     39 #define	AR_INTR_SYNC_ENABLE	0x402c	/* enable interrupts */
     40 #define	AR_INTR_ASYNC_MASK	0x4030	/* asynchronous interrupt mask */
     41 #define	AR_INTR_SYNC_MASK	0x4034	/* synchronous interrupt mask */
     42 #define	AR_INTR_ASYNC_CAUSE	0x4038	/* check pending interrupts */
     43 #define	AR_INTR_ASYNC_ENABLE	0x403c	/* enable interrupts */
     44 #define	AR5416_PCIE_SERDES	0x4040
     45 #define	AR5416_PCIE_SERDES2	0x4044
     46 #define	AR_GPIO_IN		0x4048	/* GPIO input register */
     47 #define	AR_GPIO_INTR_OUT	0x404c	/* GPIO output register */
     48 #define	AR_EEPROM_STATUS_DATA	0x407c
     49 #define	AR_OBS			0x4080
     50 #define	AR_RTC_RC		0x7000	/* reset control */
     51 #define	AR_RTC_PLL_CONTROL	0x7014
     52 #define	AR_RTC_RESET		0x7040	/* RTC reset register */
     53 #define	AR_RTC_STATUS		0x7044	/* system sleep status */
     54 #define	AR_RTC_SLEEP_CLK	0x7048
     55 #define	AR_RTC_FORCE_WAKE	0x704c	/* control MAC force wake */
     56 #define	AR_RTC_INTR_CAUSE	0x7050	/* RTC interrupt cause/clear */
     57 #define	AR_RTC_INTR_ENABLE	0x7054	/* RTC interrupt enable */
     58 #define	AR_RTC_INTR_MASK	0x7058	/* RTC interrupt mask */
     59 /* AR9280: rf long shift registers */
     60 #define	AR_AN_RF2G1_CH0         0x7810
     61 #define	AR_AN_RF5G1_CH0         0x7818
     62 #define	AR_AN_RF2G1_CH1         0x7834
     63 #define	AR_AN_RF5G1_CH1         0x783C
     64 #define	AR_AN_TOP2		0x7894
     65 #define	AR_AN_SYNTH9            0x7868
     66 #define	AR9285_AN_RF2G1		0x7820
     67 #define	AR9285_AN_RF2G2		0x7824
     68 #define	AR9285_AN_RF2G3         0x7828
     69 #define	AR9285_AN_RF2G4		0x782c
     70 #define	AR9285_AN_RF2G6		0x7834
     71 #define	AR9285_AN_RF2G7		0x7838
     72 #define	AR9285_AN_RF2G8		0x783c
     73 #define	AR9285_AN_RF2G9		0x7840
     74 #define	AR9285_AN_RXTXBB1	0x7854
     75 #define	AR9285_AN_TOP2		0x7868
     76 #define	AR9285_AN_TOP3		0x786c
     77 #define	AR9285_AN_TOP4		0x7870
     78 #define	AR9285_AN_TOP4_DEFAULT	0x10142c00
     79 
     80 #define	AR_RESET_TSF		0x8020
     81 #define	AR_RXFIFO_CFG		0x8114
     82 #define	AR_PHY_ERR_1		0x812c
     83 #define	AR_PHY_ERR_MASK_1	0x8130	/* mask for AR_PHY_ERR_1 */
     84 #define	AR_PHY_ERR_2		0x8134
     85 #define	AR_PHY_ERR_MASK_2	0x8138	/* mask for AR_PHY_ERR_2 */
     86 #define	AR_TSFOOR_THRESHOLD	0x813c
     87 #define	AR_PHY_ERR_3		0x8168
     88 #define	AR_PHY_ERR_MASK_3	0x816c	/* mask for AR_PHY_ERR_3 */
     89 #define	AR_TXOP_X		0x81ec	/* txop for legacy non-qos */
     90 #define	AR_TXOP_0_3		0x81f0	/* txop for various tid's */
     91 #define	AR_TXOP_4_7		0x81f4
     92 #define	AR_TXOP_8_11		0x81f8
     93 #define	AR_TXOP_12_15		0x81fc
     94 /* generic timers based on tsf - all uS */
     95 #define	AR_NEXT_TBTT		0x8200
     96 #define	AR_NEXT_DBA		0x8204
     97 #define	AR_NEXT_SWBA		0x8208
     98 #define	AR_NEXT_CFP		0x8208
     99 #define	AR_NEXT_HCF		0x820C
    100 #define	AR_NEXT_TIM		0x8210
    101 #define	AR_NEXT_DTIM		0x8214
    102 #define	AR_NEXT_QUIET		0x8218
    103 #define	AR_NEXT_NDP		0x821C
    104 #define	AR5416_BEACON_PERIOD	0x8220
    105 #define	AR_DBA_PERIOD		0x8224
    106 #define	AR_SWBA_PERIOD		0x8228
    107 #define	AR_HCF_PERIOD		0x822C
    108 #define	AR_TIM_PERIOD		0x8230
    109 #define	AR_DTIM_PERIOD		0x8234
    110 #define	AR_QUIET_PERIOD		0x8238
    111 #define	AR_NDP_PERIOD		0x823C
    112 #define	AR_TIMER_MODE		0x8240
    113 #define	AR_SLP32_MODE		0x8244
    114 #define	AR_SLP32_WAKE		0x8248
    115 #define	AR_SLP32_INC		0x824c
    116 #define	AR_SLP_CNT		0x8250	/* 32kHz cycles with mac asleep */
    117 #define	AR_SLP_CYCLE_CNT	0x8254	/* absolute number of 32kHz cycles */
    118 #define	AR_SLP_MIB_CTRL		0x8258
    119 #define	AR_2040_MODE		0x8318
    120 #define	AR_EXTRCCNT		0x8328	/* extension channel rx clear count */
    121 #define	AR_SELFGEN_MASK		0x832c	/* rx and cal chain masks */
    122 #define	AR_PCU_TXBUF_CTRL	0x8340
    123 #define	AR_PCU_MISC_MODE2	0x8344
    124 
    125 /* DMA & PCI Registers in PCI space (usable during sleep)*/
    126 #define	AR_RC_AHB		0x00000001	/* AHB reset */
    127 #define	AR_RC_APB		0x00000002	/* APB reset */
    128 #define	AR_RC_HOSTIF		0x00000100	/* host interface reset */
    129 
    130 #define	AR_MIRT_VAL		0x0000ffff	/* in uS */
    131 #define	AR_MIRT_VAL_S		16
    132 
    133 #define	AR_TIMT_LAST		0x0000ffff	/* Last packet threshold */
    134 #define	AR_TIMT_LAST_S		0
    135 #define	AR_TIMT_FIRST		0xffff0000	/* First packet threshold */
    136 #define	AR_TIMT_FIRST_S		16
    137 
    138 #define	AR_RIMT_LAST		0x0000ffff	/* Last packet threshold */
    139 #define	AR_RIMT_LAST_S		0
    140 #define	AR_RIMT_FIRST		0xffff0000	/* First packet threshold */
    141 #define	AR_RIMT_FIRST_S		16
    142 
    143 #define	AR_GTXTO_TIMEOUT_COUNTER    0x0000FFFF  // Mask for timeout counter (in TUs)
    144 #define	AR_GTXTO_TIMEOUT_LIMIT      0xFFFF0000  // Mask for timeout limit (in  TUs)
    145 #define	AR_GTXTO_TIMEOUT_LIMIT_S    16      // Shift for timeout limit
    146 
    147 #define	AR_GTTM_USEC          0x00000001 // usec strobe
    148 #define	AR_GTTM_IGNORE_IDLE   0x00000002 // ignore channel idle
    149 #define	AR_GTTM_RESET_IDLE    0x00000004 // reset counter on channel idle low
    150 #define	AR_GTTM_CST_USEC      0x00000008 // CST usec strobe
    151 
    152 #define	AR_CST_TIMEOUT_COUNTER    0x0000FFFF  // Mask for timeout counter (in TUs)
    153 #define	AR_CST_TIMEOUT_LIMIT      0xFFFF0000  // Mask for timeout limit (in  TUs)
    154 #define	AR_CST_TIMEOUT_LIMIT_S    16      // Shift for timeout limit
    155 
    156 /* MAC tx DMA size config  */
    157 #define	AR_TXCFG_DMASZ_MASK	0x00000003
    158 #define	AR_TXCFG_DMASZ_4B	0
    159 #define	AR_TXCFG_DMASZ_8B	1
    160 #define	AR_TXCFG_DMASZ_16B	2
    161 #define	AR_TXCFG_DMASZ_32B	3
    162 #define	AR_TXCFG_DMASZ_64B	4
    163 #define	AR_TXCFG_DMASZ_128B	5
    164 #define	AR_TXCFG_DMASZ_256B	6
    165 #define	AR_TXCFG_DMASZ_512B	7
    166 #define	AR_TXCFG_ATIM_TXPOLICY	0x00000800
    167 
    168 /* MAC rx DMA size config  */
    169 #define	AR_RXCFG_DMASZ_MASK	0x00000007
    170 #define	AR_RXCFG_DMASZ_4B	0
    171 #define	AR_RXCFG_DMASZ_8B	1
    172 #define	AR_RXCFG_DMASZ_16B	2
    173 #define	AR_RXCFG_DMASZ_32B	3
    174 #define	AR_RXCFG_DMASZ_64B	4
    175 #define	AR_RXCFG_DMASZ_128B	5
    176 #define	AR_RXCFG_DMASZ_256B	6
    177 #define	AR_RXCFG_DMASZ_512B	7
    178 
    179 /* MAC Led registers */
    180 #define	AR_MAC_LED_BLINK_SLOW	0x00000008	/* LED slowest blink rate mode */
    181 #define	AR_MAC_LED_BLINK_THRESH_SEL 0x00000070	/* LED blink threshold select */
    182 #define	AR_MAC_LED_MODE		0x00000380	/* LED mode select */
    183 #define	AR_MAC_LED_MODE_S	7
    184 #define	AR_MAC_LED_MODE_PROP	0	/* Blink prop to filtered tx/rx */
    185 #define	AR_MAC_LED_MODE_RPROP	1	/* Blink prop to unfiltered tx/rx */
    186 #define	AR_MAC_LED_MODE_SPLIT	2	/* Blink power for tx/net for rx */
    187 #define	AR_MAC_LED_MODE_RAND	3	/* Blink randomly */
    188 #define	AR_MAC_LED_MODE_POWON	5	/* Power LED on (s/w control) */
    189 #define	AR_MAC_LED_MODE_NETON	6	/* Network LED on (s/w control) */
    190 #define	AR_MAC_LED_ASSOC	0x00000c00
    191 #define	AR_MAC_LED_ASSOC_NONE	0x00000000 /* STA is not associated or trying */
    192 #define	AR_MAC_LED_ASSOC_ACTIVE	0x00000400 /* STA is associated */
    193 #define	AR_MAC_LED_ASSOC_PEND	0x00000800 /* STA is trying to associate */
    194 #define	AR_MAC_LED_ASSOC_S	10
    195 
    196 #define	AR_WA_UNTIE_RESET_EN	0x00008000	/* ena PCI reset to POR */
    197 #define	AR_WA_RESET_EN		0x00040000	/* ena AR_WA_UNTIE_RESET_EN */
    198 #define	AR_WA_ANALOG_SHIFT	0x00100000
    199 #define	AR_WA_POR_SHORT		0x00200000	/* PCIE phy reset control */
    200 
    201 #define	AR_WA_DEFAULT		0x0000073f
    202 #define	AR9280_WA_DEFAULT	0x0040073f
    203 #define	AR9285_WA_DEFAULT	0x004a05cb
    204 
    205 #define	AR_PCIE_PM_CTRL_ENA	0x00080000
    206 
    207 #define	AR_AHB_EXACT_WR_EN	0x00000000	/* write exact bytes */
    208 #define	AR_AHB_BUF_WR_EN	0x00000001	/* buffer write upto cacheline*/
    209 #define	AR_AHB_EXACT_RD_EN	0x00000000	/* read exact bytes */
    210 #define	AR_AHB_CACHELINE_RD_EN	0x00000002	/* read upto end of cacheline */
    211 #define	AR_AHB_PREFETCH_RD_EN	0x00000004	/* prefetch upto page boundary*/
    212 #define	AR_AHB_PAGE_SIZE_1K	0x00000000	/* set page-size as 1k */
    213 #define	AR_AHB_PAGE_SIZE_2K	0x00000008	/* set page-size as 2k */
    214 #define	AR_AHB_PAGE_SIZE_4K	0x00000010	/* set page-size as 4k */
    215 
    216 /* MAC PCU Registers */
    217 #define	AR_STA_ID1_PRESERVE_SEQNUM	0x20000000 /* Don't replace seq num */
    218 
    219 /* Extended PCU DIAG_SW control fields */
    220 #define	AR_DIAG_DUAL_CHAIN_INFO	0x01000000	/* dual chain channel info */
    221 #define	AR_DIAG_RX_ABORT	0x02000000	/* abort rx */
    222 #define	AR_DIAG_SATURATE_CCNT	0x04000000	/* sat. cycle cnts (no shift) */
    223 #define	AR_DIAG_OBS_PT_SEL2	0x08000000	/* observation point sel */
    224 #define	AR_DIAG_RXCLEAR_CTL_LOW	0x10000000	/* force rx_clear(ctl) low/busy */
    225 #define	AR_DIAG_RXCLEAR_EXT_LOW	0x20000000	/* force rx_clear(ext) low/busy */
    226 
    227 #define	AR_TXOP_X_VAL	0x000000FF
    228 
    229 #define	AR_RESET_TSF_ONCE	0x01000000	/* reset tsf once; self-clears*/
    230 
    231 /* Interrupts */
    232 #define	AR_ISR_TXMINTR		0x00080000	/* Maximum interrupt tx rate */
    233 #define	AR_ISR_RXMINTR		0x01000000	/* Maximum interrupt rx rate */
    234 #define	AR_ISR_TXINTM		0x40000000	/* Tx int after mitigation */
    235 #define	AR_ISR_RXINTM		0x80000000	/* Rx int after mitigation */
    236 
    237 #define	AR_ISR_S2_CST		0x00400000	/* Carrier sense timeout */
    238 #define	AR_ISR_S2_GTT		0x00800000	/* Global transmit timeout */
    239 #define	AR_ISR_S2_TSFOOR	0x40000000	/* RX TSF out of range */
    240 
    241 #define	AR_INTR_SPURIOUS	0xffffffff
    242 #define	AR_INTR_RTC_IRQ		0x00000001	/* rtc in shutdown state */
    243 #define	AR_INTR_MAC_IRQ		0x00000002	/* pending mac interrupt */
    244 #define	AR_INTR_EEP_PROT_ACCESS	0x00000004	/* eeprom protected access */
    245 #define	AR_INTR_MAC_AWAKE	0x00020000	/* mac is awake */
    246 #define	AR_INTR_MAC_ASLEEP	0x00040000	/* mac is asleep */
    247 
    248 /* Interrupt Mask Registers */
    249 #define	AR_IMR_TXMINTR		0x00080000	/* Maximum interrupt tx rate */
    250 #define	AR_IMR_RXMINTR		0x01000000	/* Maximum interrupt rx rate */
    251 #define	AR_IMR_TXINTM		0x40000000	/* Tx int after mitigation */
    252 #define	AR_IMR_RXINTM		0x80000000	/* Rx int after mitigation */
    253 
    254 #define	AR_IMR_S2_CST		0x00400000	/* Carrier sense timeout */
    255 #define	AR_IMR_S2_GTT		0x00800000	/* Global transmit timeout */
    256 
    257 /* synchronous interrupt signals */
    258 #define	AR_INTR_SYNC_RTC_IRQ		0x00000001
    259 #define	AR_INTR_SYNC_MAC_IRQ		0x00000002
    260 #define	AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS	0x00000004
    261 #define	AR_INTR_SYNC_APB_TIMEOUT	0x00000008
    262 #define	AR_INTR_SYNC_PCI_MODE_CONFLICT	0x00000010
    263 #define	AR_INTR_SYNC_HOST1_FATAL	0x00000020
    264 #define	AR_INTR_SYNC_HOST1_PERR		0x00000040
    265 #define	AR_INTR_SYNC_TRCV_FIFO_PERR	0x00000080
    266 #define	AR_INTR_SYNC_RADM_CPL_EP	0x00000100
    267 #define	AR_INTR_SYNC_RADM_CPL_DLLP_ABORT	0x00000200
    268 #define	AR_INTR_SYNC_RADM_CPL_TLP_ABORT	0x00000400
    269 #define	AR_INTR_SYNC_RADM_CPL_ECRC_ERR	0x00000800
    270 #define	AR_INTR_SYNC_RADM_CPL_TIMEOUT	0x00001000
    271 #define	AR_INTR_SYNC_LOCAL_TIMEOUT	0x00002000
    272 #define	AR_INTR_SYNC_PM_ACCESS		0x00004000
    273 #define	AR_INTR_SYNC_MAC_AWAKE		0x00008000
    274 #define	AR_INTR_SYNC_MAC_ASLEEP		0x00010000
    275 #define	AR_INTR_SYNC_MAC_SLEEP_ACCESS	0x00020000
    276 #define	AR_INTR_SYNC_ALL		0x0003FFFF
    277 
    278 /* default synchronous interrupt signals enabled */
    279 #define	AR_INTR_SYNC_DEFAULT \
    280 	(AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR | \
    281 	 AR_INTR_SYNC_RADM_CPL_EP | AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | \
    282 	 AR_INTR_SYNC_RADM_CPL_TLP_ABORT | AR_INTR_SYNC_RADM_CPL_ECRC_ERR | \
    283 	 AR_INTR_SYNC_RADM_CPL_TIMEOUT | AR_INTR_SYNC_LOCAL_TIMEOUT | \
    284 	 AR_INTR_SYNC_MAC_SLEEP_ACCESS)
    285 
    286 /* RTC registers */
    287 #define	AR_RTC_RC_M		0x00000003
    288 #define	AR_RTC_RC_MAC_WARM	0x00000001
    289 #define	AR_RTC_RC_MAC_COLD	0x00000002
    290 #define	AR_RTC_PLL_DIV		0x0000001f
    291 #define	AR_RTC_PLL_DIV_S	0
    292 #define	AR_RTC_PLL_DIV2		0x00000020
    293 #define	AR_RTC_PLL_REFDIV_5	0x000000c0
    294 
    295 #define	AR_RTC_SOWL_PLL_DIV		0x000003ff
    296 #define	AR_RTC_SOWL_PLL_DIV_S		0
    297 #define	AR_RTC_SOWL_PLL_REFDIV		0x00003C00
    298 #define	AR_RTC_SOWL_PLL_REFDIV_S	10
    299 #define	AR_RTC_SOWL_PLL_CLKSEL		0x0000C000
    300 #define	AR_RTC_SOWL_PLL_CLKSEL_S	14
    301 
    302 #define	AR_RTC_RESET_EN		0x00000001	/* Reset RTC bit */
    303 
    304 #define	AR_RTC_PM_STATUS_M	0x0000000f	/* Pwr Mgmt Status */
    305 #define	AR_RTC_STATUS_M		0x0000003f	/* RTC Status */
    306 #define	AR_RTC_STATUS_SHUTDOWN	0x00000001
    307 #define	AR_RTC_STATUS_ON	0x00000002
    308 #define	AR_RTC_STATUS_SLEEP	0x00000004
    309 #define	AR_RTC_STATUS_WAKEUP	0x00000008
    310 #define	AR_RTC_STATUS_COLDRESET	0x00000010	/* Not currently used */
    311 #define	AR_RTC_STATUS_PLLCHANGE	0x00000020	/* Not currently used */
    312 
    313 #define	AR_RTC_SLEEP_DERIVED_CLK	0x2
    314 
    315 #define	AR_RTC_FORCE_WAKE_EN	0x00000001	/* enable force wake */
    316 #define	AR_RTC_FORCE_WAKE_ON_INT 0x00000002	/* auto-wake on MAC interrupt */
    317 
    318 #define	AR_RTC_PLL_CLKSEL	0x00000300
    319 #define	AR_RTC_PLL_CLKSEL_S	8
    320 
    321 /* AR9280: rf long shift registers */
    322 #define	AR_AN_RF2G1_CH0_OB      0x03800000
    323 #define	AR_AN_RF2G1_CH0_OB_S    23
    324 #define	AR_AN_RF2G1_CH0_DB      0x1C000000
    325 #define	AR_AN_RF2G1_CH0_DB_S    26
    326 
    327 #define	AR_AN_RF5G1_CH0_OB5     0x00070000
    328 #define	AR_AN_RF5G1_CH0_OB5_S   16
    329 #define	AR_AN_RF5G1_CH0_DB5     0x00380000
    330 #define	AR_AN_RF5G1_CH0_DB5_S   19
    331 
    332 #define	AR_AN_RF2G1_CH1_OB      0x03800000
    333 #define	AR_AN_RF2G1_CH1_OB_S    23
    334 #define	AR_AN_RF2G1_CH1_DB      0x1C000000
    335 #define	AR_AN_RF2G1_CH1_DB_S    26
    336 
    337 #define	AR_AN_RF5G1_CH1_OB5     0x00070000
    338 #define	AR_AN_RF5G1_CH1_OB5_S   16
    339 #define	AR_AN_RF5G1_CH1_DB5     0x00380000
    340 #define	AR_AN_RF5G1_CH1_DB5_S   19
    341 
    342 #define	AR_AN_TOP2_XPABIAS_LVL      0xC0000000
    343 #define	AR_AN_TOP2_XPABIAS_LVL_S    30
    344 #define	AR_AN_TOP2_LOCALBIAS        0x00200000
    345 #define	AR_AN_TOP2_LOCALBIAS_S      21
    346 #define	AR_AN_TOP2_PWDCLKIND        0x00400000
    347 #define	AR_AN_TOP2_PWDCLKIND_S      22
    348 
    349 #define	AR_AN_SYNTH9_REFDIVA    0xf8000000
    350 #define	AR_AN_SYNTH9_REFDIVA_S  27
    351 
    352 /* AR9285 Analog registers */
    353 #define	AR9285_AN_RF2G3_OB_0    0x00E00000
    354 #define	AR9285_AN_RF2G3_OB_0_S    21
    355 #define	AR9285_AN_RF2G3_OB_1    0x001C0000
    356 #define	AR9285_AN_RF2G3_OB_1_S    18
    357 #define	AR9285_AN_RF2G3_OB_2    0x00038000
    358 #define	AR9285_AN_RF2G3_OB_2_S    15
    359 #define	AR9285_AN_RF2G3_OB_3    0x00007000
    360 #define	AR9285_AN_RF2G3_OB_3_S    12
    361 #define	AR9285_AN_RF2G3_OB_4    0x00000E00
    362 #define	AR9285_AN_RF2G3_OB_4_S    9
    363 
    364 #define	AR9285_AN_RF2G3_DB1_0    0x000001C0
    365 #define	AR9285_AN_RF2G3_DB1_0_S    6
    366 #define	AR9285_AN_RF2G3_DB1_1    0x00000038
    367 #define	AR9285_AN_RF2G3_DB1_1_S    3
    368 #define	AR9285_AN_RF2G3_DB1_2    0x00000007
    369 #define	AR9285_AN_RF2G3_DB1_2_S    0
    370 #define	AR9285_AN_RF2G4_DB1_3    0xE0000000
    371 #define	AR9285_AN_RF2G4_DB1_3_S    29
    372 #define	AR9285_AN_RF2G4_DB1_4    0x1C000000
    373 #define	AR9285_AN_RF2G4_DB1_4_S    26
    374 
    375 #define	AR9285_AN_RF2G4_DB2_0    0x03800000
    376 #define	AR9285_AN_RF2G4_DB2_0_S    23
    377 #define	AR9285_AN_RF2G4_DB2_1    0x00700000
    378 #define	AR9285_AN_RF2G4_DB2_1_S    20
    379 #define	AR9285_AN_RF2G4_DB2_2    0x000E0000
    380 #define	AR9285_AN_RF2G4_DB2_2_S    17
    381 #define	AR9285_AN_RF2G4_DB2_3    0x0001C000
    382 #define	AR9285_AN_RF2G4_DB2_3_S    14
    383 #define	AR9285_AN_RF2G4_DB2_4    0x00003800
    384 #define	AR9285_AN_RF2G4_DB2_4_S    11
    385 
    386 #define	AR9285_AN_TOP3_XPABIAS_LVL      0x0000000C
    387 #define	AR9285_AN_TOP3_XPABIAS_LVL_S    2
    388 
    389 /* Sleep control */
    390 #define	AR5416_SLEEP1_CAB_TIMEOUT	0xFFE00000	/* Cab timeout (TU) */
    391 #define	AR5416_SLEEP1_CAB_TIMEOUT_S	22
    392 
    393 #define	AR5416_SLEEP2_BEACON_TIMEOUT	0xFFE00000	/* Beacon timeout (TU)*/
    394 #define	AR5416_SLEEP2_BEACON_TIMEOUT_S	22
    395 
    396 /* Sleep Registers */
    397 #define	AR_SLP32_HALFCLK_LATENCY      0x000FFFFF	/* rising <-> falling edge */
    398 #define	AR_SLP32_ENA		0x00100000
    399 #define	AR_SLP32_TSF_WRITE_STATUS      0x00200000	/* tsf update in progress */
    400 
    401 #define	AR_SLP32_WAKE_XTL_TIME	0x0000FFFF	/* time to wake crystal */
    402 
    403 #define	AR_SLP32_TST_INC	0x000FFFFF
    404 
    405 #define	AR_SLP_MIB_CLEAR	0x00000001	/* clear pending */
    406 #define	AR_SLP_MIB_PENDING	0x00000002	/* clear counters */
    407 
    408 #define	AR_TIMER_MODE_TBTT		0x00000001
    409 #define	AR_TIMER_MODE_DBA		0x00000002
    410 #define	AR_TIMER_MODE_SWBA		0x00000004
    411 #define	AR_TIMER_MODE_HCF		0x00000008
    412 #define	AR_TIMER_MODE_TIM		0x00000010
    413 #define	AR_TIMER_MODE_DTIM		0x00000020
    414 #define	AR_TIMER_MODE_QUIET		0x00000040
    415 #define	AR_TIMER_MODE_NDP		0x00000080
    416 #define	AR_TIMER_MODE_OVERFLOW_INDEX	0x00000700
    417 #define	AR_TIMER_MODE_OVERFLOW_INDEX_S	8
    418 #define	AR_TIMER_MODE_THRESH		0xFFFFF000
    419 #define	AR_TIMER_MODE_THRESH_S		12
    420 
    421 /* PCU Misc modes */
    422 #define	AR_PCU_FORCE_BSSID_MATCH	0x00000001 /* force bssid to match */
    423 #define	AR_PCU_MIC_NEW_LOC_ENA		0x00000004 /* tx/rx mic keys together */
    424 #define	AR_PCU_TX_ADD_TSF		0x00000008 /* add tx_tsf + int_tsf */
    425 #define	AR_PCU_CCK_SIFS_MODE		0x00000010 /* assume 11b sifs */
    426 #define	AR_PCU_RX_ANT_UPDT		0x00000800 /* KC_RX_ANT_UPDATE */
    427 #define	AR_PCU_TXOP_TBTT_LIMIT_ENA	0x00001000 /* enforce txop / tbtt */
    428 #define	AR_PCU_MISS_BCN_IN_SLEEP	0x00004000 /* count bmiss's when sleeping */
    429 #define	AR_PCU_BUG_12306_FIX_ENA	0x00020000 /* use rx_clear to count sifs */
    430 #define	AR_PCU_FORCE_QUIET_COLL		0x00040000 /* kill xmit for channel change */
    431 #define	AR_PCU_TBTT_PROTECT		0x00200000 /* no xmit upto tbtt+20 uS */
    432 #define	AR_PCU_CLEAR_VMF		0x01000000 /* clear vmf mode (fast cc)*/
    433 #define	AR_PCU_CLEAR_BA_VALID		0x04000000 /* clear ba state */
    434 
    435 #define	AR_PCU_MISC_MODE2_HWWAR1	0x00100000
    436 
    437 /* GPIO Interrupt */
    438 #define	AR_INTR_GPIO		0x3FF00000	/* gpio interrupted */
    439 #define	AR_INTR_GPIO_S		20
    440 
    441 #define	AR_GPIO_OUT_CTRL	0x000003FF	/* 0 = out, 1 = in */
    442 #define	AR_GPIO_OUT_VAL		0x000FFC00
    443 #define	AR_GPIO_OUT_VAL_S	10
    444 #define	AR_GPIO_INTR_CTRL	0x3FF00000
    445 #define	AR_GPIO_INTR_CTRL_S	20
    446 
    447 #define	AR_2040_JOINED_RX_CLEAR	0x00000001	/* use ctl + ext rx_clear for cca */
    448 
    449 #define	AR_PCU_TXBUF_CTRL_SIZE_MASK	0x7FF
    450 #define	AR_PCU_TXBUF_CTRL_USABLE_SIZE	0x700
    451 
    452 /* Eeprom defines */
    453 #define	AR_EEPROM_STATUS_DATA_VAL           0x0000ffff
    454 #define	AR_EEPROM_STATUS_DATA_VAL_S         0
    455 #define	AR_EEPROM_STATUS_DATA_BUSY          0x00010000
    456 #define	AR_EEPROM_STATUS_DATA_BUSY_ACCESS   0x00020000
    457 #define	AR_EEPROM_STATUS_DATA_PROT_ACCESS   0x00040000
    458 #define	AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000
    459 
    460 #define	AR_SREV_REVISION_OWL_10		0x08
    461 #define	AR_SREV_REVISION_OWL_20		0x09
    462 #define	AR_SREV_REVISION_OWL_22		0x0a
    463 
    464 #define	AR_RAD5133_SREV_MAJOR		0xc0	/* Fowl: 2+5G/3x3 */
    465 #define	AR_RAD2133_SREV_MAJOR		0xd0	/* Fowl: 2G/3x3   */
    466 #define	AR_RAD5122_SREV_MAJOR		0xe0	/* Fowl: 5G/2x2   */
    467 #define	AR_RAD2122_SREV_MAJOR		0xf0	/* Fowl: 2+5G/2x2 */
    468 
    469 /* Test macro for owl 1.0 */
    470 #define	IS_5416V1(_ah)	((_ah)->ah_macRev == AR_SREV_REVISION_OWL_10)
    471 #define	IS_5416V2(_ah)	((_ah)->ah_macRev >= AR_SREV_REVISION_OWL_20)
    472 #define	IS_5416V2_2(_ah)	((_ah)->ah_macRev == AR_SREV_REVISION_OWL_22)
    473 
    474 /* Expanded Mac Silicon Rev (16 bits starting with Sowl) */
    475 #define	AR_XSREV_ID		0xFFFFFFFF	/* Chip ID */
    476 #define	AR_XSREV_ID_S		0
    477 #define	AR_XSREV_VERSION	0xFFFC0000	/* Chip version */
    478 #define	AR_XSREV_VERSION_S	18
    479 #define	AR_XSREV_TYPE		0x0003F000	/* Chip type */
    480 #define	AR_XSREV_TYPE_S		12
    481 #define	AR_XSREV_TYPE_CHAIN	0x00001000	/* Chain Mode (1:3 chains,
    482 						 * 0:2 chains) */
    483 #define	AR_XSREV_TYPE_HOST_MODE 0x00002000	/* Host Mode (1:PCI, 0:PCIe) */
    484 #define	AR_XSREV_REVISION	0x00000F00
    485 #define	AR_XSREV_REVISION_S	8
    486 
    487 #define	AR_XSREV_VERSION_OWL_PCI	0x0D
    488 #define	AR_XSREV_VERSION_OWL_PCIE	0x0C
    489 #define	AR_XSREV_REVISION_OWL_10	0	/* Owl 1.0 */
    490 #define	AR_XSREV_REVISION_OWL_20	1	/* Owl 2.0/2.1 */
    491 #define	AR_XSREV_REVISION_OWL_22	2	/* Owl 2.2 */
    492 #define	AR_XSREV_VERSION_SOWL		0x40
    493 #define	AR_XSREV_REVISION_SOWL_10	0	/* Sowl 1.0 */
    494 #define	AR_XSREV_REVISION_SOWL_11	1	/* Sowl 1.1 */
    495 #define	AR_XSREV_VERSION_MERLIN		0x80	/* Merlin Version */
    496 #define	AR_XSREV_REVISION_MERLIN_10	0	/* Merlin 1.0 */
    497 #define	AR_XSREV_REVISION_MERLIN_20	1	/* Merlin 2.0 */
    498 #define	AR_XSREV_REVISION_MERLIN_21	2	/* Merlin 2.1 */
    499 #define	AR_XSREV_VERSION_KITE		0xC0	/* Kite Version */
    500 #define	AR_XSREV_REVISION_KITE_10	0	/* Kite 1.0 */
    501 #define	AR_XSREV_REVISION_KITE_11	1	/* Kite 1.1 */
    502 #define	AR_XSREV_REVISION_KITE_12	2	/* Kite 1.2 */
    503 
    504 #define	AR_SREV_OWL_20_OR_LATER(_ah) \
    505 	(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL || \
    506 	 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_OWL_20)
    507 #define	AR_SREV_OWL_22_OR_LATER(_ah) \
    508 	(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL || \
    509 	 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_OWL_22)
    510 
    511 #define	AR_SREV_SOWL(_ah) \
    512 	(AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_SOWL)
    513 #define	AR_SREV_SOWL_10_OR_LATER(_ah) \
    514 	(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL)
    515 #define	AR_SREV_SOWL_11(_ah) \
    516 	(AR_SREV_SOWL(_ah) && \
    517 	 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_SOWL_11)
    518 
    519 #define	AR_SREV_MERLIN(_ah) \
    520 	(AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_MERLIN)
    521 #define	AR_SREV_MERLIN_10_OR_LATER(_ah)	\
    522 	(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_MERLIN)
    523 #define	AR_SREV_MERLIN_20(_ah) \
    524 	(AR_SREV_MERLIN(_ah) && \
    525 	 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_MERLIN_20)
    526 #define	AR_SREV_MERLIN_20_OR_LATER(_ah) \
    527 	(AR_SREV_MERLIN_20(_ah) || \
    528 	 AH_PRIVATE((_ah))->ah_macVersion > AR_XSREV_VERSION_MERLIN)
    529 
    530 #define	AR_SREV_KITE(_ah) \
    531 	(AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KITE)
    532 #define	AR_SREV_KITE_10_OR_LATER(_ah) \
    533 	(AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KITE)
    534 #define AR_SREV_KITE_11(_ah) \
    535 	(AR_SREV_KITE(ah) && \
    536 	 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_11)
    537 #define AR_SREV_KITE_11_OR_LATER(_ah) \
    538 	(AR_SREV_KITE_11(_ah) || \
    539 	 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_11)
    540 #define AR_SREV_KITE_12(_ah) \
    541 	(AR_SREV_KITE(ah) && \
    542 	 AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_12)
    543 #define AR_SREV_KITE_12_OR_LATER(_ah) \
    544 	(AR_SREV_KITE_12(_ah) || \
    545 	 AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_12)
    546 #endif /* _DEV_ATH_AR5416REG_H */
    547