ar9280_attach.c revision 1.1
1 /* 2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 #include "ah_devid.h" 24 25 #include "ah_eeprom_v14.h" /* XXX for tx/rx gain */ 26 27 #include "ar5416/ar9280.h" 28 #include "ar5416/ar5416reg.h" 29 #include "ar5416/ar5416phy.h" 30 31 #include "ar5416/ar9280v1.ini" 32 #include "ar5416/ar9280v2.ini" 33 34 static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */ 35 .calName = "IQ", .calType = IQ_MISMATCH_CAL, 36 .calNumSamples = MIN_CAL_SAMPLES, 37 .calCountMax = PER_MAX_LOG_COUNT, 38 .calCollect = ar5416IQCalCollect, 39 .calPostProc = ar5416IQCalibration 40 }; 41 static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */ 42 .calName = "ADC Gain", .calType = ADC_GAIN_CAL, 43 .calNumSamples = MIN_CAL_SAMPLES, 44 .calCountMax = PER_MIN_LOG_COUNT, 45 .calCollect = ar5416AdcGainCalCollect, 46 .calPostProc = ar5416AdcGainCalibration 47 }; 48 static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */ 49 .calName = "ADC DC", .calType = ADC_DC_CAL, 50 .calNumSamples = MIN_CAL_SAMPLES, 51 .calCountMax = PER_MIN_LOG_COUNT, 52 .calCollect = ar5416AdcDcCalCollect, 53 .calPostProc = ar5416AdcDcCalibration 54 }; 55 static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = { 56 .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL, 57 .calNumSamples = MIN_CAL_SAMPLES, 58 .calCountMax = INIT_LOG_COUNT, 59 .calCollect = ar5416AdcDcCalCollect, 60 .calPostProc = ar5416AdcDcCalibration 61 }; 62 63 static void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 64 static HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah); 65 static void ar9280WriteIni(struct ath_hal *ah, 66 HAL_CHANNEL_INTERNAL *chan); 67 static void ar9280SpurMitigate(struct ath_hal *ah, 68 HAL_CHANNEL_INTERNAL *chan); 69 70 static void 71 ar9280AniSetup(struct ath_hal *ah) 72 { 73 /* NB: disable ANI for reliable RIFS rx */ 74 ar5212AniAttach(ah, AH_NULL, AH_NULL, AH_FALSE); 75 } 76 77 static uint32_t 78 ar5416GetRadioRev(struct ath_hal *ah) 79 { 80 uint32_t val; 81 int i; 82 83 /* Read Radio Chip Rev Extract */ 84 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 85 for (i = 0; i < 8; i++) 86 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 87 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 88 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 89 return ath_hal_reverseBits(val, 8); 90 } 91 92 /* 93 * Attach for an AR9280 part. 94 */ 95 static struct ath_hal * 96 ar9280Attach(uint16_t devid, HAL_SOFTC sc, 97 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 98 { 99 struct ath_hal_9280 *ahp9280; 100 struct ath_hal_5212 *ahp; 101 struct ath_hal *ah; 102 uint32_t val; 103 HAL_STATUS ecode; 104 HAL_BOOL rfStatus; 105 106 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 107 __func__, sc, (void*) st, (void*) sh); 108 109 /* NB: memory is returned zero'd */ 110 ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280)); 111 if (ahp9280 == AH_NULL) { 112 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 113 "%s: cannot allocate memory for state block\n", __func__); 114 *status = HAL_ENOMEM; 115 return AH_NULL; 116 } 117 ahp = AH5212(ahp9280); 118 ah = &ahp->ah_priv.h; 119 120 ar5416InitState(AH5416(ah), devid, sc, st, sh, status); 121 122 /* XXX override with 9280 specific state */ 123 /* override 5416 methods for our needs */ 124 ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch; 125 ah->ah_configPCIE = ar9280ConfigPCIE; 126 127 AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal; 128 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal; 129 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal; 130 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal; 131 AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 132 133 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate; 134 AH5416(ah)->ah_writeIni = ar9280WriteIni; 135 AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 136 AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 137 138 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 139 /* reset chip */ 140 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", 141 __func__); 142 ecode = HAL_EIO; 143 goto bad; 144 } 145 146 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 147 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 148 __func__); 149 ecode = HAL_EIO; 150 goto bad; 151 } 152 /* Read Revisions from Chips before taking out of reset */ 153 val = OS_REG_READ(ah, AR_SREV); 154 HALDEBUG(ah, HAL_DEBUG_ATTACH, 155 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n", 156 __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION), 157 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION)); 158 /* NB: include chip type to differentiate from pre-Sowl versions */ 159 AH_PRIVATE(ah)->ah_macVersion = 160 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S; 161 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION); 162 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0; 163 164 /* setup common ini data; rf backends handle remainder */ 165 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 166 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6); 167 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2); 168 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 169 ar9280PciePhy_clkreq_always_on_L1_v2, 2); 170 HAL_INI_INIT(&ahp9280->ah_ini_xmodes, 171 ar9280Modes_fast_clock_v2, 3); 172 } else { 173 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6); 174 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2); 175 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 176 ar9280PciePhy_v1, 2); 177 } 178 ar5416AttachPCIE(ah); 179 180 ecode = ath_hal_v14EepromAttach(ah); 181 if (ecode != HAL_OK) 182 goto bad; 183 184 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 185 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 186 ecode = HAL_EIO; 187 goto bad; 188 } 189 190 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 191 192 if (!ar5212ChipTest(ah)) { 193 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 194 __func__); 195 ecode = HAL_ESELFTEST; 196 goto bad; 197 } 198 199 /* 200 * Set correct Baseband to analog shift 201 * setting to access analog chips. 202 */ 203 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 204 205 /* Read Radio Chip Rev Extract */ 206 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 207 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 208 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */ 209 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */ 210 break; 211 default: 212 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 213 AH_PRIVATE(ah)->ah_analog5GhzRev = 214 AR_RAD5133_SREV_MAJOR; 215 break; 216 } 217 #ifdef AH_DEBUG 218 HALDEBUG(ah, HAL_DEBUG_ANY, 219 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 220 "this driver\n", __func__, 221 AH_PRIVATE(ah)->ah_analog5GhzRev); 222 ecode = HAL_ENOTSUPP; 223 goto bad; 224 #endif 225 } 226 rfStatus = ar9280RfAttach(ah, &ecode); 227 if (!rfStatus) { 228 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 229 __func__, ecode); 230 goto bad; 231 } 232 233 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 234 /* setup rxgain table */ 235 switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) { 236 case AR5416_EEP_RXGAIN_13dB_BACKOFF: 237 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 238 ar9280Modes_backoff_13db_rxgain_v2, 6); 239 break; 240 case AR5416_EEP_RXGAIN_23dB_BACKOFF: 241 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 242 ar9280Modes_backoff_23db_rxgain_v2, 6); 243 break; 244 case AR5416_EEP_RXGAIN_ORIG: 245 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 246 ar9280Modes_original_rxgain_v2, 6); 247 break; 248 default: 249 HALASSERT(AH_FALSE); 250 goto bad; /* XXX ? try to continue */ 251 } 252 } 253 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 254 /* setp txgain table */ 255 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) { 256 case AR5416_EEP_TXGAIN_HIGH_POWER: 257 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 258 ar9280Modes_high_power_tx_gain_v2, 6); 259 break; 260 case AR5416_EEP_TXGAIN_ORIG: 261 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 262 ar9280Modes_original_tx_gain_v2, 6); 263 break; 264 default: 265 HALASSERT(AH_FALSE); 266 goto bad; /* XXX ? try to continue */ 267 } 268 } 269 270 /* 271 * Got everything we need now to setup the capabilities. 272 */ 273 if (!ar9280FillCapabilityInfo(ah)) { 274 ecode = HAL_EEREAD; 275 goto bad; 276 } 277 278 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 279 if (ecode != HAL_OK) { 280 HALDEBUG(ah, HAL_DEBUG_ANY, 281 "%s: error getting mac address from EEPROM\n", __func__); 282 goto bad; 283 } 284 /* XXX How about the serial number ? */ 285 /* Read Reg Domain */ 286 AH_PRIVATE(ah)->ah_currentRD = 287 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 288 289 /* 290 * ah_miscMode is populated by ar5416FillCapabilityInfo() 291 * starting from griffin. Set here to make sure that 292 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 293 * placed into hardware. 294 */ 295 if (ahp->ah_miscMode != 0) 296 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode); 297 298 ar9280AniSetup(ah); /* Anti Noise Immunity */ 299 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 300 301 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 302 303 return ah; 304 bad: 305 if (ah != AH_NULL) 306 ah->ah_detach(ah); 307 if (status) 308 *status = ecode; 309 return AH_NULL; 310 } 311 312 static void 313 ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 314 { 315 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 316 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 317 OS_DELAY(1000); 318 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 319 OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT); 320 } 321 } 322 323 static void 324 ar9280WriteIni(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan) 325 { 326 u_int modesIndex, freqIndex; 327 int regWrites = 0; 328 329 /* Setup the indices for the next set of register array writes */ 330 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 331 if (IS_CHAN_2GHZ(chan)) { 332 freqIndex = 2; 333 if (IS_CHAN_HT40(chan)) 334 modesIndex = 3; 335 else if (IS_CHAN_108G(chan)) 336 modesIndex = 5; 337 else 338 modesIndex = 4; 339 } else { 340 freqIndex = 1; 341 if (IS_CHAN_HT40(chan) || 342 IS_CHAN_TURBO(chan)) 343 modesIndex = 2; 344 else 345 modesIndex = 1; 346 } 347 348 /* Set correct Baseband to analog shift setting to access analog chips. */ 349 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 350 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 351 352 /* XXX Merlin ini fixups */ 353 /* XXX Merlin 100us delay for shift registers */ 354 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 355 modesIndex, regWrites); 356 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 357 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain, 358 modesIndex, regWrites); 359 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain, 360 modesIndex, regWrites); 361 } 362 /* XXX Merlin 100us delay for shift registers */ 363 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 364 1, regWrites); 365 366 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { 367 /* 5GHz channels w/ Fast Clock use different modal values */ 368 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes, 369 modesIndex, regWrites); 370 } 371 } 372 373 #define AR_BASE_FREQ_2GHZ 2300 374 #define AR_BASE_FREQ_5GHZ 4900 375 #define AR_SPUR_FEEQ_BOUND_HT40 19 376 #define AR_SPUR_FEEQ_BOUND_HT20 10 377 378 static void 379 ar9280SpurMitigate(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan) 380 { 381 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 382 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 383 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 384 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 385 static int inc[4] = { 0, 100, 0, 0 }; 386 387 int bb_spur = AR_NO_SPUR; 388 int freq; 389 int bin, cur_bin; 390 int bb_spur_off, spur_subchannel_sd; 391 int spur_freq_sd; 392 int spur_delta_phase; 393 int denominator; 394 int upper, lower, cur_vit_mask; 395 int tmp, newVal; 396 int i; 397 CHAN_CENTERS centers; 398 399 int8_t mask_m[123]; 400 int8_t mask_p[123]; 401 int8_t mask_amt; 402 int tmp_mask; 403 int cur_bb_spur; 404 HAL_BOOL is2GHz = IS_CHAN_2GHZ(chan); 405 406 OS_MEMZERO(&mask_m, sizeof(int8_t) * 123); 407 OS_MEMZERO(&mask_p, sizeof(int8_t) * 123); 408 409 ar5416GetChannelCenters(ah, chan, ¢ers); 410 freq = centers.synth_center; 411 412 /* 413 * Need to verify range +/- 9.38 for static ht20 and +/- 18.75 for ht40, 414 * otherwise spur is out-of-band and can be ignored. 415 */ 416 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 417 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 418 /* Get actual spur freq in MHz from EEPROM read value */ 419 if (is2GHz) { 420 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; 421 } else { 422 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; 423 } 424 425 if (AR_NO_SPUR == cur_bb_spur) 426 break; 427 cur_bb_spur = cur_bb_spur - freq; 428 429 if (IS_CHAN_HT40(chan)) { 430 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && 431 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { 432 bb_spur = cur_bb_spur; 433 break; 434 } 435 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && 436 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { 437 bb_spur = cur_bb_spur; 438 break; 439 } 440 } 441 442 if (AR_NO_SPUR == bb_spur) { 443 #if 1 444 /* 445 * MRC CCK can interfere with beacon detection and cause deaf/mute. 446 * Disable MRC CCK for now. 447 */ 448 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 449 #else 450 /* Enable MRC CCK if no spur is found in this channel. */ 451 OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 452 #endif 453 return; 454 } else { 455 /* 456 * For Merlin, spur can break CCK MRC algorithm. Disable CCK MRC if spur 457 * is found in this channel. 458 */ 459 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 460 } 461 462 bin = bb_spur * 320; 463 464 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 465 466 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 467 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 468 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 469 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 470 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal); 471 472 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 473 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 474 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 475 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 476 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 477 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); 478 479 /* Pick control or extn channel to cancel the spur */ 480 if (IS_CHAN_HT40(chan)) { 481 if (bb_spur < 0) { 482 spur_subchannel_sd = 1; 483 bb_spur_off = bb_spur + 10; 484 } else { 485 spur_subchannel_sd = 0; 486 bb_spur_off = bb_spur - 10; 487 } 488 } else { 489 spur_subchannel_sd = 0; 490 bb_spur_off = bb_spur; 491 } 492 493 /* 494 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 495 * /80 for dyn2040. 496 */ 497 if (IS_CHAN_HT40(chan)) 498 spur_delta_phase = ((bb_spur * 262144) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 499 else 500 spur_delta_phase = ((bb_spur * 524288) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 501 502 /* 503 * in 11A mode the denominator of spur_freq_sd should be 40 and 504 * it should be 44 in 11G 505 */ 506 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40; 507 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; 508 509 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 510 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 511 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 512 OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal); 513 514 /* Choose to cancel between control and extension channels */ 515 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; 516 OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); 517 518 /* 519 * ============================================ 520 * Set Pilot and Channel Masks 521 * 522 * pilot mask 1 [31:0] = +6..-26, no 0 bin 523 * pilot mask 2 [19:0] = +26..+7 524 * 525 * channel mask 1 [31:0] = +6..-26, no 0 bin 526 * channel mask 2 [19:0] = +26..+7 527 */ 528 cur_bin = -6000; 529 upper = bin + 100; 530 lower = bin - 100; 531 532 for (i = 0; i < 4; i++) { 533 int pilot_mask = 0; 534 int chan_mask = 0; 535 int bp = 0; 536 for (bp = 0; bp < 30; bp++) { 537 if ((cur_bin > lower) && (cur_bin < upper)) { 538 pilot_mask = pilot_mask | 0x1 << bp; 539 chan_mask = chan_mask | 0x1 << bp; 540 } 541 cur_bin += 100; 542 } 543 cur_bin += inc[i]; 544 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 545 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 546 } 547 548 /* ================================================= 549 * viterbi mask 1 based on channel magnitude 550 * four levels 0-3 551 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 552 * [1 2 2 1] for -9.6 or [1 2 1] for +16 553 * - enable_mask_ppm, all bins move with freq 554 * 555 * - mask_select, 8 bits for rates (reg 67,0x990c) 556 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 557 * choose which mask to use mask or mask2 558 */ 559 560 /* 561 * viterbi mask 2 2nd set for per data rate puncturing 562 * four levels 0-3 563 * - mask_select, 8 bits for rates (reg 67) 564 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 565 * [1 2 2 1] for -9.6 or [1 2 1] for +16 566 */ 567 cur_vit_mask = 6100; 568 upper = bin + 120; 569 lower = bin - 120; 570 571 for (i = 0; i < 123; i++) { 572 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 573 if ((abs(cur_vit_mask - bin)) < 75) { 574 mask_amt = 1; 575 } else { 576 mask_amt = 0; 577 } 578 if (cur_vit_mask < 0) { 579 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 580 } else { 581 mask_p[cur_vit_mask / 100] = mask_amt; 582 } 583 } 584 cur_vit_mask -= 100; 585 } 586 587 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 588 | (mask_m[48] << 26) | (mask_m[49] << 24) 589 | (mask_m[50] << 22) | (mask_m[51] << 20) 590 | (mask_m[52] << 18) | (mask_m[53] << 16) 591 | (mask_m[54] << 14) | (mask_m[55] << 12) 592 | (mask_m[56] << 10) | (mask_m[57] << 8) 593 | (mask_m[58] << 6) | (mask_m[59] << 4) 594 | (mask_m[60] << 2) | (mask_m[61] << 0); 595 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 596 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 597 598 tmp_mask = (mask_m[31] << 28) 599 | (mask_m[32] << 26) | (mask_m[33] << 24) 600 | (mask_m[34] << 22) | (mask_m[35] << 20) 601 | (mask_m[36] << 18) | (mask_m[37] << 16) 602 | (mask_m[48] << 14) | (mask_m[39] << 12) 603 | (mask_m[40] << 10) | (mask_m[41] << 8) 604 | (mask_m[42] << 6) | (mask_m[43] << 4) 605 | (mask_m[44] << 2) | (mask_m[45] << 0); 606 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 607 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 608 609 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 610 | (mask_m[18] << 26) | (mask_m[18] << 24) 611 | (mask_m[20] << 22) | (mask_m[20] << 20) 612 | (mask_m[22] << 18) | (mask_m[22] << 16) 613 | (mask_m[24] << 14) | (mask_m[24] << 12) 614 | (mask_m[25] << 10) | (mask_m[26] << 8) 615 | (mask_m[27] << 6) | (mask_m[28] << 4) 616 | (mask_m[29] << 2) | (mask_m[30] << 0); 617 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 618 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 619 620 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 621 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 622 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 623 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 624 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 625 | (mask_m[10] << 10) | (mask_m[11] << 8) 626 | (mask_m[12] << 6) | (mask_m[13] << 4) 627 | (mask_m[14] << 2) | (mask_m[15] << 0); 628 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 629 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 630 631 tmp_mask = (mask_p[15] << 28) 632 | (mask_p[14] << 26) | (mask_p[13] << 24) 633 | (mask_p[12] << 22) | (mask_p[11] << 20) 634 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 635 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 636 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 637 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 638 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 639 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 640 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 641 642 tmp_mask = (mask_p[30] << 28) 643 | (mask_p[29] << 26) | (mask_p[28] << 24) 644 | (mask_p[27] << 22) | (mask_p[26] << 20) 645 | (mask_p[25] << 18) | (mask_p[24] << 16) 646 | (mask_p[23] << 14) | (mask_p[22] << 12) 647 | (mask_p[21] << 10) | (mask_p[20] << 8) 648 | (mask_p[19] << 6) | (mask_p[18] << 4) 649 | (mask_p[17] << 2) | (mask_p[16] << 0); 650 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 651 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 652 653 tmp_mask = (mask_p[45] << 28) 654 | (mask_p[44] << 26) | (mask_p[43] << 24) 655 | (mask_p[42] << 22) | (mask_p[41] << 20) 656 | (mask_p[40] << 18) | (mask_p[39] << 16) 657 | (mask_p[38] << 14) | (mask_p[37] << 12) 658 | (mask_p[36] << 10) | (mask_p[35] << 8) 659 | (mask_p[34] << 6) | (mask_p[33] << 4) 660 | (mask_p[32] << 2) | (mask_p[31] << 0); 661 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 662 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 663 664 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 665 | (mask_p[59] << 26) | (mask_p[58] << 24) 666 | (mask_p[57] << 22) | (mask_p[56] << 20) 667 | (mask_p[55] << 18) | (mask_p[54] << 16) 668 | (mask_p[53] << 14) | (mask_p[52] << 12) 669 | (mask_p[51] << 10) | (mask_p[50] << 8) 670 | (mask_p[49] << 6) | (mask_p[48] << 4) 671 | (mask_p[47] << 2) | (mask_p[46] << 0); 672 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 673 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 674 } 675 676 /* 677 * Fill all software cached or static hardware state information. 678 * Return failure if capabilities are to come from EEPROM and 679 * cannot be read. 680 */ 681 static HAL_BOOL 682 ar9280FillCapabilityInfo(struct ath_hal *ah) 683 { 684 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 685 686 if (!ar5416FillCapabilityInfo(ah)) 687 return AH_FALSE; 688 pCap->halNumGpioPins = 10; 689 pCap->halWowSupport = AH_TRUE; 690 pCap->halWowMatchPatternExact = AH_TRUE; 691 #if 0 692 pCap->halWowMatchPatternDword = AH_TRUE; 693 #endif 694 pCap->halCSTSupport = AH_TRUE; 695 pCap->halRifsRxSupport = AH_TRUE; 696 pCap->halRifsTxSupport = AH_TRUE; 697 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */ 698 pCap->halExtChanDfsSupport = AH_TRUE; 699 #if 0 700 /* XXX bluetooth */ 701 pCap->halBtCoexSupport = AH_TRUE; 702 #endif 703 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */ 704 #if 0 705 pCap->hal4kbSplitTransSupport = AH_FALSE; 706 #endif 707 pCap->halRxStbcSupport = 1; 708 pCap->halTxStbcSupport = 1; 709 710 return AH_TRUE; 711 } 712 713 HAL_BOOL 714 ar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 715 { 716 #define ANTENNA0_CHAINMASK 0x1 717 #define ANTENNA1_CHAINMASK 0x2 718 struct ath_hal_5416 *ahp = AH5416(ah); 719 720 /* Antenna selection is done by setting the tx/rx chainmasks approp. */ 721 switch (settings) { 722 case HAL_ANT_FIXED_A: 723 /* Enable first antenna only */ 724 ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK; 725 ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK; 726 break; 727 case HAL_ANT_FIXED_B: 728 /* Enable second antenna only, after checking capability */ 729 if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK) 730 ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK; 731 ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK; 732 break; 733 case HAL_ANT_VARIABLE: 734 /* Restore original chainmask settings */ 735 /* XXX */ 736 ahp->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 737 ahp->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 738 break; 739 } 740 return AH_TRUE; 741 #undef ANTENNA0_CHAINMASK 742 #undef ANTENNA1_CHAINMASK 743 } 744 745 static const char* 746 ar9280Probe(uint16_t vendorid, uint16_t devid) 747 { 748 if (vendorid == ATHEROS_VENDOR_ID && 749 (devid == AR9280_DEVID_PCI || devid == AR9280_DEVID_PCIE)) 750 return "Atheros 9280"; 751 return AH_NULL; 752 } 753 AH_CHIP(AR9280, ar9280Probe, ar9280Attach); 754
Indexes created Fri Oct 31 04:09:52 GMT 2025