ah_osdep.c revision 1.1 1 1.1 alc /*-
2 1.1 alc * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 1.1 alc * All rights reserved.
4 1.1 alc *
5 1.1 alc * Redistribution and use in source and binary forms, with or without
6 1.1 alc * modification, are permitted provided that the following conditions
7 1.1 alc * are met:
8 1.1 alc * 1. Redistributions of source code must retain the above copyright
9 1.1 alc * notice, this list of conditions and the following disclaimer,
10 1.1 alc * without modification.
11 1.1 alc * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 1.1 alc * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 1.1 alc * redistribution must be conditioned upon including a substantially
14 1.1 alc * similar Disclaimer requirement for further binary redistribution.
15 1.1 alc *
16 1.1 alc * NO WARRANTY
17 1.1 alc * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 1.1 alc * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 1.1 alc * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 1.1 alc * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 1.1 alc * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 1.1 alc * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 1.1 alc * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 1.1 alc * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 1.1 alc * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 1.1 alc * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 1.1 alc * THE POSSIBILITY OF SUCH DAMAGES.
28 1.1 alc *
29 1.1 alc * $Id: ah_osdep.c,v 1.1 2008/12/11 05:37:40 alc Exp $
30 1.1 alc */
31 1.1 alc
32 1.1 alc #include <sys/cdefs.h>
33 1.1 alc __KERNEL_RCSID(0, "$NetBSD: ah_osdep.c,v 1.1 2008/12/11 05:37:40 alc Exp $");
34 1.1 alc
35 1.1 alc #include "opt_athhal.h"
36 1.1 alc
37 1.1 alc #include <sys/param.h>
38 1.1 alc #include <sys/systm.h>
39 1.1 alc #include <sys/kernel.h>
40 1.1 alc #include <sys/sysctl.h>
41 1.1 alc #include <sys/malloc.h>
42 1.1 alc #include <sys/proc.h>
43 1.1 alc #include <sys/kauth.h>
44 1.1 alc
45 1.1 alc #include <machine/stdarg.h>
46 1.1 alc
47 1.1 alc #include <net/if.h>
48 1.1 alc #include <net/if_dl.h>
49 1.1 alc #include <net/if_media.h>
50 1.1 alc #include <net/if_arp.h>
51 1.1 alc #include <net/if_ether.h>
52 1.1 alc
53 1.1 alc #include <external/isc/atheros_hal/dist/ah.h>
54 1.1 alc
55 1.1 alc #ifdef __mips__
56 1.1 alc #include <sys/cpu.h>
57 1.1 alc
58 1.1 alc #define ENTER lwp_t *savlwp = curlwp; curlwp = cpu_info_store.ci_curlwp;
59 1.1 alc #define EXIT curlwp = savlwp;
60 1.1 alc #else
61 1.1 alc #define ENTER /* nothing */
62 1.1 alc #define EXIT /* nothing */
63 1.1 alc #endif
64 1.1 alc
65 1.1 alc extern void ath_hal_printf(struct ath_hal *, const char*, ...)
66 1.1 alc __printflike(2,3);
67 1.1 alc extern void ath_hal_vprintf(struct ath_hal *, const char*, va_list)
68 1.1 alc __printflike(2, 0);
69 1.1 alc extern const char* ath_hal_ether_sprintf(const u_int8_t *mac);
70 1.1 alc extern void *ath_hal_malloc(size_t);
71 1.1 alc extern void ath_hal_free(void *);
72 1.1 alc #ifdef ATHHAL_ASSERT
73 1.1 alc extern void ath_hal_assert_failed(const char* filename,
74 1.1 alc int lineno, const char* msg);
75 1.1 alc #endif
76 1.1 alc #ifdef ATHHAL_DEBUG
77 1.1 alc extern void HALDEBUG(struct ath_hal *ah, const char* fmt, ...);
78 1.1 alc extern void HALDEBUGn(struct ath_hal *ah, u_int level, const char* fmt, ...);
79 1.1 alc #endif /* ATHHAL_DEBUG */
80 1.1 alc
81 1.1 alc #ifdef ATHHAL_DEBUG
82 1.1 alc static int ath_hal_debug = 0;
83 1.1 alc #endif /* ATHHAL_DEBUG */
84 1.1 alc
85 1.1 alc int ath_hal_dma_beacon_response_time = 2; /* in TU's */
86 1.1 alc int ath_hal_sw_beacon_response_time = 10; /* in TU's */
87 1.1 alc int ath_hal_additional_swba_backoff = 0; /* in TU's */
88 1.1 alc
89 1.1 alc SYSCTL_SETUP(sysctl_ath_hal, "sysctl ath.hal subtree setup")
90 1.1 alc {
91 1.1 alc int rc;
92 1.1 alc const struct sysctlnode *cnode, *rnode;
93 1.1 alc
94 1.1 alc if ((rc = sysctl_createv(clog, 0, NULL, &rnode, CTLFLAG_PERMANENT,
95 1.1 alc CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0)
96 1.1 alc goto err;
97 1.1 alc
98 1.1 alc if ((rc = sysctl_createv(clog, 0, &rnode, &rnode, CTLFLAG_PERMANENT,
99 1.1 alc CTLTYPE_NODE, "ath", SYSCTL_DESCR("Atheros driver parameters"),
100 1.1 alc NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0)
101 1.1 alc goto err;
102 1.1 alc
103 1.1 alc if ((rc = sysctl_createv(clog, 0, &rnode, &rnode, CTLFLAG_PERMANENT,
104 1.1 alc CTLTYPE_NODE, "hal", SYSCTL_DESCR("Atheros HAL parameters"),
105 1.1 alc NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0)
106 1.1 alc goto err;
107 1.1 alc
108 1.1 alc #if 0
109 1.1 alc if ((rc = sysctl_createv(clog, 0, &rnode, &cnode,
110 1.1 alc CTLFLAG_PERMANENT|CTLFLAG_READONLY, CTLTYPE_STRING, "version",
111 1.1 alc SYSCTL_DESCR("Atheros HAL version"), NULL, 0, &ath_hal_version, 0,
112 1.1 alc CTL_CREATE, CTL_EOL)) != 0)
113 1.1 alc goto err;
114 1.1 alc #endif
115 1.1 alc
116 1.1 alc if ((rc = sysctl_createv(clog, 0, &rnode, &cnode,
117 1.1 alc CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, "dma_brt",
118 1.1 alc SYSCTL_DESCR("Atheros HAL DMA beacon response time"), NULL, 0,
119 1.1 alc &ath_hal_dma_beacon_response_time, 0, CTL_CREATE, CTL_EOL)) != 0)
120 1.1 alc goto err;
121 1.1 alc
122 1.1 alc if ((rc = sysctl_createv(clog, 0, &rnode, &cnode,
123 1.1 alc CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, "sw_brt",
124 1.1 alc SYSCTL_DESCR("Atheros HAL software beacon response time"), NULL, 0,
125 1.1 alc &ath_hal_sw_beacon_response_time, 0, CTL_CREATE, CTL_EOL)) != 0)
126 1.1 alc goto err;
127 1.1 alc
128 1.1 alc if ((rc = sysctl_createv(clog, 0, &rnode, &cnode,
129 1.1 alc CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, "swba_backoff",
130 1.1 alc SYSCTL_DESCR("Atheros HAL additional SWBA backoff time"), NULL, 0,
131 1.1 alc &ath_hal_additional_swba_backoff, 0, CTL_CREATE, CTL_EOL)) != 0)
132 1.1 alc goto err;
133 1.1 alc
134 1.1 alc #ifdef ATHHAL_DEBUG
135 1.1 alc if ((rc = sysctl_createv(clog, 0, &rnode, &cnode,
136 1.1 alc CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, "debug",
137 1.1 alc SYSCTL_DESCR("Atheros HAL debugging printfs"), NULL, 0,
138 1.1 alc &ath_hal_debug, 0, CTL_CREATE, CTL_EOL)) != 0)
139 1.1 alc goto err;
140 1.1 alc #endif /* ATHHAL_DEBUG */
141 1.1 alc return;
142 1.1 alc err:
143 1.1 alc printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc);
144 1.1 alc }
145 1.1 alc
146 1.1 alc MALLOC_DEFINE(M_ATH_HAL, "ath_hal", "ath hal data");
147 1.1 alc
148 1.1 alc void*
149 1.1 alc ath_hal_malloc(size_t size)
150 1.1 alc {
151 1.1 alc void *ret;
152 1.1 alc ENTER
153 1.1 alc ret = malloc(size, M_ATH_HAL, M_NOWAIT | M_ZERO);
154 1.1 alc EXIT
155 1.1 alc return ret;
156 1.1 alc }
157 1.1 alc
158 1.1 alc void
159 1.1 alc ath_hal_free(void* p)
160 1.1 alc {
161 1.1 alc ENTER
162 1.1 alc free(p, M_ATH_HAL);
163 1.1 alc EXIT
164 1.1 alc }
165 1.1 alc
166 1.1 alc void
167 1.1 alc ath_hal_vprintf(struct ath_hal *ah, const char* fmt, va_list ap)
168 1.1 alc {
169 1.1 alc ENTER
170 1.1 alc vprintf(fmt, ap);
171 1.1 alc EXIT
172 1.1 alc }
173 1.1 alc
174 1.1 alc void
175 1.1 alc ath_hal_printf(struct ath_hal *ah, const char* fmt, ...)
176 1.1 alc {
177 1.1 alc va_list ap;
178 1.1 alc ENTER
179 1.1 alc va_start(ap, fmt);
180 1.1 alc ath_hal_vprintf(ah, fmt, ap);
181 1.1 alc va_end(ap);
182 1.1 alc EXIT
183 1.1 alc }
184 1.1 alc
185 1.1 alc const char*
186 1.1 alc ath_hal_ether_sprintf(const u_int8_t *mac)
187 1.1 alc {
188 1.1 alc const char *ret;
189 1.1 alc ENTER
190 1.1 alc ret = ether_sprintf(mac);
191 1.1 alc EXIT
192 1.1 alc return ret;
193 1.1 alc }
194 1.1 alc
195 1.1 alc #ifdef ATHHAL_DEBUG
196 1.1 alc void
197 1.1 alc HALDEBUG(struct ath_hal *ah, const char* fmt, ...)
198 1.1 alc {
199 1.1 alc if (ath_hal_debug) {
200 1.1 alc va_list ap;
201 1.1 alc ENTER
202 1.1 alc va_start(ap, fmt);
203 1.1 alc ath_hal_vprintf(ah, fmt, ap);
204 1.1 alc va_end(ap);
205 1.1 alc EXIT
206 1.1 alc }
207 1.1 alc }
208 1.1 alc
209 1.1 alc void
210 1.1 alc HALDEBUGn(struct ath_hal *ah, u_int level, const char* fmt, ...)
211 1.1 alc {
212 1.1 alc if (ath_hal_debug >= level) {
213 1.1 alc va_list ap;
214 1.1 alc ENTER
215 1.1 alc va_start(ap, fmt);
216 1.1 alc ath_hal_vprintf(ah, fmt, ap);
217 1.1 alc va_end(ap);
218 1.1 alc EXIT
219 1.1 alc }
220 1.1 alc }
221 1.1 alc #endif /* ATHHAL_DEBUG */
222 1.1 alc
223 1.1 alc #ifdef ATHHAL_DEBUG_ALQ
224 1.1 alc /*
225 1.1 alc * ALQ register tracing support.
226 1.1 alc *
227 1.1 alc * Setting hw.ath.hal.alq=1 enables tracing of all register reads and
228 1.1 alc * writes to the file /tmp/ath_hal.log. The file format is a simple
229 1.1 alc * fixed-size array of records. When done logging set hw.ath.hal.alq=0
230 1.1 alc * and then decode the file with the arcode program (that is part of the
231 1.1 alc * HAL). If you start+stop tracing the data will be appended to an
232 1.1 alc * existing file.
233 1.1 alc *
234 1.1 alc * NB: doesn't handle multiple devices properly; only one DEVICE record
235 1.1 alc * is emitted and the different devices are not identified.
236 1.1 alc */
237 1.1 alc #include <sys/alq.h>
238 1.1 alc #include <sys/pcpu.h>
239 1.1 alc #include <contrib/dev/ath/ah_decode.h>
240 1.1 alc
241 1.1 alc static struct alq *ath_hal_alq;
242 1.1 alc static int ath_hal_alq_emitdev; /* need to emit DEVICE record */
243 1.1 alc static u_int ath_hal_alq_lost; /* count of lost records */
244 1.1 alc static const char *ath_hal_logfile = "/tmp/ath_hal.log";
245 1.1 alc static u_int ath_hal_alq_qsize = 64*1024;
246 1.1 alc
247 1.1 alc static int
248 1.1 alc ath_hal_setlogging(int enable)
249 1.1 alc {
250 1.1 alc int error;
251 1.1 alc
252 1.1 alc if (enable) {
253 1.1 alc error = kauth_authorize_network(curlwp->l_cred,
254 1.1 alc KAUTH_NETWORK_INTERFACE,
255 1.1 alc KAUTH_REQ_NETWORK_INTERFACE_SETPRIV, NULL, NULL, NULL);
256 1.1 alc if (error == 0) {
257 1.1 alc error = alq_open(&ath_hal_alq, ath_hal_logfile,
258 1.1 alc curproc->p_ucred,
259 1.1 alc sizeof (struct athregrec), ath_hal_alq_qsize);
260 1.1 alc ath_hal_alq_lost = 0;
261 1.1 alc ath_hal_alq_emitdev = 1;
262 1.1 alc printf("ath_hal: logging to %s enabled\n",
263 1.1 alc ath_hal_logfile);
264 1.1 alc }
265 1.1 alc } else {
266 1.1 alc if (ath_hal_alq)
267 1.1 alc alq_close(ath_hal_alq);
268 1.1 alc ath_hal_alq = NULL;
269 1.1 alc printf("ath_hal: logging disabled\n");
270 1.1 alc error = 0;
271 1.1 alc }
272 1.1 alc return (error);
273 1.1 alc }
274 1.1 alc
275 1.1 alc static int
276 1.1 alc sysctl_hw_ath_hal_log(SYSCTL_HANDLER_ARGS)
277 1.1 alc {
278 1.1 alc int error, enable;
279 1.1 alc
280 1.1 alc enable = (ath_hal_alq != NULL);
281 1.1 alc error = sysctl_handle_int(oidp, &enable, 0, req);
282 1.1 alc if (error || !req->newptr)
283 1.1 alc return (error);
284 1.1 alc else
285 1.1 alc return (ath_hal_setlogging(enable));
286 1.1 alc }
287 1.1 alc SYSCTL_PROC(_hw_ath_hal, OID_AUTO, alq, CTLTYPE_INT|CTLFLAG_RW,
288 1.1 alc 0, 0, sysctl_hw_ath_hal_log, "I", "Enable HAL register logging");
289 1.1 alc SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_size, CTLFLAG_RW,
290 1.1 alc &ath_hal_alq_qsize, 0, "In-memory log size (#records)");
291 1.1 alc SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_lost, CTLFLAG_RW,
292 1.1 alc &ath_hal_alq_lost, 0, "Register operations not logged");
293 1.1 alc
294 1.1 alc static struct ale *
295 1.1 alc ath_hal_alq_get(struct ath_hal *ah)
296 1.1 alc {
297 1.1 alc struct ale *ale;
298 1.1 alc
299 1.1 alc if (ath_hal_alq_emitdev) {
300 1.1 alc ale = alq_get(ath_hal_alq, ALQ_NOWAIT);
301 1.1 alc if (ale) {
302 1.1 alc struct athregrec *r =
303 1.1 alc (struct athregrec *) ale->ae_data;
304 1.1 alc r->op = OP_DEVICE;
305 1.1 alc r->reg = 0;
306 1.1 alc r->val = ah->ah_devid;
307 1.1 alc alq_post(ath_hal_alq, ale);
308 1.1 alc ath_hal_alq_emitdev = 0;
309 1.1 alc } else
310 1.1 alc ath_hal_alq_lost++;
311 1.1 alc }
312 1.1 alc ale = alq_get(ath_hal_alq, ALQ_NOWAIT);
313 1.1 alc if (!ale)
314 1.1 alc ath_hal_alq_lost++;
315 1.1 alc return ale;
316 1.1 alc }
317 1.1 alc
318 1.1 alc void
319 1.1 alc ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
320 1.1 alc {
321 1.1 alc bus_space_tag_t t = BUSTAG(ah);
322 1.1 alc ENTER
323 1.1 alc
324 1.1 alc if (ath_hal_alq) {
325 1.1 alc struct ale *ale = ath_hal_alq_get(ah);
326 1.1 alc if (ale) {
327 1.1 alc struct athregrec *r = (struct athregrec *) ale->ae_data;
328 1.1 alc r->op = OP_WRITE;
329 1.1 alc r->reg = reg;
330 1.1 alc r->val = val;
331 1.1 alc alq_post(ath_hal_alq, ale);
332 1.1 alc }
333 1.1 alc }
334 1.1 alc #if _BYTE_ORDER == _BIG_ENDIAN
335 1.1 alc if (reg >= 0x4000 && reg < 0x5000)
336 1.1 alc bus_space_write_4(t, h, reg, val);
337 1.1 alc else
338 1.1 alc #endif
339 1.1 alc bus_space_write_stream_4(t, h, reg, val);
340 1.1 alc
341 1.1 alc EXIT
342 1.1 alc }
343 1.1 alc
344 1.1 alc u_int32_t
345 1.1 alc ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
346 1.1 alc {
347 1.1 alc u_int32_t val;
348 1.1 alc bus_space_handle_t h = BUSHANDLE(ah);
349 1.1 alc bus_space_tag_t t = BUSTAG(ah);
350 1.1 alc ENTER
351 1.1 alc
352 1.1 alc #if _BYTE_ORDER == _BIG_ENDIAN
353 1.1 alc if (reg >= 0x4000 && reg < 0x5000)
354 1.1 alc val = bus_space_read_4(t, h, reg);
355 1.1 alc else
356 1.1 alc #endif
357 1.1 alc val = bus_space_read_stream_4(t, h, reg);
358 1.1 alc
359 1.1 alc if (ath_hal_alq) {
360 1.1 alc struct ale *ale = ath_hal_alq_get(ah);
361 1.1 alc if (ale) {
362 1.1 alc struct athregrec *r = (struct athregrec *) ale->ae_data;
363 1.1 alc r->op = OP_READ;
364 1.1 alc r->reg = reg;
365 1.1 alc r->val = val;
366 1.1 alc alq_post(ath_hal_alq, ale);
367 1.1 alc }
368 1.1 alc }
369 1.1 alc
370 1.1 alc EXIT
371 1.1 alc return val;
372 1.1 alc }
373 1.1 alc
374 1.1 alc void
375 1.1 alc OS_MARK(struct ath_hal *ah, u_int id, u_int32_t v)
376 1.1 alc {
377 1.1 alc if (ath_hal_alq) {
378 1.1 alc struct ale *ale = ath_hal_alq_get(ah);
379 1.1 alc ENTER
380 1.1 alc if (ale) {
381 1.1 alc struct athregrec *r = (struct athregrec *) ale->ae_data;
382 1.1 alc r->op = OP_MARK;
383 1.1 alc r->reg = id;
384 1.1 alc r->val = v;
385 1.1 alc alq_post(ath_hal_alq, ale);
386 1.1 alc }
387 1.1 alc EXIT
388 1.1 alc }
389 1.1 alc }
390 1.1 alc #elif defined(ATHHAL_DEBUG) || defined(AH_REGOPS_FUNC)
391 1.1 alc /*
392 1.1 alc * Memory-mapped device register read/write. These are here
393 1.1 alc * as routines when debugging support is enabled and/or when
394 1.1 alc * explicitly configured to use function calls. The latter is
395 1.1 alc * for architectures that might need to do something before
396 1.1 alc * referencing memory (e.g. remap an i/o window).
397 1.1 alc *
398 1.1 alc * NB: see the comments in ah_osdep.h about byte-swapping register
399 1.1 alc * reads and writes to understand what's going on below.
400 1.1 alc */
401 1.1 alc
402 1.1 alc void
403 1.1 alc ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
404 1.1 alc {
405 1.1 alc bus_space_handle_t h = BUSHANDLE(ah);
406 1.1 alc bus_space_tag_t t = BUSTAG(ah);
407 1.1 alc ENTER
408 1.1 alc
409 1.1 alc #if _BYTE_ORDER == _BIG_ENDIAN
410 1.1 alc if (reg >= 0x4000 && reg < 0x5000)
411 1.1 alc bus_space_write_4(t, h, reg, val);
412 1.1 alc else
413 1.1 alc #endif
414 1.1 alc bus_space_write_stream_4(t, h, reg, val);
415 1.1 alc EXIT
416 1.1 alc }
417 1.1 alc
418 1.1 alc u_int32_t
419 1.1 alc ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
420 1.1 alc {
421 1.1 alc bus_space_handle_t h = BUSHANDLE(ah);
422 1.1 alc bus_space_tag_t t = BUSTAG(ah);
423 1.1 alc uint32_t ret;
424 1.1 alc ENTER
425 1.1 alc
426 1.1 alc #if _BYTE_ORDER == _BIG_ENDIAN
427 1.1 alc if (reg >= 0x4000 && reg < 0x5000)
428 1.1 alc ret = bus_space_read_4(t, h, reg);
429 1.1 alc else
430 1.1 alc #endif
431 1.1 alc ret = bus_space_read_stream_4(t, h, reg);
432 1.1 alc EXIT
433 1.1 alc
434 1.1 alc return ret;
435 1.1 alc }
436 1.1 alc #endif /* ATHHAL_DEBUG || AH_REGOPS_FUNC */
437 1.1 alc
438 1.1 alc #ifdef ATHHAL_ASSERT
439 1.1 alc void
440 1.1 alc ath_hal_assert_failed(const char* filename, int lineno, const char *msg)
441 1.1 alc {
442 1.1 alc ENTER
443 1.1 alc printf("Atheros HAL assertion failure: %s: line %u: %s\n",
444 1.1 alc filename, lineno, msg);
445 1.1 alc panic("ath_hal_assert");
446 1.1 alc }
447 1.1 alc #endif /* ATHHAL_ASSERT */
448 1.1 alc
449 1.1 alc /*
450 1.1 alc * Delay n microseconds.
451 1.1 alc */
452 1.1 alc void
453 1.1 alc ath_hal_delay(int n)
454 1.1 alc {
455 1.1 alc ENTER
456 1.1 alc DELAY(n);
457 1.1 alc EXIT
458 1.1 alc }
459 1.1 alc
460 1.1 alc u_int32_t
461 1.1 alc ath_hal_getuptime(struct ath_hal *ah)
462 1.1 alc {
463 1.1 alc struct bintime bt;
464 1.1 alc uint32_t ret;
465 1.1 alc ENTER
466 1.1 alc getbinuptime(&bt);
467 1.1 alc ret = (bt.sec * 1000) +
468 1.1 alc (((uint64_t)1000 * (uint32_t)(bt.frac >> 32)) >> 32);
469 1.1 alc EXIT
470 1.1 alc return ret;
471 1.1 alc }
472 1.1 alc
473 1.1 alc void
474 1.1 alc ath_hal_memzero(void *dst, size_t n)
475 1.1 alc {
476 1.1 alc ENTER
477 1.1 alc (void)memset(dst, 0, n);
478 1.1 alc EXIT
479 1.1 alc }
480 1.1 alc
481 1.1 alc void *
482 1.1 alc ath_hal_memcpy(void *dst, const void *src, size_t n)
483 1.1 alc {
484 1.1 alc void *ret;
485 1.1 alc ENTER
486 1.1 alc ret = memcpy(dst, src, n);
487 1.1 alc EXIT
488 1.1 alc return ret;
489 1.1 alc }
490