ah_osdep.c revision 1.2.4.2
1 /*- 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $Id: ah_osdep.c,v 1.2.4.2 2009/08/07 06:43:50 snj Exp $ 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: ah_osdep.c,v 1.2.4.2 2009/08/07 06:43:50 snj Exp $"); 34 35 #include "opt_athhal.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/sysctl.h> 41 #include <sys/malloc.h> 42 #include <sys/proc.h> 43 #include <sys/kauth.h> 44 45 #include <machine/stdarg.h> 46 47 #include <net/if.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 #include <net/if_arp.h> 51 #include <net/if_ether.h> 52 53 #include <external/isc/atheros_hal/dist/ah.h> 54 55 #ifdef __mips__ 56 #include <sys/cpu.h> 57 58 #define ENTER lwp_t *savlwp = curlwp; curlwp = cpu_info_store.ci_curlwp; 59 #define EXIT curlwp = savlwp; 60 #else 61 #define ENTER /* nothing */ 62 #define EXIT /* nothing */ 63 #endif 64 65 extern void ath_hal_printf(struct ath_hal *, const char*, ...); 66 extern void ath_hal_vprintf(struct ath_hal *, const char*, va_list); 67 extern const char* ath_hal_ether_sprintf(const u_int8_t *mac); 68 extern void *ath_hal_malloc(size_t); 69 extern void ath_hal_free(void *); 70 #ifdef ATHHAL_ASSERT 71 extern void ath_hal_assert_failed(const char* filename, 72 int lineno, const char* msg); 73 #endif 74 #ifdef ATHHAL_DEBUG 75 extern void HALDEBUG(struct ath_hal *ah, const char* fmt, ...); 76 extern void HALDEBUGn(struct ath_hal *ah, u_int level, const char* fmt, ...); 77 #endif /* ATHHAL_DEBUG */ 78 79 #ifdef ATHHAL_DEBUG 80 static int ath_hal_debug = 0; 81 #endif /* ATHHAL_DEBUG */ 82 83 int ath_hal_dma_beacon_response_time = 2; /* in TU's */ 84 int ath_hal_sw_beacon_response_time = 10; /* in TU's */ 85 int ath_hal_additional_swba_backoff = 0; /* in TU's */ 86 87 SYSCTL_SETUP(sysctl_ath_hal, "sysctl ath.hal subtree setup") 88 { 89 int rc; 90 const struct sysctlnode *cnode, *rnode; 91 92 if ((rc = sysctl_createv(clog, 0, NULL, &rnode, CTLFLAG_PERMANENT, 93 CTLTYPE_NODE, "hw", NULL, NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) 94 goto err; 95 96 if ((rc = sysctl_createv(clog, 0, &rnode, &rnode, CTLFLAG_PERMANENT, 97 CTLTYPE_NODE, "ath", SYSCTL_DESCR("Atheros driver parameters"), 98 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0) 99 goto err; 100 101 if ((rc = sysctl_createv(clog, 0, &rnode, &rnode, CTLFLAG_PERMANENT, 102 CTLTYPE_NODE, "hal", SYSCTL_DESCR("Atheros HAL parameters"), 103 NULL, 0, NULL, 0, CTL_CREATE, CTL_EOL)) != 0) 104 goto err; 105 106 #if 0 107 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 108 CTLFLAG_PERMANENT|CTLFLAG_READONLY, CTLTYPE_STRING, "version", 109 SYSCTL_DESCR("Atheros HAL version"), NULL, 0, &ath_hal_version, 0, 110 CTL_CREATE, CTL_EOL)) != 0) 111 goto err; 112 #endif 113 114 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, "dma_brt", 116 SYSCTL_DESCR("Atheros HAL DMA beacon response time"), NULL, 0, 117 &ath_hal_dma_beacon_response_time, 0, CTL_CREATE, CTL_EOL)) != 0) 118 goto err; 119 120 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 121 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, "sw_brt", 122 SYSCTL_DESCR("Atheros HAL software beacon response time"), NULL, 0, 123 &ath_hal_sw_beacon_response_time, 0, CTL_CREATE, CTL_EOL)) != 0) 124 goto err; 125 126 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 127 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, "swba_backoff", 128 SYSCTL_DESCR("Atheros HAL additional SWBA backoff time"), NULL, 0, 129 &ath_hal_additional_swba_backoff, 0, CTL_CREATE, CTL_EOL)) != 0) 130 goto err; 131 132 #ifdef ATHHAL_DEBUG 133 if ((rc = sysctl_createv(clog, 0, &rnode, &cnode, 134 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, "debug", 135 SYSCTL_DESCR("Atheros HAL debugging printfs"), NULL, 0, 136 &ath_hal_debug, 0, CTL_CREATE, CTL_EOL)) != 0) 137 goto err; 138 #endif /* ATHHAL_DEBUG */ 139 return; 140 err: 141 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc); 142 } 143 144 MALLOC_DEFINE(M_ATH_HAL, "ath_hal", "ath hal data"); 145 146 void* 147 ath_hal_malloc(size_t size) 148 { 149 void *ret; 150 ENTER 151 ret = malloc(size, M_ATH_HAL, M_NOWAIT | M_ZERO); 152 EXIT 153 return ret; 154 } 155 156 void 157 ath_hal_free(void* p) 158 { 159 ENTER 160 free(p, M_ATH_HAL); 161 EXIT 162 } 163 164 void 165 ath_hal_vprintf(struct ath_hal *ah, const char* fmt, va_list ap) 166 { 167 ENTER 168 vprintf(fmt, ap); 169 EXIT 170 } 171 172 void 173 ath_hal_printf(struct ath_hal *ah, const char* fmt, ...) 174 { 175 va_list ap; 176 ENTER 177 va_start(ap, fmt); 178 ath_hal_vprintf(ah, fmt, ap); 179 va_end(ap); 180 EXIT 181 } 182 183 const char* 184 ath_hal_ether_sprintf(const u_int8_t *mac) 185 { 186 const char *ret; 187 ENTER 188 ret = ether_sprintf(mac); 189 EXIT 190 return ret; 191 } 192 193 #ifdef ATHHAL_DEBUG 194 void 195 HALDEBUG(struct ath_hal *ah, const char* fmt, ...) 196 { 197 if (ath_hal_debug) { 198 va_list ap; 199 ENTER 200 va_start(ap, fmt); 201 ath_hal_vprintf(ah, fmt, ap); 202 va_end(ap); 203 EXIT 204 } 205 } 206 207 void 208 HALDEBUGn(struct ath_hal *ah, u_int level, const char* fmt, ...) 209 { 210 if (ath_hal_debug >= level) { 211 va_list ap; 212 ENTER 213 va_start(ap, fmt); 214 ath_hal_vprintf(ah, fmt, ap); 215 va_end(ap); 216 EXIT 217 } 218 } 219 #endif /* ATHHAL_DEBUG */ 220 221 #ifdef ATHHAL_DEBUG_ALQ 222 /* 223 * ALQ register tracing support. 224 * 225 * Setting hw.ath.hal.alq=1 enables tracing of all register reads and 226 * writes to the file /tmp/ath_hal.log. The file format is a simple 227 * fixed-size array of records. When done logging set hw.ath.hal.alq=0 228 * and then decode the file with the arcode program (that is part of the 229 * HAL). If you start+stop tracing the data will be appended to an 230 * existing file. 231 * 232 * NB: doesn't handle multiple devices properly; only one DEVICE record 233 * is emitted and the different devices are not identified. 234 */ 235 #include <sys/alq.h> 236 #include <sys/pcpu.h> 237 #include <contrib/dev/ath/ah_decode.h> 238 239 static struct alq *ath_hal_alq; 240 static int ath_hal_alq_emitdev; /* need to emit DEVICE record */ 241 static u_int ath_hal_alq_lost; /* count of lost records */ 242 static const char *ath_hal_logfile = "/tmp/ath_hal.log"; 243 static u_int ath_hal_alq_qsize = 64*1024; 244 245 static int 246 ath_hal_setlogging(int enable) 247 { 248 int error; 249 250 if (enable) { 251 error = kauth_authorize_network(curlwp->l_cred, 252 KAUTH_NETWORK_INTERFACE, 253 KAUTH_REQ_NETWORK_INTERFACE_SETPRIV, NULL, NULL, NULL); 254 if (error == 0) { 255 error = alq_open(&ath_hal_alq, ath_hal_logfile, 256 curproc->p_ucred, 257 sizeof (struct athregrec), ath_hal_alq_qsize); 258 ath_hal_alq_lost = 0; 259 ath_hal_alq_emitdev = 1; 260 printf("ath_hal: logging to %s enabled\n", 261 ath_hal_logfile); 262 } 263 } else { 264 if (ath_hal_alq) 265 alq_close(ath_hal_alq); 266 ath_hal_alq = NULL; 267 printf("ath_hal: logging disabled\n"); 268 error = 0; 269 } 270 return (error); 271 } 272 273 static int 274 sysctl_hw_ath_hal_log(SYSCTL_HANDLER_ARGS) 275 { 276 int error, enable; 277 278 enable = (ath_hal_alq != NULL); 279 error = sysctl_handle_int(oidp, &enable, 0, req); 280 if (error || !req->newptr) 281 return (error); 282 else 283 return (ath_hal_setlogging(enable)); 284 } 285 SYSCTL_PROC(_hw_ath_hal, OID_AUTO, alq, CTLTYPE_INT|CTLFLAG_RW, 286 0, 0, sysctl_hw_ath_hal_log, "I", "Enable HAL register logging"); 287 SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_size, CTLFLAG_RW, 288 &ath_hal_alq_qsize, 0, "In-memory log size (#records)"); 289 SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_lost, CTLFLAG_RW, 290 &ath_hal_alq_lost, 0, "Register operations not logged"); 291 292 static struct ale * 293 ath_hal_alq_get(struct ath_hal *ah) 294 { 295 struct ale *ale; 296 297 if (ath_hal_alq_emitdev) { 298 ale = alq_get(ath_hal_alq, ALQ_NOWAIT); 299 if (ale) { 300 struct athregrec *r = 301 (struct athregrec *) ale->ae_data; 302 r->op = OP_DEVICE; 303 r->reg = 0; 304 r->val = ah->ah_devid; 305 alq_post(ath_hal_alq, ale); 306 ath_hal_alq_emitdev = 0; 307 } else 308 ath_hal_alq_lost++; 309 } 310 ale = alq_get(ath_hal_alq, ALQ_NOWAIT); 311 if (!ale) 312 ath_hal_alq_lost++; 313 return ale; 314 } 315 316 void 317 ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val) 318 { 319 bus_space_tag_t t = BUSTAG(ah); 320 ENTER 321 322 if (ath_hal_alq) { 323 struct ale *ale = ath_hal_alq_get(ah); 324 if (ale) { 325 struct athregrec *r = (struct athregrec *) ale->ae_data; 326 r->op = OP_WRITE; 327 r->reg = reg; 328 r->val = val; 329 alq_post(ath_hal_alq, ale); 330 } 331 } 332 #if _BYTE_ORDER == _BIG_ENDIAN 333 if (reg >= 0x4000 && reg < 0x5000) 334 bus_space_write_4(t, h, reg, val); 335 else 336 #endif 337 bus_space_write_stream_4(t, h, reg, val); 338 339 EXIT 340 } 341 342 u_int32_t 343 ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg) 344 { 345 u_int32_t val; 346 bus_space_handle_t h = BUSHANDLE(ah); 347 bus_space_tag_t t = BUSTAG(ah); 348 ENTER 349 350 #if _BYTE_ORDER == _BIG_ENDIAN 351 if (reg >= 0x4000 && reg < 0x5000) 352 val = bus_space_read_4(t, h, reg); 353 else 354 #endif 355 val = bus_space_read_stream_4(t, h, reg); 356 357 if (ath_hal_alq) { 358 struct ale *ale = ath_hal_alq_get(ah); 359 if (ale) { 360 struct athregrec *r = (struct athregrec *) ale->ae_data; 361 r->op = OP_READ; 362 r->reg = reg; 363 r->val = val; 364 alq_post(ath_hal_alq, ale); 365 } 366 } 367 368 EXIT 369 return val; 370 } 371 372 void 373 OS_MARK(struct ath_hal *ah, u_int id, u_int32_t v) 374 { 375 if (ath_hal_alq) { 376 struct ale *ale = ath_hal_alq_get(ah); 377 ENTER 378 if (ale) { 379 struct athregrec *r = (struct athregrec *) ale->ae_data; 380 r->op = OP_MARK; 381 r->reg = id; 382 r->val = v; 383 alq_post(ath_hal_alq, ale); 384 } 385 EXIT 386 } 387 } 388 #elif defined(ATHHAL_DEBUG) || defined(AH_REGOPS_FUNC) 389 /* 390 * Memory-mapped device register read/write. These are here 391 * as routines when debugging support is enabled and/or when 392 * explicitly configured to use function calls. The latter is 393 * for architectures that might need to do something before 394 * referencing memory (e.g. remap an i/o window). 395 * 396 * NB: see the comments in ah_osdep.h about byte-swapping register 397 * reads and writes to understand what's going on below. 398 */ 399 400 void 401 ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val) 402 { 403 bus_space_handle_t h = BUSHANDLE(ah); 404 bus_space_tag_t t = BUSTAG(ah); 405 ENTER 406 407 #if _BYTE_ORDER == _BIG_ENDIAN 408 if (reg >= 0x4000 && reg < 0x5000) 409 bus_space_write_4(t, h, reg, val); 410 else 411 #endif 412 bus_space_write_stream_4(t, h, reg, val); 413 EXIT 414 } 415 416 u_int32_t 417 ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg) 418 { 419 bus_space_handle_t h = BUSHANDLE(ah); 420 bus_space_tag_t t = BUSTAG(ah); 421 uint32_t ret; 422 ENTER 423 424 #if _BYTE_ORDER == _BIG_ENDIAN 425 if (reg >= 0x4000 && reg < 0x5000) 426 ret = bus_space_read_4(t, h, reg); 427 else 428 #endif 429 ret = bus_space_read_stream_4(t, h, reg); 430 EXIT 431 432 return ret; 433 } 434 #endif /* ATHHAL_DEBUG || AH_REGOPS_FUNC */ 435 436 #ifdef ATHHAL_ASSERT 437 void 438 ath_hal_assert_failed(const char* filename, int lineno, const char *msg) 439 { 440 ENTER 441 printf("Atheros HAL assertion failure: %s: line %u: %s\n", 442 filename, lineno, msg); 443 panic("ath_hal_assert"); 444 } 445 #endif /* ATHHAL_ASSERT */ 446 447 /* 448 * Delay n microseconds. 449 */ 450 void 451 ath_hal_delay(int n) 452 { 453 ENTER 454 DELAY(n); 455 EXIT 456 } 457 458 u_int32_t 459 ath_hal_getuptime(struct ath_hal *ah) 460 { 461 struct bintime bt; 462 uint32_t ret; 463 ENTER 464 getbinuptime(&bt); 465 ret = (bt.sec * 1000) + 466 (((uint64_t)1000 * (uint32_t)(bt.frac >> 32)) >> 32); 467 EXIT 468 return ret; 469 } 470 471 void 472 ath_hal_memzero(void *dst, size_t n) 473 { 474 ENTER 475 (void)memset(dst, 0, n); 476 EXIT 477 } 478 479 void * 480 ath_hal_memcpy(void *dst, const void *src, size_t n) 481 { 482 void *ret; 483 ENTER 484 ret = memcpy(dst, src, n); 485 EXIT 486 return ret; 487 } 488
Indexes created Thu Oct 23 18:09:57 GMT 2025