kern_softint.c revision 1.1.2.16 1 1.1.2.16 ad /* $NetBSD: kern_softint.c,v 1.1.2.16 2007/10/09 13:44:28 ad Exp $ */
2 1.1.2.16 ad
3 1.1.2.16 ad /*-
4 1.1.2.16 ad * Copyright (c) 2007 The NetBSD Foundation, Inc.
5 1.1.2.16 ad * All rights reserved.
6 1.1.2.16 ad *
7 1.1.2.16 ad * This code is derived from software contributed to The NetBSD Foundation
8 1.1.2.16 ad * by Andrew Doran.
9 1.1.2.16 ad *
10 1.1.2.16 ad * Redistribution and use in source and binary forms, with or without
11 1.1.2.16 ad * modification, are permitted provided that the following conditions
12 1.1.2.16 ad * are met:
13 1.1.2.16 ad * 1. Redistributions of source code must retain the above copyright
14 1.1.2.16 ad * notice, this list of conditions and the following disclaimer.
15 1.1.2.16 ad * 2. Redistributions in binary form must reproduce the above copyright
16 1.1.2.16 ad * notice, this list of conditions and the following disclaimer in the
17 1.1.2.16 ad * documentation and/or other materials provided with the distribution.
18 1.1.2.16 ad * 3. All advertising materials mentioning features or use of this software
19 1.1.2.16 ad * must display the following acknowledgement:
20 1.1.2.16 ad * This product includes software developed by the NetBSD
21 1.1.2.16 ad * Foundation, Inc. and its contributors.
22 1.1.2.16 ad * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.1.2.16 ad * contributors may be used to endorse or promote products derived
24 1.1.2.16 ad * from this software without specific prior written permission.
25 1.1.2.16 ad *
26 1.1.2.16 ad * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.1.2.16 ad * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.1.2.16 ad * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.1.2.16 ad * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.1.2.16 ad * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.1.2.16 ad * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.1.2.16 ad * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.1.2.16 ad * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.1.2.16 ad * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.1.2.16 ad * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.1.2.16 ad * POSSIBILITY OF SUCH DAMAGE.
37 1.1.2.16 ad */
38 1.1.2.16 ad
39 1.1.2.16 ad /*
40 1.1.2.16 ad * Stub for code to be merged from the vmlocking CVS branch.
41 1.1.2.16 ad */
42 1.1.2.16 ad
43 1.1.2.16 ad #include <sys/cdefs.h>
44 1.1.2.16 ad __KERNEL_RCSID(0, "$NetBSD: kern_softint.c,v 1.1.2.16 2007/10/09 13:44:28 ad Exp $");
45 1.1.2.16 ad
46 1.1.2.16 ad #include <sys/param.h>
47 1.1.2.16 ad #include <sys/intr.h>
48 1.1.2.16 ad
49 1.1.2.16 ad u_int softint_timing;
50 1.1.2.16 ad
51 1.1.2.16 ad /*
52 1.1.2.16 ad * softint_init:
53 1.1.2.16 ad *
54 1.1.2.16 ad * Initialize per-CPU data structures. Called from mi_cpu_attach().
55 1.1.2.16 ad */
56 1.1.2.16 ad void
57 1.1.2.16 ad softint_init(struct cpu_info *ci)
58 1.1.2.16 ad {
59 1.1.2.16 ad
60 1.1.2.16 ad /* nothing yet */
61 1.1.2.16 ad }
62 1.1.2.16 ad
63 1.1.2.16 ad /*
64 1.1.2.16 ad * softint_establish:
65 1.1.2.16 ad *
66 1.1.2.16 ad * Register a software interrupt handler.
67 1.1.2.16 ad */
68 1.1.2.16 ad void *
69 1.1.2.16 ad softint_establish(u_int flags, void (*func)(void *), void *arg)
70 1.1.2.16 ad {
71 1.1.2.16 ad u_int level;
72 1.1.2.16 ad
73 1.1.2.16 ad level = (flags & SOFTINT_LVLMASK);
74 1.1.2.16 ad KASSERT(level < SOFTINT_COUNT);
75 1.1.2.16 ad
76 1.1.2.16 ad switch (level) {
77 1.1.2.16 ad case SOFTINT_CLOCK:
78 1.1.2.16 ad level = IPL_SOFTCLOCK;
79 1.1.2.16 ad break;
80 1.1.2.16 ad case SOFTINT_NET:
81 1.1.2.16 ad case SOFTINT_BIO:
82 1.1.2.16 ad level = IPL_SOFTNET;
83 1.1.2.16 ad break;
84 1.1.2.16 ad case SOFTINT_SERIAL:
85 1.1.2.16 ad #ifdef IPL_SOFTSERIAL
86 1.1.2.16 ad level = IPL_SOFTSERIAL;
87 1.1.2.16 ad #else
88 1.1.2.16 ad level = IPL_SOFTNET;
89 1.1.2.16 ad #endif
90 1.1.2.16 ad break;
91 1.1.2.16 ad default:
92 1.1.2.16 ad panic("softint_establish");
93 1.1.2.16 ad }
94 1.1.2.16 ad
95 1.1.2.16 ad return softintr_establish(level, func, arg);
96 1.1.2.16 ad }
97 1.1.2.16 ad
98 1.1.2.16 ad /*
99 1.1.2.16 ad * softint_disestablish:
100 1.1.2.16 ad *
101 1.1.2.16 ad * Unregister a software interrupt handler.
102 1.1.2.16 ad */
103 1.1.2.16 ad void
104 1.1.2.16 ad softint_disestablish(void *arg)
105 1.1.2.16 ad {
106 1.1.2.16 ad
107 1.1.2.16 ad softintr_disestablish(arg);
108 1.1.2.16 ad }
109 1.1.2.16 ad
110 1.1.2.16 ad /*
111 1.1.2.16 ad * softint_schedule:
112 1.1.2.16 ad *
113 1.1.2.16 ad * Trigger a software interrupt. Must be called from a hardware
114 1.1.2.16 ad * interrupt handler, or with preemption disabled (since we are
115 1.1.2.16 ad * using the value of curcpu()).
116 1.1.2.16 ad */
117 1.1.2.16 ad void
118 1.1.2.16 ad softint_schedule(void *arg)
119 1.1.2.16 ad {
120 1.1.2.16 ad
121 1.1.2.16 ad softintr_schedule(arg);
122 1.1.2.16 ad }
123 1.1.2.16 ad
124 1.1.2.16 ad /*
125 1.1.2.16 ad * softint_block:
126 1.1.2.16 ad *
127 1.1.2.16 ad * Update statistics when the soft interrupt blocks.
128 1.1.2.16 ad */
129 1.1.2.16 ad void
130 1.1.2.16 ad softint_block(lwp_t *l)
131 1.1.2.16 ad {
132 1.1.2.16 ad
133 1.1.2.16 ad /* nothing yet */
134 1.1.2.16 ad }
135 1.1.2.16 ad /* $NetBSD: kern_softint.c,v 1.1.2.16 2007/10/09 13:44:28 ad Exp $ */
136 1.1.2.1 ad
137 1.1.2.1 ad /*-
138 1.1.2.1 ad * Copyright (c) 2007 The NetBSD Foundation, Inc.
139 1.1.2.1 ad * All rights reserved.
140 1.1.2.1 ad *
141 1.1.2.1 ad * This code is derived from software contributed to The NetBSD Foundation
142 1.1.2.1 ad * by Andrew Doran.
143 1.1.2.1 ad *
144 1.1.2.1 ad * Redistribution and use in source and binary forms, with or without
145 1.1.2.1 ad * modification, are permitted provided that the following conditions
146 1.1.2.1 ad * are met:
147 1.1.2.1 ad * 1. Redistributions of source code must retain the above copyright
148 1.1.2.1 ad * notice, this list of conditions and the following disclaimer.
149 1.1.2.1 ad * 2. Redistributions in binary form must reproduce the above copyright
150 1.1.2.1 ad * notice, this list of conditions and the following disclaimer in the
151 1.1.2.1 ad * documentation and/or other materials provided with the distribution.
152 1.1.2.1 ad * 3. All advertising materials mentioning features or use of this software
153 1.1.2.1 ad * must display the following acknowledgement:
154 1.1.2.1 ad * This product includes software developed by the NetBSD
155 1.1.2.1 ad * Foundation, Inc. and its contributors.
156 1.1.2.1 ad * 4. Neither the name of The NetBSD Foundation nor the names of its
157 1.1.2.1 ad * contributors may be used to endorse or promote products derived
158 1.1.2.1 ad * from this software without specific prior written permission.
159 1.1.2.1 ad *
160 1.1.2.1 ad * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
161 1.1.2.1 ad * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
162 1.1.2.1 ad * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
163 1.1.2.1 ad * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
164 1.1.2.1 ad * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
165 1.1.2.1 ad * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
166 1.1.2.1 ad * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
167 1.1.2.1 ad * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
168 1.1.2.1 ad * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
169 1.1.2.1 ad * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
170 1.1.2.1 ad * POSSIBILITY OF SUCH DAMAGE.
171 1.1.2.1 ad */
172 1.1.2.1 ad
173 1.1.2.1 ad /*
174 1.1.2.2 ad * Generic software interrupt framework.
175 1.1.2.2 ad *
176 1.1.2.2 ad * Overview
177 1.1.2.2 ad *
178 1.1.2.2 ad * The soft interrupt framework provides a mechanism to schedule a
179 1.1.2.2 ad * low priority callback that runs with thread context. It allows
180 1.1.2.2 ad * for dynamic registration of software interrupts, and for fair
181 1.1.2.2 ad * queueing and prioritization of those interrupts. The callbacks
182 1.1.2.2 ad * can be scheduled to run from nearly any point in the kernel: by
183 1.1.2.2 ad * code running with thread context, by code running from a
184 1.1.2.2 ad * hardware interrupt handler, and at any interrupt priority
185 1.1.2.2 ad * level.
186 1.1.2.2 ad *
187 1.1.2.2 ad * Priority levels
188 1.1.2.2 ad *
189 1.1.2.2 ad * Since soft interrupt dispatch can be tied to the underlying
190 1.1.2.8 ad * architecture's interrupt dispatch code, it can be limited
191 1.1.2.2 ad * both by the capabilities of the hardware and the capabilities
192 1.1.2.8 ad * of the interrupt dispatch code itself. The number of priority
193 1.1.2.2 ad * levels is restricted to four. In order of priority (lowest to
194 1.1.2.2 ad * highest) the levels are: clock, bio, net, serial.
195 1.1.2.2 ad *
196 1.1.2.8 ad * The names are symbolic and in isolation do not have any direct
197 1.1.2.8 ad * connection with a particular kind of device activity: they are
198 1.1.2.8 ad * only meant as a guide.
199 1.1.2.2 ad *
200 1.1.2.2 ad * The four priority levels map directly to scheduler priority
201 1.1.2.2 ad * levels, and where the architecture implements 'fast' software
202 1.1.2.2 ad * interrupts, they also map onto interrupt priorities. The
203 1.1.2.2 ad * interrupt priorities are intended to be hidden from machine
204 1.1.2.8 ad * independent code, which should use thread-safe mechanisms to
205 1.1.2.8 ad * synchronize with software interrupts (for example: mutexes).
206 1.1.2.2 ad *
207 1.1.2.2 ad * Capabilities
208 1.1.2.2 ad *
209 1.1.2.8 ad * Software interrupts run with limited machine context. In
210 1.1.2.8 ad * particular, they do not posess any address space context. They
211 1.1.2.8 ad * should not try to operate on user space addresses, or to use
212 1.1.2.8 ad * virtual memory facilities other than those noted as interrupt
213 1.1.2.8 ad * safe.
214 1.1.2.2 ad *
215 1.1.2.2 ad * Unlike hardware interrupts, software interrupts do have thread
216 1.1.2.2 ad * context. They may block on synchronization objects, sleep, and
217 1.1.2.8 ad * resume execution at a later time.
218 1.1.2.2 ad *
219 1.1.2.8 ad * Since software interrupts are a limited resource and run with
220 1.1.2.8 ad * higher priority than most other LWPs in the system, all
221 1.1.2.8 ad * block-and-resume activity by a software interrupt must be kept
222 1.1.2.8 ad * short to allow futher processing at that level to continue. By
223 1.1.2.15 ad * extension, code running with process context must take care to
224 1.1.2.15 ad * ensure that any lock that may be taken from a software interrupt
225 1.1.2.15 ad * can not be held for more than a short period of time.
226 1.1.2.8 ad *
227 1.1.2.8 ad * The kernel does not allow software interrupts to use facilities
228 1.1.2.8 ad * or perform actions that may block for a significant amount of
229 1.1.2.8 ad * time. This means that it's not valid for a software interrupt
230 1.1.2.8 ad * to: sleep on condition variables, use the lockmgr() facility,
231 1.1.2.8 ad * or wait for resources to become available (for example,
232 1.1.2.8 ad * memory).
233 1.1.2.2 ad *
234 1.1.2.8 ad * Per-CPU operation
235 1.1.2.2 ad *
236 1.1.2.8 ad * If a soft interrupt is triggered on a CPU, it can only be
237 1.1.2.8 ad * dispatched on the same CPU. Each LWP dedicated to handling a
238 1.1.2.8 ad * soft interrupt is bound to its home CPU, so if the LWP blocks
239 1.1.2.8 ad * and needs to run again, it can only run there. Nearly all data
240 1.1.2.8 ad * structures used to manage software interrupts are per-CPU.
241 1.1.2.8 ad *
242 1.1.2.8 ad * The per-CPU requirement is intended to reduce "ping-pong" of
243 1.1.2.8 ad * cache lines between CPUs: lines occupied by data structures
244 1.1.2.8 ad * used to manage the soft interrupts, and lines occupied by data
245 1.1.2.8 ad * items being passed down to the soft interrupt. As a positive
246 1.1.2.8 ad * side effect, this also means that the soft interrupt dispatch
247 1.1.2.15 ad * code does not need to to use spinlocks to synchronize.
248 1.1.2.2 ad *
249 1.1.2.2 ad * Generic implementation
250 1.1.2.2 ad *
251 1.1.2.2 ad * A generic, low performance implementation is provided that
252 1.1.2.2 ad * works across all architectures, with no machine-dependent
253 1.1.2.2 ad * modifications needed. This implementation uses the scheduler,
254 1.1.2.2 ad * and so has a number of restrictions:
255 1.1.2.2 ad *
256 1.1.2.2 ad * 1) Since software interrupts can be triggered from any priority
257 1.1.2.2 ad * level, on architectures where the generic implementation is
258 1.1.2.8 ad * used IPL_SCHED must be equal to IPL_HIGH (it must block all
259 1.1.2.8 ad * interrupts).
260 1.1.2.2 ad *
261 1.1.2.8 ad * 2) The software interrupts are not currently preemptive, so
262 1.1.2.8 ad * must wait for the currently executing LWP to yield the CPU.
263 1.1.2.8 ad * This can introduce latency.
264 1.1.2.2 ad *
265 1.1.2.2 ad * 3) A context switch is required for each soft interrupt to be
266 1.1.2.2 ad * handled, which can be quite expensive.
267 1.1.2.2 ad *
268 1.1.2.2 ad * 'Fast' software interrupts
269 1.1.2.2 ad *
270 1.1.2.8 ad * If an architectures defines __HAVE_FAST_SOFTINTS, it implements
271 1.1.2.8 ad * the fast mechanism. Threads running either in the kernel or in
272 1.1.2.8 ad * userspace will be interrupted, but will not be preempted. When
273 1.1.2.8 ad * the soft interrupt completes execution, the interrupted LWP
274 1.1.2.8 ad * is resumed. Interrupt dispatch code must provide the minimum
275 1.1.2.8 ad * level of context necessary for the soft interrupt to block and
276 1.1.2.8 ad * be resumed at a later time. The machine-dependent dispatch
277 1.1.2.8 ad * path looks something like the following:
278 1.1.2.8 ad *
279 1.1.2.8 ad * softintr()
280 1.1.2.8 ad * {
281 1.1.2.8 ad * go to IPL_HIGH if necessary for switch;
282 1.1.2.8 ad * save any necessary registers in a format that can be
283 1.1.2.8 ad * restored by cpu_switchto if the softint blocks;
284 1.1.2.8 ad * arrange for cpu_switchto() to restore into the
285 1.1.2.8 ad * trampoline function;
286 1.1.2.8 ad * identify LWP to handle this interrupt;
287 1.1.2.8 ad * switch to the LWP's stack;
288 1.1.2.8 ad * switch register stacks, if necessary;
289 1.1.2.8 ad * assign new value of curlwp;
290 1.1.2.8 ad * call MI softint_dispatch, passing old curlwp and IPL
291 1.1.2.8 ad * to execute interrupt at;
292 1.1.2.8 ad * switch back to old stack;
293 1.1.2.8 ad * switch back to old register stack, if necessary;
294 1.1.2.8 ad * restore curlwp;
295 1.1.2.8 ad * return to interrupted LWP;
296 1.1.2.8 ad * }
297 1.1.2.8 ad *
298 1.1.2.8 ad * If the soft interrupt blocks, a trampoline function is returned
299 1.1.2.8 ad * to in the context of the interrupted LWP, as arranged for by
300 1.1.2.8 ad * softint():
301 1.1.2.8 ad *
302 1.1.2.8 ad * softint_ret()
303 1.1.2.8 ad * {
304 1.1.2.8 ad * unlock soft interrupt LWP;
305 1.1.2.8 ad * resume interrupt processing, likely returning to
306 1.1.2.8 ad * interrupted LWP or dispatching another, different
307 1.1.2.8 ad * interrupt;
308 1.1.2.8 ad * }
309 1.1.2.8 ad *
310 1.1.2.8 ad * Once the soft interrupt has fired (and even if it has blocked),
311 1.1.2.8 ad * no further soft interrupts at that level will be triggered by
312 1.1.2.8 ad * MI code until the soft interrupt handler has ceased execution.
313 1.1.2.8 ad * If a soft interrupt handler blocks and is resumed, it resumes
314 1.1.2.8 ad * execution as a normal LWP (kthread) and gains VM context. Only
315 1.1.2.8 ad * when it has completed and is ready to fire again will it
316 1.1.2.8 ad * interrupt other threads.
317 1.1.2.1 ad */
318 1.1.2.1 ad
319 1.1.2.1 ad #include <sys/cdefs.h>
320 1.1.2.16 ad __KERNEL_RCSID(0, "$NetBSD: kern_softint.c,v 1.1.2.16 2007/10/09 13:44:28 ad Exp $");
321 1.1.2.1 ad
322 1.1.2.1 ad #include <sys/param.h>
323 1.1.2.1 ad #include <sys/malloc.h>
324 1.1.2.1 ad #include <sys/proc.h>
325 1.1.2.1 ad #include <sys/intr.h>
326 1.1.2.1 ad #include <sys/mutex.h>
327 1.1.2.1 ad #include <sys/kthread.h>
328 1.1.2.1 ad #include <sys/evcnt.h>
329 1.1.2.1 ad #include <sys/cpu.h>
330 1.1.2.1 ad
331 1.1.2.1 ad #include <net/netisr.h>
332 1.1.2.1 ad
333 1.1.2.1 ad #include <uvm/uvm_extern.h>
334 1.1.2.1 ad
335 1.1.2.3 ad #define PRI_SOFTSERIAL (PRI_COUNT - 1)
336 1.1.2.3 ad #define PRI_SOFTNET (PRI_SOFTSERIAL - schedppq * 1)
337 1.1.2.3 ad #define PRI_SOFTBIO (PRI_SOFTSERIAL - schedppq * 2)
338 1.1.2.3 ad #define PRI_SOFTCLOCK (PRI_SOFTSERIAL - schedppq * 3)
339 1.1.2.1 ad
340 1.1.2.1 ad /* This could overlap with signal info in struct lwp. */
341 1.1.2.1 ad typedef struct softint {
342 1.1.2.8 ad SIMPLEQ_HEAD(, softhand) si_q;
343 1.1.2.1 ad struct lwp *si_lwp;
344 1.1.2.1 ad struct cpu_info *si_cpu;
345 1.1.2.1 ad uintptr_t si_machdep;
346 1.1.2.1 ad struct evcnt si_evcnt;
347 1.1.2.14 yamt struct evcnt si_evcnt_block;
348 1.1.2.1 ad int si_active;
349 1.1.2.2 ad char si_name[8];
350 1.1.2.14 yamt char si_name_block[8+6];
351 1.1.2.1 ad } softint_t;
352 1.1.2.1 ad
353 1.1.2.1 ad typedef struct softhand {
354 1.1.2.8 ad SIMPLEQ_ENTRY(softhand) sh_q;
355 1.1.2.1 ad void (*sh_func)(void *);
356 1.1.2.1 ad void *sh_arg;
357 1.1.2.1 ad softint_t *sh_isr;
358 1.1.2.1 ad u_int sh_pending;
359 1.1.2.1 ad u_int sh_flags;
360 1.1.2.1 ad } softhand_t;
361 1.1.2.1 ad
362 1.1.2.1 ad typedef struct softcpu {
363 1.1.2.1 ad struct cpu_info *sc_cpu;
364 1.1.2.1 ad softint_t sc_int[SOFTINT_COUNT];
365 1.1.2.1 ad softhand_t sc_hand[1];
366 1.1.2.1 ad } softcpu_t;
367 1.1.2.1 ad
368 1.1.2.1 ad static void softint_thread(void *);
369 1.1.2.1 ad static void softint_netisr(void *);
370 1.1.2.1 ad
371 1.1.2.1 ad u_int softint_bytes = 8192;
372 1.1.2.6 ad u_int softint_timing;
373 1.1.2.1 ad static u_int softint_max;
374 1.1.2.1 ad static kmutex_t softint_lock;
375 1.1.2.1 ad static void *softint_netisr_sih;
376 1.1.2.1 ad
377 1.1.2.1 ad /*
378 1.1.2.1 ad * softint_init_isr:
379 1.1.2.1 ad *
380 1.1.2.1 ad * Initialize a single interrupt level for a single CPU.
381 1.1.2.1 ad */
382 1.1.2.1 ad static void
383 1.1.2.1 ad softint_init_isr(softcpu_t *sc, const char *desc, pri_t pri, u_int level)
384 1.1.2.1 ad {
385 1.1.2.1 ad struct cpu_info *ci;
386 1.1.2.1 ad softint_t *si;
387 1.1.2.1 ad int error;
388 1.1.2.1 ad
389 1.1.2.1 ad si = &sc->sc_int[level];
390 1.1.2.1 ad ci = sc->sc_cpu;
391 1.1.2.1 ad si->si_cpu = ci;
392 1.1.2.1 ad
393 1.1.2.8 ad SIMPLEQ_INIT(&si->si_q);
394 1.1.2.1 ad
395 1.1.2.1 ad error = kthread_create(pri, KTHREAD_MPSAFE | KTHREAD_INTR |
396 1.1.2.1 ad KTHREAD_IDLE, ci, softint_thread, si, &si->si_lwp,
397 1.1.2.1 ad "soft%s/%d", desc, (int)ci->ci_cpuid);
398 1.1.2.1 ad if (error != 0)
399 1.1.2.1 ad panic("softint_init_isr: error %d", error);
400 1.1.2.1 ad
401 1.1.2.2 ad snprintf(si->si_name, sizeof(si->si_name), "%s/%d", desc,
402 1.1.2.2 ad (int)ci->ci_cpuid);
403 1.1.2.1 ad evcnt_attach_dynamic(&si->si_evcnt, EVCNT_TYPE_INTR, NULL,
404 1.1.2.2 ad "softint", si->si_name);
405 1.1.2.14 yamt snprintf(si->si_name_block, sizeof(si->si_name_block), "%s block/%d",
406 1.1.2.14 yamt desc, (int)ci->ci_cpuid);
407 1.1.2.14 yamt evcnt_attach_dynamic(&si->si_evcnt_block, EVCNT_TYPE_INTR, NULL,
408 1.1.2.14 yamt "softint", si->si_name_block);
409 1.1.2.1 ad
410 1.1.2.3 ad si->si_lwp->l_private = si;
411 1.1.2.3 ad softint_init_md(si->si_lwp, level, &si->si_machdep);
412 1.1.2.2 ad #ifdef __HAVE_FAST_SOFTINTS
413 1.1.2.2 ad si->si_lwp->l_mutex = &ci->ci_schedstate.spc_lwplock;
414 1.1.2.2 ad #endif
415 1.1.2.1 ad }
416 1.1.2.1 ad /*
417 1.1.2.1 ad * softint_init:
418 1.1.2.1 ad *
419 1.1.2.1 ad * Initialize per-CPU data structures. Called from mi_cpu_attach().
420 1.1.2.1 ad */
421 1.1.2.1 ad void
422 1.1.2.1 ad softint_init(struct cpu_info *ci)
423 1.1.2.1 ad {
424 1.1.2.1 ad static struct cpu_info *first;
425 1.1.2.1 ad softcpu_t *sc, *scfirst;
426 1.1.2.1 ad softhand_t *sh, *shmax;
427 1.1.2.1 ad
428 1.1.2.1 ad if (first == NULL) {
429 1.1.2.2 ad /* Boot CPU. */
430 1.1.2.1 ad first = ci;
431 1.1.2.1 ad mutex_init(&softint_lock, MUTEX_DEFAULT, IPL_NONE);
432 1.1.2.1 ad softint_bytes = round_page(softint_bytes);
433 1.1.2.1 ad softint_max = (softint_bytes - sizeof(softcpu_t)) /
434 1.1.2.1 ad sizeof(softhand_t);
435 1.1.2.1 ad }
436 1.1.2.1 ad
437 1.1.2.1 ad sc = (softcpu_t *)uvm_km_alloc(kernel_map, softint_bytes, 0,
438 1.1.2.1 ad UVM_KMF_WIRED | UVM_KMF_ZERO);
439 1.1.2.1 ad if (sc == NULL)
440 1.1.2.1 ad panic("softint_init_cpu: cannot allocate memory");
441 1.1.2.1 ad
442 1.1.2.1 ad ci->ci_data.cpu_softcpu = sc;
443 1.1.2.1 ad sc->sc_cpu = ci;
444 1.1.2.1 ad
445 1.1.2.1 ad softint_init_isr(sc, "net", PRI_SOFTNET, SOFTINT_NET);
446 1.1.2.1 ad softint_init_isr(sc, "bio", PRI_SOFTBIO, SOFTINT_BIO);
447 1.1.2.1 ad softint_init_isr(sc, "clk", PRI_SOFTCLOCK, SOFTINT_CLOCK);
448 1.1.2.1 ad softint_init_isr(sc, "ser", PRI_SOFTSERIAL, SOFTINT_SERIAL);
449 1.1.2.1 ad
450 1.1.2.1 ad if (first != ci) {
451 1.1.2.2 ad /* Don't lock -- autoconfiguration will prevent reentry. */
452 1.1.2.1 ad scfirst = first->ci_data.cpu_softcpu;
453 1.1.2.1 ad sh = sc->sc_hand;
454 1.1.2.1 ad memcpy(sh, scfirst->sc_hand, sizeof(*sh) * softint_max);
455 1.1.2.1 ad
456 1.1.2.1 ad /* Update pointers for this CPU. */
457 1.1.2.1 ad for (shmax = sh + softint_max; sh < shmax; sh++) {
458 1.1.2.1 ad if (sh->sh_func == NULL)
459 1.1.2.1 ad continue;
460 1.1.2.1 ad sh->sh_isr =
461 1.1.2.1 ad &sc->sc_int[sh->sh_flags & SOFTINT_LVLMASK];
462 1.1.2.1 ad }
463 1.1.2.1 ad } else {
464 1.1.2.1 ad /* Establish a handler for legacy net interrupts. */
465 1.1.2.1 ad softint_netisr_sih = softint_establish(SOFTINT_NET,
466 1.1.2.1 ad softint_netisr, NULL);
467 1.1.2.1 ad KASSERT(softint_netisr_sih != NULL);
468 1.1.2.1 ad }
469 1.1.2.1 ad }
470 1.1.2.1 ad
471 1.1.2.1 ad /*
472 1.1.2.1 ad * softint_establish:
473 1.1.2.1 ad *
474 1.1.2.1 ad * Register a software interrupt handler.
475 1.1.2.1 ad */
476 1.1.2.1 ad void *
477 1.1.2.1 ad softint_establish(u_int flags, void (*func)(void *), void *arg)
478 1.1.2.1 ad {
479 1.1.2.1 ad CPU_INFO_ITERATOR cii;
480 1.1.2.1 ad struct cpu_info *ci;
481 1.1.2.1 ad softcpu_t *sc;
482 1.1.2.1 ad softhand_t *sh;
483 1.1.2.3 ad u_int level, index;
484 1.1.2.1 ad
485 1.1.2.1 ad level = (flags & SOFTINT_LVLMASK);
486 1.1.2.1 ad KASSERT(level < SOFTINT_COUNT);
487 1.1.2.1 ad
488 1.1.2.1 ad mutex_enter(&softint_lock);
489 1.1.2.1 ad
490 1.1.2.1 ad /* Find a free slot. */
491 1.1.2.1 ad sc = curcpu()->ci_data.cpu_softcpu;
492 1.1.2.1 ad for (index = 1; index < softint_max; index++)
493 1.1.2.1 ad if (sc->sc_hand[index].sh_func == NULL)
494 1.1.2.1 ad break;
495 1.1.2.1 ad if (index == softint_max) {
496 1.1.2.1 ad mutex_exit(&softint_lock);
497 1.1.2.1 ad printf("WARNING: softint_establish: table full, "
498 1.1.2.1 ad "increase softint_bytes\n");
499 1.1.2.1 ad return NULL;
500 1.1.2.1 ad }
501 1.1.2.1 ad
502 1.1.2.1 ad /* Set up the handler on each CPU. */
503 1.1.2.1 ad for (CPU_INFO_FOREACH(cii, ci)) {
504 1.1.2.1 ad sc = ci->ci_data.cpu_softcpu;
505 1.1.2.1 ad sh = &sc->sc_hand[index];
506 1.1.2.1 ad
507 1.1.2.1 ad sh->sh_isr = &sc->sc_int[level];
508 1.1.2.1 ad sh->sh_func = func;
509 1.1.2.1 ad sh->sh_arg = arg;
510 1.1.2.1 ad sh->sh_flags = flags;
511 1.1.2.1 ad sh->sh_pending = 0;
512 1.1.2.1 ad }
513 1.1.2.1 ad
514 1.1.2.1 ad mutex_exit(&softint_lock);
515 1.1.2.1 ad
516 1.1.2.3 ad return (void *)((uint8_t *)&sc->sc_hand[index] - (uint8_t *)sc);
517 1.1.2.1 ad }
518 1.1.2.1 ad
519 1.1.2.1 ad /*
520 1.1.2.1 ad * softint_disestablish:
521 1.1.2.1 ad *
522 1.1.2.1 ad * Unregister a software interrupt handler.
523 1.1.2.1 ad */
524 1.1.2.1 ad void
525 1.1.2.1 ad softint_disestablish(void *arg)
526 1.1.2.1 ad {
527 1.1.2.1 ad CPU_INFO_ITERATOR cii;
528 1.1.2.1 ad struct cpu_info *ci;
529 1.1.2.1 ad softcpu_t *sc;
530 1.1.2.1 ad softhand_t *sh;
531 1.1.2.3 ad uintptr_t offset;
532 1.1.2.1 ad
533 1.1.2.3 ad offset = (uintptr_t)arg;
534 1.1.2.3 ad KASSERT(offset != 0 && offset < softint_bytes);
535 1.1.2.1 ad
536 1.1.2.1 ad mutex_enter(&softint_lock);
537 1.1.2.1 ad
538 1.1.2.1 ad /* Set up the handler on each CPU. */
539 1.1.2.1 ad for (CPU_INFO_FOREACH(cii, ci)) {
540 1.1.2.1 ad sc = ci->ci_data.cpu_softcpu;
541 1.1.2.3 ad sh = (softhand_t *)((uint8_t *)sc + offset);
542 1.1.2.1 ad KASSERT(sh->sh_func != NULL);
543 1.1.2.1 ad KASSERT(sh->sh_pending == 0);
544 1.1.2.1 ad sh->sh_func = NULL;
545 1.1.2.1 ad }
546 1.1.2.1 ad
547 1.1.2.1 ad mutex_exit(&softint_lock);
548 1.1.2.1 ad }
549 1.1.2.1 ad
550 1.1.2.1 ad /*
551 1.1.2.1 ad * softint_schedule:
552 1.1.2.1 ad *
553 1.1.2.1 ad * Trigger a software interrupt. Must be called from a hardware
554 1.1.2.1 ad * interrupt handler, or with preemption disabled (since we are
555 1.1.2.1 ad * using the value of curcpu()).
556 1.1.2.1 ad */
557 1.1.2.1 ad void
558 1.1.2.1 ad softint_schedule(void *arg)
559 1.1.2.1 ad {
560 1.1.2.1 ad softhand_t *sh;
561 1.1.2.1 ad softint_t *si;
562 1.1.2.3 ad uintptr_t offset;
563 1.1.2.1 ad int s;
564 1.1.2.1 ad
565 1.1.2.1 ad /* Find the handler record for this CPU. */
566 1.1.2.3 ad offset = (uintptr_t)arg;
567 1.1.2.3 ad KASSERT(offset != 0 && offset < softint_bytes);
568 1.1.2.3 ad sh = (softhand_t *)((uint8_t *)curcpu()->ci_data.cpu_softcpu + offset);
569 1.1.2.1 ad
570 1.1.2.1 ad /* If it's already pending there's nothing to do. */
571 1.1.2.1 ad if (sh->sh_pending)
572 1.1.2.1 ad return;
573 1.1.2.1 ad
574 1.1.2.1 ad /*
575 1.1.2.1 ad * Enqueue the handler into the LWP's pending list.
576 1.1.2.1 ad * If the LWP is completely idle, then make it run.
577 1.1.2.1 ad */
578 1.1.2.1 ad s = splhigh();
579 1.1.2.1 ad if (!sh->sh_pending) {
580 1.1.2.1 ad si = sh->sh_isr;
581 1.1.2.1 ad sh->sh_pending = 1;
582 1.1.2.8 ad SIMPLEQ_INSERT_TAIL(&si->si_q, sh, sh_q);
583 1.1.2.1 ad if (si->si_active == 0) {
584 1.1.2.1 ad si->si_active = 1;
585 1.1.2.1 ad softint_trigger(si->si_machdep);
586 1.1.2.1 ad }
587 1.1.2.1 ad }
588 1.1.2.1 ad splx(s);
589 1.1.2.1 ad }
590 1.1.2.1 ad
591 1.1.2.1 ad /*
592 1.1.2.1 ad * softint_execute:
593 1.1.2.1 ad *
594 1.1.2.1 ad * Invoke handlers for the specified soft interrupt.
595 1.1.2.1 ad * Must be entered at splhigh. Will drop the priority
596 1.1.2.1 ad * to the level specified, but returns back at splhigh.
597 1.1.2.1 ad */
598 1.1.2.3 ad static inline void
599 1.1.2.3 ad softint_execute(softint_t *si, lwp_t *l, int s)
600 1.1.2.1 ad {
601 1.1.2.1 ad softhand_t *sh;
602 1.1.2.11 ad bool havelock;
603 1.1.2.1 ad
604 1.1.2.1 ad KASSERT(si->si_lwp == curlwp);
605 1.1.2.1 ad KASSERT(si->si_cpu == curcpu());
606 1.1.2.1 ad KASSERT(si->si_lwp->l_wchan == NULL);
607 1.1.2.1 ad KASSERT(si->si_active);
608 1.1.2.1 ad
609 1.1.2.11 ad havelock = false;
610 1.1.2.11 ad
611 1.1.2.9 ad /*
612 1.1.2.9 ad * Note: due to priority inheritance we may have interrupted a
613 1.1.2.10 yamt * higher priority LWP. Since the soft interrupt must be quick
614 1.1.2.10 yamt * and is non-preemptable, we don't bother yielding.
615 1.1.2.9 ad */
616 1.1.2.2 ad
617 1.1.2.9 ad while (!SIMPLEQ_EMPTY(&si->si_q)) {
618 1.1.2.2 ad /*
619 1.1.2.1 ad * Pick the longest waiting handler to run. We block
620 1.1.2.1 ad * interrupts but do not lock in order to do this, as
621 1.1.2.1 ad * we are protecting against the local CPU only.
622 1.1.2.1 ad */
623 1.1.2.8 ad sh = SIMPLEQ_FIRST(&si->si_q);
624 1.1.2.8 ad SIMPLEQ_REMOVE_HEAD(&si->si_q, sh_q);
625 1.1.2.1 ad sh->sh_pending = 0;
626 1.1.2.1 ad splx(s);
627 1.1.2.1 ad
628 1.1.2.1 ad /* Run the handler. */
629 1.1.2.11 ad if ((sh->sh_flags & SOFTINT_MPSAFE) == 0 && !havelock) {
630 1.1.2.2 ad KERNEL_LOCK(1, l);
631 1.1.2.11 ad havelock = true;
632 1.1.2.1 ad }
633 1.1.2.1 ad (*sh->sh_func)(sh->sh_arg);
634 1.1.2.1 ad
635 1.1.2.1 ad (void)splhigh();
636 1.1.2.1 ad }
637 1.1.2.1 ad
638 1.1.2.11 ad if (havelock) {
639 1.1.2.11 ad KERNEL_UNLOCK_ONE(l);
640 1.1.2.11 ad }
641 1.1.2.11 ad
642 1.1.2.1 ad /*
643 1.1.2.1 ad * Unlocked, but only for statistics.
644 1.1.2.1 ad * Should be per-CPU to prevent cache ping-pong.
645 1.1.2.1 ad */
646 1.1.2.1 ad uvmexp.softs++;
647 1.1.2.1 ad
648 1.1.2.1 ad si->si_evcnt.ev_count++;
649 1.1.2.1 ad si->si_active = 0;
650 1.1.2.1 ad }
651 1.1.2.1 ad
652 1.1.2.1 ad /*
653 1.1.2.1 ad * schednetisr:
654 1.1.2.1 ad *
655 1.1.2.1 ad * Trigger a legacy network interrupt. XXX Needs to go away.
656 1.1.2.1 ad */
657 1.1.2.1 ad void
658 1.1.2.1 ad schednetisr(int isr)
659 1.1.2.1 ad {
660 1.1.2.1 ad int s;
661 1.1.2.1 ad
662 1.1.2.1 ad s = splhigh();
663 1.1.2.1 ad curcpu()->ci_data.cpu_netisrs |= (1 << isr);
664 1.1.2.1 ad softint_schedule(softint_netisr_sih);
665 1.1.2.1 ad splx(s);
666 1.1.2.1 ad }
667 1.1.2.1 ad
668 1.1.2.1 ad /*
669 1.1.2.1 ad * softintr_netisr:
670 1.1.2.1 ad *
671 1.1.2.2 ad * Dispatch legacy network interrupts. XXX Needs to go away.
672 1.1.2.1 ad */
673 1.1.2.1 ad static void
674 1.1.2.1 ad softint_netisr(void *cookie)
675 1.1.2.1 ad {
676 1.1.2.1 ad struct cpu_info *ci;
677 1.1.2.1 ad int s, bits;
678 1.1.2.1 ad
679 1.1.2.1 ad ci = curcpu();
680 1.1.2.1 ad
681 1.1.2.1 ad s = splhigh();
682 1.1.2.1 ad bits = ci->ci_data.cpu_netisrs;
683 1.1.2.1 ad ci->ci_data.cpu_netisrs = 0;
684 1.1.2.1 ad splx(s);
685 1.1.2.1 ad
686 1.1.2.1 ad #define DONETISR(which, func) \
687 1.1.2.1 ad do { \
688 1.1.2.1 ad void func(void); \
689 1.1.2.1 ad if ((bits & (1 << which)) != 0) \
690 1.1.2.1 ad func(); \
691 1.1.2.1 ad } while(0);
692 1.1.2.1 ad #include <net/netisr_dispatch.h>
693 1.1.2.1 ad #undef DONETISR
694 1.1.2.1 ad }
695 1.1.2.3 ad
696 1.1.2.3 ad #ifndef __HAVE_FAST_SOFTINTS
697 1.1.2.3 ad
698 1.1.2.3 ad /*
699 1.1.2.3 ad * softint_init_md:
700 1.1.2.3 ad *
701 1.1.2.6 ad * Perform machine-dependent initialization.
702 1.1.2.3 ad */
703 1.1.2.3 ad void
704 1.1.2.3 ad softint_init_md(lwp_t *l, u_int level, uintptr_t *machdep)
705 1.1.2.3 ad {
706 1.1.2.3 ad softint_t *si;
707 1.1.2.3 ad
708 1.1.2.7 ad *machdep = (uintptr_t)l;
709 1.1.2.3 ad si = l->l_private;
710 1.1.2.3 ad
711 1.1.2.3 ad lwp_lock(l);
712 1.1.2.3 ad /* Cheat and make the KASSERT in softint_thread() happy. */
713 1.1.2.3 ad si->si_active = 1;
714 1.1.2.3 ad l->l_stat = LSRUN;
715 1.1.2.3 ad sched_enqueue(l, false);
716 1.1.2.3 ad lwp_unlock(l);
717 1.1.2.3 ad }
718 1.1.2.3 ad
719 1.1.2.3 ad /*
720 1.1.2.3 ad * softint_trigger:
721 1.1.2.3 ad *
722 1.1.2.3 ad * Cause a soft interrupt handler to begin executing.
723 1.1.2.3 ad */
724 1.1.2.3 ad void
725 1.1.2.3 ad softint_trigger(uintptr_t machdep)
726 1.1.2.3 ad {
727 1.1.2.3 ad struct cpu_info *ci;
728 1.1.2.3 ad lwp_t *l;
729 1.1.2.3 ad
730 1.1.2.3 ad l = (lwp_t *)machdep;
731 1.1.2.3 ad ci = l->l_cpu;
732 1.1.2.3 ad
733 1.1.2.3 ad spc_lock(ci);
734 1.1.2.3 ad l->l_mutex = ci->ci_schedstate.spc_mutex;
735 1.1.2.3 ad l->l_stat = LSRUN;
736 1.1.2.3 ad sched_enqueue(l, false);
737 1.1.2.12 ad cpu_need_resched(ci, RESCHED_IMMED);
738 1.1.2.3 ad spc_unlock(ci);
739 1.1.2.3 ad }
740 1.1.2.3 ad
741 1.1.2.3 ad /*
742 1.1.2.3 ad * softint_thread:
743 1.1.2.3 ad *
744 1.1.2.6 ad * Slow path MI software interrupt dispatch.
745 1.1.2.3 ad */
746 1.1.2.3 ad void
747 1.1.2.3 ad softint_thread(void *cookie)
748 1.1.2.3 ad {
749 1.1.2.3 ad softint_t *si;
750 1.1.2.3 ad lwp_t *l;
751 1.1.2.3 ad int s;
752 1.1.2.3 ad
753 1.1.2.3 ad l = curlwp;
754 1.1.2.3 ad si = l->l_private;
755 1.1.2.3 ad s = splhigh();
756 1.1.2.3 ad
757 1.1.2.3 ad for (;;) {
758 1.1.2.3 ad softint_execute(si, l, s);
759 1.1.2.3 ad
760 1.1.2.3 ad lwp_lock(l);
761 1.1.2.3 ad l->l_stat = LSIDL;
762 1.1.2.3 ad mi_switch(l);
763 1.1.2.3 ad }
764 1.1.2.3 ad }
765 1.1.2.3 ad
766 1.1.2.3 ad #else /* !__HAVE_FAST_SOFTINTS */
767 1.1.2.3 ad
768 1.1.2.3 ad /*
769 1.1.2.3 ad * softint_thread:
770 1.1.2.3 ad *
771 1.1.2.3 ad * In the __HAVE_FAST_SOFTINTS case, the LWP is switched to without
772 1.1.2.3 ad * restoring any state, so we should not arrive here - there is a
773 1.1.2.3 ad * direct handoff between the interrupt stub and softint_dispatch().
774 1.1.2.3 ad */
775 1.1.2.3 ad void
776 1.1.2.3 ad softint_thread(void *cookie)
777 1.1.2.3 ad {
778 1.1.2.3 ad
779 1.1.2.3 ad panic("softint_thread");
780 1.1.2.3 ad }
781 1.1.2.3 ad
782 1.1.2.3 ad /*
783 1.1.2.3 ad * softint_dispatch:
784 1.1.2.3 ad *
785 1.1.2.3 ad * Entry point from machine-dependent code.
786 1.1.2.3 ad */
787 1.1.2.3 ad void
788 1.1.2.3 ad softint_dispatch(lwp_t *pinned, int s)
789 1.1.2.3 ad {
790 1.1.2.6 ad struct timeval now;
791 1.1.2.3 ad softint_t *si;
792 1.1.2.6 ad u_int timing;
793 1.1.2.3 ad lwp_t *l;
794 1.1.2.3 ad
795 1.1.2.3 ad l = curlwp;
796 1.1.2.3 ad si = l->l_private;
797 1.1.2.3 ad
798 1.1.2.3 ad /*
799 1.1.2.3 ad * Note the interrupted LWP, and mark the current LWP as running
800 1.1.2.3 ad * before proceeding. Although this must as a rule be done with
801 1.1.2.3 ad * the LWP locked, at this point no external agents will want to
802 1.1.2.3 ad * modify the interrupt LWP's state.
803 1.1.2.3 ad */
804 1.1.2.6 ad timing = (softint_timing ? LW_TIMEINTR : 0);
805 1.1.2.3 ad l->l_switchto = pinned;
806 1.1.2.3 ad l->l_stat = LSONPROC;
807 1.1.2.6 ad l->l_flag |= (LW_RUNNING | timing);
808 1.1.2.3 ad
809 1.1.2.6 ad /*
810 1.1.2.6 ad * Dispatch the interrupt. If softints are being timed, charge
811 1.1.2.6 ad * for it.
812 1.1.2.6 ad */
813 1.1.2.6 ad if (timing)
814 1.1.2.6 ad microtime(&l->l_stime);
815 1.1.2.3 ad softint_execute(si, l, s);
816 1.1.2.6 ad if (timing) {
817 1.1.2.6 ad microtime(&now);
818 1.1.2.6 ad updatertime(l, &now);
819 1.1.2.6 ad l->l_flag &= ~LW_TIMEINTR;
820 1.1.2.6 ad }
821 1.1.2.3 ad
822 1.1.2.3 ad /*
823 1.1.2.6 ad * If we blocked while handling the interrupt, the pinned LWP is
824 1.1.2.6 ad * gone so switch to the idle LWP. It will select a new LWP to
825 1.1.2.6 ad * run.
826 1.1.2.3 ad *
827 1.1.2.5 ad * We must drop the priority level as switching at IPL_HIGH could
828 1.1.2.5 ad * deadlock the system. We have already set si->si_active = 0,
829 1.1.2.5 ad * which means another interrupt at this level can be triggered.
830 1.1.2.5 ad * That's not be a problem: we are lowering to level 's' which will
831 1.1.2.6 ad * prevent softint_dispatch() from being reentered at level 's',
832 1.1.2.6 ad * until the priority is finally dropped to IPL_NONE on entry to
833 1.1.2.6 ad * the idle loop.
834 1.1.2.3 ad */
835 1.1.2.4 ad l->l_stat = LSIDL;
836 1.1.2.3 ad if (l->l_switchto == NULL) {
837 1.1.2.3 ad splx(s);
838 1.1.2.13 yamt pmap_deactivate(l);
839 1.1.2.3 ad lwp_exit_switchaway(l);
840 1.1.2.3 ad /* NOTREACHED */
841 1.1.2.3 ad }
842 1.1.2.3 ad l->l_switchto = NULL;
843 1.1.2.3 ad l->l_flag &= ~LW_RUNNING;
844 1.1.2.3 ad }
845 1.1.2.3 ad
846 1.1.2.3 ad #endif /* !__HAVE_FAST_SOFTINTS */
847 1.1.2.14 yamt
848 1.1.2.14 yamt /*
849 1.1.2.14 yamt * softint_block:
850 1.1.2.14 yamt *
851 1.1.2.14 yamt * Update statistics when the soft interrupt blocks.
852 1.1.2.14 yamt */
853 1.1.2.14 yamt void
854 1.1.2.14 yamt softint_block(lwp_t *l)
855 1.1.2.14 yamt {
856 1.1.2.14 yamt softint_t *si = l->l_private;
857 1.1.2.14 yamt
858 1.1.2.14 yamt KASSERT((l->l_flag & LW_INTR) != 0);
859 1.1.2.14 yamt si->si_evcnt_block.ev_count++;
860 1.1.2.14 yamt }
861