udivdi3.S revision 1.2.6.2
1 1.2.6.2 simonb .file "__udivdi3.s" 2 1.2.6.2 simonb 3 1.2.6.2 simonb // $NetBSD: udivdi3.S,v 1.2.6.2 2006/04/22 11:40:05 simonb Exp $ 4 1.2.6.2 simonb 5 1.2.6.2 simonb //- 6 1.2.6.2 simonb // Copyright (c) 2000, Intel Corporation 7 1.2.6.2 simonb // All rights reserved. 8 1.2.6.2 simonb // 9 1.2.6.2 simonb // Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache, 10 1.2.6.2 simonb // Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab, 11 1.2.6.2 simonb // Intel Corporation. 12 1.2.6.2 simonb // 13 1.2.6.2 simonb // WARRANTY DISCLAIMER 14 1.2.6.2 simonb // 15 1.2.6.2 simonb // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16 1.2.6.2 simonb // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17 1.2.6.2 simonb // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18 1.2.6.2 simonb // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS 19 1.2.6.2 simonb // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 20 1.2.6.2 simonb // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 21 1.2.6.2 simonb // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 22 1.2.6.2 simonb // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 23 1.2.6.2 simonb // OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING 24 1.2.6.2 simonb // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 1.2.6.2 simonb // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 1.2.6.2 simonb // 27 1.2.6.2 simonb // Intel Corporation is the author of this code, and requests that all 28 1.2.6.2 simonb // problem reports or change requests be submitted to it directly at 29 1.2.6.2 simonb // http://developer.intel.com/opensource. 30 1.2.6.2 simonb // 31 1.2.6.2 simonb 32 1.2.6.2 simonb .section .text 33 1.2.6.2 simonb .proc __udivdi3# 34 1.2.6.2 simonb .align 32 35 1.2.6.2 simonb .global __udivdi3# 36 1.2.6.2 simonb .align 32 37 1.2.6.2 simonb 38 1.2.6.2 simonb // 64-bit unsigned integer divide 39 1.2.6.2 simonb 40 1.2.6.2 simonb __udivdi3: 41 1.2.6.2 simonb 42 1.2.6.2 simonb { .mii 43 1.2.6.2 simonb alloc r31=ar.pfs,2,0,0,0 44 1.2.6.2 simonb nop.i 0 45 1.2.6.2 simonb nop.i 0;; 46 1.2.6.2 simonb } 47 1.2.6.2 simonb 48 1.2.6.2 simonb { .mmi 49 1.2.6.2 simonb 50 1.2.6.2 simonb // 64-BIT UNSIGNED INTEGER DIVIDE BEGINS HERE 51 1.2.6.2 simonb 52 1.2.6.2 simonb setf.sig f8=r32 53 1.2.6.2 simonb setf.sig f9=r33 54 1.2.6.2 simonb nop.i 0;; 55 1.2.6.2 simonb } { .mfb 56 1.2.6.2 simonb nop.m 0 57 1.2.6.2 simonb fma.s1 f6=f8,f1,f0 58 1.2.6.2 simonb nop.b 0 59 1.2.6.2 simonb } { .mfb 60 1.2.6.2 simonb nop.m 0 61 1.2.6.2 simonb fma.s1 f7=f9,f1,f0 62 1.2.6.2 simonb nop.b 0;; 63 1.2.6.2 simonb } { .mfi 64 1.2.6.2 simonb nop.m 0 65 1.2.6.2 simonb // Step (1) 66 1.2.6.2 simonb // y0 = 1 / b in f8 67 1.2.6.2 simonb frcpa.s1 f8,p6=f6,f7 68 1.2.6.2 simonb nop.i 0;; 69 1.2.6.2 simonb } { .mfi 70 1.2.6.2 simonb nop.m 0 71 1.2.6.2 simonb // Step (2) 72 1.2.6.2 simonb // e0 = 1 - b * y0 in f9 73 1.2.6.2 simonb (p6) fnma.s1 f9=f7,f8,f1 74 1.2.6.2 simonb nop.i 0 75 1.2.6.2 simonb } { .mfi 76 1.2.6.2 simonb nop.m 0 77 1.2.6.2 simonb // Step (3) 78 1.2.6.2 simonb // q0 = a * y0 in f10 79 1.2.6.2 simonb (p6) fma.s1 f10=f6,f8,f0 80 1.2.6.2 simonb nop.i 0;; 81 1.2.6.2 simonb } { .mfi 82 1.2.6.2 simonb nop.m 0 83 1.2.6.2 simonb // Step (4) 84 1.2.6.2 simonb // e1 = e0 * e0 in f11 85 1.2.6.2 simonb (p6) fma.s1 f11=f9,f9,f0 86 1.2.6.2 simonb nop.i 0 87 1.2.6.2 simonb } { .mfi 88 1.2.6.2 simonb nop.m 0 89 1.2.6.2 simonb // Step (5) 90 1.2.6.2 simonb // q1 = q0 + e0 * q0 in f10 91 1.2.6.2 simonb (p6) fma.s1 f10=f9,f10,f10 92 1.2.6.2 simonb nop.i 0;; 93 1.2.6.2 simonb } { .mfi 94 1.2.6.2 simonb nop.m 0 95 1.2.6.2 simonb // Step (6) 96 1.2.6.2 simonb // y1 = y0 + e0 * y0 in f8 97 1.2.6.2 simonb (p6) fma.s1 f8=f9,f8,f8 98 1.2.6.2 simonb nop.i 0;; 99 1.2.6.2 simonb } { .mfi 100 1.2.6.2 simonb nop.m 0 101 1.2.6.2 simonb // Step (7) 102 1.2.6.2 simonb // q2 = q1 + e1 * q1 in f9 103 1.2.6.2 simonb (p6) fma.s1 f9=f11,f10,f10 104 1.2.6.2 simonb nop.i 0;; 105 1.2.6.2 simonb } { .mfi 106 1.2.6.2 simonb nop.m 0 107 1.2.6.2 simonb // Step (8) 108 1.2.6.2 simonb // y2 = y1 + e1 * y1 in f8 109 1.2.6.2 simonb (p6) fma.s1 f8=f11,f8,f8 110 1.2.6.2 simonb nop.i 0;; 111 1.2.6.2 simonb } { .mfi 112 1.2.6.2 simonb nop.m 0 113 1.2.6.2 simonb // Step (9) 114 1.2.6.2 simonb // r2 = a - b * q2 in f10 115 1.2.6.2 simonb (p6) fnma.s1 f10=f7,f9,f6 116 1.2.6.2 simonb nop.i 0;; 117 1.2.6.2 simonb } { .mfi 118 1.2.6.2 simonb nop.m 0 119 1.2.6.2 simonb // Step (10) 120 1.2.6.2 simonb // q3 = q2 + r2 * y2 in f8 121 1.2.6.2 simonb (p6) fma.s1 f8=f10,f8,f9 122 1.2.6.2 simonb nop.i 0;; 123 1.2.6.2 simonb } { .mfb 124 1.2.6.2 simonb nop.m 0 125 1.2.6.2 simonb // (11) q = trunc(q3) 126 1.2.6.2 simonb fcvt.fxu.trunc.s1 f8=f8 127 1.2.6.2 simonb nop.b 0;; 128 1.2.6.2 simonb } { .mmi 129 1.2.6.2 simonb // quotient will be in r8 (if b != 0) 130 1.2.6.2 simonb getf.sig r8=f8 131 1.2.6.2 simonb nop.m 0 132 1.2.6.2 simonb nop.i 0;; 133 1.2.6.2 simonb } 134 1.2.6.2 simonb 135 1.2.6.2 simonb // 64-BIT UNSIGNED INTEGER DIVIDE ENDS HERE 136 1.2.6.2 simonb 137 1.2.6.2 simonb { .mmb 138 1.2.6.2 simonb nop.m 0 139 1.2.6.2 simonb nop.m 0 140 1.2.6.2 simonb br.ret.sptk b0;; 141 1.2.6.2 simonb } 142 1.2.6.2 simonb 143 1.2.6.2 simonb .endp __udivdi3 144
Indexes created Tue Sep 30 20:09:53 GMT 2025