xref: /src/sys/modules/amdgpu/Makefile

# $NetBSD: Makefile,v 1.10 2025/09/19 05:18:23 mrg Exp $

.include "../Makefile.inc"
.include "../drmkms/Makefile.inc"

KMOD=	amdgpu
IOCONF=	amdgpu.ioconf
MKLDSCRIPT=yes

WARNS=	3

.if ${MACHINE_ARCH} == "x86_64"
COPTS.amdgpu_float+=	${${ACTIVE_CC} == "gcc" :? -mhard-float :} -msse -msse2
.elif !empty(MACHINE_ARCH:Maarch64*)
COPTS.amdgpu_float+=	-march=armv8-a
.endif

.if ${MACHINE_ARCH} == "i386" || ${MACHINE_ARCH} == "x86_64" || \
	${MACHINE_CPU} == "arm" || ${MACHINE_CPU} == "aarch64"
CPPFLAGS+=	-DNACPICA=1
.endif

# sed -ne 's,^makeoptions	amdgpu	"\([^.]*\)\.amdgpu"+="\(.*\)",\1+=	\2,gp' <files.amdgpu | sed -e 's,\$S,${S},g'
# Note: order of includes is significant.
CPPFLAGS+=	-I${S}/external/bsd/drm2/dist/drm/amd/include/asic_reg
CPPFLAGS+=	-I${S}/external/bsd/drm2/dist/drm/amd/include
CPPFLAGS+=	-I${S}/external/bsd/drm2/dist/drm/amd/amdgpu
CPPFLAGS+=	-I${S}/external/bsd/drm2/dist/drm/amd/powerplay/inc
CPPFLAGS+=	-I${S}/external/bsd/drm2/dist/drm/amd/powerplay/smumgr
CPPFLAGS+=	-I${S}/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr
CPPFLAGS+=	-I${S}/external/bsd/drm2/dist/drm/amd/acp/include
CPPFLAGS+=	-I${S}/external/bsd/drm2/dist/drm/amd/display
CPPFLAGS+=	-I${S}/external/bsd/drm2/dist/drm/amd/display/include
CPPFLAGS+=	-I${S}/external/bsd/drm2/dist/drm/amd/display/dc
CPPFLAGS+=	-I${S}/external/bsd/drm2/dist/drm/amd/display/dc/inc
CPPFLAGS+=	-I${S}/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw
CPPFLAGS+=	-I${S}/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr
CPPFLAGS+=	-I${S}/external/bsd/drm2/dist/drm/amd/display/modules/inc
CPPFLAGS+=	-I${S}/external/bsd/drm2/dist/drm/amd/display/modules/hdcp
CPPFLAGS+=	-I${S}/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm
CPPFLAGS+=	-I${S}/external/bsd/drm2/dist/drm/amd/display/dmub/inc
CPPFLAGS+=	-DCONFIG_DRM_AMD_ACP=1
CPPFLAGS+=	-DCONFIG_DRM_AMD_DC=1
CPPFLAGS+=	-DCONFIG_DRM_AMD_DC_DCN=1
CPPFLAGS+=	-DCONFIG_DRM_AMD_DC_HDCP=1
CPPFLAGS+=	-DCONFIG_PERF_EVENTS=0
CWARNFLAGS+=	-Wno-missing-field-initializers
CWARNFLAGS+=	-Wno-missing-prototypes
CWARNFLAGS+=	-Wno-shadow
CWARNFLAGS+=	-Wno-pointer-arith
CWARNFLAGS+=	-Wno-override-init

# sed -ne 's,^makeoptions	amdgpu	"\([^"]*\.c\)"+="\(.*\)",\1+=	\2,gp' <files.amdgpu | sed -e 's,\$S,${S},g'
CWARNFLAGS.amdgpu_arct_reg_init.c+=	-Wno-cast-qual
CWARNFLAGS.amdgpu_bo_list.c+=	-Wno-type-limits -Wno-tautological-constant-out-of-range-compare
CWARNFLAGS.amdgpu_cgs.c+=	${CC_WNO_ARRAY_BOUNDS}
CWARNFLAGS.amdgpu_dce_aux.c+=	${CC_WNO_DANGLING_POINTER}
CWARNFLAGS.amdgpu_device.c+=	${CC_WNO_DANGLING_POINTER}
CWARNFLAGS.amdgpu_fiji_smumgr.c+=	-Wno-cast-qual
CWARNFLAGS.amdgpu_hw_ddc.c+=	-Wno-type-limits
CWARNFLAGS.amdgpu_hw_generic.c+=	-Wno-type-limits
CWARNFLAGS.amdgpu_hw_hpd.c+=	-Wno-type-limits
CWARNFLAGS.amdgpu_navi10_ppt.c+=	-Wno-type-limits
CWARNFLAGS.amdgpu_polaris10_smumgr.c+=	-Wno-cast-qual
CWARNFLAGS.amdgpu_process_pptables_v1_0.c+=	-Wno-cast-qual
CWARNFLAGS.amdgpu_rlc.c+=	${CC_WNO_MAYBE_UNINITIALIZED}
CWARNFLAGS.amdgpu_rn_clk_mgr.c+=	-Wno-type-limits
CWARNFLAGS.amdgpu_uvd.c+=	-Wno-format
CWARNFLAGS.amdgpu_vcn.c+=	-Wno-format
CWARNFLAGS.amdgpu_vega10_reg_init.c+=	-Wno-cast-qual
CWARNFLAGS.amdgpu_vega20_reg_init.c+=	-Wno-cast-qual
COPTS.amdgpu_dcn10_resource.c+=	${COPTS.amdgpu_float}
COPTS.amdgpu_dcn20_resource.c+=	${COPTS.amdgpu_float}
COPTS.amdgpu_dcn21_resource.c+=	${COPTS.amdgpu_float}
COPTS.amdgpu_dcn_calc_auto.c+=	${COPTS.amdgpu_float}
COPTS.amdgpu_dcn_calc_math.c+=	${COPTS.amdgpu_float}
COPTS.amdgpu_dcn_calcs.c+=	${COPTS.amdgpu_float}
COPTS.amdgpu_display_mode_vba.c+=	${COPTS.amdgpu_float}
COPTS.amdgpu_display_mode_vba_20.c+=	${COPTS.amdgpu_float}
COPTS.amdgpu_display_mode_vba_20v2.c+=	${COPTS.amdgpu_float}
COPTS.amdgpu_display_mode_vba_21.c+=	${COPTS.amdgpu_float}
COPTS.amdgpu_display_rq_dlg_calc_20.c+=	${COPTS.amdgpu_float}
COPTS.amdgpu_display_rq_dlg_calc_20v2.c+=	${COPTS.amdgpu_float}
COPTS.amdgpu_display_rq_dlg_calc_21.c+=	${COPTS.amdgpu_float}
COPTS.amdgpu_display_rq_dlg_helpers.c+=	${COPTS.amdgpu_float}
COPTS.amdgpu_dml1_display_rq_dlg_calc.c+=	${COPTS.amdgpu_float}
COPTS.amdgpu_dml_common_defs.c+=	${COPTS.amdgpu_float}
COPTS.amdgpu_rc_calc.c+=	${COPTS.amdgpu_float}
COPTS.amdgpu_rc_calc_dpi.c+=	${COPTS.amdgpu_float}
COPTS.amdgpu_rn_clk_mgr.c+=	${COPTS.amdgpu_float}

# sed -ne 's,^file	\(external/bsd/drm2/.*\)/[^/ 	]*	.*,.PATH:	\1,gp' <files.amdgpu | sort -u
.PATH:	${S}/external/bsd/drm2/amdgpu
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../acp
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/amdgpu_dm
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/basics
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/bios
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/bios/dce110
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/bios/dce112
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/bios/dce80
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/calcs
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/clk_mgr
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/clk_mgr/dce100
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/clk_mgr/dce110
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/clk_mgr/dce112
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/clk_mgr/dce120
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/clk_mgr/dcn10
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/clk_mgr/dcn20
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/core
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dce
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dce100
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dce110
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dce112
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dce120
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dce80
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dcn10
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dcn20
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dcn21
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dml
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dml/dcn20
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dml/dcn21
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dsc
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/gpio
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/gpio/dce110
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/gpio/dce120
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/gpio/dce80
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/gpio/dcn10
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/gpio/dcn20
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/gpio/dcn21
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/gpio/diagnostics
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/hdcp
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/irq
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/irq/dce110
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/irq/dce120
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/irq/dce80
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/irq/dcn10
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/irq/dcn20
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/irq/dcn21
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/virtual
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dmub/src
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/modules/color
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/modules/freesync
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/modules/hdcp
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/modules/info_packet
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/modules/power
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../powerplay
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../powerplay/hwmgr
.PATH:	${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../powerplay/smumgr

# sed -ne 's,^file	external/bsd/drm2/.*/\([^/ 	]*\)	.*,SRCS+=	\1,gp' <files.amdgpu | sort -u
SRCS+=	amdgpu_acp.c
SRCS+=	amdgpu_acp_hw.c
SRCS+=	amdgpu_acpi.c
SRCS+=	amdgpu_afmt.c
SRCS+=	amdgpu_amd_powerplay.c
SRCS+=	amdgpu_amdkfd.c
SRCS+=	amdgpu_arct_reg_init.c
SRCS+=	amdgpu_arcturus_ppt.c
SRCS+=	amdgpu_athub_v1_0.c
SRCS+=	amdgpu_athub_v2_0.c
SRCS+=	amdgpu_atom.c
SRCS+=	amdgpu_atombios.c
SRCS+=	amdgpu_atombios_crtc.c
SRCS+=	amdgpu_atombios_dp.c
SRCS+=	amdgpu_atombios_encoders.c
SRCS+=	amdgpu_atombios_i2c.c
SRCS+=	amdgpu_atomfirmware.c
SRCS+=	amdgpu_benchmark.c
SRCS+=	amdgpu_bios.c
SRCS+=	amdgpu_bios_parser.c
SRCS+=	amdgpu_bios_parser2.c
SRCS+=	amdgpu_bios_parser_common.c
SRCS+=	amdgpu_bios_parser_helper.c
SRCS+=	amdgpu_bios_parser_interface.c
SRCS+=	amdgpu_bo_list.c
SRCS+=	amdgpu_bw_fixed.c
SRCS+=	amdgpu_cgs.c
SRCS+=	amdgpu_ci_baco.c
SRCS+=	amdgpu_ci_smumgr.c
SRCS+=	amdgpu_cik.c
SRCS+=	amdgpu_cik_ih.c
SRCS+=	amdgpu_cik_sdma.c
SRCS+=	amdgpu_clk_mgr.c
SRCS+=	amdgpu_color_gamma.c
SRCS+=	amdgpu_command_table.c
SRCS+=	amdgpu_command_table2.c
SRCS+=	amdgpu_command_table_helper.c
SRCS+=	amdgpu_command_table_helper2.c
SRCS+=	amdgpu_command_table_helper2_dce112.c
SRCS+=	amdgpu_command_table_helper_dce110.c
SRCS+=	amdgpu_command_table_helper_dce112.c
SRCS+=	amdgpu_command_table_helper_dce80.c
SRCS+=	amdgpu_common_baco.c
SRCS+=	amdgpu_connectors.c
SRCS+=	amdgpu_conversion.c
SRCS+=	amdgpu_cs.c
SRCS+=	amdgpu_csa.c
SRCS+=	amdgpu_ctx.c
SRCS+=	amdgpu_custom_float.c
SRCS+=	amdgpu_cz_ih.c
SRCS+=	amdgpu_dc.c
SRCS+=	amdgpu_dc_common.c
SRCS+=	amdgpu_dc_debug.c
SRCS+=	amdgpu_dc_dmub_srv.c
SRCS+=	amdgpu_dc_dsc.c
SRCS+=	amdgpu_dc_helper.c
SRCS+=	amdgpu_dc_hw_sequencer.c
SRCS+=	amdgpu_dc_link.c
SRCS+=	amdgpu_dc_link_ddc.c
SRCS+=	amdgpu_dc_link_dp.c
SRCS+=	amdgpu_dc_link_hwss.c
SRCS+=	amdgpu_dc_resource.c
SRCS+=	amdgpu_dc_sink.c
SRCS+=	amdgpu_dc_stream.c
SRCS+=	amdgpu_dc_surface.c
SRCS+=	amdgpu_dc_vm_helper.c
SRCS+=	amdgpu_dce100_hw_sequencer.c
SRCS+=	amdgpu_dce100_resource.c
SRCS+=	amdgpu_dce110_clk_mgr.c
SRCS+=	amdgpu_dce110_compressor.c
SRCS+=	amdgpu_dce110_hw_sequencer.c
SRCS+=	amdgpu_dce110_mem_input_v.c
SRCS+=	amdgpu_dce110_opp_csc_v.c
SRCS+=	amdgpu_dce110_opp_regamma_v.c
SRCS+=	amdgpu_dce110_opp_v.c
SRCS+=	amdgpu_dce110_resource.c
SRCS+=	amdgpu_dce110_timing_generator.c
SRCS+=	amdgpu_dce110_timing_generator_v.c
SRCS+=	amdgpu_dce110_transform_v.c
SRCS+=	amdgpu_dce112_clk_mgr.c
SRCS+=	amdgpu_dce112_compressor.c
SRCS+=	amdgpu_dce112_hw_sequencer.c
SRCS+=	amdgpu_dce112_resource.c
SRCS+=	amdgpu_dce120_clk_mgr.c
SRCS+=	amdgpu_dce120_hw_sequencer.c
SRCS+=	amdgpu_dce120_resource.c
SRCS+=	amdgpu_dce120_timing_generator.c
SRCS+=	amdgpu_dce80_hw_sequencer.c
SRCS+=	amdgpu_dce80_resource.c
SRCS+=	amdgpu_dce80_timing_generator.c
SRCS+=	amdgpu_dce_abm.c
SRCS+=	amdgpu_dce_audio.c
SRCS+=	amdgpu_dce_aux.c
SRCS+=	amdgpu_dce_calcs.c
SRCS+=	amdgpu_dce_clk_mgr.c
SRCS+=	amdgpu_dce_clock_source.c
SRCS+=	amdgpu_dce_dmcu.c
SRCS+=	amdgpu_dce_hwseq.c
SRCS+=	amdgpu_dce_i2c.c
SRCS+=	amdgpu_dce_i2c_hw.c
SRCS+=	amdgpu_dce_i2c_sw.c
SRCS+=	amdgpu_dce_ipp.c
SRCS+=	amdgpu_dce_link_encoder.c
SRCS+=	amdgpu_dce_mem_input.c
SRCS+=	amdgpu_dce_opp.c
SRCS+=	amdgpu_dce_scl_filters.c
SRCS+=	amdgpu_dce_stream_encoder.c
SRCS+=	amdgpu_dce_transform.c
SRCS+=	amdgpu_dce_v10_0.c
SRCS+=	amdgpu_dce_v11_0.c
SRCS+=	amdgpu_dce_v6_0.c
SRCS+=	amdgpu_dce_v8_0.c
SRCS+=	amdgpu_dce_virtual.c
SRCS+=	amdgpu_dcn10_cm_common.c
SRCS+=	amdgpu_dcn10_dpp.c
SRCS+=	amdgpu_dcn10_dpp_cm.c
SRCS+=	amdgpu_dcn10_dpp_dscl.c
SRCS+=	amdgpu_dcn10_hubbub.c
SRCS+=	amdgpu_dcn10_hubp.c
SRCS+=	amdgpu_dcn10_hw_sequencer.c
SRCS+=	amdgpu_dcn10_hw_sequencer_debug.c
SRCS+=	amdgpu_dcn10_init.c
SRCS+=	amdgpu_dcn10_ipp.c
SRCS+=	amdgpu_dcn10_link_encoder.c
SRCS+=	amdgpu_dcn10_mpc.c
SRCS+=	amdgpu_dcn10_opp.c
SRCS+=	amdgpu_dcn10_optc.c
SRCS+=	amdgpu_dcn10_resource.c
SRCS+=	amdgpu_dcn10_stream_encoder.c
SRCS+=	amdgpu_dcn20_clk_mgr.c
SRCS+=	amdgpu_dcn20_dccg.c
SRCS+=	amdgpu_dcn20_dpp.c
SRCS+=	amdgpu_dcn20_dpp_cm.c
SRCS+=	amdgpu_dcn20_dsc.c
SRCS+=	amdgpu_dcn20_dwb.c
SRCS+=	amdgpu_dcn20_dwb_scl.c
SRCS+=	amdgpu_dcn20_hubbub.c
SRCS+=	amdgpu_dcn20_hubp.c
SRCS+=	amdgpu_dcn20_hwseq.c
SRCS+=	amdgpu_dcn20_init.c
SRCS+=	amdgpu_dcn20_link_encoder.c
SRCS+=	amdgpu_dcn20_mmhubbub.c
SRCS+=	amdgpu_dcn20_mpc.c
SRCS+=	amdgpu_dcn20_opp.c
SRCS+=	amdgpu_dcn20_optc.c
SRCS+=	amdgpu_dcn20_resource.c
SRCS+=	amdgpu_dcn20_stream_encoder.c
SRCS+=	amdgpu_dcn20_vmid.c
SRCS+=	amdgpu_dcn21_hubbub.c
SRCS+=	amdgpu_dcn21_hubp.c
SRCS+=	amdgpu_dcn21_hwseq.c
SRCS+=	amdgpu_dcn21_init.c
SRCS+=	amdgpu_dcn21_link_encoder.c
SRCS+=	amdgpu_dcn21_resource.c
SRCS+=	amdgpu_dcn_calc_auto.c
SRCS+=	amdgpu_dcn_calc_math.c
SRCS+=	amdgpu_dcn_calcs.c
SRCS+=	amdgpu_debugfs.c
SRCS+=	amdgpu_device.c
SRCS+=	amdgpu_df_v1_7.c
SRCS+=	amdgpu_df_v3_6.c
SRCS+=	amdgpu_discovery.c
SRCS+=	amdgpu_display.c
SRCS+=	amdgpu_display_mode_lib.c
SRCS+=	amdgpu_display_mode_vba.c
SRCS+=	amdgpu_display_mode_vba_20.c
SRCS+=	amdgpu_display_mode_vba_20v2.c
SRCS+=	amdgpu_display_mode_vba_21.c
SRCS+=	amdgpu_display_rq_dlg_calc_20.c
SRCS+=	amdgpu_display_rq_dlg_calc_20v2.c
SRCS+=	amdgpu_display_rq_dlg_calc_21.c
SRCS+=	amdgpu_display_rq_dlg_helpers.c
SRCS+=	amdgpu_dm.c
SRCS+=	amdgpu_dm_color.c
SRCS+=	amdgpu_dm_hdcp.c
SRCS+=	amdgpu_dm_helpers.c
SRCS+=	amdgpu_dm_irq.c
SRCS+=	amdgpu_dm_mst_types.c
SRCS+=	amdgpu_dm_pp_smu.c
SRCS+=	amdgpu_dm_services.c
SRCS+=	amdgpu_dma_buf.c
SRCS+=	amdgpu_dml1_display_rq_dlg_calc.c
SRCS+=	amdgpu_dml_common_defs.c
SRCS+=	amdgpu_dmub_dcn20.c
SRCS+=	amdgpu_dmub_dcn21.c
SRCS+=	amdgpu_dmub_reg.c
SRCS+=	amdgpu_dmub_srv.c
SRCS+=	amdgpu_dpm.c
SRCS+=	amdgpu_drv.c
SRCS+=	amdgpu_emu_soc.c
SRCS+=	amdgpu_encoders.c
SRCS+=	amdgpu_fb.c
SRCS+=	amdgpu_fence.c
SRCS+=	amdgpu_fiji_baco.c
SRCS+=	amdgpu_fiji_smumgr.c
SRCS+=	amdgpu_fixpt31_32.c
SRCS+=	amdgpu_freesync.c
SRCS+=	amdgpu_gart.c
SRCS+=	amdgpu_gem.c
SRCS+=	amdgpu_gfx.c
SRCS+=	amdgpu_gfx_v10_0.c
SRCS+=	amdgpu_gfx_v6_0.c
SRCS+=	amdgpu_gfx_v7_0.c
SRCS+=	amdgpu_gfx_v8_0.c
SRCS+=	amdgpu_gfx_v9_0.c
SRCS+=	amdgpu_gfx_v9_4.c
SRCS+=	amdgpu_gfxhub_v1_0.c
SRCS+=	amdgpu_gfxhub_v1_1.c
SRCS+=	amdgpu_gfxhub_v2_0.c
SRCS+=	amdgpu_gmc.c
SRCS+=	amdgpu_gmc_v10_0.c
SRCS+=	amdgpu_gmc_v6_0.c
SRCS+=	amdgpu_gmc_v7_0.c
SRCS+=	amdgpu_gmc_v8_0.c
SRCS+=	amdgpu_gmc_v9_0.c
SRCS+=	amdgpu_gpio_base.c
SRCS+=	amdgpu_gpio_service.c
SRCS+=	amdgpu_gtt_mgr.c
SRCS+=	amdgpu_hardwaremanager.c
SRCS+=	amdgpu_hdcp.c
SRCS+=	amdgpu_hdcp1_execution.c
SRCS+=	amdgpu_hdcp1_transition.c
SRCS+=	amdgpu_hdcp2_execution.c
SRCS+=	amdgpu_hdcp2_transition.c
SRCS+=	amdgpu_hdcp_ddc.c
SRCS+=	amdgpu_hdcp_log.c
SRCS+=	amdgpu_hdcp_msg.c
SRCS+=	amdgpu_hdcp_psp.c
SRCS+=	amdgpu_hw_ddc.c
SRCS+=	amdgpu_hw_factory.c
SRCS+=	amdgpu_hw_factory_dce110.c
SRCS+=	amdgpu_hw_factory_dce120.c
SRCS+=	amdgpu_hw_factory_dce80.c
SRCS+=	amdgpu_hw_factory_dcn10.c
SRCS+=	amdgpu_hw_factory_dcn20.c
SRCS+=	amdgpu_hw_factory_dcn21.c
SRCS+=	amdgpu_hw_factory_diag.c
SRCS+=	amdgpu_hw_generic.c
SRCS+=	amdgpu_hw_gpio.c
SRCS+=	amdgpu_hw_hpd.c
SRCS+=	amdgpu_hw_translate.c
SRCS+=	amdgpu_hw_translate_dce110.c
SRCS+=	amdgpu_hw_translate_dce120.c
SRCS+=	amdgpu_hw_translate_dce80.c
SRCS+=	amdgpu_hw_translate_dcn10.c
SRCS+=	amdgpu_hw_translate_dcn20.c
SRCS+=	amdgpu_hw_translate_dcn21.c
SRCS+=	amdgpu_hw_translate_diag.c
SRCS+=	amdgpu_hwmgr.c
SRCS+=	amdgpu_i2c.c
SRCS+=	amdgpu_ib.c
SRCS+=	amdgpu_iceland_ih.c
SRCS+=	amdgpu_iceland_smumgr.c
SRCS+=	amdgpu_ids.c
SRCS+=	amdgpu_ih.c
SRCS+=	amdgpu_info_packet.c
SRCS+=	amdgpu_irq.c
SRCS+=	amdgpu_irq_service.c
SRCS+=	amdgpu_irq_service_dce110.c
SRCS+=	amdgpu_irq_service_dce120.c
SRCS+=	amdgpu_irq_service_dce80.c
SRCS+=	amdgpu_irq_service_dcn10.c
SRCS+=	amdgpu_irq_service_dcn20.c
SRCS+=	amdgpu_irq_service_dcn21.c
SRCS+=	amdgpu_job.c
SRCS+=	amdgpu_jpeg.c
SRCS+=	amdgpu_jpeg_v1_0.c
SRCS+=	amdgpu_jpeg_v2_0.c
SRCS+=	amdgpu_jpeg_v2_5.c
SRCS+=	amdgpu_kms.c
SRCS+=	amdgpu_kv_dpm.c
SRCS+=	amdgpu_kv_smc.c
SRCS+=	amdgpu_log_helpers.c
SRCS+=	amdgpu_mes_v10_1.c
SRCS+=	amdgpu_mmhub.c
SRCS+=	amdgpu_mmhub_v1_0.c
SRCS+=	amdgpu_mmhub_v2_0.c
SRCS+=	amdgpu_mmhub_v9_4.c
SRCS+=	amdgpu_module.c
SRCS+=	amdgpu_mxgpu_ai.c
SRCS+=	amdgpu_mxgpu_nv.c
SRCS+=	amdgpu_mxgpu_vi.c
SRCS+=	amdgpu_navi10_ih.c
SRCS+=	amdgpu_navi10_ppt.c
SRCS+=	amdgpu_navi10_reg_init.c
SRCS+=	amdgpu_navi12_reg_init.c
SRCS+=	amdgpu_navi14_reg_init.c
SRCS+=	amdgpu_nbio.c
SRCS+=	amdgpu_nbio_v2_3.c
SRCS+=	amdgpu_nbio_v6_1.c
SRCS+=	amdgpu_nbio_v7_0.c
SRCS+=	amdgpu_nbio_v7_4.c
SRCS+=	amdgpu_nv.c
SRCS+=	amdgpu_object.c
SRCS+=	amdgpu_pci.c
SRCS+=	amdgpu_pll.c
SRCS+=	amdgpu_pm.c
SRCS+=	amdgpu_polaris10_smumgr.c
SRCS+=	amdgpu_polaris_baco.c
SRCS+=	amdgpu_power_helpers.c
SRCS+=	amdgpu_pp_overdriver.c
SRCS+=	amdgpu_pp_psm.c
SRCS+=	amdgpu_ppatomctrl.c
SRCS+=	amdgpu_ppatomfwctrl.c
SRCS+=	amdgpu_pppcielanes.c
SRCS+=	amdgpu_process_pptables_v1_0.c
SRCS+=	amdgpu_processpptables.c
SRCS+=	amdgpu_psp.c
SRCS+=	amdgpu_psp_v10_0.c
SRCS+=	amdgpu_psp_v11_0.c
SRCS+=	amdgpu_psp_v12_0.c
SRCS+=	amdgpu_psp_v3_1.c
SRCS+=	amdgpu_ras.c
SRCS+=	amdgpu_ras_eeprom.c
SRCS+=	amdgpu_rc_calc.c
SRCS+=	amdgpu_rc_calc_dpi.c
SRCS+=	amdgpu_renoir_ppt.c
SRCS+=	amdgpu_ring.c
SRCS+=	amdgpu_rlc.c
SRCS+=	amdgpu_rn_clk_mgr.c
SRCS+=	amdgpu_rn_clk_mgr_vbios_smu.c
SRCS+=	amdgpu_rv1_clk_mgr.c
SRCS+=	amdgpu_rv1_clk_mgr_vbios_smu.c
SRCS+=	amdgpu_rv2_clk_mgr.c
SRCS+=	amdgpu_sa.c
SRCS+=	amdgpu_sched.c
SRCS+=	amdgpu_sdma.c
SRCS+=	amdgpu_sdma_v2_4.c
SRCS+=	amdgpu_sdma_v3_0.c
SRCS+=	amdgpu_sdma_v4_0.c
SRCS+=	amdgpu_sdma_v5_0.c
SRCS+=	amdgpu_si.c
SRCS+=	amdgpu_si_dma.c
SRCS+=	amdgpu_si_dpm.c
SRCS+=	amdgpu_si_ih.c
SRCS+=	amdgpu_si_smc.c
SRCS+=	amdgpu_smu.c
SRCS+=	amdgpu_smu10_hwmgr.c
SRCS+=	amdgpu_smu10_smumgr.c
SRCS+=	amdgpu_smu7_baco.c
SRCS+=	amdgpu_smu7_clockpowergating.c
SRCS+=	amdgpu_smu7_hwmgr.c
SRCS+=	amdgpu_smu7_powertune.c
SRCS+=	amdgpu_smu7_smumgr.c
SRCS+=	amdgpu_smu7_thermal.c
SRCS+=	amdgpu_smu8_hwmgr.c
SRCS+=	amdgpu_smu8_smumgr.c
SRCS+=	amdgpu_smu9_baco.c
SRCS+=	amdgpu_smu9_smumgr.c
SRCS+=	amdgpu_smu_helper.c
SRCS+=	amdgpu_smu_v11_0.c
SRCS+=	amdgpu_smu_v11_0_i2c.c
SRCS+=	amdgpu_smu_v12_0.c
SRCS+=	amdgpu_smumgr.c
SRCS+=	amdgpu_soc15.c
SRCS+=	amdgpu_sync.c
SRCS+=	amdgpu_test.c
SRCS+=	amdgpu_tonga_baco.c
SRCS+=	amdgpu_tonga_ih.c
SRCS+=	amdgpu_tonga_smumgr.c
SRCS+=	amdgpu_trace_points.c
SRCS+=	amdgpu_ttm.c
SRCS+=	amdgpu_ucode.c
SRCS+=	amdgpu_umc.c
SRCS+=	amdgpu_umc_v6_0.c
SRCS+=	amdgpu_umc_v6_1.c
SRCS+=	amdgpu_uvd.c
SRCS+=	amdgpu_uvd_v4_2.c
SRCS+=	amdgpu_uvd_v5_0.c
SRCS+=	amdgpu_uvd_v6_0.c
SRCS+=	amdgpu_uvd_v7_0.c
SRCS+=	amdgpu_vce.c
SRCS+=	amdgpu_vce_v2_0.c
SRCS+=	amdgpu_vce_v3_0.c
SRCS+=	amdgpu_vce_v4_0.c
SRCS+=	amdgpu_vcn.c
SRCS+=	amdgpu_vcn_v1_0.c
SRCS+=	amdgpu_vcn_v2_0.c
SRCS+=	amdgpu_vcn_v2_5.c
SRCS+=	amdgpu_vector.c
SRCS+=	amdgpu_vega10_baco.c
SRCS+=	amdgpu_vega10_hwmgr.c
SRCS+=	amdgpu_vega10_ih.c
SRCS+=	amdgpu_vega10_powertune.c
SRCS+=	amdgpu_vega10_processpptables.c
SRCS+=	amdgpu_vega10_reg_init.c
SRCS+=	amdgpu_vega10_smumgr.c
SRCS+=	amdgpu_vega10_thermal.c
SRCS+=	amdgpu_vega12_baco.c
SRCS+=	amdgpu_vega12_hwmgr.c
SRCS+=	amdgpu_vega12_processpptables.c
SRCS+=	amdgpu_vega12_smumgr.c
SRCS+=	amdgpu_vega12_thermal.c
SRCS+=	amdgpu_vega20_baco.c
SRCS+=	amdgpu_vega20_hwmgr.c
SRCS+=	amdgpu_vega20_powertune.c
SRCS+=	amdgpu_vega20_ppt.c
SRCS+=	amdgpu_vega20_processpptables.c
SRCS+=	amdgpu_vega20_reg_init.c
SRCS+=	amdgpu_vega20_smumgr.c
SRCS+=	amdgpu_vega20_thermal.c
SRCS+=	amdgpu_vegam_smumgr.c
SRCS+=	amdgpu_vf_error.c
SRCS+=	amdgpu_vi.c
SRCS+=	amdgpu_virt.c
SRCS+=	amdgpu_virtual_link_encoder.c
SRCS+=	amdgpu_virtual_stream_encoder.c
SRCS+=	amdgpu_vm.c
SRCS+=	amdgpu_vm_cpu.c
SRCS+=	amdgpu_vm_sdma.c
SRCS+=	amdgpu_vram_mgr.c
SRCS+=	amdgpu_xgmi.c
SRCS+=	amdgpufb.c

.include <bsd.kmodule.mk>

# XXX
CFLAGS+=	${CWARNFLAGS.${.IMPSRC:T}}