Makefile revision 1.9
1 # $NetBSD: Makefile,v 1.9 2024/04/16 14:34:03 riastradh Exp $ 2 3 .include "../Makefile.inc" 4 .include "../drmkms/Makefile.inc" 5 6 KMOD= amdgpu 7 IOCONF= amdgpu.ioconf 8 MKLDSCRIPT=yes 9 10 WARNS= 3 11 12 .if ${MACHINE_ARCH} == "x86_64" 13 COPTS.amdgpu_float+= ${${ACTIVE_CC} == "gcc" :? -mhard-float :} -msse -msse2 14 .elif !empty(MACHINE_ARCH:Maarch64*) 15 COPTS.amdgpu_float+= -march=armv8-a 16 .endif 17 18 .if ${MACHINE_ARCH} == "i386" || ${MACHINE_ARCH} == "x86_64" || \ 19 ${MACHINE_CPU} == "arm" || ${MACHINE_CPU} == "aarch64" 20 CPPFLAGS+= -DNACPICA=1 21 .endif 22 23 # sed -ne 's,^makeoptions amdgpu "\([^.]*\)\.amdgpu"+="\(.*\)",\1+= \2,gp' <files.amdgpu | sed -e 's,\$S,${S},g' 24 # Note: order of includes is significant. 25 CPPFLAGS+= -I${S}/external/bsd/drm2/dist/drm/amd/include/asic_reg 26 CPPFLAGS+= -I${S}/external/bsd/drm2/dist/drm/amd/include 27 CPPFLAGS+= -I${S}/external/bsd/drm2/dist/drm/amd/amdgpu 28 CPPFLAGS+= -I${S}/external/bsd/drm2/dist/drm/amd/powerplay/inc 29 CPPFLAGS+= -I${S}/external/bsd/drm2/dist/drm/amd/powerplay/smumgr 30 CPPFLAGS+= -I${S}/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr 31 CPPFLAGS+= -I${S}/external/bsd/drm2/dist/drm/amd/acp/include 32 CPPFLAGS+= -I${S}/external/bsd/drm2/dist/drm/amd/display 33 CPPFLAGS+= -I${S}/external/bsd/drm2/dist/drm/amd/display/include 34 CPPFLAGS+= -I${S}/external/bsd/drm2/dist/drm/amd/display/dc 35 CPPFLAGS+= -I${S}/external/bsd/drm2/dist/drm/amd/display/dc/inc 36 CPPFLAGS+= -I${S}/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw 37 CPPFLAGS+= -I${S}/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr 38 CPPFLAGS+= -I${S}/external/bsd/drm2/dist/drm/amd/display/modules/inc 39 CPPFLAGS+= -I${S}/external/bsd/drm2/dist/drm/amd/display/modules/hdcp 40 CPPFLAGS+= -I${S}/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm 41 CPPFLAGS+= -I${S}/external/bsd/drm2/dist/drm/amd/display/dmub/inc 42 CPPFLAGS+= -DCONFIG_DRM_AMD_ACP=1 43 CPPFLAGS+= -DCONFIG_DRM_AMD_DC=1 44 CPPFLAGS+= -DCONFIG_DRM_AMD_DC_DCN=1 45 CPPFLAGS+= -DCONFIG_DRM_AMD_DC_HDCP=1 46 CPPFLAGS+= -DCONFIG_PERF_EVENTS=0 47 CWARNFLAGS+= -Wno-missing-field-initializers 48 CWARNFLAGS+= -Wno-missing-prototypes 49 CWARNFLAGS+= -Wno-shadow 50 CWARNFLAGS+= -Wno-pointer-arith 51 CWARNFLAGS+= -Wno-override-init 52 53 # sed -ne 's,^makeoptions amdgpu "\([^"]*\.c\)"+="\(.*\)",\1+= \2,gp' <files.amdgpu | sed -e 's,\$S,${S},g' 54 CWARNFLAGS.amdgpu_arct_reg_init.c+= -Wno-cast-qual 55 CWARNFLAGS.amdgpu_bo_list.c+= -Wno-type-limits -Wno-tautological-constant-out-of-range-compare 56 CWARNFLAGS.amdgpu_fiji_smumgr.c+= -Wno-cast-qual 57 CWARNFLAGS.amdgpu_hw_ddc.c+= -Wno-type-limits 58 CWARNFLAGS.amdgpu_hw_generic.c+= -Wno-type-limits 59 CWARNFLAGS.amdgpu_hw_hpd.c+= -Wno-type-limits 60 CWARNFLAGS.amdgpu_navi10_ppt.c+= -Wno-type-limits 61 CWARNFLAGS.amdgpu_polaris10_smumgr.c+= -Wno-cast-qual 62 CWARNFLAGS.amdgpu_process_pptables_v1_0.c+= -Wno-cast-qual 63 CWARNFLAGS.amdgpu_rlc.c+= ${CC_WNO_MAYBE_UNINITIALIZED} 64 CWARNFLAGS.amdgpu_rn_clk_mgr.c+= -Wno-type-limits 65 CWARNFLAGS.amdgpu_vega10_reg_init.c+= -Wno-cast-qual 66 CWARNFLAGS.amdgpu_vega20_reg_init.c+= -Wno-cast-qual 67 CWARNFLAGS.amdgpu_uvd.c+= -Wno-format 68 CWARNFLAGS.amdgpu_vcn.c+= -Wno-format 69 COPTS.amdgpu_dcn10_resource.c+= ${COPTS.amdgpu_float} 70 COPTS.amdgpu_dcn20_resource.c+= ${COPTS.amdgpu_float} 71 COPTS.amdgpu_dcn21_resource.c+= ${COPTS.amdgpu_float} 72 COPTS.amdgpu_dcn_calc_auto.c+= ${COPTS.amdgpu_float} 73 COPTS.amdgpu_dcn_calc_math.c+= ${COPTS.amdgpu_float} 74 COPTS.amdgpu_dcn_calcs.c+= ${COPTS.amdgpu_float} 75 COPTS.amdgpu_display_mode_vba.c+= ${COPTS.amdgpu_float} 76 COPTS.amdgpu_display_mode_vba_20.c+= ${COPTS.amdgpu_float} 77 COPTS.amdgpu_display_mode_vba_20v2.c+= ${COPTS.amdgpu_float} 78 COPTS.amdgpu_display_mode_vba_21.c+= ${COPTS.amdgpu_float} 79 COPTS.amdgpu_display_rq_dlg_calc_20.c+= ${COPTS.amdgpu_float} 80 COPTS.amdgpu_display_rq_dlg_calc_20v2.c+= ${COPTS.amdgpu_float} 81 COPTS.amdgpu_display_rq_dlg_calc_21.c+= ${COPTS.amdgpu_float} 82 COPTS.amdgpu_display_rq_dlg_helpers.c+= ${COPTS.amdgpu_float} 83 COPTS.amdgpu_dml1_display_rq_dlg_calc.c+= ${COPTS.amdgpu_float} 84 COPTS.amdgpu_dml_common_defs.c+= ${COPTS.amdgpu_float} 85 COPTS.amdgpu_rc_calc.c+= ${COPTS.amdgpu_float} 86 COPTS.amdgpu_rc_calc_dpi.c+= ${COPTS.amdgpu_float} 87 COPTS.amdgpu_rn_clk_mgr.c+= ${COPTS.amdgpu_float} 88 89 # sed -ne 's,^file \(external/bsd/drm2/.*\)/[^/ ]* .*,.PATH: \1,gp' <files.amdgpu | sort -u 90 .PATH: ${S}/external/bsd/drm2/amdgpu 91 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu 92 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../acp 93 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/amdgpu_dm 94 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc 95 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/basics 96 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/bios 97 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/bios/dce110 98 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/bios/dce112 99 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/bios/dce80 100 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/calcs 101 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/clk_mgr 102 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/clk_mgr/dce100 103 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/clk_mgr/dce110 104 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/clk_mgr/dce112 105 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/clk_mgr/dce120 106 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/clk_mgr/dcn10 107 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/clk_mgr/dcn20 108 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21 109 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/core 110 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dce 111 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dce100 112 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dce110 113 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dce112 114 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dce120 115 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dce80 116 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dcn10 117 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dcn20 118 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dcn21 119 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dml 120 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dml/dcn20 121 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dml/dcn21 122 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/dsc 123 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/gpio 124 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/gpio/dce110 125 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/gpio/dce120 126 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/gpio/dce80 127 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/gpio/dcn10 128 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/gpio/dcn20 129 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/gpio/dcn21 130 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/gpio/diagnostics 131 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/hdcp 132 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/irq 133 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/irq/dce110 134 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/irq/dce120 135 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/irq/dce80 136 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/irq/dcn10 137 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/irq/dcn20 138 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/irq/dcn21 139 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dc/virtual 140 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/dmub/src 141 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/modules/color 142 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/modules/freesync 143 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/modules/hdcp 144 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/modules/info_packet 145 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../display/modules/power 146 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../powerplay 147 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../powerplay/hwmgr 148 .PATH: ${S}/external/bsd/drm2/dist/drm/amd/amdgpu/../powerplay/smumgr 149 150 # sed -ne 's,^file external/bsd/drm2/.*/\([^/ ]*\) .*,SRCS+= \1,gp' <files.amdgpu | sort -u 151 SRCS+= amdgpu_acp.c 152 SRCS+= amdgpu_acp_hw.c 153 SRCS+= amdgpu_acpi.c 154 SRCS+= amdgpu_afmt.c 155 SRCS+= amdgpu_amd_powerplay.c 156 SRCS+= amdgpu_amdkfd.c 157 SRCS+= amdgpu_arct_reg_init.c 158 SRCS+= amdgpu_arcturus_ppt.c 159 SRCS+= amdgpu_athub_v1_0.c 160 SRCS+= amdgpu_athub_v2_0.c 161 SRCS+= amdgpu_atom.c 162 SRCS+= amdgpu_atombios.c 163 SRCS+= amdgpu_atombios_crtc.c 164 SRCS+= amdgpu_atombios_dp.c 165 SRCS+= amdgpu_atombios_encoders.c 166 SRCS+= amdgpu_atombios_i2c.c 167 SRCS+= amdgpu_atomfirmware.c 168 SRCS+= amdgpu_benchmark.c 169 SRCS+= amdgpu_bios.c 170 SRCS+= amdgpu_bios_parser.c 171 SRCS+= amdgpu_bios_parser2.c 172 SRCS+= amdgpu_bios_parser_common.c 173 SRCS+= amdgpu_bios_parser_helper.c 174 SRCS+= amdgpu_bios_parser_interface.c 175 SRCS+= amdgpu_bo_list.c 176 SRCS+= amdgpu_bw_fixed.c 177 SRCS+= amdgpu_cgs.c 178 SRCS+= amdgpu_ci_baco.c 179 SRCS+= amdgpu_ci_smumgr.c 180 SRCS+= amdgpu_cik.c 181 SRCS+= amdgpu_cik_ih.c 182 SRCS+= amdgpu_cik_sdma.c 183 SRCS+= amdgpu_clk_mgr.c 184 SRCS+= amdgpu_color_gamma.c 185 SRCS+= amdgpu_command_table.c 186 SRCS+= amdgpu_command_table2.c 187 SRCS+= amdgpu_command_table_helper.c 188 SRCS+= amdgpu_command_table_helper2.c 189 SRCS+= amdgpu_command_table_helper2_dce112.c 190 SRCS+= amdgpu_command_table_helper_dce110.c 191 SRCS+= amdgpu_command_table_helper_dce112.c 192 SRCS+= amdgpu_command_table_helper_dce80.c 193 SRCS+= amdgpu_common_baco.c 194 SRCS+= amdgpu_connectors.c 195 SRCS+= amdgpu_conversion.c 196 SRCS+= amdgpu_cs.c 197 SRCS+= amdgpu_csa.c 198 SRCS+= amdgpu_ctx.c 199 SRCS+= amdgpu_custom_float.c 200 SRCS+= amdgpu_cz_ih.c 201 SRCS+= amdgpu_dc.c 202 SRCS+= amdgpu_dc_common.c 203 SRCS+= amdgpu_dc_debug.c 204 SRCS+= amdgpu_dc_dmub_srv.c 205 SRCS+= amdgpu_dc_dsc.c 206 SRCS+= amdgpu_dc_helper.c 207 SRCS+= amdgpu_dc_hw_sequencer.c 208 SRCS+= amdgpu_dc_link.c 209 SRCS+= amdgpu_dc_link_ddc.c 210 SRCS+= amdgpu_dc_link_dp.c 211 SRCS+= amdgpu_dc_link_hwss.c 212 SRCS+= amdgpu_dc_resource.c 213 SRCS+= amdgpu_dc_sink.c 214 SRCS+= amdgpu_dc_stream.c 215 SRCS+= amdgpu_dc_surface.c 216 SRCS+= amdgpu_dc_vm_helper.c 217 SRCS+= amdgpu_dce100_hw_sequencer.c 218 SRCS+= amdgpu_dce100_resource.c 219 SRCS+= amdgpu_dce110_clk_mgr.c 220 SRCS+= amdgpu_dce110_compressor.c 221 SRCS+= amdgpu_dce110_hw_sequencer.c 222 SRCS+= amdgpu_dce110_mem_input_v.c 223 SRCS+= amdgpu_dce110_opp_csc_v.c 224 SRCS+= amdgpu_dce110_opp_regamma_v.c 225 SRCS+= amdgpu_dce110_opp_v.c 226 SRCS+= amdgpu_dce110_resource.c 227 SRCS+= amdgpu_dce110_timing_generator.c 228 SRCS+= amdgpu_dce110_timing_generator_v.c 229 SRCS+= amdgpu_dce110_transform_v.c 230 SRCS+= amdgpu_dce112_clk_mgr.c 231 SRCS+= amdgpu_dce112_compressor.c 232 SRCS+= amdgpu_dce112_hw_sequencer.c 233 SRCS+= amdgpu_dce112_resource.c 234 SRCS+= amdgpu_dce120_clk_mgr.c 235 SRCS+= amdgpu_dce120_hw_sequencer.c 236 SRCS+= amdgpu_dce120_resource.c 237 SRCS+= amdgpu_dce120_timing_generator.c 238 SRCS+= amdgpu_dce80_hw_sequencer.c 239 SRCS+= amdgpu_dce80_resource.c 240 SRCS+= amdgpu_dce80_timing_generator.c 241 SRCS+= amdgpu_dce_abm.c 242 SRCS+= amdgpu_dce_audio.c 243 SRCS+= amdgpu_dce_aux.c 244 SRCS+= amdgpu_dce_calcs.c 245 SRCS+= amdgpu_dce_clk_mgr.c 246 SRCS+= amdgpu_dce_clock_source.c 247 SRCS+= amdgpu_dce_dmcu.c 248 SRCS+= amdgpu_dce_hwseq.c 249 SRCS+= amdgpu_dce_i2c.c 250 SRCS+= amdgpu_dce_i2c_hw.c 251 SRCS+= amdgpu_dce_i2c_sw.c 252 SRCS+= amdgpu_dce_ipp.c 253 SRCS+= amdgpu_dce_link_encoder.c 254 SRCS+= amdgpu_dce_mem_input.c 255 SRCS+= amdgpu_dce_opp.c 256 SRCS+= amdgpu_dce_scl_filters.c 257 SRCS+= amdgpu_dce_stream_encoder.c 258 SRCS+= amdgpu_dce_transform.c 259 SRCS+= amdgpu_dce_v10_0.c 260 SRCS+= amdgpu_dce_v11_0.c 261 SRCS+= amdgpu_dce_v6_0.c 262 SRCS+= amdgpu_dce_v8_0.c 263 SRCS+= amdgpu_dce_virtual.c 264 SRCS+= amdgpu_dcn10_cm_common.c 265 SRCS+= amdgpu_dcn10_dpp.c 266 SRCS+= amdgpu_dcn10_dpp_cm.c 267 SRCS+= amdgpu_dcn10_dpp_dscl.c 268 SRCS+= amdgpu_dcn10_hubbub.c 269 SRCS+= amdgpu_dcn10_hubp.c 270 SRCS+= amdgpu_dcn10_hw_sequencer.c 271 SRCS+= amdgpu_dcn10_hw_sequencer_debug.c 272 SRCS+= amdgpu_dcn10_init.c 273 SRCS+= amdgpu_dcn10_ipp.c 274 SRCS+= amdgpu_dcn10_link_encoder.c 275 SRCS+= amdgpu_dcn10_mpc.c 276 SRCS+= amdgpu_dcn10_opp.c 277 SRCS+= amdgpu_dcn10_optc.c 278 SRCS+= amdgpu_dcn10_resource.c 279 SRCS+= amdgpu_dcn10_stream_encoder.c 280 SRCS+= amdgpu_dcn20_clk_mgr.c 281 SRCS+= amdgpu_dcn20_dccg.c 282 SRCS+= amdgpu_dcn20_dpp.c 283 SRCS+= amdgpu_dcn20_dpp_cm.c 284 SRCS+= amdgpu_dcn20_dsc.c 285 SRCS+= amdgpu_dcn20_dwb.c 286 SRCS+= amdgpu_dcn20_dwb_scl.c 287 SRCS+= amdgpu_dcn20_hubbub.c 288 SRCS+= amdgpu_dcn20_hubp.c 289 SRCS+= amdgpu_dcn20_hwseq.c 290 SRCS+= amdgpu_dcn20_init.c 291 SRCS+= amdgpu_dcn20_link_encoder.c 292 SRCS+= amdgpu_dcn20_mmhubbub.c 293 SRCS+= amdgpu_dcn20_mpc.c 294 SRCS+= amdgpu_dcn20_opp.c 295 SRCS+= amdgpu_dcn20_optc.c 296 SRCS+= amdgpu_dcn20_resource.c 297 SRCS+= amdgpu_dcn20_stream_encoder.c 298 SRCS+= amdgpu_dcn20_vmid.c 299 SRCS+= amdgpu_dcn21_hubbub.c 300 SRCS+= amdgpu_dcn21_hubp.c 301 SRCS+= amdgpu_dcn21_hwseq.c 302 SRCS+= amdgpu_dcn21_init.c 303 SRCS+= amdgpu_dcn21_link_encoder.c 304 SRCS+= amdgpu_dcn21_resource.c 305 SRCS+= amdgpu_dcn_calc_auto.c 306 SRCS+= amdgpu_dcn_calc_math.c 307 SRCS+= amdgpu_dcn_calcs.c 308 SRCS+= amdgpu_debugfs.c 309 SRCS+= amdgpu_device.c 310 SRCS+= amdgpu_df_v1_7.c 311 SRCS+= amdgpu_df_v3_6.c 312 SRCS+= amdgpu_discovery.c 313 SRCS+= amdgpu_display.c 314 SRCS+= amdgpu_display_mode_lib.c 315 SRCS+= amdgpu_display_mode_vba.c 316 SRCS+= amdgpu_display_mode_vba_20.c 317 SRCS+= amdgpu_display_mode_vba_20v2.c 318 SRCS+= amdgpu_display_mode_vba_21.c 319 SRCS+= amdgpu_display_rq_dlg_calc_20.c 320 SRCS+= amdgpu_display_rq_dlg_calc_20v2.c 321 SRCS+= amdgpu_display_rq_dlg_calc_21.c 322 SRCS+= amdgpu_display_rq_dlg_helpers.c 323 SRCS+= amdgpu_dm.c 324 SRCS+= amdgpu_dm_color.c 325 SRCS+= amdgpu_dm_hdcp.c 326 SRCS+= amdgpu_dm_helpers.c 327 SRCS+= amdgpu_dm_irq.c 328 SRCS+= amdgpu_dm_mst_types.c 329 SRCS+= amdgpu_dm_pp_smu.c 330 SRCS+= amdgpu_dm_services.c 331 SRCS+= amdgpu_dma_buf.c 332 SRCS+= amdgpu_dml1_display_rq_dlg_calc.c 333 SRCS+= amdgpu_dml_common_defs.c 334 SRCS+= amdgpu_dmub_dcn20.c 335 SRCS+= amdgpu_dmub_dcn21.c 336 SRCS+= amdgpu_dmub_reg.c 337 SRCS+= amdgpu_dmub_srv.c 338 SRCS+= amdgpu_dpm.c 339 SRCS+= amdgpu_drv.c 340 SRCS+= amdgpu_emu_soc.c 341 SRCS+= amdgpu_encoders.c 342 SRCS+= amdgpu_fb.c 343 SRCS+= amdgpu_fence.c 344 SRCS+= amdgpu_fiji_baco.c 345 SRCS+= amdgpu_fiji_smumgr.c 346 SRCS+= amdgpu_fixpt31_32.c 347 SRCS+= amdgpu_freesync.c 348 SRCS+= amdgpu_gart.c 349 SRCS+= amdgpu_gem.c 350 SRCS+= amdgpu_gfx.c 351 SRCS+= amdgpu_gfx_v10_0.c 352 SRCS+= amdgpu_gfx_v6_0.c 353 SRCS+= amdgpu_gfx_v7_0.c 354 SRCS+= amdgpu_gfx_v8_0.c 355 SRCS+= amdgpu_gfx_v9_0.c 356 SRCS+= amdgpu_gfx_v9_4.c 357 SRCS+= amdgpu_gfxhub_v1_0.c 358 SRCS+= amdgpu_gfxhub_v1_1.c 359 SRCS+= amdgpu_gfxhub_v2_0.c 360 SRCS+= amdgpu_gmc.c 361 SRCS+= amdgpu_gmc_v10_0.c 362 SRCS+= amdgpu_gmc_v6_0.c 363 SRCS+= amdgpu_gmc_v7_0.c 364 SRCS+= amdgpu_gmc_v8_0.c 365 SRCS+= amdgpu_gmc_v9_0.c 366 SRCS+= amdgpu_gpio_base.c 367 SRCS+= amdgpu_gpio_service.c 368 SRCS+= amdgpu_gtt_mgr.c 369 SRCS+= amdgpu_hardwaremanager.c 370 SRCS+= amdgpu_hdcp.c 371 SRCS+= amdgpu_hdcp1_execution.c 372 SRCS+= amdgpu_hdcp1_transition.c 373 SRCS+= amdgpu_hdcp2_execution.c 374 SRCS+= amdgpu_hdcp2_transition.c 375 SRCS+= amdgpu_hdcp_ddc.c 376 SRCS+= amdgpu_hdcp_log.c 377 SRCS+= amdgpu_hdcp_msg.c 378 SRCS+= amdgpu_hdcp_psp.c 379 SRCS+= amdgpu_hw_ddc.c 380 SRCS+= amdgpu_hw_factory.c 381 SRCS+= amdgpu_hw_factory_dce110.c 382 SRCS+= amdgpu_hw_factory_dce120.c 383 SRCS+= amdgpu_hw_factory_dce80.c 384 SRCS+= amdgpu_hw_factory_dcn10.c 385 SRCS+= amdgpu_hw_factory_dcn20.c 386 SRCS+= amdgpu_hw_factory_dcn21.c 387 SRCS+= amdgpu_hw_factory_diag.c 388 SRCS+= amdgpu_hw_generic.c 389 SRCS+= amdgpu_hw_gpio.c 390 SRCS+= amdgpu_hw_hpd.c 391 SRCS+= amdgpu_hw_translate.c 392 SRCS+= amdgpu_hw_translate_dce110.c 393 SRCS+= amdgpu_hw_translate_dce120.c 394 SRCS+= amdgpu_hw_translate_dce80.c 395 SRCS+= amdgpu_hw_translate_dcn10.c 396 SRCS+= amdgpu_hw_translate_dcn20.c 397 SRCS+= amdgpu_hw_translate_dcn21.c 398 SRCS+= amdgpu_hw_translate_diag.c 399 SRCS+= amdgpu_hwmgr.c 400 SRCS+= amdgpu_i2c.c 401 SRCS+= amdgpu_ib.c 402 SRCS+= amdgpu_iceland_ih.c 403 SRCS+= amdgpu_iceland_smumgr.c 404 SRCS+= amdgpu_ids.c 405 SRCS+= amdgpu_ih.c 406 SRCS+= amdgpu_info_packet.c 407 SRCS+= amdgpu_irq.c 408 SRCS+= amdgpu_irq_service.c 409 SRCS+= amdgpu_irq_service_dce110.c 410 SRCS+= amdgpu_irq_service_dce120.c 411 SRCS+= amdgpu_irq_service_dce80.c 412 SRCS+= amdgpu_irq_service_dcn10.c 413 SRCS+= amdgpu_irq_service_dcn20.c 414 SRCS+= amdgpu_irq_service_dcn21.c 415 SRCS+= amdgpu_job.c 416 SRCS+= amdgpu_jpeg.c 417 SRCS+= amdgpu_jpeg_v1_0.c 418 SRCS+= amdgpu_jpeg_v2_0.c 419 SRCS+= amdgpu_jpeg_v2_5.c 420 SRCS+= amdgpu_kms.c 421 SRCS+= amdgpu_kv_dpm.c 422 SRCS+= amdgpu_kv_smc.c 423 SRCS+= amdgpu_log_helpers.c 424 SRCS+= amdgpu_mes_v10_1.c 425 SRCS+= amdgpu_mmhub.c 426 SRCS+= amdgpu_mmhub_v1_0.c 427 SRCS+= amdgpu_mmhub_v2_0.c 428 SRCS+= amdgpu_mmhub_v9_4.c 429 SRCS+= amdgpu_module.c 430 SRCS+= amdgpu_mxgpu_ai.c 431 SRCS+= amdgpu_mxgpu_nv.c 432 SRCS+= amdgpu_mxgpu_vi.c 433 SRCS+= amdgpu_navi10_ih.c 434 SRCS+= amdgpu_navi10_ppt.c 435 SRCS+= amdgpu_navi10_reg_init.c 436 SRCS+= amdgpu_navi12_reg_init.c 437 SRCS+= amdgpu_navi14_reg_init.c 438 SRCS+= amdgpu_nbio.c 439 SRCS+= amdgpu_nbio_v2_3.c 440 SRCS+= amdgpu_nbio_v6_1.c 441 SRCS+= amdgpu_nbio_v7_0.c 442 SRCS+= amdgpu_nbio_v7_4.c 443 SRCS+= amdgpu_nv.c 444 SRCS+= amdgpu_object.c 445 SRCS+= amdgpu_pci.c 446 SRCS+= amdgpu_pll.c 447 SRCS+= amdgpu_pm.c 448 SRCS+= amdgpu_polaris10_smumgr.c 449 SRCS+= amdgpu_polaris_baco.c 450 SRCS+= amdgpu_power_helpers.c 451 SRCS+= amdgpu_pp_overdriver.c 452 SRCS+= amdgpu_pp_psm.c 453 SRCS+= amdgpu_ppatomctrl.c 454 SRCS+= amdgpu_ppatomfwctrl.c 455 SRCS+= amdgpu_pppcielanes.c 456 SRCS+= amdgpu_process_pptables_v1_0.c 457 SRCS+= amdgpu_processpptables.c 458 SRCS+= amdgpu_psp.c 459 SRCS+= amdgpu_psp_v10_0.c 460 SRCS+= amdgpu_psp_v11_0.c 461 SRCS+= amdgpu_psp_v12_0.c 462 SRCS+= amdgpu_psp_v3_1.c 463 SRCS+= amdgpu_ras.c 464 SRCS+= amdgpu_ras_eeprom.c 465 SRCS+= amdgpu_rc_calc.c 466 SRCS+= amdgpu_rc_calc_dpi.c 467 SRCS+= amdgpu_renoir_ppt.c 468 SRCS+= amdgpu_ring.c 469 SRCS+= amdgpu_rlc.c 470 SRCS+= amdgpu_rn_clk_mgr.c 471 SRCS+= amdgpu_rn_clk_mgr_vbios_smu.c 472 SRCS+= amdgpu_rv1_clk_mgr.c 473 SRCS+= amdgpu_rv1_clk_mgr_vbios_smu.c 474 SRCS+= amdgpu_rv2_clk_mgr.c 475 SRCS+= amdgpu_sa.c 476 SRCS+= amdgpu_sched.c 477 SRCS+= amdgpu_sdma.c 478 SRCS+= amdgpu_sdma_v2_4.c 479 SRCS+= amdgpu_sdma_v3_0.c 480 SRCS+= amdgpu_sdma_v4_0.c 481 SRCS+= amdgpu_sdma_v5_0.c 482 SRCS+= amdgpu_si.c 483 SRCS+= amdgpu_si_dma.c 484 SRCS+= amdgpu_si_dpm.c 485 SRCS+= amdgpu_si_ih.c 486 SRCS+= amdgpu_si_smc.c 487 SRCS+= amdgpu_smu.c 488 SRCS+= amdgpu_smu10_hwmgr.c 489 SRCS+= amdgpu_smu10_smumgr.c 490 SRCS+= amdgpu_smu7_baco.c 491 SRCS+= amdgpu_smu7_clockpowergating.c 492 SRCS+= amdgpu_smu7_hwmgr.c 493 SRCS+= amdgpu_smu7_powertune.c 494 SRCS+= amdgpu_smu7_smumgr.c 495 SRCS+= amdgpu_smu7_thermal.c 496 SRCS+= amdgpu_smu8_hwmgr.c 497 SRCS+= amdgpu_smu8_smumgr.c 498 SRCS+= amdgpu_smu9_baco.c 499 SRCS+= amdgpu_smu9_smumgr.c 500 SRCS+= amdgpu_smu_helper.c 501 SRCS+= amdgpu_smu_v11_0.c 502 SRCS+= amdgpu_smu_v11_0_i2c.c 503 SRCS+= amdgpu_smu_v12_0.c 504 SRCS+= amdgpu_smumgr.c 505 SRCS+= amdgpu_soc15.c 506 SRCS+= amdgpu_sync.c 507 SRCS+= amdgpu_test.c 508 SRCS+= amdgpu_tonga_baco.c 509 SRCS+= amdgpu_tonga_ih.c 510 SRCS+= amdgpu_tonga_smumgr.c 511 SRCS+= amdgpu_trace_points.c 512 SRCS+= amdgpu_ttm.c 513 SRCS+= amdgpu_ucode.c 514 SRCS+= amdgpu_umc.c 515 SRCS+= amdgpu_umc_v6_0.c 516 SRCS+= amdgpu_umc_v6_1.c 517 SRCS+= amdgpu_uvd.c 518 SRCS+= amdgpu_uvd_v4_2.c 519 SRCS+= amdgpu_uvd_v5_0.c 520 SRCS+= amdgpu_uvd_v6_0.c 521 SRCS+= amdgpu_uvd_v7_0.c 522 SRCS+= amdgpu_vce.c 523 SRCS+= amdgpu_vce_v2_0.c 524 SRCS+= amdgpu_vce_v3_0.c 525 SRCS+= amdgpu_vce_v4_0.c 526 SRCS+= amdgpu_vcn.c 527 SRCS+= amdgpu_vcn_v1_0.c 528 SRCS+= amdgpu_vcn_v2_0.c 529 SRCS+= amdgpu_vcn_v2_5.c 530 SRCS+= amdgpu_vector.c 531 SRCS+= amdgpu_vega10_baco.c 532 SRCS+= amdgpu_vega10_hwmgr.c 533 SRCS+= amdgpu_vega10_ih.c 534 SRCS+= amdgpu_vega10_powertune.c 535 SRCS+= amdgpu_vega10_processpptables.c 536 SRCS+= amdgpu_vega10_reg_init.c 537 SRCS+= amdgpu_vega10_smumgr.c 538 SRCS+= amdgpu_vega10_thermal.c 539 SRCS+= amdgpu_vega12_baco.c 540 SRCS+= amdgpu_vega12_hwmgr.c 541 SRCS+= amdgpu_vega12_processpptables.c 542 SRCS+= amdgpu_vega12_smumgr.c 543 SRCS+= amdgpu_vega12_thermal.c 544 SRCS+= amdgpu_vega20_baco.c 545 SRCS+= amdgpu_vega20_hwmgr.c 546 SRCS+= amdgpu_vega20_powertune.c 547 SRCS+= amdgpu_vega20_ppt.c 548 SRCS+= amdgpu_vega20_processpptables.c 549 SRCS+= amdgpu_vega20_reg_init.c 550 SRCS+= amdgpu_vega20_smumgr.c 551 SRCS+= amdgpu_vega20_thermal.c 552 SRCS+= amdgpu_vegam_smumgr.c 553 SRCS+= amdgpu_vf_error.c 554 SRCS+= amdgpu_vi.c 555 SRCS+= amdgpu_virt.c 556 SRCS+= amdgpu_virtual_link_encoder.c 557 SRCS+= amdgpu_virtual_stream_encoder.c 558 SRCS+= amdgpu_vm.c 559 SRCS+= amdgpu_vm_cpu.c 560 SRCS+= amdgpu_vm_sdma.c 561 SRCS+= amdgpu_vram_mgr.c 562 SRCS+= amdgpu_xgmi.c 563 SRCS+= amdgpufb.c 564 565 .include <bsd.kmodule.mk> 566 567 # XXX 568 CFLAGS+= ${CWARNFLAGS.${.IMPSRC:T}} 569
Indexes created Mon Oct 20 11:09:49 GMT 2025