h_mem_assist_asm.S revision 1.9
1 1.9 maxv /* $NetBSD: h_mem_assist_asm.S,v 1.9 2020/09/05 07:22:26 maxv Exp $ */ 2 1.6 maxv 3 1.1 maxv /* 4 1.9 maxv * Copyright (c) 2018-2020 Maxime Villard, m00nbsd.net 5 1.1 maxv * All rights reserved. 6 1.1 maxv * 7 1.9 maxv * This code is part of the NVMM hypervisor. 8 1.1 maxv * 9 1.1 maxv * Redistribution and use in source and binary forms, with or without 10 1.1 maxv * modification, are permitted provided that the following conditions 11 1.1 maxv * are met: 12 1.1 maxv * 1. Redistributions of source code must retain the above copyright 13 1.1 maxv * notice, this list of conditions and the following disclaimer. 14 1.1 maxv * 2. Redistributions in binary form must reproduce the above copyright 15 1.1 maxv * notice, this list of conditions and the following disclaimer in the 16 1.1 maxv * documentation and/or other materials provided with the distribution. 17 1.1 maxv * 18 1.9 maxv * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 1.9 maxv * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 1.9 maxv * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 1.9 maxv * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 1.9 maxv * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 1.9 maxv * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 1.9 maxv * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 1.9 maxv * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 1.9 maxv * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 1.9 maxv * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 1.9 maxv * SUCH DAMAGE. 29 1.1 maxv */ 30 1.1 maxv 31 1.1 maxv .globl test1_begin, test1_end 32 1.1 maxv .globl test2_begin, test2_end 33 1.1 maxv .globl test3_begin, test3_end 34 1.1 maxv .globl test4_begin, test4_end 35 1.1 maxv .globl test5_begin, test5_end 36 1.1 maxv .globl test6_begin, test6_end 37 1.1 maxv .globl test7_begin, test7_end 38 1.1 maxv .globl test8_begin, test8_end 39 1.2 maxv .globl test9_begin, test9_end 40 1.3 maxv .globl test10_begin, test10_end 41 1.3 maxv .globl test11_begin, test11_end 42 1.5 maxv .globl test12_begin, test12_end 43 1.5 maxv .globl test13_begin, test13_end 44 1.5 maxv .globl test14_begin, test14_end 45 1.8 maxv .globl test_64bit_15_begin, test_64bit_15_end 46 1.8 maxv .globl test_64bit_16_begin, test_64bit_16_end 47 1.1 maxv .text 48 1.1 maxv .code64 49 1.1 maxv 50 1.1 maxv #define TEST_END \ 51 1.1 maxv movq $0xFFFFFFFFFFFFFFFF,%rcx; \ 52 1.1 maxv rdmsr ; 53 1.1 maxv 54 1.1 maxv .align 64 55 1.1 maxv test1_begin: 56 1.1 maxv movq $0x1000,%rax 57 1.1 maxv movq $0x1000,%rbp 58 1.1 maxv 59 1.1 maxv movq $0x1000,(%rax) 60 1.1 maxv 61 1.1 maxv movq $1,%r11 62 1.1 maxv movq $0x2000,(%rax,%r11,8) 63 1.1 maxv 64 1.1 maxv movq (%rbp),%r8 65 1.1 maxv movq 8(%rbp),%rbx 66 1.1 maxv addq %rbx,%r8 67 1.1 maxv movq %r8,(%rbp) 68 1.1 maxv movb $4,(%rbp) 69 1.1 maxv 70 1.1 maxv TEST_END 71 1.1 maxv test1_end: 72 1.1 maxv 73 1.1 maxv .align 64 74 1.1 maxv test2_begin: 75 1.1 maxv movq $0x1000,%rax 76 1.1 maxv 77 1.1 maxv movq $0x1000,(%rax) 78 1.1 maxv movq $0x00FF,%rbx 79 1.1 maxv orb %bl,(%rax) 80 1.1 maxv movq $0x0400,%rcx 81 1.1 maxv orw %cx,(%rax) 82 1.1 maxv 83 1.5 maxv movq $0x0200,%rcx 84 1.5 maxv orq (%rax),%rcx 85 1.5 maxv movq %rcx,(%rax) 86 1.5 maxv 87 1.1 maxv TEST_END 88 1.1 maxv test2_end: 89 1.1 maxv 90 1.1 maxv .align 64 91 1.1 maxv test3_begin: 92 1.1 maxv movq $0x1000,%rax 93 1.1 maxv 94 1.1 maxv movq $0x1FFF,(%rax) 95 1.1 maxv movq $0x1FF0,%rbx 96 1.1 maxv andq %rbx,(%rax) 97 1.1 maxv movq $0x10C1,%rcx 98 1.1 maxv andb %cl,(%rax) 99 1.1 maxv 100 1.1 maxv TEST_END 101 1.1 maxv test3_end: 102 1.1 maxv 103 1.1 maxv .align 64 104 1.1 maxv test4_begin: 105 1.1 maxv movq $0x1000,%rax 106 1.1 maxv 107 1.1 maxv movq $0x1FFF,(%rax) 108 1.1 maxv movq $0x1FF0,%rbx 109 1.1 maxv xorq %rbx,(%rax) 110 1.1 maxv movq $0x10C0,%rcx 111 1.1 maxv xorw %cx,(%rax) 112 1.1 maxv 113 1.1 maxv TEST_END 114 1.1 maxv test4_end: 115 1.1 maxv 116 1.1 maxv .align 64 117 1.1 maxv test5_begin: 118 1.1 maxv movq $0xFFFFFFFF00001000,%rax 119 1.1 maxv 120 1.1 maxv movq $0x1FFF,(%eax) 121 1.1 maxv movb $0,(%eax,%ebx,1) 122 1.1 maxv 123 1.1 maxv TEST_END 124 1.1 maxv test5_end: 125 1.1 maxv 126 1.1 maxv .align 64 127 1.1 maxv test6_begin: 128 1.1 maxv movq $0xFFA0,%rax 129 1.1 maxv movabs %rax,0x1000 130 1.1 maxv 131 1.1 maxv movabs 0x1000,%al 132 1.1 maxv orb $0x0B,%al 133 1.1 maxv movabs %al,0x1000 134 1.1 maxv 135 1.1 maxv TEST_END 136 1.1 maxv test6_end: 137 1.1 maxv 138 1.1 maxv .align 64 139 1.1 maxv test7_begin: 140 1.1 maxv movq $0x56,%rax 141 1.1 maxv 142 1.1 maxv movq $1,%rcx 143 1.1 maxv movq $0x1000,%rdi 144 1.1 maxv rep stosb 145 1.1 maxv 146 1.1 maxv movq $0x1234,%rax 147 1.1 maxv stosw 148 1.1 maxv 149 1.1 maxv TEST_END 150 1.1 maxv test7_end: 151 1.1 maxv 152 1.1 maxv .align 64 153 1.1 maxv test8_begin: 154 1.1 maxv movq $0x1008,%rsi 155 1.1 maxv movq $0x12345678,(%rsi) 156 1.1 maxv 157 1.1 maxv movq $0x1000,%rdi 158 1.1 maxv 159 1.1 maxv lodsw 160 1.1 maxv movw %ax,(%rdi) 161 1.1 maxv addq $2,%rdi 162 1.1 maxv 163 1.1 maxv lodsb 164 1.1 maxv movb %al,(%rdi) 165 1.1 maxv addq $1,%rdi 166 1.1 maxv 167 1.1 maxv lodsb 168 1.1 maxv movb %al,(%rdi) 169 1.1 maxv addq $2,%rdi 170 1.1 maxv 171 1.1 maxv TEST_END 172 1.1 maxv test8_end: 173 1.2 maxv 174 1.2 maxv .align 64 175 1.2 maxv test9_begin: 176 1.2 maxv movq $0x1000,%rax 177 1.2 maxv 178 1.2 maxv movq $0x12345678,8(%rax) 179 1.2 maxv 180 1.2 maxv movq $0x1008,%rsi 181 1.2 maxv movq $0x1000,%rdi 182 1.2 maxv 183 1.2 maxv movq $4,%rcx 184 1.2 maxv rep movsb 185 1.2 maxv 186 1.2 maxv movq $2,%rcx 187 1.2 maxv rep movsw 188 1.2 maxv 189 1.2 maxv TEST_END 190 1.2 maxv test9_end: 191 1.2 maxv 192 1.3 maxv .align 64 193 1.3 maxv test10_begin: 194 1.3 maxv movq $0x1000,%rax 195 1.3 maxv movq $0x12345678,(%rax) 196 1.3 maxv 197 1.3 maxv movq $0xFFFFFFFFFFFFFFFF,%rbx 198 1.4 joerg movzbl (%rax),%ebx 199 1.3 maxv movq %rbx,(%rax) 200 1.3 maxv 201 1.3 maxv TEST_END 202 1.3 maxv test10_end: 203 1.3 maxv 204 1.3 maxv .align 64 205 1.3 maxv test11_begin: 206 1.3 maxv movq $0x1000,%rax 207 1.3 maxv movq $0x12345678,(%rax) 208 1.3 maxv 209 1.3 maxv movq $0xFFFFFFFFFFFFFFFF,%rbx 210 1.4 joerg movzwq (%rax),%rbx 211 1.3 maxv movq %rbx,(%rax) 212 1.3 maxv 213 1.3 maxv TEST_END 214 1.3 maxv test11_end: 215 1.5 maxv 216 1.5 maxv .align 64 217 1.5 maxv test12_begin: 218 1.5 maxv movq $0x1000,%rax 219 1.5 maxv movq $0xFFFFFFFFF2345678,(%rax) 220 1.5 maxv 221 1.5 maxv cmpb $0x78,(%rax) 222 1.5 maxv jne .L12_failure 223 1.5 maxv cmpb $0x77,(%rax) 224 1.5 maxv jl .L12_failure 225 1.5 maxv cmpb $0x79,(%rax) 226 1.5 maxv jg .L12_failure 227 1.5 maxv 228 1.5 maxv cmpw $0x5678,(%rax) 229 1.5 maxv jne .L12_failure 230 1.5 maxv cmpw $0x5677,(%rax) 231 1.5 maxv jl .L12_failure 232 1.5 maxv cmpw $0x5679,(%rax) 233 1.5 maxv jg .L12_failure 234 1.5 maxv 235 1.5 maxv cmpl $0xF2345678,(%rax) 236 1.5 maxv jne .L12_failure 237 1.5 maxv cmpl $0xF2345677,(%rax) 238 1.5 maxv jl .L12_failure 239 1.5 maxv cmpl $0xF2345679,(%rax) 240 1.5 maxv jg .L12_failure 241 1.5 maxv 242 1.5 maxv cmpq $0xFFFFFFFFF2345678,(%rax) 243 1.5 maxv jne .L12_failure 244 1.5 maxv cmpq $0xFFFFFFFFF2345677,(%rax) 245 1.5 maxv jl .L12_failure 246 1.5 maxv cmpq $0xFFFFFFFFF2345679,(%rax) 247 1.5 maxv jg .L12_failure 248 1.5 maxv 249 1.5 maxv .L12_success: 250 1.5 maxv movq $1,(%rax) 251 1.5 maxv TEST_END 252 1.5 maxv .L12_failure: 253 1.5 maxv movq $0,(%rax) 254 1.5 maxv TEST_END 255 1.5 maxv test12_end: 256 1.5 maxv 257 1.5 maxv .align 64 258 1.5 maxv test13_begin: 259 1.5 maxv movq $0x1000,%rax 260 1.5 maxv movq $0x000000001000A0FF,(%rax) 261 1.5 maxv 262 1.5 maxv movq $0xFFFF,%rcx 263 1.5 maxv subb %cl,(%rax) 264 1.5 maxv 265 1.5 maxv movq $0xA000,%rcx 266 1.5 maxv subw %cx,(%rax) 267 1.5 maxv 268 1.5 maxv movq $0x0000000F1000A0FF,%rcx 269 1.5 maxv subq (%rax),%rcx 270 1.5 maxv 271 1.5 maxv movq %rcx,(%rax) 272 1.5 maxv 273 1.5 maxv TEST_END 274 1.5 maxv test13_end: 275 1.5 maxv 276 1.5 maxv .align 64 277 1.5 maxv test14_begin: 278 1.5 maxv movq $0x1000,%rax 279 1.5 maxv movq $0xA0FF,(%rax) 280 1.5 maxv 281 1.5 maxv testb $0x0F,(%rax) 282 1.5 maxv jz .L14_failure 283 1.5 maxv 284 1.5 maxv testw $0x0F00,(%rax) 285 1.5 maxv jnz .L14_failure 286 1.5 maxv 287 1.5 maxv testl $0xA000,(%rax) 288 1.5 maxv jz .L14_failure 289 1.5 maxv 290 1.5 maxv .L14_success: 291 1.5 maxv movq $1,(%rax) 292 1.5 maxv TEST_END 293 1.5 maxv .L14_failure: 294 1.5 maxv movq $0,(%rax) 295 1.5 maxv TEST_END 296 1.5 maxv test14_end: 297 1.7 maxv 298 1.8 maxv .align 64 299 1.8 maxv test_64bit_15_begin: 300 1.8 maxv movq $0x1000,%rax 301 1.8 maxv movq $0x120000,%rbx 302 1.8 maxv movq $0x003400,%rcx 303 1.8 maxv movq $0x000056,%rdx 304 1.8 maxv 305 1.8 maxv xchgq %rbx,(%rax) 306 1.8 maxv xchgw (%rax),%cx 307 1.8 maxv xchgb %dl,(%rax) 308 1.8 maxv 309 1.8 maxv TEST_END 310 1.8 maxv test_64bit_15_end: 311 1.8 maxv 312 1.8 maxv .align 64 313 1.8 maxv test_64bit_16_begin: 314 1.8 maxv movq $0x1000,%rax 315 1.8 maxv movq $0x000000,%rbx 316 1.8 maxv movq $0x000000,%rcx 317 1.8 maxv movq $0x000000,%rdx 318 1.8 maxv 319 1.8 maxv movq $0x123456,(%rax) 320 1.8 maxv xchgq %rbx,(%eax) 321 1.8 maxv movq $0,(%rax) 322 1.8 maxv xchgq %rbx,(%eax) 323 1.8 maxv 324 1.8 maxv TEST_END 325 1.8 maxv test_64bit_16_end: 326 1.8 maxv 327 1.7 maxv /* -------------------------------------------------------------------------- */ 328 1.7 maxv 329 1.7 maxv .globl test_16bit_1_begin, test_16bit_1_end 330 1.7 maxv .globl test_16bit_2_begin, test_16bit_2_end 331 1.7 maxv .globl test_16bit_3_begin, test_16bit_3_end 332 1.7 maxv .globl test_16bit_4_begin, test_16bit_4_end 333 1.7 maxv .globl test_16bit_5_begin, test_16bit_5_end 334 1.8 maxv .globl test_16bit_6_begin, test_16bit_6_end 335 1.7 maxv 336 1.7 maxv #define TEST16_END \ 337 1.7 maxv rdmsr 338 1.7 maxv 339 1.7 maxv .code16 340 1.7 maxv 341 1.7 maxv .align 64 342 1.7 maxv test_16bit_1_begin: 343 1.7 maxv movw $0x10f1,%bx 344 1.7 maxv movw $0x123,%dx 345 1.7 maxv 346 1.7 maxv movb %dl,(%bx) 347 1.7 maxv 348 1.7 maxv TEST16_END 349 1.7 maxv test_16bit_1_end: 350 1.7 maxv 351 1.7 maxv .align 64 352 1.7 maxv test_16bit_2_begin: 353 1.7 maxv movw $0x10f1,%bx 354 1.7 maxv movw $2,%di 355 1.7 maxv movw $0x123,%dx 356 1.7 maxv 357 1.7 maxv movw %dx,(%bx,%di) 358 1.7 maxv 359 1.7 maxv TEST16_END 360 1.7 maxv test_16bit_2_end: 361 1.7 maxv 362 1.7 maxv .align 64 363 1.7 maxv test_16bit_3_begin: 364 1.7 maxv movw $0x10f1,%bp 365 1.7 maxv movw $2,%si 366 1.7 maxv movw $0x678,%dx 367 1.7 maxv 368 1.7 maxv movw %dx,-2(%bp,%si) 369 1.7 maxv 370 1.7 maxv TEST16_END 371 1.7 maxv test_16bit_3_end: 372 1.7 maxv 373 1.7 maxv .align 64 374 1.7 maxv test_16bit_4_begin: 375 1.7 maxv movw $0x10f0,%bp 376 1.7 maxv movw $2,%si 377 1.7 maxv movw $2+4+4,%di 378 1.7 maxv movw $0xFFFF,%dx 379 1.7 maxv movl $0x0001,%eax 380 1.7 maxv movl $0x0010,%ebx 381 1.7 maxv movl $0x1000,%ecx 382 1.7 maxv 383 1.7 maxv movw %dx,4(%bp,%si) /* 16bit opr 16bit adr */ 384 1.7 maxv andl %eax,4(%bp,%si) /* 32bit opr 16bit adr */ 385 1.7 maxv orw %bx,4(%ebp,%esi) /* 16bit opr 32bit adr */ 386 1.7 maxv orl %ecx,-4(%bp,%di) /* 32bit opr 16bit adr, negative */ 387 1.7 maxv 388 1.7 maxv TEST16_END 389 1.7 maxv test_16bit_4_end: 390 1.7 maxv 391 1.7 maxv .align 64 392 1.7 maxv test_16bit_5_begin: 393 1.7 maxv movb $0x12,0x1234 394 1.7 maxv 395 1.7 maxv TEST16_END 396 1.7 maxv test_16bit_5_end: 397 1.8 maxv 398 1.8 maxv .align 64 399 1.8 maxv test_16bit_6_begin: 400 1.8 maxv movw $0x1234,%bp 401 1.8 maxv movw $4,%di 402 1.8 maxv movw $0x1200,%bx 403 1.8 maxv movw $0x0034,%cx 404 1.8 maxv 405 1.8 maxv xchgw %bx,(%bp) 406 1.8 maxv xchgb -4(%bp,%di),%cl 407 1.8 maxv 408 1.8 maxv TEST16_END 409 1.8 maxv test_16bit_6_end: 410
Indexes created Thu Oct 23 22:10:10 GMT 2025