i386.c revision 1.103
1 /* $NetBSD: i386.c,v 1.103 2019/05/29 03:24:23 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.103 2019/05/29 03:24:23 msaitoh Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cacheinfo.h> 85 #include <x86/cpu_ucode.h> 86 87 #include "../cpuctl.h" 88 #include "cpuctl_i386.h" 89 90 /* Size of buffer for printing humanized numbers */ 91 #define HUMAN_BUFSIZE sizeof("999KB") 92 93 struct cpu_info { 94 const char *ci_dev; 95 int32_t ci_cpu_type; /* for cpu's without cpuid */ 96 int32_t ci_cpuid_level; /* highest cpuid supported */ 97 uint32_t ci_cpuid_extlevel; /* highest cpuid extended func lv */ 98 uint32_t ci_signature; /* X86 cpuid type */ 99 uint32_t ci_family; /* from ci_signature */ 100 uint32_t ci_model; /* from ci_signature */ 101 uint32_t ci_feat_val[10]; /* X86 CPUID feature bits 102 * [0] basic features %edx 103 * [1] basic features %ecx 104 * [2] extended features %edx 105 * [3] extended features %ecx 106 * [4] VIA padlock features 107 * [5] structure ext. feat. %ebx 108 * [6] structure ext. feat. %ecx 109 * [7] structure ext. feat. %edx 110 * [8] XCR0 bits (d:0 %eax) 111 * [9] xsave flags (d:1 %eax) 112 */ 113 uint32_t ci_cpu_class; /* CPU class */ 114 uint32_t ci_brand_id; /* Intel brand id */ 115 uint32_t ci_vendor[4]; /* vendor string */ 116 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 117 uint64_t ci_tsc_freq; /* cpu cycles/second */ 118 uint8_t ci_packageid; 119 uint8_t ci_coreid; 120 uint8_t ci_smtid; 121 uint32_t ci_initapicid; 122 uint32_t ci_max_ext_cpuid; 123 124 uint32_t ci_cur_xsave; 125 uint32_t ci_max_xsave; 126 127 struct x86_cache_info ci_cinfo[CAI_COUNT]; 128 void (*ci_info)(struct cpu_info *); 129 }; 130 131 struct cpu_nocpuid_nameclass { 132 int cpu_vendor; 133 const char *cpu_vendorname; 134 const char *cpu_name; 135 int cpu_class; 136 void (*cpu_setup)(struct cpu_info *); 137 void (*cpu_cacheinfo)(struct cpu_info *); 138 void (*cpu_info)(struct cpu_info *); 139 }; 140 141 struct cpu_cpuid_nameclass { 142 const char *cpu_id; 143 int cpu_vendor; 144 const char *cpu_vendorname; 145 struct cpu_cpuid_family { 146 int cpu_class; 147 const char *cpu_models[256]; 148 const char *cpu_model_default; 149 void (*cpu_setup)(struct cpu_info *); 150 void (*cpu_probe)(struct cpu_info *); 151 void (*cpu_info)(struct cpu_info *); 152 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 153 }; 154 155 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 156 157 /* 158 * Map Brand ID from cpuid instruction to brand name. 159 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 160 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 161 * Architectures Software Developer's Manual, Volume 2A". 162 */ 163 static const char * const i386_intel_brand[] = { 164 "", /* Unsupported */ 165 "Celeron", /* Intel (R) Celeron (TM) processor */ 166 "Pentium III", /* Intel (R) Pentium (R) III processor */ 167 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 168 "Pentium III", /* Intel (R) Pentium (R) III processor */ 169 "", /* 0x05: Reserved */ 170 "Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */ 171 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 172 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 173 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 174 "Celeron", /* Intel (R) Celeron (TM) processor */ 175 "Xeon", /* Intel (R) Xeon (TM) processor */ 176 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 177 "", /* 0x0d: Reserved */ 178 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 179 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 180 "", /* 0x10: Reserved */ 181 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 182 "Celeron M", /* Intel (R) Celeron (R) M processor */ 183 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 184 "Celeron", /* Intel (R) Celeron (R) processor */ 185 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 186 "Pentium M", /* Intel (R) Pentium (R) M processor */ 187 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 188 }; 189 190 /* 191 * AMD processors don't have Brand IDs, so we need these names for probe. 192 */ 193 static const char * const amd_brand[] = { 194 "", 195 "Duron", /* AMD Duron(tm) */ 196 "MP", /* AMD Athlon(tm) MP */ 197 "XP", /* AMD Athlon(tm) XP */ 198 "4" /* AMD Athlon(tm) 4 */ 199 }; 200 201 static int cpu_vendor; 202 static char cpu_brand_string[49]; 203 static char amd_brand_name[48]; 204 static int use_pae, largepagesize; 205 206 /* Setup functions */ 207 static void disable_tsc(struct cpu_info *); 208 static void amd_family5_setup(struct cpu_info *); 209 static void cyrix6x86_cpu_setup(struct cpu_info *); 210 static void winchip_cpu_setup(struct cpu_info *); 211 /* Brand/Model name functions */ 212 static const char *intel_family6_name(struct cpu_info *); 213 static const char *amd_amd64_name(struct cpu_info *); 214 /* Probe functions */ 215 static void amd_family6_probe(struct cpu_info *); 216 static void powernow_probe(struct cpu_info *); 217 static void intel_family_new_probe(struct cpu_info *); 218 static void via_cpu_probe(struct cpu_info *); 219 /* (Cache) Info functions */ 220 static void intel_cpu_cacheinfo(struct cpu_info *); 221 static void amd_cpu_cacheinfo(struct cpu_info *); 222 static void via_cpu_cacheinfo(struct cpu_info *); 223 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 224 static void transmeta_cpu_info(struct cpu_info *); 225 /* Common functions */ 226 static void cpu_probe_base_features(struct cpu_info *, const char *); 227 static void cpu_probe_hv_features(struct cpu_info *, const char *); 228 static void cpu_probe_features(struct cpu_info *); 229 static void print_bits(const char *, const char *, const char *, uint32_t); 230 static void identifycpu_cpuids(struct cpu_info *); 231 static const struct x86_cache_info *cache_info_lookup( 232 const struct x86_cache_info *, uint8_t); 233 static const char *print_cache_config(struct cpu_info *, int, const char *, 234 const char *); 235 static const char *print_tlb_config(struct cpu_info *, int, const char *, 236 const char *); 237 static void x86_print_cache_and_tlb_info(struct cpu_info *); 238 239 /* 240 * Note: these are just the ones that may not have a cpuid instruction. 241 * We deal with the rest in a different way. 242 */ 243 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 244 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 245 NULL, NULL, NULL }, /* CPU_386SX */ 246 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 247 NULL, NULL, NULL }, /* CPU_386 */ 248 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 249 NULL, NULL, NULL }, /* CPU_486SX */ 250 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 251 NULL, NULL, NULL }, /* CPU_486 */ 252 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 253 NULL, NULL, NULL }, /* CPU_486DLC */ 254 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 255 NULL, NULL, NULL }, /* CPU_6x86 */ 256 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 257 NULL, NULL, NULL }, /* CPU_NX586 */ 258 }; 259 260 const char *classnames[] = { 261 "386", 262 "486", 263 "586", 264 "686" 265 }; 266 267 const char *modifiers[] = { 268 "", 269 "OverDrive", 270 "Dual", 271 "" 272 }; 273 274 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 275 { 276 /* 277 * For Intel processors, check Chapter 35Model-specific 278 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 279 * Software Developer's Manual, Volume 3C". 280 */ 281 "GenuineIntel", 282 CPUVENDOR_INTEL, 283 "Intel", 284 /* Family 4 */ 285 { { 286 CPUCLASS_486, 287 { 288 "486DX", "486DX", "486SX", "486DX2", "486SL", 289 "486SX2", 0, "486DX2 W/B Enhanced", 290 "486DX4", 0, 0, 0, 0, 0, 0, 0, 291 }, 292 "486", /* Default */ 293 NULL, 294 NULL, 295 intel_cpu_cacheinfo, 296 }, 297 /* Family 5 */ 298 { 299 CPUCLASS_586, 300 { 301 "Pentium (P5 A-step)", "Pentium (P5)", 302 "Pentium (P54C)", "Pentium (P24T)", 303 "Pentium/MMX", "Pentium", 0, 304 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 305 "Quark X1000", 0, 0, 0, 0, 0, 0, 306 }, 307 "Pentium", /* Default */ 308 NULL, 309 NULL, 310 intel_cpu_cacheinfo, 311 }, 312 /* Family 6 */ 313 { 314 CPUCLASS_686, 315 { 316 [0x00] = "Pentium Pro (A-step)", 317 [0x01] = "Pentium Pro", 318 [0x03] = "Pentium II (Klamath)", 319 [0x04] = "Pentium Pro", 320 [0x05] = "Pentium II/Celeron (Deschutes)", 321 [0x06] = "Celeron (Mendocino)", 322 [0x07] = "Pentium III (Katmai)", 323 [0x08] = "Pentium III (Coppermine)", 324 [0x09] = "Pentium M (Banias)", 325 [0x0a] = "Pentium III Xeon (Cascades)", 326 [0x0b] = "Pentium III (Tualatin)", 327 [0x0d] = "Pentium M (Dothan)", 328 [0x0e] = "Pentium Core Duo, Core solo", 329 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 330 "Core 2 Quad 6xxx, " 331 "Core 2 Extreme 6xxx, " 332 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 333 "and Pentium DC", 334 [0x15] = "EP80579 Integrated Processor", 335 [0x16] = "Celeron (45nm)", 336 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 337 "Core 2 Quad 8xxx and 9xxx", 338 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 339 "(Nehalem)", 340 [0x1c] = "45nm Atom Family", 341 [0x1d] = "XeonMP 74xx (Nehalem)", 342 [0x1e] = "Core i7 and i5", 343 [0x1f] = "Core i7 and i5", 344 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 345 [0x26] = "Atom Family", 346 [0x27] = "Atom Family", 347 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 348 "i3 2xxx", 349 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 350 [0x2d] = "Xeon E5 Sandy Bridge family, " 351 "Core i7-39xx Extreme", 352 [0x2e] = "Xeon 75xx & 65xx", 353 [0x2f] = "Xeon E7 family", 354 [0x35] = "Atom Family", 355 [0x36] = "Atom S1000", 356 [0x37] = "Atom E3000, Z3[67]00", 357 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 358 "Ivy Bridge", 359 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 360 "(Haswell)", 361 [0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)", 362 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 363 "Core i7-49xx Extreme", 364 [0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), " 365 "Core i7-59xx Extreme", 366 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 367 "(Haswell)", 368 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 369 "(Haswell)", 370 [0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)", 371 [0x4a] = "Atom Z3400", 372 [0x4c] = "Atom X[57]-Z8000 (Airmont)", 373 [0x4d] = "Atom C2000", 374 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 375 [0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme", 376 [0x55] = "Xeon Scalable (Skylake, Cascade Lake, Copper Lake)", 377 [0x56] = "Xeon D-1500 (Broadwell)", 378 [0x57] = "Xeon Phi [357]200 (Knights Landing)", 379 [0x5a] = "Atom E3500", 380 [0x5c] = "Atom (Goldmont)", 381 [0x5d] = "Atom X3-C3000 (Silvermont)", 382 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 383 [0x5f] = "Atom (Goldmont, Denverton)", 384 [0x66] = "8th gen Core i3 (Cannon Lake)", 385 [0x6a] = "Future Xeon (Ice Lake)", 386 [0x6c] = "Future Xeon (Ice Lake)", 387 [0x7a] = "Atom (Goldmont Plus)", 388 [0x7d] = "Future Core (Ice Lake)", 389 [0x7e] = "Future Core (Ice Lake)", 390 [0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)", 391 [0x86] = "Atom (Tremont)", 392 [0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 393 [0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 394 }, 395 "Pentium Pro, II or III", /* Default */ 396 NULL, 397 intel_family_new_probe, 398 intel_cpu_cacheinfo, 399 }, 400 /* Family > 6 */ 401 { 402 CPUCLASS_686, 403 { 404 0, 0, 0, 0, 0, 0, 0, 0, 405 0, 0, 0, 0, 0, 0, 0, 0, 406 }, 407 "Pentium 4", /* Default */ 408 NULL, 409 intel_family_new_probe, 410 intel_cpu_cacheinfo, 411 } } 412 }, 413 { 414 "AuthenticAMD", 415 CPUVENDOR_AMD, 416 "AMD", 417 /* Family 4 */ 418 { { 419 CPUCLASS_486, 420 { 421 0, 0, 0, "Am486DX2 W/T", 422 0, 0, 0, "Am486DX2 W/B", 423 "Am486DX4 W/T or Am5x86 W/T 150", 424 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 425 0, 0, "Am5x86 W/T 133/160", 426 "Am5x86 W/B 133/160", 427 }, 428 "Am486 or Am5x86", /* Default */ 429 NULL, 430 NULL, 431 NULL, 432 }, 433 /* Family 5 */ 434 { 435 CPUCLASS_586, 436 { 437 "K5", "K5", "K5", "K5", 0, 0, "K6", 438 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 439 "K6-2+/III+", 0, 0, 440 }, 441 "K5 or K6", /* Default */ 442 amd_family5_setup, 443 NULL, 444 amd_cpu_cacheinfo, 445 }, 446 /* Family 6 */ 447 { 448 CPUCLASS_686, 449 { 450 0, "Athlon Model 1", "Athlon Model 2", 451 "Duron", "Athlon Model 4 (Thunderbird)", 452 0, "Athlon", "Duron", "Athlon", 0, 453 "Athlon", 0, 0, 0, 0, 0, 454 }, 455 "K7 (Athlon)", /* Default */ 456 NULL, 457 amd_family6_probe, 458 amd_cpu_cacheinfo, 459 }, 460 /* Family > 6 */ 461 { 462 CPUCLASS_686, 463 { 464 0, 0, 0, 0, 0, 0, 0, 0, 465 0, 0, 0, 0, 0, 0, 0, 0, 466 }, 467 "Unknown K8 (Athlon)", /* Default */ 468 NULL, 469 amd_family6_probe, 470 amd_cpu_cacheinfo, 471 } } 472 }, 473 { 474 "CyrixInstead", 475 CPUVENDOR_CYRIX, 476 "Cyrix", 477 /* Family 4 */ 478 { { 479 CPUCLASS_486, 480 { 481 0, 0, 0, 482 "MediaGX", 483 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 484 }, 485 "486", /* Default */ 486 cyrix6x86_cpu_setup, /* XXX ?? */ 487 NULL, 488 NULL, 489 }, 490 /* Family 5 */ 491 { 492 CPUCLASS_586, 493 { 494 0, 0, "6x86", 0, 495 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 496 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 497 }, 498 "6x86", /* Default */ 499 cyrix6x86_cpu_setup, 500 NULL, 501 NULL, 502 }, 503 /* Family 6 */ 504 { 505 CPUCLASS_686, 506 { 507 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 508 0, 0, 0, 0, 0, 0, 0, 0, 509 }, 510 "6x86MX", /* Default */ 511 cyrix6x86_cpu_setup, 512 NULL, 513 NULL, 514 }, 515 /* Family > 6 */ 516 { 517 CPUCLASS_686, 518 { 519 0, 0, 0, 0, 0, 0, 0, 0, 520 0, 0, 0, 0, 0, 0, 0, 0, 521 }, 522 "Unknown 6x86MX", /* Default */ 523 NULL, 524 NULL, 525 NULL, 526 } } 527 }, 528 { /* MediaGX is now owned by National Semiconductor */ 529 "Geode by NSC", 530 CPUVENDOR_CYRIX, /* XXX */ 531 "National Semiconductor", 532 /* Family 4, NSC never had any of these */ 533 { { 534 CPUCLASS_486, 535 { 536 0, 0, 0, 0, 0, 0, 0, 0, 537 0, 0, 0, 0, 0, 0, 0, 0, 538 }, 539 "486 compatible", /* Default */ 540 NULL, 541 NULL, 542 NULL, 543 }, 544 /* Family 5: Geode family, formerly MediaGX */ 545 { 546 CPUCLASS_586, 547 { 548 0, 0, 0, 0, 549 "Geode GX1", 550 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 551 }, 552 "Geode", /* Default */ 553 cyrix6x86_cpu_setup, 554 NULL, 555 amd_cpu_cacheinfo, 556 }, 557 /* Family 6, not yet available from NSC */ 558 { 559 CPUCLASS_686, 560 { 561 0, 0, 0, 0, 0, 0, 0, 0, 562 0, 0, 0, 0, 0, 0, 0, 0, 563 }, 564 "Pentium Pro compatible", /* Default */ 565 NULL, 566 NULL, 567 NULL, 568 }, 569 /* Family > 6, not yet available from NSC */ 570 { 571 CPUCLASS_686, 572 { 573 0, 0, 0, 0, 0, 0, 0, 0, 574 0, 0, 0, 0, 0, 0, 0, 0, 575 }, 576 "Pentium Pro compatible", /* Default */ 577 NULL, 578 NULL, 579 NULL, 580 } } 581 }, 582 { 583 "CentaurHauls", 584 CPUVENDOR_IDT, 585 "IDT", 586 /* Family 4, IDT never had any of these */ 587 { { 588 CPUCLASS_486, 589 { 590 0, 0, 0, 0, 0, 0, 0, 0, 591 0, 0, 0, 0, 0, 0, 0, 0, 592 }, 593 "486 compatible", /* Default */ 594 NULL, 595 NULL, 596 NULL, 597 }, 598 /* Family 5 */ 599 { 600 CPUCLASS_586, 601 { 602 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 603 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 604 }, 605 "WinChip", /* Default */ 606 winchip_cpu_setup, 607 NULL, 608 NULL, 609 }, 610 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 611 { 612 CPUCLASS_686, 613 { 614 0, 0, 0, 0, 0, 0, "C3 Samuel", 615 "C3 Samuel 2/Ezra", "C3 Ezra-T", 616 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 617 0, "VIA Nano", 618 }, 619 "Unknown VIA/IDT", /* Default */ 620 NULL, 621 via_cpu_probe, 622 via_cpu_cacheinfo, 623 }, 624 /* Family > 6, not yet available from VIA */ 625 { 626 CPUCLASS_686, 627 { 628 0, 0, 0, 0, 0, 0, 0, 0, 629 0, 0, 0, 0, 0, 0, 0, 0, 630 }, 631 "Pentium Pro compatible", /* Default */ 632 NULL, 633 NULL, 634 NULL, 635 } } 636 }, 637 { 638 "GenuineTMx86", 639 CPUVENDOR_TRANSMETA, 640 "Transmeta", 641 /* Family 4, Transmeta never had any of these */ 642 { { 643 CPUCLASS_486, 644 { 645 0, 0, 0, 0, 0, 0, 0, 0, 646 0, 0, 0, 0, 0, 0, 0, 0, 647 }, 648 "486 compatible", /* Default */ 649 NULL, 650 NULL, 651 NULL, 652 }, 653 /* Family 5 */ 654 { 655 CPUCLASS_586, 656 { 657 0, 0, 0, 0, 0, 0, 0, 0, 658 0, 0, 0, 0, 0, 0, 0, 0, 659 }, 660 "Crusoe", /* Default */ 661 NULL, 662 NULL, 663 transmeta_cpu_info, 664 }, 665 /* Family 6, not yet available from Transmeta */ 666 { 667 CPUCLASS_686, 668 { 669 0, 0, 0, 0, 0, 0, 0, 0, 670 0, 0, 0, 0, 0, 0, 0, 0, 671 }, 672 "Pentium Pro compatible", /* Default */ 673 NULL, 674 NULL, 675 NULL, 676 }, 677 /* Family > 6, not yet available from Transmeta */ 678 { 679 CPUCLASS_686, 680 { 681 0, 0, 0, 0, 0, 0, 0, 0, 682 0, 0, 0, 0, 0, 0, 0, 0, 683 }, 684 "Pentium Pro compatible", /* Default */ 685 NULL, 686 NULL, 687 NULL, 688 } } 689 } 690 }; 691 692 /* 693 * disable the TSC such that we don't use the TSC in microtime(9) 694 * because some CPUs got the implementation wrong. 695 */ 696 static void 697 disable_tsc(struct cpu_info *ci) 698 { 699 if (ci->ci_feat_val[0] & CPUID_TSC) { 700 ci->ci_feat_val[0] &= ~CPUID_TSC; 701 aprint_error("WARNING: broken TSC disabled\n"); 702 } 703 } 704 705 static void 706 amd_family5_setup(struct cpu_info *ci) 707 { 708 709 switch (ci->ci_model) { 710 case 0: /* AMD-K5 Model 0 */ 711 /* 712 * According to the AMD Processor Recognition App Note, 713 * the AMD-K5 Model 0 uses the wrong bit to indicate 714 * support for global PTEs, instead using bit 9 (APIC) 715 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 716 */ 717 if (ci->ci_feat_val[0] & CPUID_APIC) 718 ci->ci_feat_val[0] = 719 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 720 /* 721 * XXX But pmap_pg_g is already initialized -- need to kick 722 * XXX the pmap somehow. How does the MP branch do this? 723 */ 724 break; 725 } 726 } 727 728 static void 729 cyrix6x86_cpu_setup(struct cpu_info *ci) 730 { 731 732 /* 733 * Do not disable the TSC on the Geode GX, it's reported to 734 * work fine. 735 */ 736 if (ci->ci_signature != 0x552) 737 disable_tsc(ci); 738 } 739 740 static void 741 winchip_cpu_setup(struct cpu_info *ci) 742 { 743 switch (ci->ci_model) { 744 case 4: /* WinChip C6 */ 745 disable_tsc(ci); 746 } 747 } 748 749 750 static const char * 751 intel_family6_name(struct cpu_info *ci) 752 { 753 const char *ret = NULL; 754 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 755 756 if (ci->ci_model == 5) { 757 switch (l2cache) { 758 case 0: 759 case 128 * 1024: 760 ret = "Celeron (Covington)"; 761 break; 762 case 256 * 1024: 763 ret = "Mobile Pentium II (Dixon)"; 764 break; 765 case 512 * 1024: 766 ret = "Pentium II"; 767 break; 768 case 1 * 1024 * 1024: 769 case 2 * 1024 * 1024: 770 ret = "Pentium II Xeon"; 771 break; 772 } 773 } else if (ci->ci_model == 6) { 774 switch (l2cache) { 775 case 256 * 1024: 776 case 512 * 1024: 777 ret = "Mobile Pentium II"; 778 break; 779 } 780 } else if (ci->ci_model == 7) { 781 switch (l2cache) { 782 case 512 * 1024: 783 ret = "Pentium III"; 784 break; 785 case 1 * 1024 * 1024: 786 case 2 * 1024 * 1024: 787 ret = "Pentium III Xeon"; 788 break; 789 } 790 } else if (ci->ci_model >= 8) { 791 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 792 switch (ci->ci_brand_id) { 793 case 0x3: 794 if (ci->ci_signature == 0x6B1) 795 ret = "Celeron"; 796 break; 797 case 0x8: 798 if (ci->ci_signature >= 0xF13) 799 ret = "genuine processor"; 800 break; 801 case 0xB: 802 if (ci->ci_signature >= 0xF13) 803 ret = "Xeon MP"; 804 break; 805 case 0xE: 806 if (ci->ci_signature < 0xF13) 807 ret = "Xeon"; 808 break; 809 } 810 if (ret == NULL) 811 ret = i386_intel_brand[ci->ci_brand_id]; 812 } 813 } 814 815 return ret; 816 } 817 818 /* 819 * Identify AMD64 CPU names from cpuid. 820 * 821 * Based on: 822 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 823 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 824 * "Revision Guide for AMD NPT Family 0Fh Processors" 825 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 826 * and other miscellaneous reports. 827 * 828 * This is all rather pointless, these are cross 'brand' since the raw 829 * silicon is shared. 830 */ 831 static const char * 832 amd_amd64_name(struct cpu_info *ci) 833 { 834 static char family_str[32]; 835 836 /* Only called if family >= 15 */ 837 838 switch (ci->ci_family) { 839 case 15: 840 switch (ci->ci_model) { 841 case 0x21: /* rev JH-E1/E6 */ 842 case 0x41: /* rev JH-F2 */ 843 return "Dual-Core Opteron"; 844 case 0x23: /* rev JH-E6 (Toledo) */ 845 return "Dual-Core Opteron or Athlon 64 X2"; 846 case 0x43: /* rev JH-F2 (Windsor) */ 847 return "Athlon 64 FX or Athlon 64 X2"; 848 case 0x24: /* rev SH-E5 (Lancaster?) */ 849 return "Mobile Athlon 64 or Turion 64"; 850 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 851 return "Opteron or Athlon 64 FX"; 852 case 0x15: /* rev SH-D0 */ 853 case 0x25: /* rev SH-E4 */ 854 return "Opteron"; 855 case 0x27: /* rev DH-E4, SH-E4 */ 856 return "Athlon 64 or Athlon 64 FX or Opteron"; 857 case 0x48: /* rev BH-F2 */ 858 return "Turion 64 X2"; 859 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 860 case 0x07: /* rev SH-CG (ClawHammer) */ 861 case 0x0b: /* rev CH-CG */ 862 case 0x14: /* rev SH-D0 */ 863 case 0x17: /* rev SH-D0 */ 864 case 0x1b: /* rev CH-D0 */ 865 return "Athlon 64"; 866 case 0x2b: /* rev BH-E4 (Manchester) */ 867 case 0x4b: /* rev BH-F2 (Windsor) */ 868 return "Athlon 64 X2"; 869 case 0x6b: /* rev BH-G1 (Brisbane) */ 870 return "Athlon X2 or Athlon 64 X2"; 871 case 0x08: /* rev CH-CG */ 872 case 0x0c: /* rev DH-CG (Newcastle) */ 873 case 0x0e: /* rev DH-CG (Newcastle?) */ 874 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 875 case 0x18: /* rev CH-D0 */ 876 case 0x1c: /* rev DH-D0 (Winchester) */ 877 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 878 case 0x2c: /* rev DH-E3/E6 */ 879 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 880 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 881 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 882 case 0x6f: /* rev DH-G1 */ 883 return "Athlon 64 or Sempron"; 884 default: 885 break; 886 } 887 return "Unknown AMD64 CPU"; 888 889 #if 0 890 case 16: 891 return "Family 10h"; 892 case 17: 893 return "Family 11h"; 894 case 18: 895 return "Family 12h"; 896 case 19: 897 return "Family 14h"; 898 case 20: 899 return "Family 15h"; 900 #endif 901 902 default: 903 break; 904 } 905 906 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 907 return family_str; 908 } 909 910 static void 911 intel_family_new_probe(struct cpu_info *ci) 912 { 913 uint32_t descs[4]; 914 915 x86_cpuid(0x80000000, descs); 916 917 /* 918 * Determine extended feature flags. 919 */ 920 if (descs[0] >= 0x80000001) { 921 x86_cpuid(0x80000001, descs); 922 ci->ci_feat_val[2] |= descs[3]; 923 ci->ci_feat_val[3] |= descs[2]; 924 } 925 } 926 927 static void 928 via_cpu_probe(struct cpu_info *ci) 929 { 930 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 931 u_int descs[4]; 932 u_int lfunc; 933 934 /* 935 * Determine the largest extended function value. 936 */ 937 x86_cpuid(0x80000000, descs); 938 lfunc = descs[0]; 939 940 /* 941 * Determine the extended feature flags. 942 */ 943 if (lfunc >= 0x80000001) { 944 x86_cpuid(0x80000001, descs); 945 ci->ci_feat_val[2] |= descs[3]; 946 } 947 948 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 949 return; 950 951 /* Nehemiah or Esther */ 952 x86_cpuid(0xc0000000, descs); 953 lfunc = descs[0]; 954 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 955 return; 956 957 x86_cpuid(0xc0000001, descs); 958 lfunc = descs[3]; 959 ci->ci_feat_val[4] = lfunc; 960 } 961 962 static void 963 amd_family6_probe(struct cpu_info *ci) 964 { 965 uint32_t descs[4]; 966 char *p; 967 size_t i; 968 969 x86_cpuid(0x80000000, descs); 970 971 /* 972 * Determine the extended feature flags. 973 */ 974 if (descs[0] >= 0x80000001) { 975 x86_cpuid(0x80000001, descs); 976 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 977 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 978 } 979 980 if (*cpu_brand_string == '\0') 981 return; 982 983 for (i = 1; i < __arraycount(amd_brand); i++) 984 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 985 ci->ci_brand_id = i; 986 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 987 break; 988 } 989 } 990 991 static void 992 intel_cpu_cacheinfo(struct cpu_info *ci) 993 { 994 const struct x86_cache_info *cai; 995 u_int descs[4]; 996 int iterations, i, j; 997 int type, level; 998 int ways, partitions, linesize, sets; 999 int caitype = -1; 1000 int totalsize; 1001 uint8_t desc; 1002 1003 /* Return if the cpu is old pre-cpuid instruction cpu */ 1004 if (ci->ci_cpu_type >= 0) 1005 return; 1006 1007 if (ci->ci_cpuid_level < 2) 1008 return; 1009 1010 /* 1011 * Parse the cache info from `cpuid leaf 2', if we have it. 1012 * XXX This is kinda ugly, but hey, so is the architecture... 1013 */ 1014 x86_cpuid(2, descs); 1015 iterations = descs[0] & 0xff; 1016 while (iterations-- > 0) { 1017 for (i = 0; i < 4; i++) { 1018 if (descs[i] & 0x80000000) 1019 continue; 1020 for (j = 0; j < 4; j++) { 1021 /* 1022 * The least significant byte in EAX 1023 * ((desc[0] >> 0) & 0xff) is always 0x01 and 1024 * it should be ignored. 1025 */ 1026 if (i == 0 && j == 0) 1027 continue; 1028 desc = (descs[i] >> (j * 8)) & 0xff; 1029 if (desc == 0) 1030 continue; 1031 cai = cache_info_lookup(intel_cpuid_cache_info, 1032 desc); 1033 if (cai != NULL) 1034 ci->ci_cinfo[cai->cai_index] = *cai; 1035 else if ((verbose != 0) && (desc != 0xff) 1036 && (desc != 0xfe)) 1037 aprint_error_dev(ci->ci_dev, "error:" 1038 " Unknown cacheinfo desc %02x\n", 1039 desc); 1040 } 1041 } 1042 x86_cpuid(2, descs); 1043 } 1044 1045 if (ci->ci_cpuid_level < 4) 1046 return; 1047 1048 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1049 for (i = 0; ; i++) { 1050 x86_cpuid2(4, i, descs); 1051 type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE); 1052 if (type == CPUID_DCP_CACHETYPE_N) 1053 break; 1054 level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL); 1055 switch (level) { 1056 case 1: 1057 if (type == CPUID_DCP_CACHETYPE_I) 1058 caitype = CAI_ICACHE; 1059 else if (type == CPUID_DCP_CACHETYPE_D) 1060 caitype = CAI_DCACHE; 1061 else 1062 caitype = -1; 1063 break; 1064 case 2: 1065 if (type == CPUID_DCP_CACHETYPE_U) 1066 caitype = CAI_L2CACHE; 1067 else 1068 caitype = -1; 1069 break; 1070 case 3: 1071 if (type == CPUID_DCP_CACHETYPE_U) 1072 caitype = CAI_L3CACHE; 1073 else 1074 caitype = -1; 1075 break; 1076 default: 1077 caitype = -1; 1078 break; 1079 } 1080 if (caitype == -1) { 1081 aprint_error_dev(ci->ci_dev, 1082 "error: unknown cache level&type (%d & %d)\n", 1083 level, type); 1084 continue; 1085 } 1086 ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1; 1087 partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS) 1088 + 1; 1089 linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE) 1090 + 1; 1091 sets = descs[2] + 1; 1092 totalsize = ways * partitions * linesize * sets; 1093 ci->ci_cinfo[caitype].cai_totalsize = totalsize; 1094 ci->ci_cinfo[caitype].cai_associativity = ways; 1095 ci->ci_cinfo[caitype].cai_linesize = linesize; 1096 } 1097 1098 if (ci->ci_cpuid_level < 0x18) 1099 return; 1100 /* Parse the TLB info from `cpuid leaf 18H', if we have it. */ 1101 x86_cpuid(0x18, descs); 1102 iterations = descs[0]; 1103 for (i = 0; i <= iterations; i++) { 1104 uint32_t pgsize; 1105 bool full; 1106 1107 x86_cpuid2(0x18, i, descs); 1108 type = __SHIFTOUT(descs[3], CPUID_DATP_TCTYPE); 1109 if (type == CPUID_DATP_TCTYPE_N) 1110 continue; 1111 level = __SHIFTOUT(descs[3], CPUID_DATP_TCLEVEL); 1112 pgsize = __SHIFTOUT(descs[1], CPUID_DATP_PGSIZE); 1113 switch (level) { 1114 case 1: 1115 if (type == CPUID_DATP_TCTYPE_I) { 1116 switch (pgsize) { 1117 case CPUID_DATP_PGSIZE_4KB: 1118 caitype = CAI_ITLB; 1119 break; 1120 case CPUID_DATP_PGSIZE_2MB 1121 | CPUID_DATP_PGSIZE_4MB: 1122 caitype = CAI_ITLB2; 1123 break; 1124 case CPUID_DATP_PGSIZE_1GB: 1125 caitype = CAI_L1_1GBITLB; 1126 break; 1127 default: 1128 aprint_error_dev(ci->ci_dev, 1129 "error: unknown ITLB size (%d)\n", 1130 pgsize); 1131 caitype = CAI_ITLB; 1132 break; 1133 } 1134 } else if (type == CPUID_DATP_TCTYPE_D) { 1135 switch (pgsize) { 1136 case CPUID_DATP_PGSIZE_4KB: 1137 caitype = CAI_DTLB; 1138 break; 1139 case CPUID_DATP_PGSIZE_2MB 1140 | CPUID_DATP_PGSIZE_4MB: 1141 caitype = CAI_DTLB2; 1142 break; 1143 case CPUID_DATP_PGSIZE_1GB: 1144 caitype = CAI_L1_1GBDTLB; 1145 break; 1146 default: 1147 aprint_error_dev(ci->ci_dev, 1148 "error: unknown DTLB size (%d)\n", 1149 pgsize); 1150 caitype = CAI_DTLB; 1151 break; 1152 } 1153 } else 1154 caitype = -1; 1155 break; 1156 case 2: 1157 if (type == CPUID_DATP_TCTYPE_I) 1158 caitype = CAI_L2_ITLB; 1159 else if (type == CPUID_DATP_TCTYPE_D) 1160 caitype = CAI_L2_DTLB; 1161 else if (type == CPUID_DATP_TCTYPE_U) { 1162 switch (pgsize) { 1163 case CPUID_DATP_PGSIZE_4KB: 1164 caitype = CAI_L2_STLB; 1165 break; 1166 case CPUID_DATP_PGSIZE_4KB 1167 | CPUID_DATP_PGSIZE_2MB: 1168 caitype = CAI_L2_STLB2; 1169 break; 1170 case CPUID_DATP_PGSIZE_2MB 1171 | CPUID_DATP_PGSIZE_4MB: 1172 caitype = CAI_L2_STLB3; 1173 break; 1174 default: 1175 aprint_error_dev(ci->ci_dev, 1176 "error: unknown L2 STLB size (%d)\n", 1177 pgsize); 1178 caitype = CAI_DTLB; 1179 break; 1180 } 1181 } else 1182 caitype = -1; 1183 break; 1184 case 3: 1185 /* XXX need work for L3 TLB */ 1186 caitype = CAI_L3CACHE; 1187 break; 1188 default: 1189 caitype = -1; 1190 break; 1191 } 1192 if (caitype == -1) { 1193 aprint_error_dev(ci->ci_dev, 1194 "error: unknown TLB level&type (%d & %d)\n", 1195 level, type); 1196 continue; 1197 } 1198 switch (pgsize) { 1199 case CPUID_DATP_PGSIZE_4KB: 1200 linesize = 4 * 1024; 1201 break; 1202 case CPUID_DATP_PGSIZE_2MB: 1203 linesize = 2 * 1024 * 1024; 1204 break; 1205 case CPUID_DATP_PGSIZE_4MB: 1206 linesize = 4 * 1024 * 1024; 1207 break; 1208 case CPUID_DATP_PGSIZE_1GB: 1209 linesize = 1024 * 1024 * 1024; 1210 break; 1211 case CPUID_DATP_PGSIZE_2MB | CPUID_DATP_PGSIZE_4MB: 1212 aprint_error_dev(ci->ci_dev, 1213 "WARINING: Currently 2M/4M info can't print correctly\n"); 1214 linesize = 4 * 1024 * 1024; 1215 break; 1216 default: 1217 aprint_error_dev(ci->ci_dev, 1218 "error: Unknown size combination\n"); 1219 linesize = 4 * 1024; 1220 break; 1221 } 1222 ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS); 1223 sets = descs[2]; 1224 full = descs[3] & CPUID_DATP_FULLASSOC; 1225 ci->ci_cinfo[caitype].cai_totalsize 1226 = ways * sets; /* entries */ 1227 ci->ci_cinfo[caitype].cai_associativity 1228 = full ? 0xff : ways; 1229 ci->ci_cinfo[caitype].cai_linesize = linesize; /* pg size */ 1230 } 1231 } 1232 1233 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 1234 AMD_L2CACHE_INFO; 1235 1236 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 1237 AMD_L3CACHE_INFO; 1238 1239 static void 1240 amd_cpu_cacheinfo(struct cpu_info *ci) 1241 { 1242 const struct x86_cache_info *cp; 1243 struct x86_cache_info *cai; 1244 u_int descs[4]; 1245 u_int lfunc; 1246 1247 /* 1248 * K5 model 0 has none of this info. 1249 */ 1250 if (ci->ci_family == 5 && ci->ci_model == 0) 1251 return; 1252 1253 /* 1254 * Determine the largest extended function value. 1255 */ 1256 x86_cpuid(0x80000000, descs); 1257 lfunc = descs[0]; 1258 1259 /* 1260 * Determine L1 cache/TLB info. 1261 */ 1262 if (lfunc < 0x80000005) { 1263 /* No L1 cache info available. */ 1264 return; 1265 } 1266 1267 x86_cpuid(0x80000005, descs); 1268 1269 /* 1270 * K6-III and higher have large page TLBs. 1271 */ 1272 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1273 cai = &ci->ci_cinfo[CAI_ITLB2]; 1274 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1275 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1276 cai->cai_linesize = largepagesize; 1277 1278 cai = &ci->ci_cinfo[CAI_DTLB2]; 1279 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1280 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1281 cai->cai_linesize = largepagesize; 1282 } 1283 1284 cai = &ci->ci_cinfo[CAI_ITLB]; 1285 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1286 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1287 cai->cai_linesize = (4 * 1024); 1288 1289 cai = &ci->ci_cinfo[CAI_DTLB]; 1290 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1291 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1292 cai->cai_linesize = (4 * 1024); 1293 1294 cai = &ci->ci_cinfo[CAI_DCACHE]; 1295 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1296 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1297 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1298 1299 cai = &ci->ci_cinfo[CAI_ICACHE]; 1300 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1301 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1302 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1303 1304 /* 1305 * Determine L2 cache/TLB info. 1306 */ 1307 if (lfunc < 0x80000006) { 1308 /* No L2 cache info available. */ 1309 return; 1310 } 1311 1312 x86_cpuid(0x80000006, descs); 1313 1314 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1315 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1316 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1317 cai->cai_linesize = (4 * 1024); 1318 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1319 cai->cai_associativity); 1320 if (cp != NULL) 1321 cai->cai_associativity = cp->cai_associativity; 1322 else 1323 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1324 1325 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1326 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1327 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1328 cai->cai_linesize = largepagesize; 1329 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1330 cai->cai_associativity); 1331 if (cp != NULL) 1332 cai->cai_associativity = cp->cai_associativity; 1333 else 1334 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1335 1336 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1337 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1338 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1339 cai->cai_linesize = (4 * 1024); 1340 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1341 cai->cai_associativity); 1342 if (cp != NULL) 1343 cai->cai_associativity = cp->cai_associativity; 1344 else 1345 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1346 1347 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1348 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1349 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1350 cai->cai_linesize = largepagesize; 1351 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1352 cai->cai_associativity); 1353 if (cp != NULL) 1354 cai->cai_associativity = cp->cai_associativity; 1355 else 1356 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1357 1358 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1359 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1360 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1361 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1362 1363 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1364 cai->cai_associativity); 1365 if (cp != NULL) 1366 cai->cai_associativity = cp->cai_associativity; 1367 else 1368 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1369 1370 /* 1371 * Determine L3 cache info on AMD Family 10h and newer processors 1372 */ 1373 if (ci->ci_family >= 0x10) { 1374 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1375 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1376 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1377 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1378 1379 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1380 cai->cai_associativity); 1381 if (cp != NULL) 1382 cai->cai_associativity = cp->cai_associativity; 1383 else 1384 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1385 } 1386 1387 /* 1388 * Determine 1GB TLB info. 1389 */ 1390 if (lfunc < 0x80000019) { 1391 /* No 1GB TLB info available. */ 1392 return; 1393 } 1394 1395 x86_cpuid(0x80000019, descs); 1396 1397 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1398 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1399 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1400 cai->cai_linesize = (1024 * 1024 * 1024); 1401 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1402 cai->cai_associativity); 1403 if (cp != NULL) 1404 cai->cai_associativity = cp->cai_associativity; 1405 else 1406 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1407 1408 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1409 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1410 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1411 cai->cai_linesize = (1024 * 1024 * 1024); 1412 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1413 cai->cai_associativity); 1414 if (cp != NULL) 1415 cai->cai_associativity = cp->cai_associativity; 1416 else 1417 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1418 1419 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1420 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1421 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1422 cai->cai_linesize = (1024 * 1024 * 1024); 1423 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1424 cai->cai_associativity); 1425 if (cp != NULL) 1426 cai->cai_associativity = cp->cai_associativity; 1427 else 1428 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1429 1430 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1431 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1432 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1433 cai->cai_linesize = (1024 * 1024 * 1024); 1434 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1435 cai->cai_associativity); 1436 if (cp != NULL) 1437 cai->cai_associativity = cp->cai_associativity; 1438 else 1439 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1440 } 1441 1442 static void 1443 via_cpu_cacheinfo(struct cpu_info *ci) 1444 { 1445 struct x86_cache_info *cai; 1446 int stepping; 1447 u_int descs[4]; 1448 u_int lfunc; 1449 1450 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1451 1452 /* 1453 * Determine the largest extended function value. 1454 */ 1455 x86_cpuid(0x80000000, descs); 1456 lfunc = descs[0]; 1457 1458 /* 1459 * Determine L1 cache/TLB info. 1460 */ 1461 if (lfunc < 0x80000005) { 1462 /* No L1 cache info available. */ 1463 return; 1464 } 1465 1466 x86_cpuid(0x80000005, descs); 1467 1468 cai = &ci->ci_cinfo[CAI_ITLB]; 1469 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1470 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1471 cai->cai_linesize = (4 * 1024); 1472 1473 cai = &ci->ci_cinfo[CAI_DTLB]; 1474 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1475 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1476 cai->cai_linesize = (4 * 1024); 1477 1478 cai = &ci->ci_cinfo[CAI_DCACHE]; 1479 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1480 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1481 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1482 if (ci->ci_model == 9 && stepping == 8) { 1483 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1484 cai->cai_associativity = 2; 1485 } 1486 1487 cai = &ci->ci_cinfo[CAI_ICACHE]; 1488 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1489 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1490 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1491 if (ci->ci_model == 9 && stepping == 8) { 1492 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1493 cai->cai_associativity = 2; 1494 } 1495 1496 /* 1497 * Determine L2 cache/TLB info. 1498 */ 1499 if (lfunc < 0x80000006) { 1500 /* No L2 cache info available. */ 1501 return; 1502 } 1503 1504 x86_cpuid(0x80000006, descs); 1505 1506 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1507 if (ci->ci_model >= 9) { 1508 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1509 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1510 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1511 } else { 1512 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1513 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1514 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1515 } 1516 } 1517 1518 static void 1519 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1520 { 1521 u_int descs[4]; 1522 1523 x86_cpuid(0x80860007, descs); 1524 *frequency = descs[0]; 1525 *voltage = descs[1]; 1526 *percentage = descs[2]; 1527 } 1528 1529 static void 1530 transmeta_cpu_info(struct cpu_info *ci) 1531 { 1532 u_int descs[4], nreg; 1533 u_int frequency, voltage, percentage; 1534 1535 x86_cpuid(0x80860000, descs); 1536 nreg = descs[0]; 1537 if (nreg >= 0x80860001) { 1538 x86_cpuid(0x80860001, descs); 1539 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1540 (descs[1] >> 24) & 0xff, 1541 (descs[1] >> 16) & 0xff, 1542 (descs[1] >> 8) & 0xff, 1543 descs[1] & 0xff); 1544 } 1545 if (nreg >= 0x80860002) { 1546 x86_cpuid(0x80860002, descs); 1547 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1548 (descs[1] >> 24) & 0xff, 1549 (descs[1] >> 16) & 0xff, 1550 (descs[1] >> 8) & 0xff, 1551 descs[1] & 0xff, 1552 descs[2]); 1553 } 1554 if (nreg >= 0x80860006) { 1555 union { 1556 char text[65]; 1557 u_int descs[4][4]; 1558 } info; 1559 int i; 1560 1561 for (i=0; i<4; i++) { 1562 x86_cpuid(0x80860003 + i, info.descs[i]); 1563 } 1564 info.text[64] = '\0'; 1565 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1566 } 1567 1568 if (nreg >= 0x80860007) { 1569 tmx86_get_longrun_status(&frequency, 1570 &voltage, &percentage); 1571 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1572 frequency, voltage, percentage); 1573 } 1574 } 1575 1576 static void 1577 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1578 { 1579 u_int descs[4]; 1580 int i; 1581 uint32_t brand[12]; 1582 1583 memset(ci, 0, sizeof(*ci)); 1584 ci->ci_dev = cpuname; 1585 1586 ci->ci_cpu_type = x86_identify(); 1587 if (ci->ci_cpu_type >= 0) { 1588 /* Old pre-cpuid instruction cpu */ 1589 ci->ci_cpuid_level = -1; 1590 return; 1591 } 1592 1593 /* 1594 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1595 * function. 1596 */ 1597 1598 /* 1599 * Fn0000_0000: 1600 * - Save cpuid max level. 1601 * - Save vendor string. 1602 */ 1603 x86_cpuid(0, descs); 1604 ci->ci_cpuid_level = descs[0]; 1605 /* Save vendor string */ 1606 ci->ci_vendor[0] = descs[1]; 1607 ci->ci_vendor[2] = descs[2]; 1608 ci->ci_vendor[1] = descs[3]; 1609 ci->ci_vendor[3] = 0; 1610 1611 /* 1612 * Fn8000_0000: 1613 * - Get cpuid extended function's max level. 1614 */ 1615 x86_cpuid(0x80000000, descs); 1616 if (descs[0] >= 0x80000000) 1617 ci->ci_cpuid_extlevel = descs[0]; 1618 else { 1619 /* Set lower value than 0x80000000 */ 1620 ci->ci_cpuid_extlevel = 0; 1621 } 1622 1623 /* 1624 * Fn8000_000[2-4]: 1625 * - Save brand string. 1626 */ 1627 if (ci->ci_cpuid_extlevel >= 0x80000004) { 1628 x86_cpuid(0x80000002, brand); 1629 x86_cpuid(0x80000003, brand + 4); 1630 x86_cpuid(0x80000004, brand + 8); 1631 for (i = 0; i < 48; i++) 1632 if (((char *) brand)[i] != ' ') 1633 break; 1634 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1635 } 1636 1637 if (ci->ci_cpuid_level < 1) 1638 return; 1639 1640 /* 1641 * Fn0000_0001: 1642 * - Get CPU family, model and stepping (from eax). 1643 * - Initial local APIC ID and brand ID (from ebx) 1644 * - CPUID2 (from ecx) 1645 * - CPUID (from edx) 1646 */ 1647 x86_cpuid(1, descs); 1648 ci->ci_signature = descs[0]; 1649 1650 /* Extract full family/model values */ 1651 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1652 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1653 1654 /* Brand is low order 8 bits of ebx */ 1655 ci->ci_brand_id = __SHIFTOUT(descs[1], CPUID_BRAND_INDEX); 1656 /* Initial local APIC ID */ 1657 ci->ci_initapicid = __SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID); 1658 1659 ci->ci_feat_val[1] = descs[2]; 1660 ci->ci_feat_val[0] = descs[3]; 1661 1662 if (ci->ci_cpuid_level < 3) 1663 return; 1664 1665 /* 1666 * If the processor serial number misfeature is present and supported, 1667 * extract it here. 1668 */ 1669 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1670 ci->ci_cpu_serial[0] = ci->ci_signature; 1671 x86_cpuid(3, descs); 1672 ci->ci_cpu_serial[2] = descs[2]; 1673 ci->ci_cpu_serial[1] = descs[3]; 1674 } 1675 1676 if (ci->ci_cpuid_level < 0x7) 1677 return; 1678 1679 x86_cpuid(7, descs); 1680 ci->ci_feat_val[5] = descs[1]; 1681 ci->ci_feat_val[6] = descs[2]; 1682 ci->ci_feat_val[7] = descs[3]; 1683 1684 if (ci->ci_cpuid_level < 0xd) 1685 return; 1686 1687 /* Get support XCR0 bits */ 1688 x86_cpuid2(0xd, 0, descs); 1689 ci->ci_feat_val[8] = descs[0]; /* Actually 64 bits */ 1690 ci->ci_cur_xsave = descs[1]; 1691 ci->ci_max_xsave = descs[2]; 1692 1693 /* Additional flags (eg xsaveopt support) */ 1694 x86_cpuid2(0xd, 1, descs); 1695 ci->ci_feat_val[9] = descs[0]; /* Actually 64 bits */ 1696 } 1697 1698 static void 1699 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1700 { 1701 uint32_t descs[4]; 1702 char hv_sig[13]; 1703 char *p; 1704 const char *hv_name; 1705 int i; 1706 1707 /* 1708 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1709 * http://lkml.org/lkml/2008/10/1/246 1710 * 1711 * KB1009458: Mechanisms to determine if software is running in 1712 * a VMware virtual machine 1713 * http://kb.vmware.com/kb/1009458 1714 */ 1715 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1716 x86_cpuid(0x40000000, descs); 1717 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1718 memcpy(p, &descs[i], sizeof(descs[i])); 1719 *p = '\0'; 1720 /* 1721 * HV vendor ID string 1722 * ------------+-------------- 1723 * HAXM "HAXMHAXMHAXM" 1724 * KVM "KVMKVMKVM" 1725 * Microsoft "Microsoft Hv" 1726 * QEMU(TCG) "TCGTCGTCGTCG" 1727 * VMware "VMwareVMware" 1728 * Xen "XenVMMXenVMM" 1729 * NetBSD "___ NVMM ___" 1730 */ 1731 if (strncmp(hv_sig, "HAXMHAXMHAXM", 12) == 0) 1732 hv_name = "HAXM"; 1733 else if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1734 hv_name = "KVM"; 1735 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1736 hv_name = "Hyper-V"; 1737 else if (strncmp(hv_sig, "TCGTCGTCGTCG", 12) == 0) 1738 hv_name = "QEMU(TCG)"; 1739 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1740 hv_name = "VMware"; 1741 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1742 hv_name = "Xen"; 1743 else if (strncmp(hv_sig, "___ NVMM ___", 12) == 0) 1744 hv_name = "NVMM"; 1745 else 1746 hv_name = "unknown"; 1747 1748 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1749 } 1750 } 1751 1752 static void 1753 cpu_probe_features(struct cpu_info *ci) 1754 { 1755 const struct cpu_cpuid_nameclass *cpup = NULL; 1756 unsigned int i; 1757 1758 if (ci->ci_cpuid_level < 1) 1759 return; 1760 1761 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1762 if (!strncmp((char *)ci->ci_vendor, 1763 i386_cpuid_cpus[i].cpu_id, 12)) { 1764 cpup = &i386_cpuid_cpus[i]; 1765 break; 1766 } 1767 } 1768 1769 if (cpup == NULL) 1770 return; 1771 1772 i = ci->ci_family - CPU_MINFAMILY; 1773 1774 if (i >= __arraycount(cpup->cpu_family)) 1775 i = __arraycount(cpup->cpu_family) - 1; 1776 1777 if (cpup->cpu_family[i].cpu_probe == NULL) 1778 return; 1779 1780 (*cpup->cpu_family[i].cpu_probe)(ci); 1781 } 1782 1783 static void 1784 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1785 { 1786 char buf[32 * 16]; 1787 char *bp; 1788 1789 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1790 1791 if (val == 0 || fmt == NULL) 1792 return; 1793 1794 snprintb_m(buf, sizeof(buf), fmt, val, 1795 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1796 bp = buf; 1797 while (*bp != '\0') { 1798 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1799 bp += strlen(bp) + 1; 1800 } 1801 } 1802 1803 static void 1804 dump_descs(uint32_t leafstart, uint32_t leafend, const char *cpuname, 1805 const char *blockname) 1806 { 1807 uint32_t descs[4]; 1808 uint32_t leaf; 1809 1810 aprint_verbose("%s: highest %s info %08x\n", cpuname, blockname, 1811 leafend); 1812 1813 if (verbose) { 1814 for (leaf = leafstart; leaf <= leafend; leaf++) { 1815 x86_cpuid(leaf, descs); 1816 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1817 leaf, descs[0], descs[1], descs[2], descs[3]); 1818 } 1819 } 1820 } 1821 1822 static void 1823 identifycpu_cpuids_intel_0x04(struct cpu_info *ci) 1824 { 1825 u_int lp_max = 1; /* logical processors per package */ 1826 u_int smt_max; /* smt per core */ 1827 u_int core_max = 1; /* core per package */ 1828 u_int smt_bits, core_bits; 1829 uint32_t descs[4]; 1830 1831 /* 1832 * 253668.pdf 7.10.2 1833 */ 1834 1835 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1836 x86_cpuid(1, descs); 1837 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1838 } 1839 x86_cpuid2(4, 0, descs); 1840 core_max = __SHIFTOUT(descs[0], CPUID_DCP_CORE_P_PKG) + 1; 1841 1842 assert(lp_max >= core_max); 1843 smt_max = lp_max / core_max; 1844 smt_bits = ilog2(smt_max - 1) + 1; 1845 core_bits = ilog2(core_max - 1) + 1; 1846 1847 if (smt_bits + core_bits) 1848 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1849 1850 if (core_bits) 1851 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1852 __BITS(smt_bits, smt_bits + core_bits - 1)); 1853 1854 if (smt_bits) 1855 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1856 __BITS((int)0, (int)(smt_bits - 1))); 1857 } 1858 1859 static void 1860 identifycpu_cpuids_intel_0x0b(struct cpu_info *ci) 1861 { 1862 const char *cpuname = ci->ci_dev; 1863 u_int smt_bits, core_bits, core_shift = 0, pkg_shift = 0; 1864 uint32_t descs[4]; 1865 int i; 1866 1867 x86_cpuid(0x0b, descs); 1868 if (descs[1] == 0) { 1869 identifycpu_cpuids_intel_0x04(ci); 1870 return; 1871 } 1872 1873 for (i = 0; ; i++) { 1874 unsigned int shiftnum, lvltype; 1875 x86_cpuid2(0x0b, i, descs); 1876 1877 /* On invalid level, (EAX and) EBX return 0 */ 1878 if (descs[1] == 0) 1879 break; 1880 1881 shiftnum = __SHIFTOUT(descs[0], CPUID_TOP_SHIFTNUM); 1882 lvltype = __SHIFTOUT(descs[2], CPUID_TOP_LVLTYPE); 1883 switch (lvltype) { 1884 case CPUID_TOP_LVLTYPE_SMT: 1885 core_shift = shiftnum; 1886 break; 1887 case CPUID_TOP_LVLTYPE_CORE: 1888 pkg_shift = shiftnum; 1889 break; 1890 case CPUID_TOP_LVLTYPE_INVAL: 1891 aprint_verbose("%s: Invalid level type\n", cpuname); 1892 break; 1893 default: 1894 aprint_verbose("%s: Unknown level type(%d) \n", 1895 cpuname, lvltype); 1896 break; 1897 } 1898 } 1899 1900 assert(pkg_shift >= core_shift); 1901 smt_bits = core_shift; 1902 core_bits = pkg_shift - core_shift; 1903 1904 ci->ci_packageid = ci->ci_initapicid >> pkg_shift; 1905 1906 if (core_bits) 1907 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1908 __BITS(core_shift, pkg_shift - 1)); 1909 1910 if (smt_bits) 1911 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1912 __BITS((int)0, core_shift - 1)); 1913 } 1914 1915 static void 1916 identifycpu_cpuids_intel(struct cpu_info *ci) 1917 { 1918 const char *cpuname = ci->ci_dev; 1919 1920 if (ci->ci_cpuid_level >= 0x0b) 1921 identifycpu_cpuids_intel_0x0b(ci); 1922 else if (ci->ci_cpuid_level >= 4) 1923 identifycpu_cpuids_intel_0x04(ci); 1924 1925 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1926 ci->ci_packageid); 1927 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1928 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1929 } 1930 1931 static void 1932 identifycpu_cpuids_amd(struct cpu_info *ci) 1933 { 1934 const char *cpuname = ci->ci_dev; 1935 u_int lp_max, core_max; 1936 int n, cpu_family, apic_id, smt_bits, core_bits = 0; 1937 uint32_t descs[4]; 1938 1939 apic_id = ci->ci_initapicid; 1940 cpu_family = CPUID_TO_FAMILY(ci->ci_signature); 1941 1942 if (cpu_family < 0xf) 1943 return; 1944 1945 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1946 x86_cpuid(1, descs); 1947 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1948 1949 if (cpu_family >= 0x10 && ci->ci_max_ext_cpuid >= 0x8000008) { 1950 x86_cpuid(0x8000008, descs); 1951 core_max = (descs[2] & 0xff) + 1; 1952 n = (descs[2] >> 12) & 0x0f; 1953 if (n != 0) 1954 core_bits = n; 1955 } 1956 } else { 1957 lp_max = 1; 1958 } 1959 core_max = lp_max; 1960 1961 smt_bits = ilog2((lp_max / core_max) - 1) + 1; 1962 if (core_bits == 0) 1963 core_bits = ilog2(core_max - 1) + 1; 1964 1965 #if 0 /* MSRs need kernel mode */ 1966 if (cpu_family < 0x11) { 1967 const uint64_t reg = rdmsr(MSR_NB_CFG); 1968 if ((reg & NB_CFG_INITAPICCPUIDLO) == 0) { 1969 const u_int node_id = apic_id & __BITS(0, 2); 1970 apic_id = (cpu_family == 0xf) ? 1971 (apic_id >> core_bits) | (node_id << core_bits) : 1972 (apic_id >> 5) | (node_id << 2); 1973 } 1974 } 1975 #endif 1976 1977 if (cpu_family == 0x17) { 1978 x86_cpuid(0x8000001e, descs); 1979 const u_int threads = ((descs[1] >> 8) & 0xff) + 1; 1980 smt_bits = ilog2(threads); 1981 core_bits -= smt_bits; 1982 } 1983 1984 if (smt_bits + core_bits) { 1985 if (smt_bits + core_bits < 32) 1986 ci->ci_packageid = 0; 1987 } 1988 if (core_bits) { 1989 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1990 ci->ci_coreid = __SHIFTOUT(apic_id, core_mask); 1991 } 1992 if (smt_bits) { 1993 u_int smt_mask = __BITS(0, smt_bits - 1); 1994 ci->ci_smtid = __SHIFTOUT(apic_id, smt_mask); 1995 } 1996 1997 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1998 ci->ci_packageid); 1999 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 2000 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 2001 } 2002 2003 static void 2004 identifycpu_cpuids(struct cpu_info *ci) 2005 { 2006 const char *cpuname = ci->ci_dev; 2007 2008 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 2009 ci->ci_packageid = ci->ci_initapicid; 2010 ci->ci_coreid = 0; 2011 ci->ci_smtid = 0; 2012 2013 if (cpu_vendor == CPUVENDOR_INTEL) 2014 identifycpu_cpuids_intel(ci); 2015 else if (cpu_vendor == CPUVENDOR_AMD) 2016 identifycpu_cpuids_amd(ci); 2017 } 2018 2019 void 2020 identifycpu(int fd, const char *cpuname) 2021 { 2022 const char *name = "", *modifier, *vendorname, *brand = ""; 2023 int class = CPUCLASS_386; 2024 unsigned int i; 2025 int modif, family; 2026 const struct cpu_cpuid_nameclass *cpup = NULL; 2027 const struct cpu_cpuid_family *cpufam; 2028 struct cpu_info *ci, cistore; 2029 u_int descs[4]; 2030 size_t sz; 2031 struct cpu_ucode_version ucode; 2032 union { 2033 struct cpu_ucode_version_amd amd; 2034 struct cpu_ucode_version_intel1 intel1; 2035 } ucvers; 2036 2037 ci = &cistore; 2038 cpu_probe_base_features(ci, cpuname); 2039 dump_descs(0x00000000, ci->ci_cpuid_level, cpuname, "basic"); 2040 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 2041 x86_cpuid(0x40000000, descs); 2042 dump_descs(0x40000000, descs[0], cpuname, "hypervisor"); 2043 } 2044 dump_descs(0x80000000, ci->ci_cpuid_extlevel, cpuname, "extended"); 2045 2046 cpu_probe_hv_features(ci, cpuname); 2047 cpu_probe_features(ci); 2048 2049 if (ci->ci_cpu_type >= 0) { 2050 /* Old pre-cpuid instruction cpu */ 2051 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 2052 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 2053 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 2054 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 2055 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 2056 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 2057 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 2058 modifier = ""; 2059 } else { 2060 /* CPU which support cpuid instruction */ 2061 modif = (ci->ci_signature >> 12) & 0x3; 2062 family = ci->ci_family; 2063 if (family < CPU_MINFAMILY) 2064 errx(1, "identifycpu: strange family value"); 2065 if (family > CPU_MAXFAMILY) 2066 family = CPU_MAXFAMILY; 2067 2068 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 2069 if (!strncmp((char *)ci->ci_vendor, 2070 i386_cpuid_cpus[i].cpu_id, 12)) { 2071 cpup = &i386_cpuid_cpus[i]; 2072 break; 2073 } 2074 } 2075 2076 if (cpup == NULL) { 2077 cpu_vendor = CPUVENDOR_UNKNOWN; 2078 if (ci->ci_vendor[0] != '\0') 2079 vendorname = (char *)&ci->ci_vendor[0]; 2080 else 2081 vendorname = "Unknown"; 2082 class = family - 3; 2083 modifier = ""; 2084 name = ""; 2085 ci->ci_info = NULL; 2086 } else { 2087 cpu_vendor = cpup->cpu_vendor; 2088 vendorname = cpup->cpu_vendorname; 2089 modifier = modifiers[modif]; 2090 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 2091 name = cpufam->cpu_models[ci->ci_model]; 2092 if (name == NULL || *name == '\0') 2093 name = cpufam->cpu_model_default; 2094 class = cpufam->cpu_class; 2095 ci->ci_info = cpufam->cpu_info; 2096 2097 if (cpu_vendor == CPUVENDOR_INTEL) { 2098 if (ci->ci_family == 6 && ci->ci_model >= 5) { 2099 const char *tmp; 2100 tmp = intel_family6_name(ci); 2101 if (tmp != NULL) 2102 name = tmp; 2103 } 2104 if (ci->ci_family == 15 && 2105 ci->ci_brand_id < 2106 __arraycount(i386_intel_brand) && 2107 i386_intel_brand[ci->ci_brand_id]) 2108 name = 2109 i386_intel_brand[ci->ci_brand_id]; 2110 } 2111 2112 if (cpu_vendor == CPUVENDOR_AMD) { 2113 if (ci->ci_family == 6 && ci->ci_model >= 6) { 2114 if (ci->ci_brand_id == 1) 2115 /* 2116 * It's Duron. We override the 2117 * name, since it might have 2118 * been misidentified as Athlon. 2119 */ 2120 name = 2121 amd_brand[ci->ci_brand_id]; 2122 else 2123 brand = amd_brand_name; 2124 } 2125 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 2126 == 0xf) { 2127 /* Identify AMD64 CPU names. */ 2128 const char *tmp; 2129 tmp = amd_amd64_name(ci); 2130 if (tmp != NULL) 2131 name = tmp; 2132 } 2133 } 2134 2135 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 2136 vendorname = "VIA"; 2137 } 2138 } 2139 2140 ci->ci_cpu_class = class; 2141 2142 sz = sizeof(ci->ci_tsc_freq); 2143 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 2144 sz = sizeof(use_pae); 2145 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 2146 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 2147 2148 /* 2149 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 2150 * we try to determine from the family/model values. 2151 */ 2152 if (*cpu_brand_string != '\0') 2153 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 2154 2155 aprint_normal("%s: %s", cpuname, vendorname); 2156 if (*modifier) 2157 aprint_normal(" %s", modifier); 2158 if (*name) 2159 aprint_normal(" %s", name); 2160 if (*brand) 2161 aprint_normal(" %s", brand); 2162 aprint_normal(" (%s-class)", classnames[class]); 2163 2164 if (ci->ci_tsc_freq != 0) 2165 aprint_normal(", %ju.%02ju MHz", 2166 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 2167 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 2168 aprint_normal("\n"); 2169 2170 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 2171 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 2172 if (ci->ci_signature != 0) 2173 aprint_normal(" (id %#x)", ci->ci_signature); 2174 aprint_normal("\n"); 2175 2176 if (ci->ci_info) 2177 (*ci->ci_info)(ci); 2178 2179 /* 2180 * display CPU feature flags 2181 */ 2182 2183 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 2184 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 2185 2186 /* These next two are actually common definitions! */ 2187 print_bits(cpuname, "features2", 2188 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 2189 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 2190 print_bits(cpuname, "features3", 2191 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 2192 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 2193 2194 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 2195 ci->ci_feat_val[4]); 2196 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2197 print_bits(cpuname, "features5", CPUID_SEF_FLAGS, 2198 ci->ci_feat_val[5]); 2199 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2200 print_bits(cpuname, "features6", CPUID_SEF_FLAGS1, 2201 ci->ci_feat_val[6]); 2202 2203 if (cpu_vendor == CPUVENDOR_INTEL) 2204 print_bits(cpuname, "features7", CPUID_SEF_FLAGS2, 2205 ci->ci_feat_val[7]); 2206 2207 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[8]); 2208 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 2209 ci->ci_feat_val[9]); 2210 2211 if (ci->ci_max_xsave != 0) { 2212 aprint_normal("%s: xsave area size: current %d, maximum %d", 2213 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 2214 aprint_normal(", xgetbv %sabled\n", 2215 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 2216 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 2217 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 2218 x86_xgetbv()); 2219 } 2220 2221 x86_print_cache_and_tlb_info(ci); 2222 2223 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 2224 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 2225 cpuname, 2226 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 2227 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 2228 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 2229 } 2230 2231 if (ci->ci_cpu_class == CPUCLASS_386) 2232 errx(1, "NetBSD requires an 80486 or later processor"); 2233 2234 if (ci->ci_cpu_type == CPU_486DLC) { 2235 #ifndef CYRIX_CACHE_WORKS 2236 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 2237 #else 2238 #ifndef CYRIX_CACHE_REALLY_WORKS 2239 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 2240 #else 2241 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 2242 #endif 2243 #endif 2244 } 2245 2246 /* 2247 * Everything past this point requires a Pentium or later. 2248 */ 2249 if (ci->ci_cpuid_level < 0) 2250 return; 2251 2252 identifycpu_cpuids(ci); 2253 2254 if ((ci->ci_cpuid_level >= 5) 2255 && ((cpu_vendor == CPUVENDOR_INTEL) 2256 || (cpu_vendor == CPUVENDOR_AMD))) { 2257 uint16_t lmin, lmax; 2258 x86_cpuid(5, descs); 2259 2260 print_bits(cpuname, "MONITOR/MWAIT extensions", 2261 CPUID_MON_FLAGS, descs[2]); 2262 lmin = __SHIFTOUT(descs[0], CPUID_MON_MINSIZE); 2263 lmax = __SHIFTOUT(descs[1], CPUID_MON_MAXSIZE); 2264 aprint_normal("%s: monitor-line size %hu", cpuname, lmin); 2265 if (lmin != lmax) 2266 aprint_normal("-%hu", lmax); 2267 aprint_normal("\n"); 2268 2269 for (i = 0; i <= 7; i++) { 2270 unsigned int num = CPUID_MON_SUBSTATE(descs[3], i); 2271 2272 if (num != 0) 2273 aprint_normal("%s: C%u substates %u\n", 2274 cpuname, i, num); 2275 } 2276 } 2277 if ((ci->ci_cpuid_level >= 6) 2278 && ((cpu_vendor == CPUVENDOR_INTEL) 2279 || (cpu_vendor == CPUVENDOR_AMD))) { 2280 x86_cpuid(6, descs); 2281 print_bits(cpuname, "DSPM-eax", CPUID_DSPM_FLAGS, descs[0]); 2282 print_bits(cpuname, "DSPM-ecx", CPUID_DSPM_FLAGS1, descs[2]); 2283 } 2284 if ((ci->ci_cpuid_level >= 7) 2285 && ((cpu_vendor == CPUVENDOR_INTEL) 2286 || (cpu_vendor == CPUVENDOR_AMD))) { 2287 x86_cpuid(7, descs); 2288 aprint_verbose("%s: SEF highest subleaf %08x\n", 2289 cpuname, descs[0]); 2290 } 2291 2292 if (cpu_vendor == CPUVENDOR_AMD) { 2293 x86_cpuid(0x80000000, descs); 2294 if (descs[0] >= 0x80000000) 2295 ci->ci_max_ext_cpuid = descs[0]; 2296 else 2297 ci->ci_max_ext_cpuid = 0; 2298 if (descs[0] >= 0x80000007) 2299 powernow_probe(ci); 2300 2301 if ((descs[0] >= 0x8000000a) 2302 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 2303 x86_cpuid(0x8000000a, descs); 2304 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 2305 descs[0] & 0xf); 2306 aprint_verbose("%s: SVM NASID %d\n", cpuname, 2307 descs[1]); 2308 print_bits(cpuname, "SVM features", 2309 CPUID_AMD_SVM_FLAGS, descs[3]); 2310 } 2311 } else if (cpu_vendor == CPUVENDOR_INTEL) { 2312 int32_t bi_index; 2313 2314 for (bi_index = 1; bi_index <= ci->ci_cpuid_level; bi_index++) { 2315 x86_cpuid(bi_index, descs); 2316 switch (bi_index) { 2317 case 0x0a: 2318 print_bits(cpuname, "Perfmon-eax", 2319 CPUID_PERF_FLAGS0, descs[0]); 2320 print_bits(cpuname, "Perfmon-ebx", 2321 CPUID_PERF_FLAGS1, descs[1]); 2322 print_bits(cpuname, "Perfmon-edx", 2323 CPUID_PERF_FLAGS3, descs[3]); 2324 break; 2325 default: 2326 #if 0 2327 aprint_verbose("%s: basic %08x-eax %08x\n", 2328 cpuname, bi_index, descs[0]); 2329 aprint_verbose("%s: basic %08x-ebx %08x\n", 2330 cpuname, bi_index, descs[1]); 2331 aprint_verbose("%s: basic %08x-ecx %08x\n", 2332 cpuname, bi_index, descs[2]); 2333 aprint_verbose("%s: basic %08x-edx %08x\n", 2334 cpuname, bi_index, descs[3]); 2335 #endif 2336 break; 2337 } 2338 } 2339 } 2340 2341 #ifdef INTEL_ONDEMAND_CLOCKMOD 2342 clockmod_init(); 2343 #endif 2344 2345 if (cpu_vendor == CPUVENDOR_AMD) 2346 ucode.loader_version = CPU_UCODE_LOADER_AMD; 2347 else if (cpu_vendor == CPUVENDOR_INTEL) 2348 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 2349 else 2350 return; 2351 2352 ucode.data = &ucvers; 2353 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 2354 #ifdef __i386__ 2355 struct cpu_ucode_version_64 ucode_64; 2356 if (errno != ENOTTY) 2357 return; 2358 /* Try the 64 bit ioctl */ 2359 memset(&ucode_64, 0, sizeof ucode_64); 2360 ucode_64.data = &ucvers; 2361 ucode_64.loader_version = ucode.loader_version; 2362 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 2363 return; 2364 #else 2365 return; 2366 #endif 2367 } 2368 2369 if (cpu_vendor == CPUVENDOR_AMD) 2370 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2371 else if (cpu_vendor == CPUVENDOR_INTEL) 2372 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2373 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2374 } 2375 2376 static const struct x86_cache_info * 2377 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 2378 { 2379 int i; 2380 2381 for (i = 0; cai[i].cai_desc != 0; i++) { 2382 if (cai[i].cai_desc == desc) 2383 return (&cai[i]); 2384 } 2385 2386 return (NULL); 2387 } 2388 2389 static const char * 2390 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2391 const char *sep) 2392 { 2393 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2394 char human_num[HUMAN_BUFSIZE]; 2395 2396 if (cai->cai_totalsize == 0) 2397 return sep; 2398 2399 if (sep == NULL) 2400 aprint_verbose_dev(ci->ci_dev, ""); 2401 else 2402 aprint_verbose("%s", sep); 2403 if (name != NULL) 2404 aprint_verbose("%s ", name); 2405 2406 if (cai->cai_string != NULL) { 2407 aprint_verbose("%s ", cai->cai_string); 2408 } else { 2409 (void)humanize_number(human_num, sizeof(human_num), 2410 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2411 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2412 } 2413 switch (cai->cai_associativity) { 2414 case 0: 2415 aprint_verbose("disabled"); 2416 break; 2417 case 1: 2418 aprint_verbose("direct-mapped"); 2419 break; 2420 case 0xff: 2421 aprint_verbose("fully associative"); 2422 break; 2423 default: 2424 aprint_verbose("%d-way", cai->cai_associativity); 2425 break; 2426 } 2427 return ", "; 2428 } 2429 2430 static const char * 2431 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2432 const char *sep) 2433 { 2434 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2435 char human_num[HUMAN_BUFSIZE]; 2436 2437 if (cai->cai_totalsize == 0) 2438 return sep; 2439 2440 if (sep == NULL) 2441 aprint_verbose_dev(ci->ci_dev, ""); 2442 else 2443 aprint_verbose("%s", sep); 2444 if (name != NULL) 2445 aprint_verbose("%s ", name); 2446 2447 if (cai->cai_string != NULL) { 2448 aprint_verbose("%s", cai->cai_string); 2449 } else { 2450 (void)humanize_number(human_num, sizeof(human_num), 2451 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2452 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2453 human_num); 2454 switch (cai->cai_associativity) { 2455 case 0: 2456 aprint_verbose("disabled"); 2457 break; 2458 case 1: 2459 aprint_verbose("direct-mapped"); 2460 break; 2461 case 0xff: 2462 aprint_verbose("fully associative"); 2463 break; 2464 default: 2465 aprint_verbose("%d-way", cai->cai_associativity); 2466 break; 2467 } 2468 } 2469 return ", "; 2470 } 2471 2472 static void 2473 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2474 { 2475 const char *sep = NULL; 2476 2477 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2478 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2479 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 2480 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 2481 if (sep != NULL) 2482 aprint_verbose("\n"); 2483 } 2484 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2485 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 2486 if (sep != NULL) 2487 aprint_verbose("\n"); 2488 } 2489 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2490 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 2491 if (sep != NULL) 2492 aprint_verbose("\n"); 2493 } 2494 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2495 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2496 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2497 if (sep != NULL) 2498 aprint_verbose("\n"); 2499 } 2500 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 2501 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 2502 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 2503 if (sep != NULL) 2504 aprint_verbose("\n"); 2505 } 2506 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 2507 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 2508 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 2509 if (sep != NULL) 2510 aprint_verbose("\n"); 2511 } 2512 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 2513 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 2514 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 2515 if (sep != NULL) 2516 aprint_verbose("\n"); 2517 } 2518 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 2519 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 2520 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 2521 if (sep != NULL) 2522 aprint_verbose("\n"); 2523 } 2524 if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) { 2525 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL); 2526 sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep); 2527 sep = print_tlb_config(ci, CAI_L2_STLB3, NULL, sep); 2528 if (sep != NULL) 2529 aprint_verbose("\n"); 2530 } 2531 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 2532 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", 2533 NULL); 2534 if (sep != NULL) 2535 aprint_verbose("\n"); 2536 } 2537 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 2538 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", 2539 NULL); 2540 if (sep != NULL) 2541 aprint_verbose("\n"); 2542 } 2543 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 2544 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", 2545 NULL); 2546 if (sep != NULL) 2547 aprint_verbose("\n"); 2548 } 2549 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 2550 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", 2551 NULL); 2552 if (sep != NULL) 2553 aprint_verbose("\n"); 2554 } 2555 } 2556 2557 static void 2558 powernow_probe(struct cpu_info *ci) 2559 { 2560 uint32_t regs[4]; 2561 char buf[256]; 2562 2563 x86_cpuid(0x80000007, regs); 2564 2565 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2566 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 2567 buf); 2568 } 2569 2570 bool 2571 identifycpu_bind(void) 2572 { 2573 2574 return true; 2575 } 2576 2577 int 2578 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2579 { 2580 struct cpu_info ci; 2581 int loader_version, res; 2582 struct cpu_ucode_version versreq; 2583 2584 cpu_probe_base_features(&ci, "unknown"); 2585 2586 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2587 loader_version = CPU_UCODE_LOADER_AMD; 2588 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2589 loader_version = CPU_UCODE_LOADER_INTEL1; 2590 else 2591 return -1; 2592 2593 /* check whether the kernel understands this loader version */ 2594 versreq.loader_version = loader_version; 2595 versreq.data = 0; 2596 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2597 if (res) 2598 return -1; 2599 2600 switch (loader_version) { 2601 case CPU_UCODE_LOADER_AMD: 2602 if (uc->cpu_nr != -1) { 2603 /* printf? */ 2604 return -1; 2605 } 2606 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2607 break; 2608 case CPU_UCODE_LOADER_INTEL1: 2609 if (uc->cpu_nr == -1) 2610 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2611 else 2612 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2613 break; 2614 default: /* can't happen */ 2615 return -1; 2616 } 2617 uc->loader_version = loader_version; 2618 return 0; 2619 } 2620
Indexes created Tue Sep 23 07:09:52 GMT 2025