i386.c revision 1.104
1 /* $NetBSD: i386.c,v 1.104 2019/07/26 10:03:40 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.104 2019/07/26 10:03:40 msaitoh Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cacheinfo.h> 85 #include <x86/cpu_ucode.h> 86 87 #include "../cpuctl.h" 88 #include "cpuctl_i386.h" 89 90 /* Size of buffer for printing humanized numbers */ 91 #define HUMAN_BUFSIZE sizeof("999KB") 92 93 struct cpu_info { 94 const char *ci_dev; 95 int32_t ci_cpu_type; /* for cpu's without cpuid */ 96 int32_t ci_cpuid_level; /* highest cpuid supported */ 97 uint32_t ci_cpuid_extlevel; /* highest cpuid extended func lv */ 98 uint32_t ci_signature; /* X86 cpuid type */ 99 uint32_t ci_family; /* from ci_signature */ 100 uint32_t ci_model; /* from ci_signature */ 101 uint32_t ci_feat_val[10]; /* X86 CPUID feature bits 102 * [0] basic features %edx 103 * [1] basic features %ecx 104 * [2] extended features %edx 105 * [3] extended features %ecx 106 * [4] VIA padlock features 107 * [5] structure ext. feat. %ebx 108 * [6] structure ext. feat. %ecx 109 * [7] structure ext. feat. %edx 110 * [8] XCR0 bits (d:0 %eax) 111 * [9] xsave flags (d:1 %eax) 112 */ 113 uint32_t ci_cpu_class; /* CPU class */ 114 uint32_t ci_brand_id; /* Intel brand id */ 115 uint32_t ci_vendor[4]; /* vendor string */ 116 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 117 uint64_t ci_tsc_freq; /* cpu cycles/second */ 118 uint8_t ci_packageid; 119 uint8_t ci_coreid; 120 uint8_t ci_smtid; 121 uint32_t ci_initapicid; 122 uint32_t ci_max_ext_cpuid; 123 124 uint32_t ci_cur_xsave; 125 uint32_t ci_max_xsave; 126 127 struct x86_cache_info ci_cinfo[CAI_COUNT]; 128 void (*ci_info)(struct cpu_info *); 129 }; 130 131 struct cpu_nocpuid_nameclass { 132 int cpu_vendor; 133 const char *cpu_vendorname; 134 const char *cpu_name; 135 int cpu_class; 136 void (*cpu_setup)(struct cpu_info *); 137 void (*cpu_cacheinfo)(struct cpu_info *); 138 void (*cpu_info)(struct cpu_info *); 139 }; 140 141 struct cpu_cpuid_nameclass { 142 const char *cpu_id; 143 int cpu_vendor; 144 const char *cpu_vendorname; 145 struct cpu_cpuid_family { 146 int cpu_class; 147 const char *cpu_models[256]; 148 const char *cpu_model_default; 149 void (*cpu_setup)(struct cpu_info *); 150 void (*cpu_probe)(struct cpu_info *); 151 void (*cpu_info)(struct cpu_info *); 152 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 153 }; 154 155 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 156 157 /* 158 * Map Brand ID from cpuid instruction to brand name. 159 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 160 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 161 * Architectures Software Developer's Manual, Volume 2A". 162 */ 163 static const char * const i386_intel_brand[] = { 164 "", /* Unsupported */ 165 "Celeron", /* Intel (R) Celeron (TM) processor */ 166 "Pentium III", /* Intel (R) Pentium (R) III processor */ 167 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 168 "Pentium III", /* Intel (R) Pentium (R) III processor */ 169 "", /* 0x05: Reserved */ 170 "Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */ 171 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 172 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 173 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 174 "Celeron", /* Intel (R) Celeron (TM) processor */ 175 "Xeon", /* Intel (R) Xeon (TM) processor */ 176 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 177 "", /* 0x0d: Reserved */ 178 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 179 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 180 "", /* 0x10: Reserved */ 181 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 182 "Celeron M", /* Intel (R) Celeron (R) M processor */ 183 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 184 "Celeron", /* Intel (R) Celeron (R) processor */ 185 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 186 "Pentium M", /* Intel (R) Pentium (R) M processor */ 187 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 188 }; 189 190 /* 191 * AMD processors don't have Brand IDs, so we need these names for probe. 192 */ 193 static const char * const amd_brand[] = { 194 "", 195 "Duron", /* AMD Duron(tm) */ 196 "MP", /* AMD Athlon(tm) MP */ 197 "XP", /* AMD Athlon(tm) XP */ 198 "4" /* AMD Athlon(tm) 4 */ 199 }; 200 201 static int cpu_vendor; 202 static char cpu_brand_string[49]; 203 static char amd_brand_name[48]; 204 static int use_pae, largepagesize; 205 206 /* Setup functions */ 207 static void disable_tsc(struct cpu_info *); 208 static void amd_family5_setup(struct cpu_info *); 209 static void cyrix6x86_cpu_setup(struct cpu_info *); 210 static void winchip_cpu_setup(struct cpu_info *); 211 /* Brand/Model name functions */ 212 static const char *intel_family6_name(struct cpu_info *); 213 static const char *amd_amd64_name(struct cpu_info *); 214 /* Probe functions */ 215 static void amd_family6_probe(struct cpu_info *); 216 static void powernow_probe(struct cpu_info *); 217 static void intel_family_new_probe(struct cpu_info *); 218 static void via_cpu_probe(struct cpu_info *); 219 /* (Cache) Info functions */ 220 static void cpu_dcp_cacheinfo(struct cpu_info *, uint32_t); 221 static void intel_cpu_cacheinfo(struct cpu_info *); 222 static void amd_cpu_cacheinfo(struct cpu_info *); 223 static void via_cpu_cacheinfo(struct cpu_info *); 224 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 225 static void transmeta_cpu_info(struct cpu_info *); 226 /* Common functions */ 227 static void cpu_probe_base_features(struct cpu_info *, const char *); 228 static void cpu_probe_hv_features(struct cpu_info *, const char *); 229 static void cpu_probe_features(struct cpu_info *); 230 static void print_bits(const char *, const char *, const char *, uint32_t); 231 static void identifycpu_cpuids(struct cpu_info *); 232 static const struct x86_cache_info *cache_info_lookup( 233 const struct x86_cache_info *, uint8_t); 234 static const char *print_cache_config(struct cpu_info *, int, const char *, 235 const char *); 236 static const char *print_tlb_config(struct cpu_info *, int, const char *, 237 const char *); 238 static void x86_print_cache_and_tlb_info(struct cpu_info *); 239 240 /* 241 * Note: these are just the ones that may not have a cpuid instruction. 242 * We deal with the rest in a different way. 243 */ 244 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 245 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 246 NULL, NULL, NULL }, /* CPU_386SX */ 247 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 248 NULL, NULL, NULL }, /* CPU_386 */ 249 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 250 NULL, NULL, NULL }, /* CPU_486SX */ 251 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 252 NULL, NULL, NULL }, /* CPU_486 */ 253 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 254 NULL, NULL, NULL }, /* CPU_486DLC */ 255 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 256 NULL, NULL, NULL }, /* CPU_6x86 */ 257 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 258 NULL, NULL, NULL }, /* CPU_NX586 */ 259 }; 260 261 const char *classnames[] = { 262 "386", 263 "486", 264 "586", 265 "686" 266 }; 267 268 const char *modifiers[] = { 269 "", 270 "OverDrive", 271 "Dual", 272 "" 273 }; 274 275 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 276 { 277 /* 278 * For Intel processors, check Chapter 35Model-specific 279 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 280 * Software Developer's Manual, Volume 3C". 281 */ 282 "GenuineIntel", 283 CPUVENDOR_INTEL, 284 "Intel", 285 /* Family 4 */ 286 { { 287 CPUCLASS_486, 288 { 289 "486DX", "486DX", "486SX", "486DX2", "486SL", 290 "486SX2", 0, "486DX2 W/B Enhanced", 291 "486DX4", 0, 0, 0, 0, 0, 0, 0, 292 }, 293 "486", /* Default */ 294 NULL, 295 NULL, 296 intel_cpu_cacheinfo, 297 }, 298 /* Family 5 */ 299 { 300 CPUCLASS_586, 301 { 302 "Pentium (P5 A-step)", "Pentium (P5)", 303 "Pentium (P54C)", "Pentium (P24T)", 304 "Pentium/MMX", "Pentium", 0, 305 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 306 "Quark X1000", 0, 0, 0, 0, 0, 0, 307 }, 308 "Pentium", /* Default */ 309 NULL, 310 NULL, 311 intel_cpu_cacheinfo, 312 }, 313 /* Family 6 */ 314 { 315 CPUCLASS_686, 316 { 317 [0x00] = "Pentium Pro (A-step)", 318 [0x01] = "Pentium Pro", 319 [0x03] = "Pentium II (Klamath)", 320 [0x04] = "Pentium Pro", 321 [0x05] = "Pentium II/Celeron (Deschutes)", 322 [0x06] = "Celeron (Mendocino)", 323 [0x07] = "Pentium III (Katmai)", 324 [0x08] = "Pentium III (Coppermine)", 325 [0x09] = "Pentium M (Banias)", 326 [0x0a] = "Pentium III Xeon (Cascades)", 327 [0x0b] = "Pentium III (Tualatin)", 328 [0x0d] = "Pentium M (Dothan)", 329 [0x0e] = "Pentium Core Duo, Core solo", 330 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 331 "Core 2 Quad 6xxx, " 332 "Core 2 Extreme 6xxx, " 333 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 334 "and Pentium DC", 335 [0x15] = "EP80579 Integrated Processor", 336 [0x16] = "Celeron (45nm)", 337 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 338 "Core 2 Quad 8xxx and 9xxx", 339 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 340 "(Nehalem)", 341 [0x1c] = "45nm Atom Family", 342 [0x1d] = "XeonMP 74xx (Nehalem)", 343 [0x1e] = "Core i7 and i5", 344 [0x1f] = "Core i7 and i5", 345 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 346 [0x26] = "Atom Family", 347 [0x27] = "Atom Family", 348 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 349 "i3 2xxx", 350 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 351 [0x2d] = "Xeon E5 Sandy Bridge family, " 352 "Core i7-39xx Extreme", 353 [0x2e] = "Xeon 75xx & 65xx", 354 [0x2f] = "Xeon E7 family", 355 [0x35] = "Atom Family", 356 [0x36] = "Atom S1000", 357 [0x37] = "Atom E3000, Z3[67]00", 358 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 359 "Ivy Bridge", 360 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 361 "(Haswell)", 362 [0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)", 363 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 364 "Core i7-49xx Extreme", 365 [0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), " 366 "Core i7-59xx Extreme", 367 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 368 "(Haswell)", 369 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 370 "(Haswell)", 371 [0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)", 372 [0x4a] = "Atom Z3400", 373 [0x4c] = "Atom X[57]-Z8000 (Airmont)", 374 [0x4d] = "Atom C2000", 375 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 376 [0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme", 377 [0x55] = "Xeon Scalable (Skylake, Cascade Lake, Copper Lake)", 378 [0x56] = "Xeon D-1500 (Broadwell)", 379 [0x57] = "Xeon Phi [357]200 (Knights Landing)", 380 [0x5a] = "Atom E3500", 381 [0x5c] = "Atom (Goldmont)", 382 [0x5d] = "Atom X3-C3000 (Silvermont)", 383 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 384 [0x5f] = "Atom (Goldmont, Denverton)", 385 [0x66] = "8th gen Core i3 (Cannon Lake)", 386 [0x6a] = "Future Xeon (Ice Lake)", 387 [0x6c] = "Future Xeon (Ice Lake)", 388 [0x7a] = "Atom (Goldmont Plus)", 389 [0x7d] = "Future Core (Ice Lake)", 390 [0x7e] = "Future Core (Ice Lake)", 391 [0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)", 392 [0x86] = "Atom (Tremont)", 393 [0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 394 [0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 395 }, 396 "Pentium Pro, II or III", /* Default */ 397 NULL, 398 intel_family_new_probe, 399 intel_cpu_cacheinfo, 400 }, 401 /* Family > 6 */ 402 { 403 CPUCLASS_686, 404 { 405 0, 0, 0, 0, 0, 0, 0, 0, 406 0, 0, 0, 0, 0, 0, 0, 0, 407 }, 408 "Pentium 4", /* Default */ 409 NULL, 410 intel_family_new_probe, 411 intel_cpu_cacheinfo, 412 } } 413 }, 414 { 415 "AuthenticAMD", 416 CPUVENDOR_AMD, 417 "AMD", 418 /* Family 4 */ 419 { { 420 CPUCLASS_486, 421 { 422 0, 0, 0, "Am486DX2 W/T", 423 0, 0, 0, "Am486DX2 W/B", 424 "Am486DX4 W/T or Am5x86 W/T 150", 425 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 426 0, 0, "Am5x86 W/T 133/160", 427 "Am5x86 W/B 133/160", 428 }, 429 "Am486 or Am5x86", /* Default */ 430 NULL, 431 NULL, 432 NULL, 433 }, 434 /* Family 5 */ 435 { 436 CPUCLASS_586, 437 { 438 "K5", "K5", "K5", "K5", 0, 0, "K6", 439 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 440 "K6-2+/III+", 0, 0, 441 }, 442 "K5 or K6", /* Default */ 443 amd_family5_setup, 444 NULL, 445 amd_cpu_cacheinfo, 446 }, 447 /* Family 6 */ 448 { 449 CPUCLASS_686, 450 { 451 0, "Athlon Model 1", "Athlon Model 2", 452 "Duron", "Athlon Model 4 (Thunderbird)", 453 0, "Athlon", "Duron", "Athlon", 0, 454 "Athlon", 0, 0, 0, 0, 0, 455 }, 456 "K7 (Athlon)", /* Default */ 457 NULL, 458 amd_family6_probe, 459 amd_cpu_cacheinfo, 460 }, 461 /* Family > 6 */ 462 { 463 CPUCLASS_686, 464 { 465 0, 0, 0, 0, 0, 0, 0, 0, 466 0, 0, 0, 0, 0, 0, 0, 0, 467 }, 468 "Unknown K8 (Athlon)", /* Default */ 469 NULL, 470 amd_family6_probe, 471 amd_cpu_cacheinfo, 472 } } 473 }, 474 { 475 "CyrixInstead", 476 CPUVENDOR_CYRIX, 477 "Cyrix", 478 /* Family 4 */ 479 { { 480 CPUCLASS_486, 481 { 482 0, 0, 0, 483 "MediaGX", 484 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 485 }, 486 "486", /* Default */ 487 cyrix6x86_cpu_setup, /* XXX ?? */ 488 NULL, 489 NULL, 490 }, 491 /* Family 5 */ 492 { 493 CPUCLASS_586, 494 { 495 0, 0, "6x86", 0, 496 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 497 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 498 }, 499 "6x86", /* Default */ 500 cyrix6x86_cpu_setup, 501 NULL, 502 NULL, 503 }, 504 /* Family 6 */ 505 { 506 CPUCLASS_686, 507 { 508 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 509 0, 0, 0, 0, 0, 0, 0, 0, 510 }, 511 "6x86MX", /* Default */ 512 cyrix6x86_cpu_setup, 513 NULL, 514 NULL, 515 }, 516 /* Family > 6 */ 517 { 518 CPUCLASS_686, 519 { 520 0, 0, 0, 0, 0, 0, 0, 0, 521 0, 0, 0, 0, 0, 0, 0, 0, 522 }, 523 "Unknown 6x86MX", /* Default */ 524 NULL, 525 NULL, 526 NULL, 527 } } 528 }, 529 { /* MediaGX is now owned by National Semiconductor */ 530 "Geode by NSC", 531 CPUVENDOR_CYRIX, /* XXX */ 532 "National Semiconductor", 533 /* Family 4, NSC never had any of these */ 534 { { 535 CPUCLASS_486, 536 { 537 0, 0, 0, 0, 0, 0, 0, 0, 538 0, 0, 0, 0, 0, 0, 0, 0, 539 }, 540 "486 compatible", /* Default */ 541 NULL, 542 NULL, 543 NULL, 544 }, 545 /* Family 5: Geode family, formerly MediaGX */ 546 { 547 CPUCLASS_586, 548 { 549 0, 0, 0, 0, 550 "Geode GX1", 551 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 552 }, 553 "Geode", /* Default */ 554 cyrix6x86_cpu_setup, 555 NULL, 556 amd_cpu_cacheinfo, 557 }, 558 /* Family 6, not yet available from NSC */ 559 { 560 CPUCLASS_686, 561 { 562 0, 0, 0, 0, 0, 0, 0, 0, 563 0, 0, 0, 0, 0, 0, 0, 0, 564 }, 565 "Pentium Pro compatible", /* Default */ 566 NULL, 567 NULL, 568 NULL, 569 }, 570 /* Family > 6, not yet available from NSC */ 571 { 572 CPUCLASS_686, 573 { 574 0, 0, 0, 0, 0, 0, 0, 0, 575 0, 0, 0, 0, 0, 0, 0, 0, 576 }, 577 "Pentium Pro compatible", /* Default */ 578 NULL, 579 NULL, 580 NULL, 581 } } 582 }, 583 { 584 "CentaurHauls", 585 CPUVENDOR_IDT, 586 "IDT", 587 /* Family 4, IDT never had any of these */ 588 { { 589 CPUCLASS_486, 590 { 591 0, 0, 0, 0, 0, 0, 0, 0, 592 0, 0, 0, 0, 0, 0, 0, 0, 593 }, 594 "486 compatible", /* Default */ 595 NULL, 596 NULL, 597 NULL, 598 }, 599 /* Family 5 */ 600 { 601 CPUCLASS_586, 602 { 603 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 604 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 605 }, 606 "WinChip", /* Default */ 607 winchip_cpu_setup, 608 NULL, 609 NULL, 610 }, 611 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 612 { 613 CPUCLASS_686, 614 { 615 0, 0, 0, 0, 0, 0, "C3 Samuel", 616 "C3 Samuel 2/Ezra", "C3 Ezra-T", 617 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 618 0, "VIA Nano", 619 }, 620 "Unknown VIA/IDT", /* Default */ 621 NULL, 622 via_cpu_probe, 623 via_cpu_cacheinfo, 624 }, 625 /* Family > 6, not yet available from VIA */ 626 { 627 CPUCLASS_686, 628 { 629 0, 0, 0, 0, 0, 0, 0, 0, 630 0, 0, 0, 0, 0, 0, 0, 0, 631 }, 632 "Pentium Pro compatible", /* Default */ 633 NULL, 634 NULL, 635 NULL, 636 } } 637 }, 638 { 639 "GenuineTMx86", 640 CPUVENDOR_TRANSMETA, 641 "Transmeta", 642 /* Family 4, Transmeta never had any of these */ 643 { { 644 CPUCLASS_486, 645 { 646 0, 0, 0, 0, 0, 0, 0, 0, 647 0, 0, 0, 0, 0, 0, 0, 0, 648 }, 649 "486 compatible", /* Default */ 650 NULL, 651 NULL, 652 NULL, 653 }, 654 /* Family 5 */ 655 { 656 CPUCLASS_586, 657 { 658 0, 0, 0, 0, 0, 0, 0, 0, 659 0, 0, 0, 0, 0, 0, 0, 0, 660 }, 661 "Crusoe", /* Default */ 662 NULL, 663 NULL, 664 transmeta_cpu_info, 665 }, 666 /* Family 6, not yet available from Transmeta */ 667 { 668 CPUCLASS_686, 669 { 670 0, 0, 0, 0, 0, 0, 0, 0, 671 0, 0, 0, 0, 0, 0, 0, 0, 672 }, 673 "Pentium Pro compatible", /* Default */ 674 NULL, 675 NULL, 676 NULL, 677 }, 678 /* Family > 6, not yet available from Transmeta */ 679 { 680 CPUCLASS_686, 681 { 682 0, 0, 0, 0, 0, 0, 0, 0, 683 0, 0, 0, 0, 0, 0, 0, 0, 684 }, 685 "Pentium Pro compatible", /* Default */ 686 NULL, 687 NULL, 688 NULL, 689 } } 690 } 691 }; 692 693 /* 694 * disable the TSC such that we don't use the TSC in microtime(9) 695 * because some CPUs got the implementation wrong. 696 */ 697 static void 698 disable_tsc(struct cpu_info *ci) 699 { 700 if (ci->ci_feat_val[0] & CPUID_TSC) { 701 ci->ci_feat_val[0] &= ~CPUID_TSC; 702 aprint_error("WARNING: broken TSC disabled\n"); 703 } 704 } 705 706 static void 707 amd_family5_setup(struct cpu_info *ci) 708 { 709 710 switch (ci->ci_model) { 711 case 0: /* AMD-K5 Model 0 */ 712 /* 713 * According to the AMD Processor Recognition App Note, 714 * the AMD-K5 Model 0 uses the wrong bit to indicate 715 * support for global PTEs, instead using bit 9 (APIC) 716 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 717 */ 718 if (ci->ci_feat_val[0] & CPUID_APIC) 719 ci->ci_feat_val[0] = 720 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 721 /* 722 * XXX But pmap_pg_g is already initialized -- need to kick 723 * XXX the pmap somehow. How does the MP branch do this? 724 */ 725 break; 726 } 727 } 728 729 static void 730 cyrix6x86_cpu_setup(struct cpu_info *ci) 731 { 732 733 /* 734 * Do not disable the TSC on the Geode GX, it's reported to 735 * work fine. 736 */ 737 if (ci->ci_signature != 0x552) 738 disable_tsc(ci); 739 } 740 741 static void 742 winchip_cpu_setup(struct cpu_info *ci) 743 { 744 switch (ci->ci_model) { 745 case 4: /* WinChip C6 */ 746 disable_tsc(ci); 747 } 748 } 749 750 751 static const char * 752 intel_family6_name(struct cpu_info *ci) 753 { 754 const char *ret = NULL; 755 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 756 757 if (ci->ci_model == 5) { 758 switch (l2cache) { 759 case 0: 760 case 128 * 1024: 761 ret = "Celeron (Covington)"; 762 break; 763 case 256 * 1024: 764 ret = "Mobile Pentium II (Dixon)"; 765 break; 766 case 512 * 1024: 767 ret = "Pentium II"; 768 break; 769 case 1 * 1024 * 1024: 770 case 2 * 1024 * 1024: 771 ret = "Pentium II Xeon"; 772 break; 773 } 774 } else if (ci->ci_model == 6) { 775 switch (l2cache) { 776 case 256 * 1024: 777 case 512 * 1024: 778 ret = "Mobile Pentium II"; 779 break; 780 } 781 } else if (ci->ci_model == 7) { 782 switch (l2cache) { 783 case 512 * 1024: 784 ret = "Pentium III"; 785 break; 786 case 1 * 1024 * 1024: 787 case 2 * 1024 * 1024: 788 ret = "Pentium III Xeon"; 789 break; 790 } 791 } else if (ci->ci_model >= 8) { 792 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 793 switch (ci->ci_brand_id) { 794 case 0x3: 795 if (ci->ci_signature == 0x6B1) 796 ret = "Celeron"; 797 break; 798 case 0x8: 799 if (ci->ci_signature >= 0xF13) 800 ret = "genuine processor"; 801 break; 802 case 0xB: 803 if (ci->ci_signature >= 0xF13) 804 ret = "Xeon MP"; 805 break; 806 case 0xE: 807 if (ci->ci_signature < 0xF13) 808 ret = "Xeon"; 809 break; 810 } 811 if (ret == NULL) 812 ret = i386_intel_brand[ci->ci_brand_id]; 813 } 814 } 815 816 return ret; 817 } 818 819 /* 820 * Identify AMD64 CPU names from cpuid. 821 * 822 * Based on: 823 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 824 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 825 * "Revision Guide for AMD NPT Family 0Fh Processors" 826 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 827 * and other miscellaneous reports. 828 * 829 * This is all rather pointless, these are cross 'brand' since the raw 830 * silicon is shared. 831 */ 832 static const char * 833 amd_amd64_name(struct cpu_info *ci) 834 { 835 static char family_str[32]; 836 837 /* Only called if family >= 15 */ 838 839 switch (ci->ci_family) { 840 case 15: 841 switch (ci->ci_model) { 842 case 0x21: /* rev JH-E1/E6 */ 843 case 0x41: /* rev JH-F2 */ 844 return "Dual-Core Opteron"; 845 case 0x23: /* rev JH-E6 (Toledo) */ 846 return "Dual-Core Opteron or Athlon 64 X2"; 847 case 0x43: /* rev JH-F2 (Windsor) */ 848 return "Athlon 64 FX or Athlon 64 X2"; 849 case 0x24: /* rev SH-E5 (Lancaster?) */ 850 return "Mobile Athlon 64 or Turion 64"; 851 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 852 return "Opteron or Athlon 64 FX"; 853 case 0x15: /* rev SH-D0 */ 854 case 0x25: /* rev SH-E4 */ 855 return "Opteron"; 856 case 0x27: /* rev DH-E4, SH-E4 */ 857 return "Athlon 64 or Athlon 64 FX or Opteron"; 858 case 0x48: /* rev BH-F2 */ 859 return "Turion 64 X2"; 860 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 861 case 0x07: /* rev SH-CG (ClawHammer) */ 862 case 0x0b: /* rev CH-CG */ 863 case 0x14: /* rev SH-D0 */ 864 case 0x17: /* rev SH-D0 */ 865 case 0x1b: /* rev CH-D0 */ 866 return "Athlon 64"; 867 case 0x2b: /* rev BH-E4 (Manchester) */ 868 case 0x4b: /* rev BH-F2 (Windsor) */ 869 return "Athlon 64 X2"; 870 case 0x6b: /* rev BH-G1 (Brisbane) */ 871 return "Athlon X2 or Athlon 64 X2"; 872 case 0x08: /* rev CH-CG */ 873 case 0x0c: /* rev DH-CG (Newcastle) */ 874 case 0x0e: /* rev DH-CG (Newcastle?) */ 875 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 876 case 0x18: /* rev CH-D0 */ 877 case 0x1c: /* rev DH-D0 (Winchester) */ 878 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 879 case 0x2c: /* rev DH-E3/E6 */ 880 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 881 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 882 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 883 case 0x6f: /* rev DH-G1 */ 884 return "Athlon 64 or Sempron"; 885 default: 886 break; 887 } 888 return "Unknown AMD64 CPU"; 889 890 #if 0 891 case 16: 892 return "Family 10h"; 893 case 17: 894 return "Family 11h"; 895 case 18: 896 return "Family 12h"; 897 case 19: 898 return "Family 14h"; 899 case 20: 900 return "Family 15h"; 901 #endif 902 903 default: 904 break; 905 } 906 907 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 908 return family_str; 909 } 910 911 static void 912 intel_family_new_probe(struct cpu_info *ci) 913 { 914 uint32_t descs[4]; 915 916 x86_cpuid(0x80000000, descs); 917 918 /* 919 * Determine extended feature flags. 920 */ 921 if (descs[0] >= 0x80000001) { 922 x86_cpuid(0x80000001, descs); 923 ci->ci_feat_val[2] |= descs[3]; 924 ci->ci_feat_val[3] |= descs[2]; 925 } 926 } 927 928 static void 929 via_cpu_probe(struct cpu_info *ci) 930 { 931 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 932 u_int descs[4]; 933 u_int lfunc; 934 935 /* 936 * Determine the largest extended function value. 937 */ 938 x86_cpuid(0x80000000, descs); 939 lfunc = descs[0]; 940 941 /* 942 * Determine the extended feature flags. 943 */ 944 if (lfunc >= 0x80000001) { 945 x86_cpuid(0x80000001, descs); 946 ci->ci_feat_val[2] |= descs[3]; 947 } 948 949 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 950 return; 951 952 /* Nehemiah or Esther */ 953 x86_cpuid(0xc0000000, descs); 954 lfunc = descs[0]; 955 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 956 return; 957 958 x86_cpuid(0xc0000001, descs); 959 lfunc = descs[3]; 960 ci->ci_feat_val[4] = lfunc; 961 } 962 963 static void 964 amd_family6_probe(struct cpu_info *ci) 965 { 966 uint32_t descs[4]; 967 char *p; 968 size_t i; 969 970 x86_cpuid(0x80000000, descs); 971 972 /* 973 * Determine the extended feature flags. 974 */ 975 if (descs[0] >= 0x80000001) { 976 x86_cpuid(0x80000001, descs); 977 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 978 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 979 } 980 981 if (*cpu_brand_string == '\0') 982 return; 983 984 for (i = 1; i < __arraycount(amd_brand); i++) 985 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 986 ci->ci_brand_id = i; 987 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 988 break; 989 } 990 } 991 992 /* 993 * Get cache info from one of the following: 994 * Intel Deterministic Cache Parameter Leaf (0x04) 995 * AMD Cache Topology Information Leaf (0x8000001d) 996 */ 997 static void 998 cpu_dcp_cacheinfo(struct cpu_info *ci, uint32_t leaf) 999 { 1000 u_int descs[4]; 1001 int type, level, ways, partitions, linesize, sets, totalsize; 1002 int caitype = -1; 1003 int i; 1004 1005 for (i = 0; ; i++) { 1006 x86_cpuid2(leaf, i, descs); 1007 type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE); 1008 if (type == CPUID_DCP_CACHETYPE_N) 1009 break; 1010 level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL); 1011 switch (level) { 1012 case 1: 1013 if (type == CPUID_DCP_CACHETYPE_I) 1014 caitype = CAI_ICACHE; 1015 else if (type == CPUID_DCP_CACHETYPE_D) 1016 caitype = CAI_DCACHE; 1017 else 1018 caitype = -1; 1019 break; 1020 case 2: 1021 if (type == CPUID_DCP_CACHETYPE_U) 1022 caitype = CAI_L2CACHE; 1023 else 1024 caitype = -1; 1025 break; 1026 case 3: 1027 if (type == CPUID_DCP_CACHETYPE_U) 1028 caitype = CAI_L3CACHE; 1029 else 1030 caitype = -1; 1031 break; 1032 default: 1033 caitype = -1; 1034 break; 1035 } 1036 if (caitype == -1) { 1037 aprint_error_dev(ci->ci_dev, 1038 "error: unknown cache level&type (%d & %d)\n", 1039 level, type); 1040 continue; 1041 } 1042 ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1; 1043 partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS) 1044 + 1; 1045 linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE) 1046 + 1; 1047 sets = descs[2] + 1; 1048 totalsize = ways * partitions * linesize * sets; 1049 ci->ci_cinfo[caitype].cai_totalsize = totalsize; 1050 ci->ci_cinfo[caitype].cai_associativity = ways; 1051 ci->ci_cinfo[caitype].cai_linesize = linesize; 1052 } 1053 } 1054 1055 static void 1056 intel_cpu_cacheinfo(struct cpu_info *ci) 1057 { 1058 const struct x86_cache_info *cai; 1059 u_int descs[4]; 1060 int iterations, i, j; 1061 int type, level, ways, linesize, sets; 1062 int caitype = -1; 1063 uint8_t desc; 1064 1065 /* Return if the cpu is old pre-cpuid instruction cpu */ 1066 if (ci->ci_cpu_type >= 0) 1067 return; 1068 1069 if (ci->ci_cpuid_level < 2) 1070 return; 1071 1072 /* 1073 * Parse the cache info from `cpuid leaf 2', if we have it. 1074 * XXX This is kinda ugly, but hey, so is the architecture... 1075 */ 1076 x86_cpuid(2, descs); 1077 iterations = descs[0] & 0xff; 1078 while (iterations-- > 0) { 1079 for (i = 0; i < 4; i++) { 1080 if (descs[i] & 0x80000000) 1081 continue; 1082 for (j = 0; j < 4; j++) { 1083 /* 1084 * The least significant byte in EAX 1085 * ((desc[0] >> 0) & 0xff) is always 0x01 and 1086 * it should be ignored. 1087 */ 1088 if (i == 0 && j == 0) 1089 continue; 1090 desc = (descs[i] >> (j * 8)) & 0xff; 1091 if (desc == 0) 1092 continue; 1093 cai = cache_info_lookup(intel_cpuid_cache_info, 1094 desc); 1095 if (cai != NULL) 1096 ci->ci_cinfo[cai->cai_index] = *cai; 1097 else if ((verbose != 0) && (desc != 0xff) 1098 && (desc != 0xfe)) 1099 aprint_error_dev(ci->ci_dev, "error:" 1100 " Unknown cacheinfo desc %02x\n", 1101 desc); 1102 } 1103 } 1104 x86_cpuid(2, descs); 1105 } 1106 1107 if (ci->ci_cpuid_level < 4) 1108 return; 1109 1110 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1111 cpu_dcp_cacheinfo(ci, 4); 1112 1113 if (ci->ci_cpuid_level < 0x18) 1114 return; 1115 /* Parse the TLB info from `cpuid leaf 18H', if we have it. */ 1116 x86_cpuid(0x18, descs); 1117 iterations = descs[0]; 1118 for (i = 0; i <= iterations; i++) { 1119 uint32_t pgsize; 1120 bool full; 1121 1122 x86_cpuid2(0x18, i, descs); 1123 type = __SHIFTOUT(descs[3], CPUID_DATP_TCTYPE); 1124 if (type == CPUID_DATP_TCTYPE_N) 1125 continue; 1126 level = __SHIFTOUT(descs[3], CPUID_DATP_TCLEVEL); 1127 pgsize = __SHIFTOUT(descs[1], CPUID_DATP_PGSIZE); 1128 switch (level) { 1129 case 1: 1130 if (type == CPUID_DATP_TCTYPE_I) { 1131 switch (pgsize) { 1132 case CPUID_DATP_PGSIZE_4KB: 1133 caitype = CAI_ITLB; 1134 break; 1135 case CPUID_DATP_PGSIZE_2MB 1136 | CPUID_DATP_PGSIZE_4MB: 1137 caitype = CAI_ITLB2; 1138 break; 1139 case CPUID_DATP_PGSIZE_1GB: 1140 caitype = CAI_L1_1GBITLB; 1141 break; 1142 default: 1143 aprint_error_dev(ci->ci_dev, 1144 "error: unknown ITLB size (%d)\n", 1145 pgsize); 1146 caitype = CAI_ITLB; 1147 break; 1148 } 1149 } else if (type == CPUID_DATP_TCTYPE_D) { 1150 switch (pgsize) { 1151 case CPUID_DATP_PGSIZE_4KB: 1152 caitype = CAI_DTLB; 1153 break; 1154 case CPUID_DATP_PGSIZE_2MB 1155 | CPUID_DATP_PGSIZE_4MB: 1156 caitype = CAI_DTLB2; 1157 break; 1158 case CPUID_DATP_PGSIZE_1GB: 1159 caitype = CAI_L1_1GBDTLB; 1160 break; 1161 default: 1162 aprint_error_dev(ci->ci_dev, 1163 "error: unknown DTLB size (%d)\n", 1164 pgsize); 1165 caitype = CAI_DTLB; 1166 break; 1167 } 1168 } else 1169 caitype = -1; 1170 break; 1171 case 2: 1172 if (type == CPUID_DATP_TCTYPE_I) 1173 caitype = CAI_L2_ITLB; 1174 else if (type == CPUID_DATP_TCTYPE_D) 1175 caitype = CAI_L2_DTLB; 1176 else if (type == CPUID_DATP_TCTYPE_U) { 1177 switch (pgsize) { 1178 case CPUID_DATP_PGSIZE_4KB: 1179 caitype = CAI_L2_STLB; 1180 break; 1181 case CPUID_DATP_PGSIZE_4KB 1182 | CPUID_DATP_PGSIZE_2MB: 1183 caitype = CAI_L2_STLB2; 1184 break; 1185 case CPUID_DATP_PGSIZE_2MB 1186 | CPUID_DATP_PGSIZE_4MB: 1187 caitype = CAI_L2_STLB3; 1188 break; 1189 default: 1190 aprint_error_dev(ci->ci_dev, 1191 "error: unknown L2 STLB size (%d)\n", 1192 pgsize); 1193 caitype = CAI_DTLB; 1194 break; 1195 } 1196 } else 1197 caitype = -1; 1198 break; 1199 case 3: 1200 /* XXX need work for L3 TLB */ 1201 caitype = CAI_L3CACHE; 1202 break; 1203 default: 1204 caitype = -1; 1205 break; 1206 } 1207 if (caitype == -1) { 1208 aprint_error_dev(ci->ci_dev, 1209 "error: unknown TLB level&type (%d & %d)\n", 1210 level, type); 1211 continue; 1212 } 1213 switch (pgsize) { 1214 case CPUID_DATP_PGSIZE_4KB: 1215 linesize = 4 * 1024; 1216 break; 1217 case CPUID_DATP_PGSIZE_2MB: 1218 linesize = 2 * 1024 * 1024; 1219 break; 1220 case CPUID_DATP_PGSIZE_4MB: 1221 linesize = 4 * 1024 * 1024; 1222 break; 1223 case CPUID_DATP_PGSIZE_1GB: 1224 linesize = 1024 * 1024 * 1024; 1225 break; 1226 case CPUID_DATP_PGSIZE_2MB | CPUID_DATP_PGSIZE_4MB: 1227 aprint_error_dev(ci->ci_dev, 1228 "WARINING: Currently 2M/4M info can't print correctly\n"); 1229 linesize = 4 * 1024 * 1024; 1230 break; 1231 default: 1232 aprint_error_dev(ci->ci_dev, 1233 "error: Unknown size combination\n"); 1234 linesize = 4 * 1024; 1235 break; 1236 } 1237 ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS); 1238 sets = descs[2]; 1239 full = descs[3] & CPUID_DATP_FULLASSOC; 1240 ci->ci_cinfo[caitype].cai_totalsize 1241 = ways * sets; /* entries */ 1242 ci->ci_cinfo[caitype].cai_associativity 1243 = full ? 0xff : ways; 1244 ci->ci_cinfo[caitype].cai_linesize = linesize; /* pg size */ 1245 } 1246 } 1247 1248 static const struct x86_cache_info amd_cpuid_l2l3cache_assoc_info[] = 1249 AMD_L2L3CACHE_INFO; 1250 1251 static void 1252 amd_cpu_cacheinfo(struct cpu_info *ci) 1253 { 1254 const struct x86_cache_info *cp; 1255 struct x86_cache_info *cai; 1256 u_int descs[4]; 1257 u_int lfunc; 1258 1259 /* K5 model 0 has none of this info. */ 1260 if (ci->ci_family == 5 && ci->ci_model == 0) 1261 return; 1262 1263 /* Determine the largest extended function value. */ 1264 x86_cpuid(0x80000000, descs); 1265 lfunc = descs[0]; 1266 1267 if (lfunc < 0x80000005) 1268 return; 1269 1270 /* Determine L1 cache/TLB info. */ 1271 x86_cpuid(0x80000005, descs); 1272 1273 /* K6-III and higher have large page TLBs. */ 1274 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1275 cai = &ci->ci_cinfo[CAI_ITLB2]; 1276 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1277 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1278 cai->cai_linesize = largepagesize; 1279 1280 cai = &ci->ci_cinfo[CAI_DTLB2]; 1281 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1282 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1283 cai->cai_linesize = largepagesize; 1284 } 1285 1286 cai = &ci->ci_cinfo[CAI_ITLB]; 1287 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1288 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1289 cai->cai_linesize = (4 * 1024); 1290 1291 cai = &ci->ci_cinfo[CAI_DTLB]; 1292 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1293 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1294 cai->cai_linesize = (4 * 1024); 1295 1296 cai = &ci->ci_cinfo[CAI_DCACHE]; 1297 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1298 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1299 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1300 1301 cai = &ci->ci_cinfo[CAI_ICACHE]; 1302 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1303 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1304 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1305 1306 if (lfunc < 0x80000006) 1307 return; 1308 1309 /* Determine L2 cache/TLB info. */ 1310 x86_cpuid(0x80000006, descs); 1311 1312 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1313 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1314 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1315 cai->cai_linesize = (4 * 1024); 1316 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1317 cai->cai_associativity); 1318 if (cp != NULL) 1319 cai->cai_associativity = cp->cai_associativity; 1320 else 1321 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1322 1323 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1324 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1325 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1326 cai->cai_linesize = largepagesize; 1327 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1328 cai->cai_associativity); 1329 if (cp != NULL) 1330 cai->cai_associativity = cp->cai_associativity; 1331 else 1332 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1333 1334 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1335 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1336 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1337 cai->cai_linesize = (4 * 1024); 1338 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1339 cai->cai_associativity); 1340 if (cp != NULL) 1341 cai->cai_associativity = cp->cai_associativity; 1342 else 1343 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1344 1345 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1346 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1347 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1348 cai->cai_linesize = largepagesize; 1349 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1350 cai->cai_associativity); 1351 if (cp != NULL) 1352 cai->cai_associativity = cp->cai_associativity; 1353 else 1354 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1355 1356 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1357 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1358 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1359 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1360 1361 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1362 cai->cai_associativity); 1363 if (cp != NULL) 1364 cai->cai_associativity = cp->cai_associativity; 1365 else 1366 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1367 1368 /* Determine L3 cache info on AMD Family 10h and newer processors */ 1369 if (ci->ci_family >= 0x10) { 1370 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1371 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1372 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1373 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1374 1375 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1376 cai->cai_associativity); 1377 if (cp != NULL) 1378 cai->cai_associativity = cp->cai_associativity; 1379 else 1380 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1381 } 1382 1383 if (lfunc < 0x80000019) 1384 return; 1385 1386 /* Determine 1GB TLB info. */ 1387 x86_cpuid(0x80000019, descs); 1388 1389 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1390 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1391 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1392 cai->cai_linesize = (1024 * 1024 * 1024); 1393 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1394 cai->cai_associativity); 1395 if (cp != NULL) 1396 cai->cai_associativity = cp->cai_associativity; 1397 else 1398 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1399 1400 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1401 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1402 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1403 cai->cai_linesize = (1024 * 1024 * 1024); 1404 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1405 cai->cai_associativity); 1406 if (cp != NULL) 1407 cai->cai_associativity = cp->cai_associativity; 1408 else 1409 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1410 1411 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1412 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1413 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1414 cai->cai_linesize = (1024 * 1024 * 1024); 1415 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1416 cai->cai_associativity); 1417 if (cp != NULL) 1418 cai->cai_associativity = cp->cai_associativity; 1419 else 1420 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1421 1422 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1423 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1424 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1425 cai->cai_linesize = (1024 * 1024 * 1024); 1426 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1427 cai->cai_associativity); 1428 if (cp != NULL) 1429 cai->cai_associativity = cp->cai_associativity; 1430 else 1431 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1432 1433 if (lfunc < 0x8000001d) 1434 return; 1435 1436 cpu_dcp_cacheinfo(ci, 0x8000001d); 1437 } 1438 1439 static void 1440 via_cpu_cacheinfo(struct cpu_info *ci) 1441 { 1442 struct x86_cache_info *cai; 1443 int stepping; 1444 u_int descs[4]; 1445 u_int lfunc; 1446 1447 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1448 1449 /* 1450 * Determine the largest extended function value. 1451 */ 1452 x86_cpuid(0x80000000, descs); 1453 lfunc = descs[0]; 1454 1455 /* 1456 * Determine L1 cache/TLB info. 1457 */ 1458 if (lfunc < 0x80000005) { 1459 /* No L1 cache info available. */ 1460 return; 1461 } 1462 1463 x86_cpuid(0x80000005, descs); 1464 1465 cai = &ci->ci_cinfo[CAI_ITLB]; 1466 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1467 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1468 cai->cai_linesize = (4 * 1024); 1469 1470 cai = &ci->ci_cinfo[CAI_DTLB]; 1471 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1472 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1473 cai->cai_linesize = (4 * 1024); 1474 1475 cai = &ci->ci_cinfo[CAI_DCACHE]; 1476 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1477 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1478 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1479 if (ci->ci_model == 9 && stepping == 8) { 1480 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1481 cai->cai_associativity = 2; 1482 } 1483 1484 cai = &ci->ci_cinfo[CAI_ICACHE]; 1485 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1486 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1487 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1488 if (ci->ci_model == 9 && stepping == 8) { 1489 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1490 cai->cai_associativity = 2; 1491 } 1492 1493 /* 1494 * Determine L2 cache/TLB info. 1495 */ 1496 if (lfunc < 0x80000006) { 1497 /* No L2 cache info available. */ 1498 return; 1499 } 1500 1501 x86_cpuid(0x80000006, descs); 1502 1503 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1504 if (ci->ci_model >= 9) { 1505 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1506 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1507 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1508 } else { 1509 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1510 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1511 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1512 } 1513 } 1514 1515 static void 1516 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1517 { 1518 u_int descs[4]; 1519 1520 x86_cpuid(0x80860007, descs); 1521 *frequency = descs[0]; 1522 *voltage = descs[1]; 1523 *percentage = descs[2]; 1524 } 1525 1526 static void 1527 transmeta_cpu_info(struct cpu_info *ci) 1528 { 1529 u_int descs[4], nreg; 1530 u_int frequency, voltage, percentage; 1531 1532 x86_cpuid(0x80860000, descs); 1533 nreg = descs[0]; 1534 if (nreg >= 0x80860001) { 1535 x86_cpuid(0x80860001, descs); 1536 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1537 (descs[1] >> 24) & 0xff, 1538 (descs[1] >> 16) & 0xff, 1539 (descs[1] >> 8) & 0xff, 1540 descs[1] & 0xff); 1541 } 1542 if (nreg >= 0x80860002) { 1543 x86_cpuid(0x80860002, descs); 1544 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1545 (descs[1] >> 24) & 0xff, 1546 (descs[1] >> 16) & 0xff, 1547 (descs[1] >> 8) & 0xff, 1548 descs[1] & 0xff, 1549 descs[2]); 1550 } 1551 if (nreg >= 0x80860006) { 1552 union { 1553 char text[65]; 1554 u_int descs[4][4]; 1555 } info; 1556 int i; 1557 1558 for (i=0; i<4; i++) { 1559 x86_cpuid(0x80860003 + i, info.descs[i]); 1560 } 1561 info.text[64] = '\0'; 1562 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1563 } 1564 1565 if (nreg >= 0x80860007) { 1566 tmx86_get_longrun_status(&frequency, 1567 &voltage, &percentage); 1568 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1569 frequency, voltage, percentage); 1570 } 1571 } 1572 1573 static void 1574 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1575 { 1576 u_int descs[4]; 1577 int i; 1578 uint32_t brand[12]; 1579 1580 memset(ci, 0, sizeof(*ci)); 1581 ci->ci_dev = cpuname; 1582 1583 ci->ci_cpu_type = x86_identify(); 1584 if (ci->ci_cpu_type >= 0) { 1585 /* Old pre-cpuid instruction cpu */ 1586 ci->ci_cpuid_level = -1; 1587 return; 1588 } 1589 1590 /* 1591 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1592 * function. 1593 */ 1594 1595 /* 1596 * Fn0000_0000: 1597 * - Save cpuid max level. 1598 * - Save vendor string. 1599 */ 1600 x86_cpuid(0, descs); 1601 ci->ci_cpuid_level = descs[0]; 1602 /* Save vendor string */ 1603 ci->ci_vendor[0] = descs[1]; 1604 ci->ci_vendor[2] = descs[2]; 1605 ci->ci_vendor[1] = descs[3]; 1606 ci->ci_vendor[3] = 0; 1607 1608 /* 1609 * Fn8000_0000: 1610 * - Get cpuid extended function's max level. 1611 */ 1612 x86_cpuid(0x80000000, descs); 1613 if (descs[0] >= 0x80000000) 1614 ci->ci_cpuid_extlevel = descs[0]; 1615 else { 1616 /* Set lower value than 0x80000000 */ 1617 ci->ci_cpuid_extlevel = 0; 1618 } 1619 1620 /* 1621 * Fn8000_000[2-4]: 1622 * - Save brand string. 1623 */ 1624 if (ci->ci_cpuid_extlevel >= 0x80000004) { 1625 x86_cpuid(0x80000002, brand); 1626 x86_cpuid(0x80000003, brand + 4); 1627 x86_cpuid(0x80000004, brand + 8); 1628 for (i = 0; i < 48; i++) 1629 if (((char *) brand)[i] != ' ') 1630 break; 1631 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1632 } 1633 1634 if (ci->ci_cpuid_level < 1) 1635 return; 1636 1637 /* 1638 * Fn0000_0001: 1639 * - Get CPU family, model and stepping (from eax). 1640 * - Initial local APIC ID and brand ID (from ebx) 1641 * - CPUID2 (from ecx) 1642 * - CPUID (from edx) 1643 */ 1644 x86_cpuid(1, descs); 1645 ci->ci_signature = descs[0]; 1646 1647 /* Extract full family/model values */ 1648 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1649 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1650 1651 /* Brand is low order 8 bits of ebx */ 1652 ci->ci_brand_id = __SHIFTOUT(descs[1], CPUID_BRAND_INDEX); 1653 /* Initial local APIC ID */ 1654 ci->ci_initapicid = __SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID); 1655 1656 ci->ci_feat_val[1] = descs[2]; 1657 ci->ci_feat_val[0] = descs[3]; 1658 1659 if (ci->ci_cpuid_level < 3) 1660 return; 1661 1662 /* 1663 * If the processor serial number misfeature is present and supported, 1664 * extract it here. 1665 */ 1666 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1667 ci->ci_cpu_serial[0] = ci->ci_signature; 1668 x86_cpuid(3, descs); 1669 ci->ci_cpu_serial[2] = descs[2]; 1670 ci->ci_cpu_serial[1] = descs[3]; 1671 } 1672 1673 if (ci->ci_cpuid_level < 0x7) 1674 return; 1675 1676 x86_cpuid(7, descs); 1677 ci->ci_feat_val[5] = descs[1]; 1678 ci->ci_feat_val[6] = descs[2]; 1679 ci->ci_feat_val[7] = descs[3]; 1680 1681 if (ci->ci_cpuid_level < 0xd) 1682 return; 1683 1684 /* Get support XCR0 bits */ 1685 x86_cpuid2(0xd, 0, descs); 1686 ci->ci_feat_val[8] = descs[0]; /* Actually 64 bits */ 1687 ci->ci_cur_xsave = descs[1]; 1688 ci->ci_max_xsave = descs[2]; 1689 1690 /* Additional flags (eg xsaveopt support) */ 1691 x86_cpuid2(0xd, 1, descs); 1692 ci->ci_feat_val[9] = descs[0]; /* Actually 64 bits */ 1693 } 1694 1695 static void 1696 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1697 { 1698 uint32_t descs[4]; 1699 char hv_sig[13]; 1700 char *p; 1701 const char *hv_name; 1702 int i; 1703 1704 /* 1705 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1706 * http://lkml.org/lkml/2008/10/1/246 1707 * 1708 * KB1009458: Mechanisms to determine if software is running in 1709 * a VMware virtual machine 1710 * http://kb.vmware.com/kb/1009458 1711 */ 1712 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1713 x86_cpuid(0x40000000, descs); 1714 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1715 memcpy(p, &descs[i], sizeof(descs[i])); 1716 *p = '\0'; 1717 /* 1718 * HV vendor ID string 1719 * ------------+-------------- 1720 * HAXM "HAXMHAXMHAXM" 1721 * KVM "KVMKVMKVM" 1722 * Microsoft "Microsoft Hv" 1723 * QEMU(TCG) "TCGTCGTCGTCG" 1724 * VMware "VMwareVMware" 1725 * Xen "XenVMMXenVMM" 1726 * NetBSD "___ NVMM ___" 1727 */ 1728 if (strncmp(hv_sig, "HAXMHAXMHAXM", 12) == 0) 1729 hv_name = "HAXM"; 1730 else if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1731 hv_name = "KVM"; 1732 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1733 hv_name = "Hyper-V"; 1734 else if (strncmp(hv_sig, "TCGTCGTCGTCG", 12) == 0) 1735 hv_name = "QEMU(TCG)"; 1736 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1737 hv_name = "VMware"; 1738 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1739 hv_name = "Xen"; 1740 else if (strncmp(hv_sig, "___ NVMM ___", 12) == 0) 1741 hv_name = "NVMM"; 1742 else 1743 hv_name = "unknown"; 1744 1745 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1746 } 1747 } 1748 1749 static void 1750 cpu_probe_features(struct cpu_info *ci) 1751 { 1752 const struct cpu_cpuid_nameclass *cpup = NULL; 1753 unsigned int i; 1754 1755 if (ci->ci_cpuid_level < 1) 1756 return; 1757 1758 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1759 if (!strncmp((char *)ci->ci_vendor, 1760 i386_cpuid_cpus[i].cpu_id, 12)) { 1761 cpup = &i386_cpuid_cpus[i]; 1762 break; 1763 } 1764 } 1765 1766 if (cpup == NULL) 1767 return; 1768 1769 i = ci->ci_family - CPU_MINFAMILY; 1770 1771 if (i >= __arraycount(cpup->cpu_family)) 1772 i = __arraycount(cpup->cpu_family) - 1; 1773 1774 if (cpup->cpu_family[i].cpu_probe == NULL) 1775 return; 1776 1777 (*cpup->cpu_family[i].cpu_probe)(ci); 1778 } 1779 1780 static void 1781 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1782 { 1783 char buf[32 * 16]; 1784 char *bp; 1785 1786 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1787 1788 if (val == 0 || fmt == NULL) 1789 return; 1790 1791 snprintb_m(buf, sizeof(buf), fmt, val, 1792 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1793 bp = buf; 1794 while (*bp != '\0') { 1795 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1796 bp += strlen(bp) + 1; 1797 } 1798 } 1799 1800 static void 1801 dump_descs(uint32_t leafstart, uint32_t leafend, const char *cpuname, 1802 const char *blockname) 1803 { 1804 uint32_t descs[4]; 1805 uint32_t leaf; 1806 1807 aprint_verbose("%s: highest %s info %08x\n", cpuname, blockname, 1808 leafend); 1809 1810 if (verbose) { 1811 for (leaf = leafstart; leaf <= leafend; leaf++) { 1812 x86_cpuid(leaf, descs); 1813 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1814 leaf, descs[0], descs[1], descs[2], descs[3]); 1815 } 1816 } 1817 } 1818 1819 static void 1820 identifycpu_cpuids_intel_0x04(struct cpu_info *ci) 1821 { 1822 u_int lp_max = 1; /* logical processors per package */ 1823 u_int smt_max; /* smt per core */ 1824 u_int core_max = 1; /* core per package */ 1825 u_int smt_bits, core_bits; 1826 uint32_t descs[4]; 1827 1828 /* 1829 * 253668.pdf 7.10.2 1830 */ 1831 1832 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1833 x86_cpuid(1, descs); 1834 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1835 } 1836 x86_cpuid2(4, 0, descs); 1837 core_max = __SHIFTOUT(descs[0], CPUID_DCP_CORE_P_PKG) + 1; 1838 1839 assert(lp_max >= core_max); 1840 smt_max = lp_max / core_max; 1841 smt_bits = ilog2(smt_max - 1) + 1; 1842 core_bits = ilog2(core_max - 1) + 1; 1843 1844 if (smt_bits + core_bits) 1845 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1846 1847 if (core_bits) 1848 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1849 __BITS(smt_bits, smt_bits + core_bits - 1)); 1850 1851 if (smt_bits) 1852 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1853 __BITS((int)0, (int)(smt_bits - 1))); 1854 } 1855 1856 static void 1857 identifycpu_cpuids_intel_0x0b(struct cpu_info *ci) 1858 { 1859 const char *cpuname = ci->ci_dev; 1860 u_int smt_bits, core_bits, core_shift = 0, pkg_shift = 0; 1861 uint32_t descs[4]; 1862 int i; 1863 1864 x86_cpuid(0x0b, descs); 1865 if (descs[1] == 0) { 1866 identifycpu_cpuids_intel_0x04(ci); 1867 return; 1868 } 1869 1870 for (i = 0; ; i++) { 1871 unsigned int shiftnum, lvltype; 1872 x86_cpuid2(0x0b, i, descs); 1873 1874 /* On invalid level, (EAX and) EBX return 0 */ 1875 if (descs[1] == 0) 1876 break; 1877 1878 shiftnum = __SHIFTOUT(descs[0], CPUID_TOP_SHIFTNUM); 1879 lvltype = __SHIFTOUT(descs[2], CPUID_TOP_LVLTYPE); 1880 switch (lvltype) { 1881 case CPUID_TOP_LVLTYPE_SMT: 1882 core_shift = shiftnum; 1883 break; 1884 case CPUID_TOP_LVLTYPE_CORE: 1885 pkg_shift = shiftnum; 1886 break; 1887 case CPUID_TOP_LVLTYPE_INVAL: 1888 aprint_verbose("%s: Invalid level type\n", cpuname); 1889 break; 1890 default: 1891 aprint_verbose("%s: Unknown level type(%d) \n", 1892 cpuname, lvltype); 1893 break; 1894 } 1895 } 1896 1897 assert(pkg_shift >= core_shift); 1898 smt_bits = core_shift; 1899 core_bits = pkg_shift - core_shift; 1900 1901 ci->ci_packageid = ci->ci_initapicid >> pkg_shift; 1902 1903 if (core_bits) 1904 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1905 __BITS(core_shift, pkg_shift - 1)); 1906 1907 if (smt_bits) 1908 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1909 __BITS((int)0, core_shift - 1)); 1910 } 1911 1912 static void 1913 identifycpu_cpuids_intel(struct cpu_info *ci) 1914 { 1915 const char *cpuname = ci->ci_dev; 1916 1917 if (ci->ci_cpuid_level >= 0x0b) 1918 identifycpu_cpuids_intel_0x0b(ci); 1919 else if (ci->ci_cpuid_level >= 4) 1920 identifycpu_cpuids_intel_0x04(ci); 1921 1922 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1923 ci->ci_packageid); 1924 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1925 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1926 } 1927 1928 static void 1929 identifycpu_cpuids_amd(struct cpu_info *ci) 1930 { 1931 const char *cpuname = ci->ci_dev; 1932 u_int lp_max, core_max; 1933 int n, cpu_family, apic_id, smt_bits, core_bits = 0; 1934 uint32_t descs[4]; 1935 1936 apic_id = ci->ci_initapicid; 1937 cpu_family = CPUID_TO_FAMILY(ci->ci_signature); 1938 1939 if (cpu_family < 0xf) 1940 return; 1941 1942 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1943 x86_cpuid(1, descs); 1944 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1945 1946 if (cpu_family >= 0x10 && ci->ci_max_ext_cpuid >= 0x8000008) { 1947 x86_cpuid(0x8000008, descs); 1948 core_max = (descs[2] & 0xff) + 1; 1949 n = (descs[2] >> 12) & 0x0f; 1950 if (n != 0) 1951 core_bits = n; 1952 } 1953 } else { 1954 lp_max = 1; 1955 } 1956 core_max = lp_max; 1957 1958 smt_bits = ilog2((lp_max / core_max) - 1) + 1; 1959 if (core_bits == 0) 1960 core_bits = ilog2(core_max - 1) + 1; 1961 1962 #if 0 /* MSRs need kernel mode */ 1963 if (cpu_family < 0x11) { 1964 const uint64_t reg = rdmsr(MSR_NB_CFG); 1965 if ((reg & NB_CFG_INITAPICCPUIDLO) == 0) { 1966 const u_int node_id = apic_id & __BITS(0, 2); 1967 apic_id = (cpu_family == 0xf) ? 1968 (apic_id >> core_bits) | (node_id << core_bits) : 1969 (apic_id >> 5) | (node_id << 2); 1970 } 1971 } 1972 #endif 1973 1974 if (cpu_family == 0x17) { 1975 x86_cpuid(0x8000001e, descs); 1976 const u_int threads = ((descs[1] >> 8) & 0xff) + 1; 1977 smt_bits = ilog2(threads); 1978 core_bits -= smt_bits; 1979 } 1980 1981 if (smt_bits + core_bits) { 1982 if (smt_bits + core_bits < 32) 1983 ci->ci_packageid = 0; 1984 } 1985 if (core_bits) { 1986 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1987 ci->ci_coreid = __SHIFTOUT(apic_id, core_mask); 1988 } 1989 if (smt_bits) { 1990 u_int smt_mask = __BITS(0, smt_bits - 1); 1991 ci->ci_smtid = __SHIFTOUT(apic_id, smt_mask); 1992 } 1993 1994 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1995 ci->ci_packageid); 1996 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1997 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1998 } 1999 2000 static void 2001 identifycpu_cpuids(struct cpu_info *ci) 2002 { 2003 const char *cpuname = ci->ci_dev; 2004 2005 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 2006 ci->ci_packageid = ci->ci_initapicid; 2007 ci->ci_coreid = 0; 2008 ci->ci_smtid = 0; 2009 2010 if (cpu_vendor == CPUVENDOR_INTEL) 2011 identifycpu_cpuids_intel(ci); 2012 else if (cpu_vendor == CPUVENDOR_AMD) 2013 identifycpu_cpuids_amd(ci); 2014 } 2015 2016 void 2017 identifycpu(int fd, const char *cpuname) 2018 { 2019 const char *name = "", *modifier, *vendorname, *brand = ""; 2020 int class = CPUCLASS_386; 2021 unsigned int i; 2022 int modif, family; 2023 const struct cpu_cpuid_nameclass *cpup = NULL; 2024 const struct cpu_cpuid_family *cpufam; 2025 struct cpu_info *ci, cistore; 2026 u_int descs[4]; 2027 size_t sz; 2028 struct cpu_ucode_version ucode; 2029 union { 2030 struct cpu_ucode_version_amd amd; 2031 struct cpu_ucode_version_intel1 intel1; 2032 } ucvers; 2033 2034 ci = &cistore; 2035 cpu_probe_base_features(ci, cpuname); 2036 dump_descs(0x00000000, ci->ci_cpuid_level, cpuname, "basic"); 2037 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 2038 x86_cpuid(0x40000000, descs); 2039 dump_descs(0x40000000, descs[0], cpuname, "hypervisor"); 2040 } 2041 dump_descs(0x80000000, ci->ci_cpuid_extlevel, cpuname, "extended"); 2042 2043 cpu_probe_hv_features(ci, cpuname); 2044 cpu_probe_features(ci); 2045 2046 if (ci->ci_cpu_type >= 0) { 2047 /* Old pre-cpuid instruction cpu */ 2048 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 2049 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 2050 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 2051 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 2052 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 2053 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 2054 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 2055 modifier = ""; 2056 } else { 2057 /* CPU which support cpuid instruction */ 2058 modif = (ci->ci_signature >> 12) & 0x3; 2059 family = ci->ci_family; 2060 if (family < CPU_MINFAMILY) 2061 errx(1, "identifycpu: strange family value"); 2062 if (family > CPU_MAXFAMILY) 2063 family = CPU_MAXFAMILY; 2064 2065 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 2066 if (!strncmp((char *)ci->ci_vendor, 2067 i386_cpuid_cpus[i].cpu_id, 12)) { 2068 cpup = &i386_cpuid_cpus[i]; 2069 break; 2070 } 2071 } 2072 2073 if (cpup == NULL) { 2074 cpu_vendor = CPUVENDOR_UNKNOWN; 2075 if (ci->ci_vendor[0] != '\0') 2076 vendorname = (char *)&ci->ci_vendor[0]; 2077 else 2078 vendorname = "Unknown"; 2079 class = family - 3; 2080 modifier = ""; 2081 name = ""; 2082 ci->ci_info = NULL; 2083 } else { 2084 cpu_vendor = cpup->cpu_vendor; 2085 vendorname = cpup->cpu_vendorname; 2086 modifier = modifiers[modif]; 2087 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 2088 name = cpufam->cpu_models[ci->ci_model]; 2089 if (name == NULL || *name == '\0') 2090 name = cpufam->cpu_model_default; 2091 class = cpufam->cpu_class; 2092 ci->ci_info = cpufam->cpu_info; 2093 2094 if (cpu_vendor == CPUVENDOR_INTEL) { 2095 if (ci->ci_family == 6 && ci->ci_model >= 5) { 2096 const char *tmp; 2097 tmp = intel_family6_name(ci); 2098 if (tmp != NULL) 2099 name = tmp; 2100 } 2101 if (ci->ci_family == 15 && 2102 ci->ci_brand_id < 2103 __arraycount(i386_intel_brand) && 2104 i386_intel_brand[ci->ci_brand_id]) 2105 name = 2106 i386_intel_brand[ci->ci_brand_id]; 2107 } 2108 2109 if (cpu_vendor == CPUVENDOR_AMD) { 2110 if (ci->ci_family == 6 && ci->ci_model >= 6) { 2111 if (ci->ci_brand_id == 1) 2112 /* 2113 * It's Duron. We override the 2114 * name, since it might have 2115 * been misidentified as Athlon. 2116 */ 2117 name = 2118 amd_brand[ci->ci_brand_id]; 2119 else 2120 brand = amd_brand_name; 2121 } 2122 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 2123 == 0xf) { 2124 /* Identify AMD64 CPU names. */ 2125 const char *tmp; 2126 tmp = amd_amd64_name(ci); 2127 if (tmp != NULL) 2128 name = tmp; 2129 } 2130 } 2131 2132 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 2133 vendorname = "VIA"; 2134 } 2135 } 2136 2137 ci->ci_cpu_class = class; 2138 2139 sz = sizeof(ci->ci_tsc_freq); 2140 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 2141 sz = sizeof(use_pae); 2142 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 2143 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 2144 2145 /* 2146 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 2147 * we try to determine from the family/model values. 2148 */ 2149 if (*cpu_brand_string != '\0') 2150 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 2151 2152 aprint_normal("%s: %s", cpuname, vendorname); 2153 if (*modifier) 2154 aprint_normal(" %s", modifier); 2155 if (*name) 2156 aprint_normal(" %s", name); 2157 if (*brand) 2158 aprint_normal(" %s", brand); 2159 aprint_normal(" (%s-class)", classnames[class]); 2160 2161 if (ci->ci_tsc_freq != 0) 2162 aprint_normal(", %ju.%02ju MHz", 2163 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 2164 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 2165 aprint_normal("\n"); 2166 2167 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 2168 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 2169 if (ci->ci_signature != 0) 2170 aprint_normal(" (id %#x)", ci->ci_signature); 2171 aprint_normal("\n"); 2172 2173 if (ci->ci_info) 2174 (*ci->ci_info)(ci); 2175 2176 /* 2177 * display CPU feature flags 2178 */ 2179 2180 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 2181 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 2182 2183 /* These next two are actually common definitions! */ 2184 print_bits(cpuname, "features2", 2185 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 2186 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 2187 print_bits(cpuname, "features3", 2188 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 2189 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 2190 2191 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 2192 ci->ci_feat_val[4]); 2193 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2194 print_bits(cpuname, "features5", CPUID_SEF_FLAGS, 2195 ci->ci_feat_val[5]); 2196 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2197 print_bits(cpuname, "features6", CPUID_SEF_FLAGS1, 2198 ci->ci_feat_val[6]); 2199 2200 if (cpu_vendor == CPUVENDOR_INTEL) 2201 print_bits(cpuname, "features7", CPUID_SEF_FLAGS2, 2202 ci->ci_feat_val[7]); 2203 2204 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[8]); 2205 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 2206 ci->ci_feat_val[9]); 2207 2208 if (ci->ci_max_xsave != 0) { 2209 aprint_normal("%s: xsave area size: current %d, maximum %d", 2210 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 2211 aprint_normal(", xgetbv %sabled\n", 2212 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 2213 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 2214 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 2215 x86_xgetbv()); 2216 } 2217 2218 x86_print_cache_and_tlb_info(ci); 2219 2220 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 2221 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 2222 cpuname, 2223 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 2224 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 2225 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 2226 } 2227 2228 if (ci->ci_cpu_class == CPUCLASS_386) 2229 errx(1, "NetBSD requires an 80486 or later processor"); 2230 2231 if (ci->ci_cpu_type == CPU_486DLC) { 2232 #ifndef CYRIX_CACHE_WORKS 2233 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 2234 #else 2235 #ifndef CYRIX_CACHE_REALLY_WORKS 2236 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 2237 #else 2238 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 2239 #endif 2240 #endif 2241 } 2242 2243 /* 2244 * Everything past this point requires a Pentium or later. 2245 */ 2246 if (ci->ci_cpuid_level < 0) 2247 return; 2248 2249 identifycpu_cpuids(ci); 2250 2251 if ((ci->ci_cpuid_level >= 5) 2252 && ((cpu_vendor == CPUVENDOR_INTEL) 2253 || (cpu_vendor == CPUVENDOR_AMD))) { 2254 uint16_t lmin, lmax; 2255 x86_cpuid(5, descs); 2256 2257 print_bits(cpuname, "MONITOR/MWAIT extensions", 2258 CPUID_MON_FLAGS, descs[2]); 2259 lmin = __SHIFTOUT(descs[0], CPUID_MON_MINSIZE); 2260 lmax = __SHIFTOUT(descs[1], CPUID_MON_MAXSIZE); 2261 aprint_normal("%s: monitor-line size %hu", cpuname, lmin); 2262 if (lmin != lmax) 2263 aprint_normal("-%hu", lmax); 2264 aprint_normal("\n"); 2265 2266 for (i = 0; i <= 7; i++) { 2267 unsigned int num = CPUID_MON_SUBSTATE(descs[3], i); 2268 2269 if (num != 0) 2270 aprint_normal("%s: C%u substates %u\n", 2271 cpuname, i, num); 2272 } 2273 } 2274 if ((ci->ci_cpuid_level >= 6) 2275 && ((cpu_vendor == CPUVENDOR_INTEL) 2276 || (cpu_vendor == CPUVENDOR_AMD))) { 2277 x86_cpuid(6, descs); 2278 print_bits(cpuname, "DSPM-eax", CPUID_DSPM_FLAGS, descs[0]); 2279 print_bits(cpuname, "DSPM-ecx", CPUID_DSPM_FLAGS1, descs[2]); 2280 } 2281 if ((ci->ci_cpuid_level >= 7) 2282 && ((cpu_vendor == CPUVENDOR_INTEL) 2283 || (cpu_vendor == CPUVENDOR_AMD))) { 2284 x86_cpuid(7, descs); 2285 aprint_verbose("%s: SEF highest subleaf %08x\n", 2286 cpuname, descs[0]); 2287 } 2288 2289 if (cpu_vendor == CPUVENDOR_AMD) { 2290 x86_cpuid(0x80000000, descs); 2291 if (descs[0] >= 0x80000000) 2292 ci->ci_max_ext_cpuid = descs[0]; 2293 else 2294 ci->ci_max_ext_cpuid = 0; 2295 if (descs[0] >= 0x80000007) 2296 powernow_probe(ci); 2297 2298 if ((descs[0] >= 0x8000000a) 2299 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 2300 x86_cpuid(0x8000000a, descs); 2301 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 2302 descs[0] & 0xf); 2303 aprint_verbose("%s: SVM NASID %d\n", cpuname, 2304 descs[1]); 2305 print_bits(cpuname, "SVM features", 2306 CPUID_AMD_SVM_FLAGS, descs[3]); 2307 } 2308 } else if (cpu_vendor == CPUVENDOR_INTEL) { 2309 int32_t bi_index; 2310 2311 for (bi_index = 1; bi_index <= ci->ci_cpuid_level; bi_index++) { 2312 x86_cpuid(bi_index, descs); 2313 switch (bi_index) { 2314 case 0x0a: 2315 print_bits(cpuname, "Perfmon-eax", 2316 CPUID_PERF_FLAGS0, descs[0]); 2317 print_bits(cpuname, "Perfmon-ebx", 2318 CPUID_PERF_FLAGS1, descs[1]); 2319 print_bits(cpuname, "Perfmon-edx", 2320 CPUID_PERF_FLAGS3, descs[3]); 2321 break; 2322 default: 2323 #if 0 2324 aprint_verbose("%s: basic %08x-eax %08x\n", 2325 cpuname, bi_index, descs[0]); 2326 aprint_verbose("%s: basic %08x-ebx %08x\n", 2327 cpuname, bi_index, descs[1]); 2328 aprint_verbose("%s: basic %08x-ecx %08x\n", 2329 cpuname, bi_index, descs[2]); 2330 aprint_verbose("%s: basic %08x-edx %08x\n", 2331 cpuname, bi_index, descs[3]); 2332 #endif 2333 break; 2334 } 2335 } 2336 } 2337 2338 #ifdef INTEL_ONDEMAND_CLOCKMOD 2339 clockmod_init(); 2340 #endif 2341 2342 if (cpu_vendor == CPUVENDOR_AMD) 2343 ucode.loader_version = CPU_UCODE_LOADER_AMD; 2344 else if (cpu_vendor == CPUVENDOR_INTEL) 2345 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 2346 else 2347 return; 2348 2349 ucode.data = &ucvers; 2350 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 2351 #ifdef __i386__ 2352 struct cpu_ucode_version_64 ucode_64; 2353 if (errno != ENOTTY) 2354 return; 2355 /* Try the 64 bit ioctl */ 2356 memset(&ucode_64, 0, sizeof ucode_64); 2357 ucode_64.data = &ucvers; 2358 ucode_64.loader_version = ucode.loader_version; 2359 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 2360 return; 2361 #else 2362 return; 2363 #endif 2364 } 2365 2366 if (cpu_vendor == CPUVENDOR_AMD) 2367 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2368 else if (cpu_vendor == CPUVENDOR_INTEL) 2369 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2370 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2371 } 2372 2373 static const struct x86_cache_info * 2374 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 2375 { 2376 int i; 2377 2378 for (i = 0; cai[i].cai_desc != 0; i++) { 2379 if (cai[i].cai_desc == desc) 2380 return (&cai[i]); 2381 } 2382 2383 return (NULL); 2384 } 2385 2386 static const char * 2387 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2388 const char *sep) 2389 { 2390 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2391 char human_num[HUMAN_BUFSIZE]; 2392 2393 if (cai->cai_totalsize == 0) 2394 return sep; 2395 2396 if (sep == NULL) 2397 aprint_verbose_dev(ci->ci_dev, ""); 2398 else 2399 aprint_verbose("%s", sep); 2400 if (name != NULL) 2401 aprint_verbose("%s ", name); 2402 2403 if (cai->cai_string != NULL) { 2404 aprint_verbose("%s ", cai->cai_string); 2405 } else { 2406 (void)humanize_number(human_num, sizeof(human_num), 2407 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2408 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2409 } 2410 switch (cai->cai_associativity) { 2411 case 0: 2412 aprint_verbose("disabled"); 2413 break; 2414 case 1: 2415 aprint_verbose("direct-mapped"); 2416 break; 2417 case 0xff: 2418 aprint_verbose("fully associative"); 2419 break; 2420 default: 2421 aprint_verbose("%d-way", cai->cai_associativity); 2422 break; 2423 } 2424 return ", "; 2425 } 2426 2427 static const char * 2428 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2429 const char *sep) 2430 { 2431 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2432 char human_num[HUMAN_BUFSIZE]; 2433 2434 if (cai->cai_totalsize == 0) 2435 return sep; 2436 2437 if (sep == NULL) 2438 aprint_verbose_dev(ci->ci_dev, ""); 2439 else 2440 aprint_verbose("%s", sep); 2441 if (name != NULL) 2442 aprint_verbose("%s ", name); 2443 2444 if (cai->cai_string != NULL) { 2445 aprint_verbose("%s", cai->cai_string); 2446 } else { 2447 (void)humanize_number(human_num, sizeof(human_num), 2448 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2449 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2450 human_num); 2451 switch (cai->cai_associativity) { 2452 case 0: 2453 aprint_verbose("disabled"); 2454 break; 2455 case 1: 2456 aprint_verbose("direct-mapped"); 2457 break; 2458 case 0xff: 2459 aprint_verbose("fully associative"); 2460 break; 2461 default: 2462 aprint_verbose("%d-way", cai->cai_associativity); 2463 break; 2464 } 2465 } 2466 return ", "; 2467 } 2468 2469 static void 2470 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2471 { 2472 const char *sep = NULL; 2473 2474 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2475 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2476 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 2477 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 2478 if (sep != NULL) 2479 aprint_verbose("\n"); 2480 } 2481 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2482 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 2483 if (sep != NULL) 2484 aprint_verbose("\n"); 2485 } 2486 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2487 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 2488 if (sep != NULL) 2489 aprint_verbose("\n"); 2490 } 2491 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2492 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2493 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2494 if (sep != NULL) 2495 aprint_verbose("\n"); 2496 } 2497 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 2498 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 2499 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 2500 if (sep != NULL) 2501 aprint_verbose("\n"); 2502 } 2503 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 2504 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 2505 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 2506 if (sep != NULL) 2507 aprint_verbose("\n"); 2508 } 2509 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 2510 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 2511 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 2512 if (sep != NULL) 2513 aprint_verbose("\n"); 2514 } 2515 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 2516 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 2517 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 2518 if (sep != NULL) 2519 aprint_verbose("\n"); 2520 } 2521 if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) { 2522 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL); 2523 sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep); 2524 sep = print_tlb_config(ci, CAI_L2_STLB3, NULL, sep); 2525 if (sep != NULL) 2526 aprint_verbose("\n"); 2527 } 2528 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 2529 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", 2530 NULL); 2531 if (sep != NULL) 2532 aprint_verbose("\n"); 2533 } 2534 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 2535 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", 2536 NULL); 2537 if (sep != NULL) 2538 aprint_verbose("\n"); 2539 } 2540 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 2541 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", 2542 NULL); 2543 if (sep != NULL) 2544 aprint_verbose("\n"); 2545 } 2546 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 2547 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", 2548 NULL); 2549 if (sep != NULL) 2550 aprint_verbose("\n"); 2551 } 2552 } 2553 2554 static void 2555 powernow_probe(struct cpu_info *ci) 2556 { 2557 uint32_t regs[4]; 2558 char buf[256]; 2559 2560 x86_cpuid(0x80000007, regs); 2561 2562 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2563 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 2564 buf); 2565 } 2566 2567 bool 2568 identifycpu_bind(void) 2569 { 2570 2571 return true; 2572 } 2573 2574 int 2575 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2576 { 2577 struct cpu_info ci; 2578 int loader_version, res; 2579 struct cpu_ucode_version versreq; 2580 2581 cpu_probe_base_features(&ci, "unknown"); 2582 2583 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2584 loader_version = CPU_UCODE_LOADER_AMD; 2585 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2586 loader_version = CPU_UCODE_LOADER_INTEL1; 2587 else 2588 return -1; 2589 2590 /* check whether the kernel understands this loader version */ 2591 versreq.loader_version = loader_version; 2592 versreq.data = 0; 2593 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2594 if (res) 2595 return -1; 2596 2597 switch (loader_version) { 2598 case CPU_UCODE_LOADER_AMD: 2599 if (uc->cpu_nr != -1) { 2600 /* printf? */ 2601 return -1; 2602 } 2603 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2604 break; 2605 case CPU_UCODE_LOADER_INTEL1: 2606 if (uc->cpu_nr == -1) 2607 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2608 else 2609 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2610 break; 2611 default: /* can't happen */ 2612 return -1; 2613 } 2614 uc->loader_version = loader_version; 2615 return 0; 2616 } 2617
Indexes created Sat Sep 27 14:09:57 GMT 2025