i386.c revision 1.104.2.10
1 /* $NetBSD: i386.c,v 1.104.2.10 2022/01/31 17:51:00 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.104.2.10 2022/01/31 17:51:00 martin Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cpu_ucode.h> 85 86 #include "../cpuctl.h" 87 #include "cpuctl_i386.h" 88 89 /* Size of buffer for printing humanized numbers */ 90 #define HUMAN_BUFSIZE sizeof("999KB") 91 92 struct cpu_nocpuid_nameclass { 93 int cpu_vendor; 94 const char *cpu_vendorname; 95 const char *cpu_name; 96 int cpu_class; 97 void (*cpu_setup)(struct cpu_info *); 98 void (*cpu_cacheinfo)(struct cpu_info *); 99 void (*cpu_info)(struct cpu_info *); 100 }; 101 102 struct cpu_cpuid_nameclass { 103 const char *cpu_id; 104 int cpu_vendor; 105 const char *cpu_vendorname; 106 struct cpu_cpuid_family { 107 int cpu_class; 108 const char *cpu_models[256]; 109 const char *cpu_model_default; 110 void (*cpu_setup)(struct cpu_info *); 111 void (*cpu_probe)(struct cpu_info *); 112 void (*cpu_info)(struct cpu_info *); 113 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 114 }; 115 116 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 117 118 /* 119 * Map Brand ID from cpuid instruction to brand name. 120 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 121 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 122 * Architectures Software Developer's Manual, Volume 2A". 123 */ 124 static const char * const i386_intel_brand[] = { 125 "", /* Unsupported */ 126 "Celeron", /* Intel (R) Celeron (TM) processor */ 127 "Pentium III", /* Intel (R) Pentium (R) III processor */ 128 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 129 "Pentium III", /* Intel (R) Pentium (R) III processor */ 130 "", /* 0x05: Reserved */ 131 "Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */ 132 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 133 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 134 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 135 "Celeron", /* Intel (R) Celeron (TM) processor */ 136 "Xeon", /* Intel (R) Xeon (TM) processor */ 137 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 138 "", /* 0x0d: Reserved */ 139 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 140 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 141 "", /* 0x10: Reserved */ 142 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 143 "Celeron M", /* Intel (R) Celeron (R) M processor */ 144 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 145 "Celeron", /* Intel (R) Celeron (R) processor */ 146 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 147 "Pentium M", /* Intel (R) Pentium (R) M processor */ 148 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 149 }; 150 151 /* 152 * AMD processors don't have Brand IDs, so we need these names for probe. 153 */ 154 static const char * const amd_brand[] = { 155 "", 156 "Duron", /* AMD Duron(tm) */ 157 "MP", /* AMD Athlon(tm) MP */ 158 "XP", /* AMD Athlon(tm) XP */ 159 "4" /* AMD Athlon(tm) 4 */ 160 }; 161 162 int cpu_vendor; 163 static char cpu_brand_string[49]; 164 static char amd_brand_name[48]; 165 static int use_pae, largepagesize; 166 167 /* Setup functions */ 168 static void disable_tsc(struct cpu_info *); 169 static void amd_family5_setup(struct cpu_info *); 170 static void cyrix6x86_cpu_setup(struct cpu_info *); 171 static void winchip_cpu_setup(struct cpu_info *); 172 /* Brand/Model name functions */ 173 static const char *intel_family6_name(struct cpu_info *); 174 static const char *amd_amd64_name(struct cpu_info *); 175 /* Probe functions */ 176 static void amd_family6_probe(struct cpu_info *); 177 static void powernow_probe(struct cpu_info *); 178 static void intel_family_new_probe(struct cpu_info *); 179 static void via_cpu_probe(struct cpu_info *); 180 /* (Cache) Info functions */ 181 static void intel_cpu_cacheinfo(struct cpu_info *); 182 static void amd_cpu_cacheinfo(struct cpu_info *); 183 static void via_cpu_cacheinfo(struct cpu_info *); 184 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 185 static void transmeta_cpu_info(struct cpu_info *); 186 /* Common functions */ 187 static void cpu_probe_base_features(struct cpu_info *, const char *); 188 static void cpu_probe_hv_features(struct cpu_info *, const char *); 189 static void cpu_probe_features(struct cpu_info *); 190 static void print_bits(const char *, const char *, const char *, uint32_t); 191 static void identifycpu_cpuids(struct cpu_info *); 192 static const char *print_cache_config(struct cpu_info *, int, const char *, 193 const char *); 194 static const char *print_tlb_config(struct cpu_info *, int, const char *, 195 const char *); 196 static void x86_print_cache_and_tlb_info(struct cpu_info *); 197 198 /* 199 * Note: these are just the ones that may not have a cpuid instruction. 200 * We deal with the rest in a different way. 201 */ 202 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 203 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 204 NULL, NULL, NULL }, /* CPU_386SX */ 205 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 206 NULL, NULL, NULL }, /* CPU_386 */ 207 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 208 NULL, NULL, NULL }, /* CPU_486SX */ 209 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 210 NULL, NULL, NULL }, /* CPU_486 */ 211 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 212 NULL, NULL, NULL }, /* CPU_486DLC */ 213 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 214 NULL, NULL, NULL }, /* CPU_6x86 */ 215 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 216 NULL, NULL, NULL }, /* CPU_NX586 */ 217 }; 218 219 const char *classnames[] = { 220 "386", 221 "486", 222 "586", 223 "686" 224 }; 225 226 const char *modifiers[] = { 227 "", 228 "OverDrive", 229 "Dual", 230 "" 231 }; 232 233 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 234 { 235 /* 236 * For Intel processors, check Chapter 35Model-specific 237 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 238 * Software Developer's Manual, Volume 3C". 239 */ 240 "GenuineIntel", 241 CPUVENDOR_INTEL, 242 "Intel", 243 /* Family 4 */ 244 { { 245 CPUCLASS_486, 246 { 247 "486DX", "486DX", "486SX", "486DX2", "486SL", 248 "486SX2", 0, "486DX2 W/B Enhanced", 249 "486DX4", 0, 0, 0, 0, 0, 0, 0, 250 }, 251 "486", /* Default */ 252 NULL, 253 NULL, 254 intel_cpu_cacheinfo, 255 }, 256 /* Family 5 */ 257 { 258 CPUCLASS_586, 259 { 260 "Pentium (P5 A-step)", "Pentium (P5)", 261 "Pentium (P54C)", "Pentium (P24T)", 262 "Pentium/MMX", "Pentium", 0, 263 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 264 "Quark X1000", 0, 0, 0, 0, 0, 0, 265 }, 266 "Pentium", /* Default */ 267 NULL, 268 NULL, 269 intel_cpu_cacheinfo, 270 }, 271 /* Family 6 */ 272 { 273 CPUCLASS_686, 274 { 275 [0x00] = "Pentium Pro (A-step)", 276 [0x01] = "Pentium Pro", 277 [0x03] = "Pentium II (Klamath)", 278 [0x04] = "Pentium Pro", 279 [0x05] = "Pentium II/Celeron (Deschutes)", 280 [0x06] = "Celeron (Mendocino)", 281 [0x07] = "Pentium III (Katmai)", 282 [0x08] = "Pentium III (Coppermine)", 283 [0x09] = "Pentium M (Banias)", 284 [0x0a] = "Pentium III Xeon (Cascades)", 285 [0x0b] = "Pentium III (Tualatin)", 286 [0x0d] = "Pentium M (Dothan)", 287 [0x0e] = "Pentium Core Duo, Core solo", 288 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 289 "Core 2 Quad 6xxx, " 290 "Core 2 Extreme 6xxx, " 291 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 292 "and Pentium DC", 293 [0x15] = "EP80579 Integrated Processor", 294 [0x16] = "Celeron (45nm)", 295 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 296 "Core 2 Quad 8xxx and 9xxx", 297 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 298 "(Nehalem)", 299 [0x1c] = "45nm Atom Family", 300 [0x1d] = "XeonMP 74xx (Nehalem)", 301 [0x1e] = "Core i7 and i5", 302 [0x1f] = "Core i7 and i5", 303 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 304 [0x26] = "Atom Family", 305 [0x27] = "Atom Family", 306 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 307 "i3 2xxx", 308 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 309 [0x2d] = "Xeon E5 Sandy Bridge family, " 310 "Core i7-39xx Extreme", 311 [0x2e] = "Xeon 75xx & 65xx", 312 [0x2f] = "Xeon E7 family", 313 [0x35] = "Atom Family", 314 [0x36] = "Atom S1000", 315 [0x37] = "Atom E3000, Z3[67]00", 316 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 317 "Ivy Bridge", 318 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 319 "(Haswell)", 320 [0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)", 321 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 322 "Core i7-49xx Extreme", 323 [0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), " 324 "Core i7-59xx Extreme", 325 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 326 "(Haswell)", 327 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 328 "(Haswell)", 329 [0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)", 330 [0x4a] = "Atom Z3400", 331 [0x4c] = "Atom X[57]-Z8000 (Airmont)", 332 [0x4d] = "Atom C2000", 333 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 334 [0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme", 335 [0x55] = "Xeon Scalable (Skylake, Cascade Lake, Copper Lake)", 336 [0x56] = "Xeon D-1500 (Broadwell)", 337 [0x57] = "Xeon Phi [357]200 (Knights Landing)", 338 [0x5a] = "Atom E3500", 339 [0x5c] = "Atom (Goldmont)", 340 [0x5d] = "Atom X3-C3000 (Silvermont)", 341 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 342 [0x5f] = "Atom (Goldmont, Denverton)", 343 [0x66] = "8th gen Core i3 (Cannon Lake)", 344 [0x6a] = "3rd gen Xeon Scalable (Ice Lake)", 345 [0x6c] = "3rd gen Xeon Scalable (Ice Lake)", 346 [0x7a] = "Atom (Goldmont Plus)", 347 [0x7d] = "10th gen Core (Ice Lake)", 348 [0x7e] = "10th gen Core (Ice Lake)", 349 [0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)", 350 [0x86] = "Atom (Tremont)", 351 [0x8c] = "11th gen Core (Tiger Lake)", 352 [0x8d] = "11th gen Core (Tiger Lake)", 353 [0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 354 [0x8f] = "future Xeon (Sapphire Rapids)", 355 [0x96] = "Atom x6000E (Elkhart Lake)", 356 [0x97] = "12th gen Core (Alder Lake)", 357 [0x9a] = "12th gen Core (Alder Lake)", 358 [0x9c] = "Pentium Silver N6xxx, Celeron N45xx, Celeron N51xx (Jasper Lake)", 359 [0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 360 [0xa5] = "10th gen Core (Comet Lake)", 361 [0xa6] = "10th gen Core (Comet Lake)", 362 [0xa7] = "11th gen Core (Rocket Lake)", 363 [0xa8] = "11th gen Core (Rocket Lake)", 364 [0xbf] = "12th gen Core (Alder Lake)", 365 }, 366 "Pentium Pro, II or III", /* Default */ 367 NULL, 368 intel_family_new_probe, 369 intel_cpu_cacheinfo, 370 }, 371 /* Family > 6 */ 372 { 373 CPUCLASS_686, 374 { 375 0, 0, 0, 0, 0, 0, 0, 0, 376 0, 0, 0, 0, 0, 0, 0, 0, 377 }, 378 "Pentium 4", /* Default */ 379 NULL, 380 intel_family_new_probe, 381 intel_cpu_cacheinfo, 382 } } 383 }, 384 { 385 "AuthenticAMD", 386 CPUVENDOR_AMD, 387 "AMD", 388 /* Family 4 */ 389 { { 390 CPUCLASS_486, 391 { 392 0, 0, 0, "Am486DX2 W/T", 393 0, 0, 0, "Am486DX2 W/B", 394 "Am486DX4 W/T or Am5x86 W/T 150", 395 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 396 0, 0, "Am5x86 W/T 133/160", 397 "Am5x86 W/B 133/160", 398 }, 399 "Am486 or Am5x86", /* Default */ 400 NULL, 401 NULL, 402 NULL, 403 }, 404 /* Family 5 */ 405 { 406 CPUCLASS_586, 407 { 408 "K5", "K5", "K5", "K5", 0, 0, "K6", 409 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 410 "K6-2+/III+", 0, 0, 411 }, 412 "K5 or K6", /* Default */ 413 amd_family5_setup, 414 NULL, 415 amd_cpu_cacheinfo, 416 }, 417 /* Family 6 */ 418 { 419 CPUCLASS_686, 420 { 421 0, "Athlon Model 1", "Athlon Model 2", 422 "Duron", "Athlon Model 4 (Thunderbird)", 423 0, "Athlon", "Duron", "Athlon", 0, 424 "Athlon", 0, 0, 0, 0, 0, 425 }, 426 "K7 (Athlon)", /* Default */ 427 NULL, 428 amd_family6_probe, 429 amd_cpu_cacheinfo, 430 }, 431 /* Family > 6 */ 432 { 433 CPUCLASS_686, 434 { 435 0, 0, 0, 0, 0, 0, 0, 0, 436 0, 0, 0, 0, 0, 0, 0, 0, 437 }, 438 "Unknown K8 (Athlon)", /* Default */ 439 NULL, 440 amd_family6_probe, 441 amd_cpu_cacheinfo, 442 } } 443 }, 444 { 445 "CyrixInstead", 446 CPUVENDOR_CYRIX, 447 "Cyrix", 448 /* Family 4 */ 449 { { 450 CPUCLASS_486, 451 { 452 0, 0, 0, 453 "MediaGX", 454 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 455 }, 456 "486", /* Default */ 457 cyrix6x86_cpu_setup, /* XXX ?? */ 458 NULL, 459 NULL, 460 }, 461 /* Family 5 */ 462 { 463 CPUCLASS_586, 464 { 465 0, 0, "6x86", 0, 466 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 467 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 468 }, 469 "6x86", /* Default */ 470 cyrix6x86_cpu_setup, 471 NULL, 472 NULL, 473 }, 474 /* Family 6 */ 475 { 476 CPUCLASS_686, 477 { 478 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 479 0, 0, 0, 0, 0, 0, 0, 0, 480 }, 481 "6x86MX", /* Default */ 482 cyrix6x86_cpu_setup, 483 NULL, 484 NULL, 485 }, 486 /* Family > 6 */ 487 { 488 CPUCLASS_686, 489 { 490 0, 0, 0, 0, 0, 0, 0, 0, 491 0, 0, 0, 0, 0, 0, 0, 0, 492 }, 493 "Unknown 6x86MX", /* Default */ 494 NULL, 495 NULL, 496 NULL, 497 } } 498 }, 499 { /* MediaGX is now owned by National Semiconductor */ 500 "Geode by NSC", 501 CPUVENDOR_CYRIX, /* XXX */ 502 "National Semiconductor", 503 /* Family 4, NSC never had any of these */ 504 { { 505 CPUCLASS_486, 506 { 507 0, 0, 0, 0, 0, 0, 0, 0, 508 0, 0, 0, 0, 0, 0, 0, 0, 509 }, 510 "486 compatible", /* Default */ 511 NULL, 512 NULL, 513 NULL, 514 }, 515 /* Family 5: Geode family, formerly MediaGX */ 516 { 517 CPUCLASS_586, 518 { 519 0, 0, 0, 0, 520 "Geode GX1", 521 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 522 }, 523 "Geode", /* Default */ 524 cyrix6x86_cpu_setup, 525 NULL, 526 amd_cpu_cacheinfo, 527 }, 528 /* Family 6, not yet available from NSC */ 529 { 530 CPUCLASS_686, 531 { 532 0, 0, 0, 0, 0, 0, 0, 0, 533 0, 0, 0, 0, 0, 0, 0, 0, 534 }, 535 "Pentium Pro compatible", /* Default */ 536 NULL, 537 NULL, 538 NULL, 539 }, 540 /* Family > 6, not yet available from NSC */ 541 { 542 CPUCLASS_686, 543 { 544 0, 0, 0, 0, 0, 0, 0, 0, 545 0, 0, 0, 0, 0, 0, 0, 0, 546 }, 547 "Pentium Pro compatible", /* Default */ 548 NULL, 549 NULL, 550 NULL, 551 } } 552 }, 553 { 554 "CentaurHauls", 555 CPUVENDOR_IDT, 556 "IDT", 557 /* Family 4, IDT never had any of these */ 558 { { 559 CPUCLASS_486, 560 { 561 0, 0, 0, 0, 0, 0, 0, 0, 562 0, 0, 0, 0, 0, 0, 0, 0, 563 }, 564 "486 compatible", /* Default */ 565 NULL, 566 NULL, 567 NULL, 568 }, 569 /* Family 5 */ 570 { 571 CPUCLASS_586, 572 { 573 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 574 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 575 }, 576 "WinChip", /* Default */ 577 winchip_cpu_setup, 578 NULL, 579 NULL, 580 }, 581 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 582 { 583 CPUCLASS_686, 584 { 585 0, 0, 0, 0, 0, 0, "C3 Samuel", 586 "C3 Samuel 2/Ezra", "C3 Ezra-T", 587 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 588 0, "VIA Nano", 589 }, 590 "Unknown VIA/IDT", /* Default */ 591 NULL, 592 via_cpu_probe, 593 via_cpu_cacheinfo, 594 }, 595 /* Family > 6, not yet available from VIA */ 596 { 597 CPUCLASS_686, 598 { 599 0, 0, 0, 0, 0, 0, 0, 0, 600 0, 0, 0, 0, 0, 0, 0, 0, 601 }, 602 "Pentium Pro compatible", /* Default */ 603 NULL, 604 NULL, 605 NULL, 606 } } 607 }, 608 { 609 "GenuineTMx86", 610 CPUVENDOR_TRANSMETA, 611 "Transmeta", 612 /* Family 4, Transmeta never had any of these */ 613 { { 614 CPUCLASS_486, 615 { 616 0, 0, 0, 0, 0, 0, 0, 0, 617 0, 0, 0, 0, 0, 0, 0, 0, 618 }, 619 "486 compatible", /* Default */ 620 NULL, 621 NULL, 622 NULL, 623 }, 624 /* Family 5 */ 625 { 626 CPUCLASS_586, 627 { 628 0, 0, 0, 0, 0, 0, 0, 0, 629 0, 0, 0, 0, 0, 0, 0, 0, 630 }, 631 "Crusoe", /* Default */ 632 NULL, 633 NULL, 634 transmeta_cpu_info, 635 }, 636 /* Family 6, not yet available from Transmeta */ 637 { 638 CPUCLASS_686, 639 { 640 0, 0, 0, 0, 0, 0, 0, 0, 641 0, 0, 0, 0, 0, 0, 0, 0, 642 }, 643 "Pentium Pro compatible", /* Default */ 644 NULL, 645 NULL, 646 NULL, 647 }, 648 /* Family > 6, not yet available from Transmeta */ 649 { 650 CPUCLASS_686, 651 { 652 0, 0, 0, 0, 0, 0, 0, 0, 653 0, 0, 0, 0, 0, 0, 0, 0, 654 }, 655 "Pentium Pro compatible", /* Default */ 656 NULL, 657 NULL, 658 NULL, 659 } } 660 } 661 }; 662 663 /* 664 * disable the TSC such that we don't use the TSC in microtime(9) 665 * because some CPUs got the implementation wrong. 666 */ 667 static void 668 disable_tsc(struct cpu_info *ci) 669 { 670 if (ci->ci_feat_val[0] & CPUID_TSC) { 671 ci->ci_feat_val[0] &= ~CPUID_TSC; 672 aprint_error("WARNING: broken TSC disabled\n"); 673 } 674 } 675 676 static void 677 amd_family5_setup(struct cpu_info *ci) 678 { 679 680 switch (ci->ci_model) { 681 case 0: /* AMD-K5 Model 0 */ 682 /* 683 * According to the AMD Processor Recognition App Note, 684 * the AMD-K5 Model 0 uses the wrong bit to indicate 685 * support for global PTEs, instead using bit 9 (APIC) 686 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 687 */ 688 if (ci->ci_feat_val[0] & CPUID_APIC) 689 ci->ci_feat_val[0] = 690 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 691 /* 692 * XXX But pmap_pg_g is already initialized -- need to kick 693 * XXX the pmap somehow. How does the MP branch do this? 694 */ 695 break; 696 } 697 } 698 699 static void 700 cyrix6x86_cpu_setup(struct cpu_info *ci) 701 { 702 703 /* 704 * Do not disable the TSC on the Geode GX, it's reported to 705 * work fine. 706 */ 707 if (ci->ci_signature != 0x552) 708 disable_tsc(ci); 709 } 710 711 static void 712 winchip_cpu_setup(struct cpu_info *ci) 713 { 714 switch (ci->ci_model) { 715 case 4: /* WinChip C6 */ 716 disable_tsc(ci); 717 } 718 } 719 720 721 static const char * 722 intel_family6_name(struct cpu_info *ci) 723 { 724 const char *ret = NULL; 725 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 726 727 if (ci->ci_model == 5) { 728 switch (l2cache) { 729 case 0: 730 case 128 * 1024: 731 ret = "Celeron (Covington)"; 732 break; 733 case 256 * 1024: 734 ret = "Mobile Pentium II (Dixon)"; 735 break; 736 case 512 * 1024: 737 ret = "Pentium II"; 738 break; 739 case 1 * 1024 * 1024: 740 case 2 * 1024 * 1024: 741 ret = "Pentium II Xeon"; 742 break; 743 } 744 } else if (ci->ci_model == 6) { 745 switch (l2cache) { 746 case 256 * 1024: 747 case 512 * 1024: 748 ret = "Mobile Pentium II"; 749 break; 750 } 751 } else if (ci->ci_model == 7) { 752 switch (l2cache) { 753 case 512 * 1024: 754 ret = "Pentium III"; 755 break; 756 case 1 * 1024 * 1024: 757 case 2 * 1024 * 1024: 758 ret = "Pentium III Xeon"; 759 break; 760 } 761 } else if (ci->ci_model >= 8) { 762 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 763 switch (ci->ci_brand_id) { 764 case 0x3: 765 if (ci->ci_signature == 0x6B1) 766 ret = "Celeron"; 767 break; 768 case 0x8: 769 if (ci->ci_signature >= 0xF13) 770 ret = "genuine processor"; 771 break; 772 case 0xB: 773 if (ci->ci_signature >= 0xF13) 774 ret = "Xeon MP"; 775 break; 776 case 0xE: 777 if (ci->ci_signature < 0xF13) 778 ret = "Xeon"; 779 break; 780 } 781 if (ret == NULL) 782 ret = i386_intel_brand[ci->ci_brand_id]; 783 } 784 } 785 786 return ret; 787 } 788 789 /* 790 * Identify AMD64 CPU names from cpuid. 791 * 792 * Based on: 793 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 794 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 795 * "Revision Guide for AMD NPT Family 0Fh Processors" 796 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 797 * and other miscellaneous reports. 798 * 799 * This is all rather pointless, these are cross 'brand' since the raw 800 * silicon is shared. 801 */ 802 static const char * 803 amd_amd64_name(struct cpu_info *ci) 804 { 805 static char family_str[32]; 806 807 /* Only called if family >= 15 */ 808 809 switch (ci->ci_family) { 810 case 15: 811 switch (ci->ci_model) { 812 case 0x21: /* rev JH-E1/E6 */ 813 case 0x41: /* rev JH-F2 */ 814 return "Dual-Core Opteron"; 815 case 0x23: /* rev JH-E6 (Toledo) */ 816 return "Dual-Core Opteron or Athlon 64 X2"; 817 case 0x43: /* rev JH-F2 (Windsor) */ 818 return "Athlon 64 FX or Athlon 64 X2"; 819 case 0x24: /* rev SH-E5 (Lancaster?) */ 820 return "Mobile Athlon 64 or Turion 64"; 821 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 822 return "Opteron or Athlon 64 FX"; 823 case 0x15: /* rev SH-D0 */ 824 case 0x25: /* rev SH-E4 */ 825 return "Opteron"; 826 case 0x27: /* rev DH-E4, SH-E4 */ 827 return "Athlon 64 or Athlon 64 FX or Opteron"; 828 case 0x48: /* rev BH-F2 */ 829 return "Turion 64 X2"; 830 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 831 case 0x07: /* rev SH-CG (ClawHammer) */ 832 case 0x0b: /* rev CH-CG */ 833 case 0x14: /* rev SH-D0 */ 834 case 0x17: /* rev SH-D0 */ 835 case 0x1b: /* rev CH-D0 */ 836 return "Athlon 64"; 837 case 0x2b: /* rev BH-E4 (Manchester) */ 838 case 0x4b: /* rev BH-F2 (Windsor) */ 839 return "Athlon 64 X2"; 840 case 0x6b: /* rev BH-G1 (Brisbane) */ 841 return "Athlon X2 or Athlon 64 X2"; 842 case 0x08: /* rev CH-CG */ 843 case 0x0c: /* rev DH-CG (Newcastle) */ 844 case 0x0e: /* rev DH-CG (Newcastle?) */ 845 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 846 case 0x18: /* rev CH-D0 */ 847 case 0x1c: /* rev DH-D0 (Winchester) */ 848 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 849 case 0x2c: /* rev DH-E3/E6 */ 850 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 851 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 852 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 853 case 0x6f: /* rev DH-G1 */ 854 return "Athlon 64 or Sempron"; 855 default: 856 break; 857 } 858 return "Unknown AMD64 CPU"; 859 860 #if 0 861 case 16: 862 return "Family 10h"; 863 case 17: 864 return "Family 11h"; 865 case 18: 866 return "Family 12h"; 867 case 19: 868 return "Family 14h"; 869 case 20: 870 return "Family 15h"; 871 #endif 872 873 default: 874 break; 875 } 876 877 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 878 return family_str; 879 } 880 881 static void 882 intel_family_new_probe(struct cpu_info *ci) 883 { 884 uint32_t descs[4]; 885 886 x86_cpuid(0x80000000, descs); 887 888 /* 889 * Determine extended feature flags. 890 */ 891 if (descs[0] >= 0x80000001) { 892 x86_cpuid(0x80000001, descs); 893 ci->ci_feat_val[2] |= descs[3]; 894 ci->ci_feat_val[3] |= descs[2]; 895 } 896 } 897 898 static void 899 via_cpu_probe(struct cpu_info *ci) 900 { 901 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 902 u_int descs[4]; 903 u_int lfunc; 904 905 /* 906 * Determine the largest extended function value. 907 */ 908 x86_cpuid(0x80000000, descs); 909 lfunc = descs[0]; 910 911 /* 912 * Determine the extended feature flags. 913 */ 914 if (lfunc >= 0x80000001) { 915 x86_cpuid(0x80000001, descs); 916 ci->ci_feat_val[2] |= descs[3]; 917 } 918 919 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 920 return; 921 922 /* Nehemiah or Esther */ 923 x86_cpuid(0xc0000000, descs); 924 lfunc = descs[0]; 925 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 926 return; 927 928 x86_cpuid(0xc0000001, descs); 929 lfunc = descs[3]; 930 ci->ci_feat_val[4] = lfunc; 931 } 932 933 static void 934 amd_family6_probe(struct cpu_info *ci) 935 { 936 uint32_t descs[4]; 937 char *p; 938 size_t i; 939 940 x86_cpuid(0x80000000, descs); 941 942 /* 943 * Determine the extended feature flags. 944 */ 945 if (descs[0] >= 0x80000001) { 946 x86_cpuid(0x80000001, descs); 947 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 948 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 949 } 950 951 if (*cpu_brand_string == '\0') 952 return; 953 954 for (i = 1; i < __arraycount(amd_brand); i++) 955 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 956 ci->ci_brand_id = i; 957 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 958 break; 959 } 960 } 961 962 static void 963 intel_cpu_cacheinfo(struct cpu_info *ci) 964 { 965 const struct x86_cache_info *cai; 966 u_int descs[4]; 967 int iterations, i, j; 968 int type, level, ways, linesize, sets; 969 int caitype = -1; 970 uint8_t desc; 971 972 /* Return if the cpu is old pre-cpuid instruction cpu */ 973 if (ci->ci_cpu_type >= 0) 974 return; 975 976 if (ci->ci_max_cpuid < 2) 977 return; 978 979 /* 980 * Parse the cache info from `cpuid leaf 2', if we have it. 981 * XXX This is kinda ugly, but hey, so is the architecture... 982 */ 983 x86_cpuid(2, descs); 984 iterations = descs[0] & 0xff; 985 while (iterations-- > 0) { 986 for (i = 0; i < 4; i++) { 987 if (descs[i] & 0x80000000) 988 continue; 989 for (j = 0; j < 4; j++) { 990 /* 991 * The least significant byte in EAX 992 * ((desc[0] >> 0) & 0xff) is always 0x01 and 993 * it should be ignored. 994 */ 995 if (i == 0 && j == 0) 996 continue; 997 desc = (descs[i] >> (j * 8)) & 0xff; 998 if (desc == 0) 999 continue; 1000 cai = cpu_cacheinfo_lookup( 1001 intel_cpuid_cache_info, desc); 1002 if (cai != NULL) 1003 ci->ci_cinfo[cai->cai_index] = *cai; 1004 else if ((verbose != 0) && (desc != 0xff) 1005 && (desc != 0xfe)) 1006 aprint_error_dev(ci->ci_dev, "error:" 1007 " Unknown cacheinfo desc %02x\n", 1008 desc); 1009 } 1010 } 1011 x86_cpuid(2, descs); 1012 } 1013 1014 if (ci->ci_max_cpuid < 4) 1015 return; 1016 1017 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1018 cpu_dcp_cacheinfo(ci, 4); 1019 1020 if (ci->ci_max_cpuid < 0x18) 1021 return; 1022 /* Parse the TLB info from `cpuid leaf 18H', if we have it. */ 1023 x86_cpuid(0x18, descs); 1024 iterations = descs[0]; 1025 for (i = 0; i <= iterations; i++) { 1026 uint32_t pgsize; 1027 bool full; 1028 1029 x86_cpuid2(0x18, i, descs); 1030 type = __SHIFTOUT(descs[3], CPUID_DATP_TCTYPE); 1031 if (type == CPUID_DATP_TCTYPE_N) 1032 continue; 1033 level = __SHIFTOUT(descs[3], CPUID_DATP_TCLEVEL); 1034 pgsize = __SHIFTOUT(descs[1], CPUID_DATP_PGSIZE); 1035 switch (level) { 1036 case 1: 1037 if (type == CPUID_DATP_TCTYPE_I) { 1038 switch (pgsize) { 1039 case CPUID_DATP_PGSIZE_4KB: 1040 caitype = CAI_ITLB; 1041 break; 1042 case CPUID_DATP_PGSIZE_2MB 1043 | CPUID_DATP_PGSIZE_4MB: 1044 caitype = CAI_ITLB2; 1045 break; 1046 case CPUID_DATP_PGSIZE_1GB: 1047 caitype = CAI_L1_1GBITLB; 1048 break; 1049 default: 1050 aprint_error_dev(ci->ci_dev, 1051 "error: unknown ITLB size (%d)\n", 1052 pgsize); 1053 caitype = CAI_ITLB; 1054 break; 1055 } 1056 } else if (type == CPUID_DATP_TCTYPE_D) { 1057 switch (pgsize) { 1058 case CPUID_DATP_PGSIZE_4KB: 1059 caitype = CAI_DTLB; 1060 break; 1061 case CPUID_DATP_PGSIZE_2MB 1062 | CPUID_DATP_PGSIZE_4MB: 1063 caitype = CAI_DTLB2; 1064 break; 1065 case CPUID_DATP_PGSIZE_1GB: 1066 caitype = CAI_L1_1GBDTLB; 1067 break; 1068 default: 1069 aprint_error_dev(ci->ci_dev, 1070 "error: unknown DTLB size (%d)\n", 1071 pgsize); 1072 caitype = CAI_DTLB; 1073 break; 1074 } 1075 } else 1076 caitype = -1; 1077 break; 1078 case 2: 1079 if (type == CPUID_DATP_TCTYPE_I) 1080 caitype = CAI_L2_ITLB; 1081 else if (type == CPUID_DATP_TCTYPE_D) 1082 caitype = CAI_L2_DTLB; 1083 else if (type == CPUID_DATP_TCTYPE_U) { 1084 if (pgsize == CPUID_DATP_PGSIZE_4KB) 1085 caitype = CAI_L2_STLB; 1086 else if (pgsize == (CPUID_DATP_PGSIZE_4KB 1087 | CPUID_DATP_PGSIZE_2MB)) 1088 caitype = CAI_L2_STLB2; 1089 else if (pgsize == (CPUID_DATP_PGSIZE_2MB 1090 | CPUID_DATP_PGSIZE_4MB)) 1091 caitype = CAI_L2_STLB3; 1092 else if ((pgsize & CPUID_DATP_PGSIZE_1GB) 1093 != 0) { 1094 /* FIXME: 1GB max TLB */ 1095 caitype = CAI_L2_STLB3; 1096 linesize = 1024 * 1024 * 1024; 1097 } else if ((pgsize & CPUID_DATP_PGSIZE_4MB) 1098 != 0) { 1099 /* FIXME: 4MB max TLB */ 1100 caitype = CAI_L2_STLB3; 1101 linesize = 4 * 1024 * 1024; 1102 } else if ((pgsize & CPUID_DATP_PGSIZE_2MB) 1103 != 0) { 1104 /* FIXME: 2MB max TLB */ 1105 caitype = CAI_L2_STLB2; 1106 linesize = 2 * 1024 * 1024; 1107 } else { 1108 aprint_error_dev(ci->ci_dev, "error: " 1109 "unknown L2 STLB size (%d)\n", 1110 pgsize); 1111 caitype = CAI_L2_STLB; 1112 linesize = 4 * 1024; 1113 } 1114 } else 1115 caitype = -1; 1116 break; 1117 case 3: 1118 /* XXX need work for L3 TLB */ 1119 caitype = CAI_L3CACHE; 1120 break; 1121 default: 1122 caitype = -1; 1123 break; 1124 } 1125 if (caitype == -1) { 1126 aprint_error_dev(ci->ci_dev, 1127 "error: unknown TLB level&type (%d & %d)\n", 1128 level, type); 1129 continue; 1130 } 1131 switch (pgsize) { 1132 case CPUID_DATP_PGSIZE_4KB: 1133 linesize = 4 * 1024; 1134 break; 1135 case CPUID_DATP_PGSIZE_2MB: 1136 linesize = 2 * 1024 * 1024; 1137 break; 1138 case CPUID_DATP_PGSIZE_4MB: 1139 linesize = 4 * 1024 * 1024; 1140 break; 1141 case CPUID_DATP_PGSIZE_1GB: 1142 linesize = 1024 * 1024 * 1024; 1143 break; 1144 default: 1145 if ((pgsize & CPUID_DATP_PGSIZE_1GB) != 0) 1146 linesize = 1024 * 1024 * 1024; /* MAX 1G */ 1147 else if ((pgsize & CPUID_DATP_PGSIZE_4MB) != 0) 1148 linesize = 4 * 1024 * 1024; /* MAX 4M */ 1149 else if ((pgsize & CPUID_DATP_PGSIZE_2MB) != 0) 1150 linesize = 2 * 1024 * 1024; /* MAX 2M */ 1151 else 1152 linesize = 4 * 1024; /* XXX default to 4K */ 1153 aprint_error_dev(ci->ci_dev, "WARNING: Currently " 1154 "this info can't print correctly " 1155 "(level = %d, pgsize = %d)\n", 1156 level, pgsize); 1157 break; 1158 } 1159 ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS); 1160 sets = descs[2]; 1161 full = descs[3] & CPUID_DATP_FULLASSOC; 1162 ci->ci_cinfo[caitype].cai_totalsize 1163 = ways * sets; /* entries */ 1164 ci->ci_cinfo[caitype].cai_associativity 1165 = full ? 0xff : ways; 1166 ci->ci_cinfo[caitype].cai_linesize = linesize; /* pg size */ 1167 } 1168 } 1169 1170 static const struct x86_cache_info amd_cpuid_l2l3cache_assoc_info[] = 1171 AMD_L2L3CACHE_INFO; 1172 1173 static void 1174 amd_cpu_cacheinfo(struct cpu_info *ci) 1175 { 1176 const struct x86_cache_info *cp; 1177 struct x86_cache_info *cai; 1178 u_int descs[4]; 1179 u_int lfunc; 1180 1181 /* K5 model 0 has none of this info. */ 1182 if (ci->ci_family == 5 && ci->ci_model == 0) 1183 return; 1184 1185 /* Determine the largest extended function value. */ 1186 x86_cpuid(0x80000000, descs); 1187 lfunc = descs[0]; 1188 1189 if (lfunc < 0x80000005) 1190 return; 1191 1192 /* Determine L1 cache/TLB info. */ 1193 x86_cpuid(0x80000005, descs); 1194 1195 /* K6-III and higher have large page TLBs. */ 1196 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1197 cai = &ci->ci_cinfo[CAI_ITLB2]; 1198 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1199 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1200 cai->cai_linesize = largepagesize; 1201 1202 cai = &ci->ci_cinfo[CAI_DTLB2]; 1203 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1204 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1205 cai->cai_linesize = largepagesize; 1206 } 1207 1208 cai = &ci->ci_cinfo[CAI_ITLB]; 1209 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1210 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1211 cai->cai_linesize = (4 * 1024); 1212 1213 cai = &ci->ci_cinfo[CAI_DTLB]; 1214 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1215 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1216 cai->cai_linesize = (4 * 1024); 1217 1218 cai = &ci->ci_cinfo[CAI_DCACHE]; 1219 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1220 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1221 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1222 1223 cai = &ci->ci_cinfo[CAI_ICACHE]; 1224 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1225 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1226 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1227 1228 if (lfunc < 0x80000006) 1229 return; 1230 1231 /* Determine L2 cache/TLB info. */ 1232 x86_cpuid(0x80000006, descs); 1233 1234 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1235 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1236 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1237 cai->cai_linesize = (4 * 1024); 1238 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1239 cai->cai_associativity); 1240 if (cp != NULL) 1241 cai->cai_associativity = cp->cai_associativity; 1242 else 1243 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1244 1245 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1246 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1247 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1248 cai->cai_linesize = largepagesize; 1249 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1250 cai->cai_associativity); 1251 if (cp != NULL) 1252 cai->cai_associativity = cp->cai_associativity; 1253 else 1254 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1255 1256 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1257 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1258 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1259 cai->cai_linesize = (4 * 1024); 1260 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1261 cai->cai_associativity); 1262 if (cp != NULL) 1263 cai->cai_associativity = cp->cai_associativity; 1264 else 1265 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1266 1267 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1268 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1269 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1270 cai->cai_linesize = largepagesize; 1271 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1272 cai->cai_associativity); 1273 if (cp != NULL) 1274 cai->cai_associativity = cp->cai_associativity; 1275 else 1276 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1277 1278 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1279 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1280 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1281 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1282 1283 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1284 cai->cai_associativity); 1285 if (cp != NULL) 1286 cai->cai_associativity = cp->cai_associativity; 1287 else 1288 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1289 1290 /* Determine L3 cache info on AMD Family 10h and newer processors */ 1291 if (ci->ci_family >= 0x10) { 1292 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1293 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1294 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1295 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1296 1297 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1298 cai->cai_associativity); 1299 if (cp != NULL) 1300 cai->cai_associativity = cp->cai_associativity; 1301 else 1302 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1303 } 1304 1305 if (lfunc < 0x80000019) 1306 return; 1307 1308 /* Determine 1GB TLB info. */ 1309 x86_cpuid(0x80000019, descs); 1310 1311 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1312 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1313 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1314 cai->cai_linesize = (1024 * 1024 * 1024); 1315 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1316 cai->cai_associativity); 1317 if (cp != NULL) 1318 cai->cai_associativity = cp->cai_associativity; 1319 else 1320 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1321 1322 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1323 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1324 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1325 cai->cai_linesize = (1024 * 1024 * 1024); 1326 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1327 cai->cai_associativity); 1328 if (cp != NULL) 1329 cai->cai_associativity = cp->cai_associativity; 1330 else 1331 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1332 1333 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1334 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1335 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1336 cai->cai_linesize = (1024 * 1024 * 1024); 1337 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1338 cai->cai_associativity); 1339 if (cp != NULL) 1340 cai->cai_associativity = cp->cai_associativity; 1341 else 1342 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1343 1344 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1345 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1346 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1347 cai->cai_linesize = (1024 * 1024 * 1024); 1348 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1349 cai->cai_associativity); 1350 if (cp != NULL) 1351 cai->cai_associativity = cp->cai_associativity; 1352 else 1353 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1354 1355 if (lfunc < 0x8000001d) 1356 return; 1357 1358 if (ci->ci_feat_val[3] & CPUID_TOPOEXT) 1359 cpu_dcp_cacheinfo(ci, 0x8000001d); 1360 } 1361 1362 static void 1363 via_cpu_cacheinfo(struct cpu_info *ci) 1364 { 1365 struct x86_cache_info *cai; 1366 int stepping; 1367 u_int descs[4]; 1368 u_int lfunc; 1369 1370 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1371 1372 /* 1373 * Determine the largest extended function value. 1374 */ 1375 x86_cpuid(0x80000000, descs); 1376 lfunc = descs[0]; 1377 1378 /* 1379 * Determine L1 cache/TLB info. 1380 */ 1381 if (lfunc < 0x80000005) { 1382 /* No L1 cache info available. */ 1383 return; 1384 } 1385 1386 x86_cpuid(0x80000005, descs); 1387 1388 cai = &ci->ci_cinfo[CAI_ITLB]; 1389 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1390 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1391 cai->cai_linesize = (4 * 1024); 1392 1393 cai = &ci->ci_cinfo[CAI_DTLB]; 1394 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1395 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1396 cai->cai_linesize = (4 * 1024); 1397 1398 cai = &ci->ci_cinfo[CAI_DCACHE]; 1399 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1400 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1401 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1402 if (ci->ci_model == 9 && stepping == 8) { 1403 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1404 cai->cai_associativity = 2; 1405 } 1406 1407 cai = &ci->ci_cinfo[CAI_ICACHE]; 1408 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1409 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1410 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1411 if (ci->ci_model == 9 && stepping == 8) { 1412 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1413 cai->cai_associativity = 2; 1414 } 1415 1416 /* 1417 * Determine L2 cache/TLB info. 1418 */ 1419 if (lfunc < 0x80000006) { 1420 /* No L2 cache info available. */ 1421 return; 1422 } 1423 1424 x86_cpuid(0x80000006, descs); 1425 1426 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1427 if (ci->ci_model >= 9) { 1428 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1429 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1430 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1431 } else { 1432 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1433 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1434 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1435 } 1436 } 1437 1438 static void 1439 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1440 { 1441 u_int descs[4]; 1442 1443 x86_cpuid(0x80860007, descs); 1444 *frequency = descs[0]; 1445 *voltage = descs[1]; 1446 *percentage = descs[2]; 1447 } 1448 1449 static void 1450 transmeta_cpu_info(struct cpu_info *ci) 1451 { 1452 u_int descs[4], nreg; 1453 u_int frequency, voltage, percentage; 1454 1455 x86_cpuid(0x80860000, descs); 1456 nreg = descs[0]; 1457 if (nreg >= 0x80860001) { 1458 x86_cpuid(0x80860001, descs); 1459 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1460 (descs[1] >> 24) & 0xff, 1461 (descs[1] >> 16) & 0xff, 1462 (descs[1] >> 8) & 0xff, 1463 descs[1] & 0xff); 1464 } 1465 if (nreg >= 0x80860002) { 1466 x86_cpuid(0x80860002, descs); 1467 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1468 (descs[1] >> 24) & 0xff, 1469 (descs[1] >> 16) & 0xff, 1470 (descs[1] >> 8) & 0xff, 1471 descs[1] & 0xff, 1472 descs[2]); 1473 } 1474 if (nreg >= 0x80860006) { 1475 union { 1476 char text[65]; 1477 u_int descs[4][4]; 1478 } info; 1479 int i; 1480 1481 for (i=0; i<4; i++) { 1482 x86_cpuid(0x80860003 + i, info.descs[i]); 1483 } 1484 info.text[64] = '\0'; 1485 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1486 } 1487 1488 if (nreg >= 0x80860007) { 1489 tmx86_get_longrun_status(&frequency, 1490 &voltage, &percentage); 1491 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1492 frequency, voltage, percentage); 1493 } 1494 } 1495 1496 static void 1497 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1498 { 1499 u_int descs[4]; 1500 int i; 1501 uint32_t brand[12]; 1502 1503 memset(ci, 0, sizeof(*ci)); 1504 ci->ci_dev = cpuname; 1505 1506 ci->ci_cpu_type = x86_identify(); 1507 if (ci->ci_cpu_type >= 0) { 1508 /* Old pre-cpuid instruction cpu */ 1509 ci->ci_max_cpuid = -1; 1510 return; 1511 } 1512 1513 /* 1514 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1515 * function. 1516 */ 1517 1518 /* 1519 * Fn0000_0000: 1520 * - Save cpuid max level. 1521 * - Save vendor string. 1522 */ 1523 x86_cpuid(0, descs); 1524 ci->ci_max_cpuid = descs[0]; 1525 /* Save vendor string */ 1526 ci->ci_vendor[0] = descs[1]; 1527 ci->ci_vendor[2] = descs[2]; 1528 ci->ci_vendor[1] = descs[3]; 1529 ci->ci_vendor[3] = 0; 1530 1531 /* 1532 * Fn8000_0000: 1533 * - Get cpuid extended function's max level. 1534 */ 1535 x86_cpuid(0x80000000, descs); 1536 if (descs[0] >= 0x80000000) 1537 ci->ci_max_ext_cpuid = descs[0]; 1538 else { 1539 /* Set lower value than 0x80000000 */ 1540 ci->ci_max_ext_cpuid = 0; 1541 } 1542 1543 /* 1544 * Fn8000_000[2-4]: 1545 * - Save brand string. 1546 */ 1547 if (ci->ci_max_ext_cpuid >= 0x80000004) { 1548 x86_cpuid(0x80000002, brand); 1549 x86_cpuid(0x80000003, brand + 4); 1550 x86_cpuid(0x80000004, brand + 8); 1551 for (i = 0; i < 48; i++) 1552 if (((char *) brand)[i] != ' ') 1553 break; 1554 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1555 } 1556 1557 if (ci->ci_max_cpuid < 1) 1558 return; 1559 1560 /* 1561 * Fn0000_0001: 1562 * - Get CPU family, model and stepping (from eax). 1563 * - Initial local APIC ID and brand ID (from ebx) 1564 * - CPUID2 (from ecx) 1565 * - CPUID (from edx) 1566 */ 1567 x86_cpuid(1, descs); 1568 ci->ci_signature = descs[0]; 1569 1570 /* Extract full family/model values */ 1571 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1572 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1573 1574 /* Brand is low order 8 bits of ebx */ 1575 ci->ci_brand_id = __SHIFTOUT(descs[1], CPUID_BRAND_INDEX); 1576 /* Initial local APIC ID */ 1577 ci->ci_initapicid = __SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID); 1578 1579 ci->ci_feat_val[1] = descs[2]; 1580 ci->ci_feat_val[0] = descs[3]; 1581 1582 if (ci->ci_max_cpuid < 3) 1583 return; 1584 1585 /* 1586 * If the processor serial number misfeature is present and supported, 1587 * extract it here. 1588 */ 1589 if ((ci->ci_feat_val[0] & CPUID_PSN) != 0) { 1590 ci->ci_cpu_serial[0] = ci->ci_signature; 1591 x86_cpuid(3, descs); 1592 ci->ci_cpu_serial[2] = descs[2]; 1593 ci->ci_cpu_serial[1] = descs[3]; 1594 } 1595 1596 if (ci->ci_max_cpuid < 0x7) 1597 return; 1598 1599 x86_cpuid(7, descs); 1600 ci->ci_feat_val[5] = descs[1]; 1601 ci->ci_feat_val[6] = descs[2]; 1602 ci->ci_feat_val[7] = descs[3]; 1603 1604 if (ci->ci_max_cpuid < 0xd) 1605 return; 1606 1607 /* Get support XCR0 bits */ 1608 x86_cpuid2(0xd, 0, descs); 1609 ci->ci_feat_val[8] = descs[0]; /* Actually 64 bits */ 1610 ci->ci_cur_xsave = descs[1]; 1611 ci->ci_max_xsave = descs[2]; 1612 1613 /* Additional flags (eg xsaveopt support) */ 1614 x86_cpuid2(0xd, 1, descs); 1615 ci->ci_feat_val[9] = descs[0]; /* Actually 64 bits */ 1616 } 1617 1618 static void 1619 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1620 { 1621 uint32_t descs[4]; 1622 char hv_sig[13]; 1623 char *p; 1624 const char *hv_name; 1625 int i; 1626 1627 /* 1628 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1629 * http://lkml.org/lkml/2008/10/1/246 1630 * 1631 * KB1009458: Mechanisms to determine if software is running in 1632 * a VMware virtual machine 1633 * http://kb.vmware.com/kb/1009458 1634 */ 1635 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1636 x86_cpuid(0x40000000, descs); 1637 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1638 memcpy(p, &descs[i], sizeof(descs[i])); 1639 *p = '\0'; 1640 /* 1641 * HV vendor ID string 1642 * ------------+-------------- 1643 * HAXM "HAXMHAXMHAXM" 1644 * KVM "KVMKVMKVM" 1645 * Microsoft "Microsoft Hv" 1646 * QEMU(TCG) "TCGTCGTCGTCG" 1647 * VMware "VMwareVMware" 1648 * Xen "XenVMMXenVMM" 1649 * NetBSD "___ NVMM ___" 1650 */ 1651 if (strncmp(hv_sig, "HAXMHAXMHAXM", 12) == 0) 1652 hv_name = "HAXM"; 1653 else if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1654 hv_name = "KVM"; 1655 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1656 hv_name = "Hyper-V"; 1657 else if (strncmp(hv_sig, "TCGTCGTCGTCG", 12) == 0) 1658 hv_name = "QEMU(TCG)"; 1659 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1660 hv_name = "VMware"; 1661 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1662 hv_name = "Xen"; 1663 else if (strncmp(hv_sig, "___ NVMM ___", 12) == 0) 1664 hv_name = "NVMM"; 1665 else 1666 hv_name = "unknown"; 1667 1668 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1669 } 1670 } 1671 1672 static void 1673 cpu_probe_features(struct cpu_info *ci) 1674 { 1675 const struct cpu_cpuid_nameclass *cpup = NULL; 1676 unsigned int i; 1677 1678 if (ci->ci_max_cpuid < 1) 1679 return; 1680 1681 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1682 if (!strncmp((char *)ci->ci_vendor, 1683 i386_cpuid_cpus[i].cpu_id, 12)) { 1684 cpup = &i386_cpuid_cpus[i]; 1685 break; 1686 } 1687 } 1688 1689 if (cpup == NULL) 1690 return; 1691 1692 i = ci->ci_family - CPU_MINFAMILY; 1693 1694 if (i >= __arraycount(cpup->cpu_family)) 1695 i = __arraycount(cpup->cpu_family) - 1; 1696 1697 if (cpup->cpu_family[i].cpu_probe == NULL) 1698 return; 1699 1700 (*cpup->cpu_family[i].cpu_probe)(ci); 1701 } 1702 1703 static void 1704 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1705 { 1706 char buf[32 * 16]; 1707 char *bp; 1708 1709 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1710 1711 if (val == 0 || fmt == NULL) 1712 return; 1713 1714 snprintb_m(buf, sizeof(buf), fmt, val, 1715 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1716 bp = buf; 1717 while (*bp != '\0') { 1718 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1719 bp += strlen(bp) + 1; 1720 } 1721 } 1722 1723 static void 1724 dump_descs(uint32_t leafstart, uint32_t leafend, const char *cpuname, 1725 const char *blockname) 1726 { 1727 uint32_t descs[4]; 1728 uint32_t leaf; 1729 1730 aprint_verbose("%s: highest %s info %08x\n", cpuname, blockname, 1731 leafend); 1732 1733 if (verbose) { 1734 for (leaf = leafstart; leaf <= leafend; leaf++) { 1735 x86_cpuid(leaf, descs); 1736 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1737 leaf, descs[0], descs[1], descs[2], descs[3]); 1738 } 1739 } 1740 } 1741 1742 static void 1743 identifycpu_cpuids_intel_0x04(struct cpu_info *ci) 1744 { 1745 u_int lp_max = 1; /* logical processors per package */ 1746 u_int smt_max; /* smt per core */ 1747 u_int core_max = 1; /* core per package */ 1748 u_int smt_bits, core_bits; 1749 uint32_t descs[4]; 1750 1751 /* 1752 * 253668.pdf 7.10.2 1753 */ 1754 1755 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1756 x86_cpuid(1, descs); 1757 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1758 } 1759 x86_cpuid2(4, 0, descs); 1760 core_max = __SHIFTOUT(descs[0], CPUID_DCP_CORE_P_PKG) + 1; 1761 1762 assert(lp_max >= core_max); 1763 smt_max = lp_max / core_max; 1764 smt_bits = ilog2(smt_max - 1) + 1; 1765 core_bits = ilog2(core_max - 1) + 1; 1766 1767 if (smt_bits + core_bits) 1768 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1769 1770 if (core_bits) 1771 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1772 __BITS(smt_bits, smt_bits + core_bits - 1)); 1773 1774 if (smt_bits) 1775 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1776 __BITS((int)0, (int)(smt_bits - 1))); 1777 } 1778 1779 static void 1780 identifycpu_cpuids_intel_0x0b(struct cpu_info *ci) 1781 { 1782 const char *cpuname = ci->ci_dev; 1783 u_int smt_bits, core_bits, core_shift = 0, pkg_shift = 0; 1784 uint32_t descs[4]; 1785 int i; 1786 1787 x86_cpuid(0x0b, descs); 1788 if (descs[1] == 0) { 1789 identifycpu_cpuids_intel_0x04(ci); 1790 return; 1791 } 1792 1793 for (i = 0; ; i++) { 1794 unsigned int shiftnum, lvltype; 1795 x86_cpuid2(0x0b, i, descs); 1796 1797 /* On invalid level, (EAX and) EBX return 0 */ 1798 if (descs[1] == 0) 1799 break; 1800 1801 shiftnum = __SHIFTOUT(descs[0], CPUID_TOP_SHIFTNUM); 1802 lvltype = __SHIFTOUT(descs[2], CPUID_TOP_LVLTYPE); 1803 switch (lvltype) { 1804 case CPUID_TOP_LVLTYPE_SMT: 1805 core_shift = shiftnum; 1806 break; 1807 case CPUID_TOP_LVLTYPE_CORE: 1808 pkg_shift = shiftnum; 1809 break; 1810 case CPUID_TOP_LVLTYPE_INVAL: 1811 aprint_verbose("%s: Invalid level type\n", cpuname); 1812 break; 1813 default: 1814 aprint_verbose("%s: Unknown level type(%d) \n", 1815 cpuname, lvltype); 1816 break; 1817 } 1818 } 1819 1820 assert(pkg_shift >= core_shift); 1821 smt_bits = core_shift; 1822 core_bits = pkg_shift - core_shift; 1823 1824 ci->ci_packageid = ci->ci_initapicid >> pkg_shift; 1825 1826 if (core_bits) 1827 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1828 __BITS(core_shift, pkg_shift - 1)); 1829 1830 if (smt_bits) 1831 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1832 __BITS((int)0, core_shift - 1)); 1833 } 1834 1835 static void 1836 identifycpu_cpuids_intel(struct cpu_info *ci) 1837 { 1838 const char *cpuname = ci->ci_dev; 1839 1840 if (ci->ci_max_cpuid >= 0x0b) 1841 identifycpu_cpuids_intel_0x0b(ci); 1842 else if (ci->ci_max_cpuid >= 4) 1843 identifycpu_cpuids_intel_0x04(ci); 1844 1845 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1846 ci->ci_packageid); 1847 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1848 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1849 } 1850 1851 static void 1852 identifycpu_cpuids_amd(struct cpu_info *ci) 1853 { 1854 const char *cpuname = ci->ci_dev; 1855 u_int lp_max, core_max; 1856 int n, cpu_family, apic_id, smt_bits, core_bits = 0; 1857 uint32_t descs[4]; 1858 1859 apic_id = ci->ci_initapicid; 1860 cpu_family = CPUID_TO_FAMILY(ci->ci_signature); 1861 1862 if (cpu_family < 0xf) 1863 return; 1864 1865 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1866 x86_cpuid(1, descs); 1867 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1868 1869 if (cpu_family >= 0x10 && ci->ci_max_ext_cpuid >= 0x8000008) { 1870 x86_cpuid(0x8000008, descs); 1871 core_max = (descs[2] & 0xff) + 1; 1872 n = (descs[2] >> 12) & 0x0f; 1873 if (n != 0) 1874 core_bits = n; 1875 } 1876 } else { 1877 lp_max = 1; 1878 } 1879 core_max = lp_max; 1880 1881 smt_bits = ilog2((lp_max / core_max) - 1) + 1; 1882 if (core_bits == 0) 1883 core_bits = ilog2(core_max - 1) + 1; 1884 1885 #if 0 /* MSRs need kernel mode */ 1886 if (cpu_family < 0x11) { 1887 const uint64_t reg = rdmsr(MSR_NB_CFG); 1888 if ((reg & NB_CFG_INITAPICCPUIDLO) == 0) { 1889 const u_int node_id = apic_id & __BITS(0, 2); 1890 apic_id = (cpu_family == 0xf) ? 1891 (apic_id >> core_bits) | (node_id << core_bits) : 1892 (apic_id >> 5) | (node_id << 2); 1893 } 1894 } 1895 #endif 1896 1897 if (cpu_family >= 0x17) { 1898 x86_cpuid(0x8000001e, descs); 1899 const u_int threads = ((descs[1] >> 8) & 0xff) + 1; 1900 smt_bits = ilog2(threads); 1901 core_bits -= smt_bits; 1902 } 1903 1904 if (smt_bits + core_bits) { 1905 if (smt_bits + core_bits < 32) 1906 ci->ci_packageid = 0; 1907 } 1908 if (core_bits) { 1909 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1910 ci->ci_coreid = __SHIFTOUT(apic_id, core_mask); 1911 } 1912 if (smt_bits) { 1913 u_int smt_mask = __BITS(0, smt_bits - 1); 1914 ci->ci_smtid = __SHIFTOUT(apic_id, smt_mask); 1915 } 1916 1917 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1918 ci->ci_packageid); 1919 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1920 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1921 } 1922 1923 static void 1924 identifycpu_cpuids(struct cpu_info *ci) 1925 { 1926 const char *cpuname = ci->ci_dev; 1927 1928 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1929 ci->ci_packageid = ci->ci_initapicid; 1930 ci->ci_coreid = 0; 1931 ci->ci_smtid = 0; 1932 1933 if (cpu_vendor == CPUVENDOR_INTEL) 1934 identifycpu_cpuids_intel(ci); 1935 else if (cpu_vendor == CPUVENDOR_AMD) 1936 identifycpu_cpuids_amd(ci); 1937 } 1938 1939 void 1940 identifycpu(int fd, const char *cpuname) 1941 { 1942 const char *name = "", *modifier, *vendorname, *brand = ""; 1943 int class = CPUCLASS_386; 1944 unsigned int i; 1945 int modif, family; 1946 const struct cpu_cpuid_nameclass *cpup = NULL; 1947 const struct cpu_cpuid_family *cpufam; 1948 struct cpu_info *ci, cistore; 1949 u_int descs[4]; 1950 size_t sz; 1951 struct cpu_ucode_version ucode; 1952 union { 1953 struct cpu_ucode_version_amd amd; 1954 struct cpu_ucode_version_intel1 intel1; 1955 } ucvers; 1956 1957 ci = &cistore; 1958 cpu_probe_base_features(ci, cpuname); 1959 dump_descs(0x00000000, ci->ci_max_cpuid, cpuname, "basic"); 1960 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1961 x86_cpuid(0x40000000, descs); 1962 dump_descs(0x40000000, descs[0], cpuname, "hypervisor"); 1963 } 1964 dump_descs(0x80000000, ci->ci_max_ext_cpuid, cpuname, "extended"); 1965 1966 cpu_probe_hv_features(ci, cpuname); 1967 cpu_probe_features(ci); 1968 1969 if (ci->ci_cpu_type >= 0) { 1970 /* Old pre-cpuid instruction cpu */ 1971 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1972 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1973 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1974 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1975 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1976 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1977 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1978 modifier = ""; 1979 } else { 1980 /* CPU which support cpuid instruction */ 1981 modif = (ci->ci_signature >> 12) & 0x3; 1982 family = ci->ci_family; 1983 if (family < CPU_MINFAMILY) 1984 errx(1, "identifycpu: strange family value"); 1985 if (family > CPU_MAXFAMILY) 1986 family = CPU_MAXFAMILY; 1987 1988 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1989 if (!strncmp((char *)ci->ci_vendor, 1990 i386_cpuid_cpus[i].cpu_id, 12)) { 1991 cpup = &i386_cpuid_cpus[i]; 1992 break; 1993 } 1994 } 1995 1996 if (cpup == NULL) { 1997 cpu_vendor = CPUVENDOR_UNKNOWN; 1998 if (ci->ci_vendor[0] != '\0') 1999 vendorname = (char *)&ci->ci_vendor[0]; 2000 else 2001 vendorname = "Unknown"; 2002 class = family - 3; 2003 modifier = ""; 2004 name = ""; 2005 ci->ci_info = NULL; 2006 } else { 2007 cpu_vendor = cpup->cpu_vendor; 2008 vendorname = cpup->cpu_vendorname; 2009 modifier = modifiers[modif]; 2010 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 2011 name = cpufam->cpu_models[ci->ci_model]; 2012 if (name == NULL || *name == '\0') 2013 name = cpufam->cpu_model_default; 2014 class = cpufam->cpu_class; 2015 ci->ci_info = cpufam->cpu_info; 2016 2017 if (cpu_vendor == CPUVENDOR_INTEL) { 2018 if (ci->ci_family == 6 && ci->ci_model >= 5) { 2019 const char *tmp; 2020 tmp = intel_family6_name(ci); 2021 if (tmp != NULL) 2022 name = tmp; 2023 } 2024 if (ci->ci_family == 15 && 2025 ci->ci_brand_id < 2026 __arraycount(i386_intel_brand) && 2027 i386_intel_brand[ci->ci_brand_id]) 2028 name = 2029 i386_intel_brand[ci->ci_brand_id]; 2030 } 2031 2032 if (cpu_vendor == CPUVENDOR_AMD) { 2033 if (ci->ci_family == 6 && ci->ci_model >= 6) { 2034 if (ci->ci_brand_id == 1) 2035 /* 2036 * It's Duron. We override the 2037 * name, since it might have 2038 * been misidentified as Athlon. 2039 */ 2040 name = 2041 amd_brand[ci->ci_brand_id]; 2042 else 2043 brand = amd_brand_name; 2044 } 2045 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 2046 == 0xf) { 2047 /* Identify AMD64 CPU names. */ 2048 const char *tmp; 2049 tmp = amd_amd64_name(ci); 2050 if (tmp != NULL) 2051 name = tmp; 2052 } 2053 } 2054 2055 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 2056 vendorname = "VIA"; 2057 } 2058 } 2059 2060 ci->ci_cpu_class = class; 2061 2062 sz = sizeof(ci->ci_tsc_freq); 2063 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 2064 sz = sizeof(use_pae); 2065 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 2066 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 2067 2068 /* 2069 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 2070 * we try to determine from the family/model values. 2071 */ 2072 if (*cpu_brand_string != '\0') 2073 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 2074 2075 aprint_normal("%s: %s", cpuname, vendorname); 2076 if (*modifier) 2077 aprint_normal(" %s", modifier); 2078 if (*name) 2079 aprint_normal(" %s", name); 2080 if (*brand) 2081 aprint_normal(" %s", brand); 2082 aprint_normal(" (%s-class)", classnames[class]); 2083 2084 if (ci->ci_tsc_freq != 0) 2085 aprint_normal(", %ju.%02ju MHz", 2086 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 2087 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 2088 aprint_normal("\n"); 2089 2090 (void)cpu_tsc_freq_cpuid(ci); 2091 2092 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 2093 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 2094 if (ci->ci_signature != 0) 2095 aprint_normal(" (id %#x)", ci->ci_signature); 2096 aprint_normal("\n"); 2097 2098 if (ci->ci_info) 2099 (*ci->ci_info)(ci); 2100 2101 /* 2102 * display CPU feature flags 2103 */ 2104 2105 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 2106 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 2107 2108 /* These next two are actually common definitions! */ 2109 print_bits(cpuname, "features2", 2110 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 2111 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 2112 print_bits(cpuname, "features3", 2113 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 2114 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 2115 2116 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 2117 ci->ci_feat_val[4]); 2118 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2119 print_bits(cpuname, "features5", CPUID_SEF_FLAGS, 2120 ci->ci_feat_val[5]); 2121 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2122 print_bits(cpuname, "features6", CPUID_SEF_FLAGS1, 2123 ci->ci_feat_val[6]); 2124 2125 if (cpu_vendor == CPUVENDOR_INTEL) 2126 print_bits(cpuname, "features7", CPUID_SEF_FLAGS2, 2127 ci->ci_feat_val[7]); 2128 2129 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[8]); 2130 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 2131 ci->ci_feat_val[9]); 2132 2133 if (ci->ci_max_xsave != 0) { 2134 aprint_normal("%s: xsave area size: current %d, maximum %d", 2135 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 2136 aprint_normal(", xgetbv %sabled\n", 2137 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 2138 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 2139 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 2140 x86_xgetbv()); 2141 } 2142 2143 x86_print_cache_and_tlb_info(ci); 2144 2145 if (ci->ci_max_cpuid >= 3 && (ci->ci_feat_val[0] & CPUID_PSN)) { 2146 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 2147 cpuname, 2148 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 2149 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 2150 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 2151 } 2152 2153 if (ci->ci_cpu_class == CPUCLASS_386) 2154 errx(1, "NetBSD requires an 80486 or later processor"); 2155 2156 if (ci->ci_cpu_type == CPU_486DLC) { 2157 #ifndef CYRIX_CACHE_WORKS 2158 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 2159 #else 2160 #ifndef CYRIX_CACHE_REALLY_WORKS 2161 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 2162 #else 2163 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 2164 #endif 2165 #endif 2166 } 2167 2168 /* 2169 * Everything past this point requires a Pentium or later. 2170 */ 2171 if (ci->ci_max_cpuid < 0) 2172 return; 2173 2174 identifycpu_cpuids(ci); 2175 2176 if ((ci->ci_max_cpuid >= 5) 2177 && ((cpu_vendor == CPUVENDOR_INTEL) 2178 || (cpu_vendor == CPUVENDOR_AMD))) { 2179 uint16_t lmin, lmax; 2180 x86_cpuid(5, descs); 2181 2182 print_bits(cpuname, "MONITOR/MWAIT extensions", 2183 CPUID_MON_FLAGS, descs[2]); 2184 lmin = __SHIFTOUT(descs[0], CPUID_MON_MINSIZE); 2185 lmax = __SHIFTOUT(descs[1], CPUID_MON_MAXSIZE); 2186 aprint_normal("%s: monitor-line size %hu", cpuname, lmin); 2187 if (lmin != lmax) 2188 aprint_normal("-%hu", lmax); 2189 aprint_normal("\n"); 2190 2191 for (i = 0; i <= 7; i++) { 2192 unsigned int num = CPUID_MON_SUBSTATE(descs[3], i); 2193 2194 if (num != 0) 2195 aprint_normal("%s: C%u substates %u\n", 2196 cpuname, i, num); 2197 } 2198 } 2199 if ((ci->ci_max_cpuid >= 6) 2200 && ((cpu_vendor == CPUVENDOR_INTEL) 2201 || (cpu_vendor == CPUVENDOR_AMD))) { 2202 x86_cpuid(6, descs); 2203 print_bits(cpuname, "DSPM-eax", CPUID_DSPM_FLAGS, descs[0]); 2204 print_bits(cpuname, "DSPM-ecx", CPUID_DSPM_FLAGS1, descs[2]); 2205 } 2206 if ((ci->ci_max_cpuid >= 7) 2207 && ((cpu_vendor == CPUVENDOR_INTEL) 2208 || (cpu_vendor == CPUVENDOR_AMD))) { 2209 x86_cpuid(7, descs); 2210 aprint_verbose("%s: SEF highest subleaf %08x\n", 2211 cpuname, descs[0]); 2212 if (descs[0] >= 1) { 2213 x86_cpuid2(7, 1, descs); 2214 print_bits(cpuname, "SEF-subleaf1-eax", 2215 CPUID_SEF1_FLAGS_A, descs[0]); 2216 } 2217 } 2218 2219 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) { 2220 if (ci->ci_max_ext_cpuid >= 0x80000007) 2221 powernow_probe(ci); 2222 2223 if (ci->ci_max_ext_cpuid >= 0x80000008) { 2224 x86_cpuid(0x80000008, descs); 2225 print_bits(cpuname, "AMD Extended features", 2226 CPUID_CAPEX_FLAGS, descs[1]); 2227 } 2228 } 2229 2230 if (cpu_vendor == CPUVENDOR_AMD) { 2231 if ((ci->ci_max_ext_cpuid >= 0x8000000a) 2232 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 2233 x86_cpuid(0x8000000a, descs); 2234 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 2235 descs[0] & 0xf); 2236 aprint_verbose("%s: SVM NASID %d\n", cpuname, 2237 descs[1]); 2238 print_bits(cpuname, "SVM features", 2239 CPUID_AMD_SVM_FLAGS, descs[3]); 2240 } 2241 if (ci->ci_max_ext_cpuid >= 0x8000001f) { 2242 x86_cpuid(0x8000001f, descs); 2243 print_bits(cpuname, "Encrypted Memory features", 2244 CPUID_AMD_ENCMEM_FLAGS, descs[0]); 2245 } 2246 } else if (cpu_vendor == CPUVENDOR_INTEL) { 2247 if (ci->ci_max_cpuid >= 0x0a) { 2248 x86_cpuid(0x0a, descs); 2249 print_bits(cpuname, "Perfmon-eax", 2250 CPUID_PERF_FLAGS0, descs[0]); 2251 print_bits(cpuname, "Perfmon-ebx", 2252 CPUID_PERF_FLAGS1, descs[1]); 2253 print_bits(cpuname, "Perfmon-edx", 2254 CPUID_PERF_FLAGS3, descs[3]); 2255 } 2256 if (ci->ci_max_cpuid >= 0x1a) { 2257 x86_cpuid(0x1a, descs); 2258 if (descs[0] != 0) { 2259 aprint_verbose("%s: Hybrid: Core type %02x, " 2260 "Native Model ID %07x\n", 2261 cpuname, 2262 (uint8_t)__SHIFTOUT(descs[0], 2263 CPUID_HYBRID_CORETYPE), 2264 (uint32_t)__SHIFTOUT(descs[0], 2265 CPUID_HYBRID_NATIVEID)); 2266 } 2267 } 2268 } 2269 2270 #ifdef INTEL_ONDEMAND_CLOCKMOD 2271 clockmod_init(); 2272 #endif 2273 2274 if (cpu_vendor == CPUVENDOR_AMD) 2275 ucode.loader_version = CPU_UCODE_LOADER_AMD; 2276 else if (cpu_vendor == CPUVENDOR_INTEL) 2277 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 2278 else 2279 return; 2280 2281 ucode.data = &ucvers; 2282 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 2283 #ifdef __i386__ 2284 struct cpu_ucode_version_64 ucode_64; 2285 if (errno != ENOTTY) 2286 return; 2287 /* Try the 64 bit ioctl */ 2288 memset(&ucode_64, 0, sizeof ucode_64); 2289 ucode_64.data = &ucvers; 2290 ucode_64.loader_version = ucode.loader_version; 2291 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 2292 return; 2293 #else 2294 return; 2295 #endif 2296 } 2297 2298 if (cpu_vendor == CPUVENDOR_AMD) 2299 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2300 else if (cpu_vendor == CPUVENDOR_INTEL) 2301 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2302 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2303 } 2304 2305 static const char * 2306 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2307 const char *sep) 2308 { 2309 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2310 char human_num[HUMAN_BUFSIZE]; 2311 2312 if (cai->cai_totalsize == 0) 2313 return sep; 2314 2315 if (sep == NULL) 2316 aprint_verbose_dev(ci->ci_dev, ""); 2317 else 2318 aprint_verbose("%s", sep); 2319 if (name != NULL) 2320 aprint_verbose("%s ", name); 2321 2322 if (cai->cai_string != NULL) { 2323 aprint_verbose("%s ", cai->cai_string); 2324 } else { 2325 (void)humanize_number(human_num, sizeof(human_num), 2326 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2327 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2328 } 2329 switch (cai->cai_associativity) { 2330 case 0: 2331 aprint_verbose("disabled"); 2332 break; 2333 case 1: 2334 aprint_verbose("direct-mapped"); 2335 break; 2336 case 0xff: 2337 aprint_verbose("fully associative"); 2338 break; 2339 default: 2340 aprint_verbose("%d-way", cai->cai_associativity); 2341 break; 2342 } 2343 return ", "; 2344 } 2345 2346 static const char * 2347 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2348 const char *sep) 2349 { 2350 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2351 char human_num[HUMAN_BUFSIZE]; 2352 2353 if (cai->cai_totalsize == 0) 2354 return sep; 2355 2356 if (sep == NULL) 2357 aprint_verbose_dev(ci->ci_dev, ""); 2358 else 2359 aprint_verbose("%s", sep); 2360 if ((name != NULL) && (sep == NULL)) 2361 aprint_verbose("%s ", name); 2362 2363 if (cai->cai_string != NULL) { 2364 aprint_verbose("%s", cai->cai_string); 2365 } else { 2366 (void)humanize_number(human_num, sizeof(human_num), 2367 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2368 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2369 human_num); 2370 switch (cai->cai_associativity) { 2371 case 0: 2372 aprint_verbose("disabled"); 2373 break; 2374 case 1: 2375 aprint_verbose("direct-mapped"); 2376 break; 2377 case 0xff: 2378 aprint_verbose("fully associative"); 2379 break; 2380 default: 2381 aprint_verbose("%d-way", cai->cai_associativity); 2382 break; 2383 } 2384 } 2385 return ", "; 2386 } 2387 2388 static void 2389 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2390 { 2391 const char *sep = NULL; 2392 2393 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2394 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2395 sep = print_cache_config(ci, CAI_ICACHE, "I-cache:", NULL); 2396 sep = print_cache_config(ci, CAI_DCACHE, "D-cache:", sep); 2397 if (sep != NULL) 2398 aprint_verbose("\n"); 2399 } 2400 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2401 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache:", NULL); 2402 if (sep != NULL) 2403 aprint_verbose("\n"); 2404 } 2405 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2406 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache:", NULL); 2407 if (sep != NULL) 2408 aprint_verbose("\n"); 2409 } 2410 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2411 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2412 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2413 if (sep != NULL) 2414 aprint_verbose("\n"); 2415 } 2416 2417 sep = print_tlb_config(ci, CAI_ITLB, "ITLB:", NULL); 2418 sep = print_tlb_config(ci, CAI_ITLB2, "ITLB:", sep); 2419 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "ITLB:", sep); 2420 if (sep != NULL) 2421 aprint_verbose("\n"); 2422 2423 sep = print_tlb_config(ci, CAI_DTLB, "DTLB:", NULL); 2424 sep = print_tlb_config(ci, CAI_DTLB2, "DTLB:", sep); 2425 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "DTLB:", sep); 2426 if (sep != NULL) 2427 aprint_verbose("\n"); 2428 2429 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB:", NULL); 2430 sep = print_tlb_config(ci, CAI_L2_ITLB2, "L2 ITLB:", sep); 2431 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 ITLB:", sep); 2432 if (sep != NULL) 2433 aprint_verbose("\n"); 2434 2435 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB:", NULL); 2436 sep = print_tlb_config(ci, CAI_L2_DTLB2, "L2 DTLB:", sep); 2437 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 DTLB:", sep); 2438 if (sep != NULL) 2439 aprint_verbose("\n"); 2440 2441 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB:", NULL); 2442 sep = print_tlb_config(ci, CAI_L2_STLB2, "L2 STLB:", sep); 2443 sep = print_tlb_config(ci, CAI_L2_STLB3, "L2 STLB:", sep); 2444 if (sep != NULL) 2445 aprint_verbose("\n"); 2446 } 2447 2448 static void 2449 powernow_probe(struct cpu_info *ci) 2450 { 2451 uint32_t regs[4]; 2452 char buf[256]; 2453 2454 x86_cpuid(0x80000007, regs); 2455 2456 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2457 aprint_normal_dev(ci->ci_dev, "Power Management features: %s\n", buf); 2458 } 2459 2460 bool 2461 identifycpu_bind(void) 2462 { 2463 2464 return true; 2465 } 2466 2467 int 2468 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2469 { 2470 struct cpu_info ci; 2471 int loader_version, res; 2472 struct cpu_ucode_version versreq; 2473 2474 cpu_probe_base_features(&ci, "unknown"); 2475 2476 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2477 loader_version = CPU_UCODE_LOADER_AMD; 2478 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2479 loader_version = CPU_UCODE_LOADER_INTEL1; 2480 else 2481 return -1; 2482 2483 /* check whether the kernel understands this loader version */ 2484 versreq.loader_version = loader_version; 2485 versreq.data = 0; 2486 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2487 if (res) 2488 return -1; 2489 2490 switch (loader_version) { 2491 case CPU_UCODE_LOADER_AMD: 2492 if (uc->cpu_nr != -1) { 2493 /* printf? */ 2494 return -1; 2495 } 2496 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2497 break; 2498 case CPU_UCODE_LOADER_INTEL1: 2499 if (uc->cpu_nr == -1) 2500 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2501 else 2502 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2503 break; 2504 default: /* can't happen */ 2505 return -1; 2506 } 2507 uc->loader_version = loader_version; 2508 return 0; 2509 } 2510
Indexes created Thu Oct 23 22:10:10 GMT 2025