i386.c revision 1.104.2.12
1 /* $NetBSD: i386.c,v 1.104.2.12 2023/01/23 13:04:11 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.104.2.12 2023/01/23 13:04:11 martin Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cpu_ucode.h> 85 86 #include "../cpuctl.h" 87 #include "cpuctl_i386.h" 88 89 /* Size of buffer for printing humanized numbers */ 90 #define HUMAN_BUFSIZE sizeof("999KB") 91 92 struct cpu_nocpuid_nameclass { 93 int cpu_vendor; 94 const char *cpu_vendorname; 95 const char *cpu_name; 96 int cpu_class; 97 void (*cpu_setup)(struct cpu_info *); 98 void (*cpu_cacheinfo)(struct cpu_info *); 99 void (*cpu_info)(struct cpu_info *); 100 }; 101 102 struct cpu_cpuid_nameclass { 103 const char *cpu_id; 104 int cpu_vendor; 105 const char *cpu_vendorname; 106 struct cpu_cpuid_family { 107 int cpu_class; 108 const char *cpu_models[256]; 109 const char *cpu_model_default; 110 void (*cpu_setup)(struct cpu_info *); 111 void (*cpu_probe)(struct cpu_info *); 112 void (*cpu_info)(struct cpu_info *); 113 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 114 }; 115 116 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 117 118 /* 119 * Map Brand ID from cpuid instruction to brand name. 120 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 121 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 122 * Architectures Software Developer's Manual, Volume 2A". 123 */ 124 static const char * const i386_intel_brand[] = { 125 "", /* Unsupported */ 126 "Celeron", /* Intel (R) Celeron (TM) processor */ 127 "Pentium III", /* Intel (R) Pentium (R) III processor */ 128 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 129 "Pentium III", /* Intel (R) Pentium (R) III processor */ 130 "", /* 0x05: Reserved */ 131 "Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */ 132 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 133 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 134 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 135 "Celeron", /* Intel (R) Celeron (TM) processor */ 136 "Xeon", /* Intel (R) Xeon (TM) processor */ 137 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 138 "", /* 0x0d: Reserved */ 139 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 140 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 141 "", /* 0x10: Reserved */ 142 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 143 "Celeron M", /* Intel (R) Celeron (R) M processor */ 144 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 145 "Celeron", /* Intel (R) Celeron (R) processor */ 146 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 147 "Pentium M", /* Intel (R) Pentium (R) M processor */ 148 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 149 }; 150 151 /* 152 * AMD processors don't have Brand IDs, so we need these names for probe. 153 */ 154 static const char * const amd_brand[] = { 155 "", 156 "Duron", /* AMD Duron(tm) */ 157 "MP", /* AMD Athlon(tm) MP */ 158 "XP", /* AMD Athlon(tm) XP */ 159 "4" /* AMD Athlon(tm) 4 */ 160 }; 161 162 int cpu_vendor; 163 static char cpu_brand_string[49]; 164 static char amd_brand_name[48]; 165 static int use_pae, largepagesize; 166 167 /* Setup functions */ 168 static void disable_tsc(struct cpu_info *); 169 static void amd_family5_setup(struct cpu_info *); 170 static void cyrix6x86_cpu_setup(struct cpu_info *); 171 static void winchip_cpu_setup(struct cpu_info *); 172 /* Brand/Model name functions */ 173 static const char *intel_family6_name(struct cpu_info *); 174 static const char *amd_amd64_name(struct cpu_info *); 175 /* Probe functions */ 176 static void amd_family6_probe(struct cpu_info *); 177 static void powernow_probe(struct cpu_info *); 178 static void intel_family_new_probe(struct cpu_info *); 179 static void via_cpu_probe(struct cpu_info *); 180 /* (Cache) Info functions */ 181 static void intel_cpu_cacheinfo(struct cpu_info *); 182 static void amd_cpu_cacheinfo(struct cpu_info *); 183 static void via_cpu_cacheinfo(struct cpu_info *); 184 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 185 static void transmeta_cpu_info(struct cpu_info *); 186 /* Common functions */ 187 static void cpu_probe_base_features(struct cpu_info *, const char *); 188 static void cpu_probe_hv_features(struct cpu_info *, const char *); 189 static void cpu_probe_features(struct cpu_info *); 190 static void print_bits(const char *, const char *, const char *, uint32_t); 191 static void identifycpu_cpuids(struct cpu_info *); 192 static const char *print_cache_config(struct cpu_info *, int, const char *, 193 const char *); 194 static const char *print_tlb_config(struct cpu_info *, int, const char *, 195 const char *); 196 static void x86_print_cache_and_tlb_info(struct cpu_info *); 197 198 /* 199 * Note: these are just the ones that may not have a cpuid instruction. 200 * We deal with the rest in a different way. 201 */ 202 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 203 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 204 NULL, NULL, NULL }, /* CPU_386SX */ 205 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 206 NULL, NULL, NULL }, /* CPU_386 */ 207 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 208 NULL, NULL, NULL }, /* CPU_486SX */ 209 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 210 NULL, NULL, NULL }, /* CPU_486 */ 211 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 212 NULL, NULL, NULL }, /* CPU_486DLC */ 213 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 214 NULL, NULL, NULL }, /* CPU_6x86 */ 215 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 216 NULL, NULL, NULL }, /* CPU_NX586 */ 217 }; 218 219 const char *classnames[] = { 220 "386", 221 "486", 222 "586", 223 "686" 224 }; 225 226 const char *modifiers[] = { 227 "", 228 "OverDrive", 229 "Dual", 230 "" 231 }; 232 233 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 234 { 235 /* 236 * For Intel processors, check Chapter 35Model-specific 237 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 238 * Software Developer's Manual, Volume 3C". 239 */ 240 "GenuineIntel", 241 CPUVENDOR_INTEL, 242 "Intel", 243 /* Family 4 */ 244 { { 245 CPUCLASS_486, 246 { 247 "486DX", "486DX", "486SX", "486DX2", "486SL", 248 "486SX2", 0, "486DX2 W/B Enhanced", 249 "486DX4", 0, 0, 0, 0, 0, 0, 0, 250 }, 251 "486", /* Default */ 252 NULL, 253 NULL, 254 intel_cpu_cacheinfo, 255 }, 256 /* Family 5 */ 257 { 258 CPUCLASS_586, 259 { 260 "Pentium (P5 A-step)", "Pentium (P5)", 261 "Pentium (P54C)", "Pentium (P24T)", 262 "Pentium/MMX", "Pentium", 0, 263 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 264 "Quark X1000", 0, 0, 0, 0, 0, 0, 265 }, 266 "Pentium", /* Default */ 267 NULL, 268 NULL, 269 intel_cpu_cacheinfo, 270 }, 271 /* Family 6 */ 272 { 273 CPUCLASS_686, 274 { 275 [0x00] = "Pentium Pro (A-step)", 276 [0x01] = "Pentium Pro", 277 [0x03] = "Pentium II (Klamath)", 278 [0x04] = "Pentium Pro", 279 [0x05] = "Pentium II/Celeron (Deschutes)", 280 [0x06] = "Celeron (Mendocino)", 281 [0x07] = "Pentium III (Katmai)", 282 [0x08] = "Pentium III (Coppermine)", 283 [0x09] = "Pentium M (Banias)", 284 [0x0a] = "Pentium III Xeon (Cascades)", 285 [0x0b] = "Pentium III (Tualatin)", 286 [0x0d] = "Pentium M (Dothan)", 287 [0x0e] = "Pentium Core Duo, Core solo", 288 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 289 "Core 2 Quad 6xxx, " 290 "Core 2 Extreme 6xxx, " 291 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 292 "and Pentium DC", 293 [0x15] = "EP80579 Integrated Processor", 294 [0x16] = "Celeron (45nm)", 295 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 296 "Core 2 Quad 8xxx and 9xxx", 297 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 298 "(Nehalem)", 299 [0x1c] = "45nm Atom Family", 300 [0x1d] = "XeonMP 74xx (Nehalem)", 301 [0x1e] = "Core i7 and i5", 302 [0x1f] = "Core i7 and i5", 303 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 304 [0x26] = "Atom Family", 305 [0x27] = "Atom Family", 306 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 307 "i3 2xxx", 308 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 309 [0x2d] = "Xeon E5 Sandy Bridge family, " 310 "Core i7-39xx Extreme", 311 [0x2e] = "Xeon 75xx & 65xx", 312 [0x2f] = "Xeon E7 family", 313 [0x35] = "Atom Family", 314 [0x36] = "Atom S1000", 315 [0x37] = "Atom E3000, Z3[67]00", 316 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 317 "Ivy Bridge", 318 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 319 "(Haswell)", 320 [0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)", 321 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 322 "Core i7-49xx Extreme", 323 [0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), " 324 "Core i7-59xx Extreme", 325 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 326 "(Haswell)", 327 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 328 "(Haswell)", 329 [0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)", 330 [0x4a] = "Atom Z3400", 331 [0x4c] = "Atom X[57]-Z8000 (Airmont)", 332 [0x4d] = "Atom C2000", 333 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 334 [0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme", 335 [0x55] = "Xeon Scalable (Skylake, Cascade Lake, Copper Lake)", 336 [0x56] = "Xeon D-1500 (Broadwell)", 337 [0x57] = "Xeon Phi [357]200 (Knights Landing)", 338 [0x5a] = "Atom E3500", 339 [0x5c] = "Atom (Goldmont)", 340 [0x5d] = "Atom X3-C3000 (Silvermont)", 341 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 342 [0x5f] = "Atom (Goldmont, Denverton)", 343 [0x66] = "8th gen Core i3 (Cannon Lake)", 344 [0x6a] = "3rd gen Xeon Scalable (Ice Lake)", 345 [0x6c] = "3rd gen Xeon Scalable (Ice Lake)", 346 [0x7a] = "Atom (Goldmont Plus)", 347 [0x7d] = "10th gen Core (Ice Lake)", 348 [0x7e] = "10th gen Core (Ice Lake)", 349 [0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)", 350 [0x86] = "Atom (Tremont)", 351 [0x8c] = "11th gen Core (Tiger Lake)", 352 [0x8d] = "11th gen Core (Tiger Lake)", 353 [0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 354 [0x8f] = "4th gen Xeon Scalable (Sapphire Rapids)", 355 [0x96] = "Atom x6000E (Elkhart Lake)", 356 [0x97] = "12th gen Core (Alder Lake)", 357 [0x9a] = "12th gen Core (Alder Lake)", 358 [0x9c] = "Pentium Silver N6xxx, Celeron N45xx, Celeron N51xx (Jasper Lake)", 359 [0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 360 [0xa5] = "10th gen Core (Comet Lake)", 361 [0xa6] = "10th gen Core (Comet Lake)", 362 [0xa7] = "11th gen Core (Rocket Lake)", 363 [0xa8] = "11th gen Core (Rocket Lake)", 364 [0xba] = "13th gen Core (Raptor Lake)", 365 [0xb7] = "13th gen Core (Raptor Lake)", 366 [0xbf] = "13th gen Core (Raptor Lake)", 367 }, 368 "Pentium Pro, II or III", /* Default */ 369 NULL, 370 intel_family_new_probe, 371 intel_cpu_cacheinfo, 372 }, 373 /* Family > 6 */ 374 { 375 CPUCLASS_686, 376 { 377 0, 0, 0, 0, 0, 0, 0, 0, 378 0, 0, 0, 0, 0, 0, 0, 0, 379 }, 380 "Pentium 4", /* Default */ 381 NULL, 382 intel_family_new_probe, 383 intel_cpu_cacheinfo, 384 } } 385 }, 386 { 387 "AuthenticAMD", 388 CPUVENDOR_AMD, 389 "AMD", 390 /* Family 4 */ 391 { { 392 CPUCLASS_486, 393 { 394 0, 0, 0, "Am486DX2 W/T", 395 0, 0, 0, "Am486DX2 W/B", 396 "Am486DX4 W/T or Am5x86 W/T 150", 397 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 398 0, 0, "Am5x86 W/T 133/160", 399 "Am5x86 W/B 133/160", 400 }, 401 "Am486 or Am5x86", /* Default */ 402 NULL, 403 NULL, 404 NULL, 405 }, 406 /* Family 5 */ 407 { 408 CPUCLASS_586, 409 { 410 "K5", "K5", "K5", "K5", 0, 0, "K6", 411 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 412 "K6-2+/III+", 0, 0, 413 }, 414 "K5 or K6", /* Default */ 415 amd_family5_setup, 416 NULL, 417 amd_cpu_cacheinfo, 418 }, 419 /* Family 6 */ 420 { 421 CPUCLASS_686, 422 { 423 0, "Athlon Model 1", "Athlon Model 2", 424 "Duron", "Athlon Model 4 (Thunderbird)", 425 0, "Athlon", "Duron", "Athlon", 0, 426 "Athlon", 0, 0, 0, 0, 0, 427 }, 428 "K7 (Athlon)", /* Default */ 429 NULL, 430 amd_family6_probe, 431 amd_cpu_cacheinfo, 432 }, 433 /* Family > 6 */ 434 { 435 CPUCLASS_686, 436 { 437 0, 0, 0, 0, 0, 0, 0, 0, 438 0, 0, 0, 0, 0, 0, 0, 0, 439 }, 440 "Unknown K8 (Athlon)", /* Default */ 441 NULL, 442 amd_family6_probe, 443 amd_cpu_cacheinfo, 444 } } 445 }, 446 { 447 "CyrixInstead", 448 CPUVENDOR_CYRIX, 449 "Cyrix", 450 /* Family 4 */ 451 { { 452 CPUCLASS_486, 453 { 454 0, 0, 0, 455 "MediaGX", 456 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 457 }, 458 "486", /* Default */ 459 cyrix6x86_cpu_setup, /* XXX ?? */ 460 NULL, 461 NULL, 462 }, 463 /* Family 5 */ 464 { 465 CPUCLASS_586, 466 { 467 0, 0, "6x86", 0, 468 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 469 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 470 }, 471 "6x86", /* Default */ 472 cyrix6x86_cpu_setup, 473 NULL, 474 NULL, 475 }, 476 /* Family 6 */ 477 { 478 CPUCLASS_686, 479 { 480 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 481 0, 0, 0, 0, 0, 0, 0, 0, 482 }, 483 "6x86MX", /* Default */ 484 cyrix6x86_cpu_setup, 485 NULL, 486 NULL, 487 }, 488 /* Family > 6 */ 489 { 490 CPUCLASS_686, 491 { 492 0, 0, 0, 0, 0, 0, 0, 0, 493 0, 0, 0, 0, 0, 0, 0, 0, 494 }, 495 "Unknown 6x86MX", /* Default */ 496 NULL, 497 NULL, 498 NULL, 499 } } 500 }, 501 { /* MediaGX is now owned by National Semiconductor */ 502 "Geode by NSC", 503 CPUVENDOR_CYRIX, /* XXX */ 504 "National Semiconductor", 505 /* Family 4, NSC never had any of these */ 506 { { 507 CPUCLASS_486, 508 { 509 0, 0, 0, 0, 0, 0, 0, 0, 510 0, 0, 0, 0, 0, 0, 0, 0, 511 }, 512 "486 compatible", /* Default */ 513 NULL, 514 NULL, 515 NULL, 516 }, 517 /* Family 5: Geode family, formerly MediaGX */ 518 { 519 CPUCLASS_586, 520 { 521 0, 0, 0, 0, 522 "Geode GX1", 523 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 524 }, 525 "Geode", /* Default */ 526 cyrix6x86_cpu_setup, 527 NULL, 528 amd_cpu_cacheinfo, 529 }, 530 /* Family 6, not yet available from NSC */ 531 { 532 CPUCLASS_686, 533 { 534 0, 0, 0, 0, 0, 0, 0, 0, 535 0, 0, 0, 0, 0, 0, 0, 0, 536 }, 537 "Pentium Pro compatible", /* Default */ 538 NULL, 539 NULL, 540 NULL, 541 }, 542 /* Family > 6, not yet available from NSC */ 543 { 544 CPUCLASS_686, 545 { 546 0, 0, 0, 0, 0, 0, 0, 0, 547 0, 0, 0, 0, 0, 0, 0, 0, 548 }, 549 "Pentium Pro compatible", /* Default */ 550 NULL, 551 NULL, 552 NULL, 553 } } 554 }, 555 { 556 "CentaurHauls", 557 CPUVENDOR_IDT, 558 "IDT", 559 /* Family 4, IDT never had any of these */ 560 { { 561 CPUCLASS_486, 562 { 563 0, 0, 0, 0, 0, 0, 0, 0, 564 0, 0, 0, 0, 0, 0, 0, 0, 565 }, 566 "486 compatible", /* Default */ 567 NULL, 568 NULL, 569 NULL, 570 }, 571 /* Family 5 */ 572 { 573 CPUCLASS_586, 574 { 575 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 576 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 577 }, 578 "WinChip", /* Default */ 579 winchip_cpu_setup, 580 NULL, 581 NULL, 582 }, 583 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 584 { 585 CPUCLASS_686, 586 { 587 0, 0, 0, 0, 0, 0, "C3 Samuel", 588 "C3 Samuel 2/Ezra", "C3 Ezra-T", 589 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 590 0, "VIA Nano", 591 }, 592 "Unknown VIA/IDT", /* Default */ 593 NULL, 594 via_cpu_probe, 595 via_cpu_cacheinfo, 596 }, 597 /* Family > 6, not yet available from VIA */ 598 { 599 CPUCLASS_686, 600 { 601 0, 0, 0, 0, 0, 0, 0, 0, 602 0, 0, 0, 0, 0, 0, 0, 0, 603 }, 604 "Pentium Pro compatible", /* Default */ 605 NULL, 606 NULL, 607 NULL, 608 } } 609 }, 610 { 611 "GenuineTMx86", 612 CPUVENDOR_TRANSMETA, 613 "Transmeta", 614 /* Family 4, Transmeta never had any of these */ 615 { { 616 CPUCLASS_486, 617 { 618 0, 0, 0, 0, 0, 0, 0, 0, 619 0, 0, 0, 0, 0, 0, 0, 0, 620 }, 621 "486 compatible", /* Default */ 622 NULL, 623 NULL, 624 NULL, 625 }, 626 /* Family 5 */ 627 { 628 CPUCLASS_586, 629 { 630 0, 0, 0, 0, 0, 0, 0, 0, 631 0, 0, 0, 0, 0, 0, 0, 0, 632 }, 633 "Crusoe", /* Default */ 634 NULL, 635 NULL, 636 transmeta_cpu_info, 637 }, 638 /* Family 6, not yet available from Transmeta */ 639 { 640 CPUCLASS_686, 641 { 642 0, 0, 0, 0, 0, 0, 0, 0, 643 0, 0, 0, 0, 0, 0, 0, 0, 644 }, 645 "Pentium Pro compatible", /* Default */ 646 NULL, 647 NULL, 648 NULL, 649 }, 650 /* Family > 6, not yet available from Transmeta */ 651 { 652 CPUCLASS_686, 653 { 654 0, 0, 0, 0, 0, 0, 0, 0, 655 0, 0, 0, 0, 0, 0, 0, 0, 656 }, 657 "Pentium Pro compatible", /* Default */ 658 NULL, 659 NULL, 660 NULL, 661 } } 662 } 663 }; 664 665 /* 666 * disable the TSC such that we don't use the TSC in microtime(9) 667 * because some CPUs got the implementation wrong. 668 */ 669 static void 670 disable_tsc(struct cpu_info *ci) 671 { 672 if (ci->ci_feat_val[0] & CPUID_TSC) { 673 ci->ci_feat_val[0] &= ~CPUID_TSC; 674 aprint_error("WARNING: broken TSC disabled\n"); 675 } 676 } 677 678 static void 679 amd_family5_setup(struct cpu_info *ci) 680 { 681 682 switch (ci->ci_model) { 683 case 0: /* AMD-K5 Model 0 */ 684 /* 685 * According to the AMD Processor Recognition App Note, 686 * the AMD-K5 Model 0 uses the wrong bit to indicate 687 * support for global PTEs, instead using bit 9 (APIC) 688 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 689 */ 690 if (ci->ci_feat_val[0] & CPUID_APIC) 691 ci->ci_feat_val[0] = 692 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 693 /* 694 * XXX But pmap_pg_g is already initialized -- need to kick 695 * XXX the pmap somehow. How does the MP branch do this? 696 */ 697 break; 698 } 699 } 700 701 static void 702 cyrix6x86_cpu_setup(struct cpu_info *ci) 703 { 704 705 /* 706 * Do not disable the TSC on the Geode GX, it's reported to 707 * work fine. 708 */ 709 if (ci->ci_signature != 0x552) 710 disable_tsc(ci); 711 } 712 713 static void 714 winchip_cpu_setup(struct cpu_info *ci) 715 { 716 switch (ci->ci_model) { 717 case 4: /* WinChip C6 */ 718 disable_tsc(ci); 719 } 720 } 721 722 723 static const char * 724 intel_family6_name(struct cpu_info *ci) 725 { 726 const char *ret = NULL; 727 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 728 729 if (ci->ci_model == 5) { 730 switch (l2cache) { 731 case 0: 732 case 128 * 1024: 733 ret = "Celeron (Covington)"; 734 break; 735 case 256 * 1024: 736 ret = "Mobile Pentium II (Dixon)"; 737 break; 738 case 512 * 1024: 739 ret = "Pentium II"; 740 break; 741 case 1 * 1024 * 1024: 742 case 2 * 1024 * 1024: 743 ret = "Pentium II Xeon"; 744 break; 745 } 746 } else if (ci->ci_model == 6) { 747 switch (l2cache) { 748 case 256 * 1024: 749 case 512 * 1024: 750 ret = "Mobile Pentium II"; 751 break; 752 } 753 } else if (ci->ci_model == 7) { 754 switch (l2cache) { 755 case 512 * 1024: 756 ret = "Pentium III"; 757 break; 758 case 1 * 1024 * 1024: 759 case 2 * 1024 * 1024: 760 ret = "Pentium III Xeon"; 761 break; 762 } 763 } else if (ci->ci_model >= 8) { 764 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 765 switch (ci->ci_brand_id) { 766 case 0x3: 767 if (ci->ci_signature == 0x6B1) 768 ret = "Celeron"; 769 break; 770 case 0x8: 771 if (ci->ci_signature >= 0xF13) 772 ret = "genuine processor"; 773 break; 774 case 0xB: 775 if (ci->ci_signature >= 0xF13) 776 ret = "Xeon MP"; 777 break; 778 case 0xE: 779 if (ci->ci_signature < 0xF13) 780 ret = "Xeon"; 781 break; 782 } 783 if (ret == NULL) 784 ret = i386_intel_brand[ci->ci_brand_id]; 785 } 786 } 787 788 return ret; 789 } 790 791 /* 792 * Identify AMD64 CPU names from cpuid. 793 * 794 * Based on: 795 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 796 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 797 * "Revision Guide for AMD NPT Family 0Fh Processors" 798 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 799 * and other miscellaneous reports. 800 * 801 * This is all rather pointless, these are cross 'brand' since the raw 802 * silicon is shared. 803 */ 804 static const char * 805 amd_amd64_name(struct cpu_info *ci) 806 { 807 static char family_str[32]; 808 809 /* Only called if family >= 15 */ 810 811 switch (ci->ci_family) { 812 case 15: 813 switch (ci->ci_model) { 814 case 0x21: /* rev JH-E1/E6 */ 815 case 0x41: /* rev JH-F2 */ 816 return "Dual-Core Opteron"; 817 case 0x23: /* rev JH-E6 (Toledo) */ 818 return "Dual-Core Opteron or Athlon 64 X2"; 819 case 0x43: /* rev JH-F2 (Windsor) */ 820 return "Athlon 64 FX or Athlon 64 X2"; 821 case 0x24: /* rev SH-E5 (Lancaster?) */ 822 return "Mobile Athlon 64 or Turion 64"; 823 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 824 return "Opteron or Athlon 64 FX"; 825 case 0x15: /* rev SH-D0 */ 826 case 0x25: /* rev SH-E4 */ 827 return "Opteron"; 828 case 0x27: /* rev DH-E4, SH-E4 */ 829 return "Athlon 64 or Athlon 64 FX or Opteron"; 830 case 0x48: /* rev BH-F2 */ 831 return "Turion 64 X2"; 832 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 833 case 0x07: /* rev SH-CG (ClawHammer) */ 834 case 0x0b: /* rev CH-CG */ 835 case 0x14: /* rev SH-D0 */ 836 case 0x17: /* rev SH-D0 */ 837 case 0x1b: /* rev CH-D0 */ 838 return "Athlon 64"; 839 case 0x2b: /* rev BH-E4 (Manchester) */ 840 case 0x4b: /* rev BH-F2 (Windsor) */ 841 return "Athlon 64 X2"; 842 case 0x6b: /* rev BH-G1 (Brisbane) */ 843 return "Athlon X2 or Athlon 64 X2"; 844 case 0x08: /* rev CH-CG */ 845 case 0x0c: /* rev DH-CG (Newcastle) */ 846 case 0x0e: /* rev DH-CG (Newcastle?) */ 847 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 848 case 0x18: /* rev CH-D0 */ 849 case 0x1c: /* rev DH-D0 (Winchester) */ 850 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 851 case 0x2c: /* rev DH-E3/E6 */ 852 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 853 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 854 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 855 case 0x6f: /* rev DH-G1 */ 856 return "Athlon 64 or Sempron"; 857 default: 858 break; 859 } 860 return "Unknown AMD64 CPU"; 861 862 #if 0 863 case 16: 864 return "Family 10h"; 865 case 17: 866 return "Family 11h"; 867 case 18: 868 return "Family 12h"; 869 case 19: 870 return "Family 14h"; 871 case 20: 872 return "Family 15h"; 873 #endif 874 875 default: 876 break; 877 } 878 879 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 880 return family_str; 881 } 882 883 static void 884 intel_family_new_probe(struct cpu_info *ci) 885 { 886 uint32_t descs[4]; 887 888 x86_cpuid(0x80000000, descs); 889 890 /* 891 * Determine extended feature flags. 892 */ 893 if (descs[0] >= 0x80000001) { 894 x86_cpuid(0x80000001, descs); 895 ci->ci_feat_val[2] |= descs[3]; 896 ci->ci_feat_val[3] |= descs[2]; 897 } 898 } 899 900 static void 901 via_cpu_probe(struct cpu_info *ci) 902 { 903 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 904 u_int descs[4]; 905 u_int lfunc; 906 907 /* 908 * Determine the largest extended function value. 909 */ 910 x86_cpuid(0x80000000, descs); 911 lfunc = descs[0]; 912 913 /* 914 * Determine the extended feature flags. 915 */ 916 if (lfunc >= 0x80000001) { 917 x86_cpuid(0x80000001, descs); 918 ci->ci_feat_val[2] |= descs[3]; 919 } 920 921 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 922 return; 923 924 /* Nehemiah or Esther */ 925 x86_cpuid(0xc0000000, descs); 926 lfunc = descs[0]; 927 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 928 return; 929 930 x86_cpuid(0xc0000001, descs); 931 lfunc = descs[3]; 932 ci->ci_feat_val[4] = lfunc; 933 } 934 935 static void 936 amd_family6_probe(struct cpu_info *ci) 937 { 938 uint32_t descs[4]; 939 char *p; 940 size_t i; 941 942 x86_cpuid(0x80000000, descs); 943 944 /* 945 * Determine the extended feature flags. 946 */ 947 if (descs[0] >= 0x80000001) { 948 x86_cpuid(0x80000001, descs); 949 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 950 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 951 } 952 953 if (*cpu_brand_string == '\0') 954 return; 955 956 for (i = 1; i < __arraycount(amd_brand); i++) 957 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 958 ci->ci_brand_id = i; 959 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 960 break; 961 } 962 } 963 964 static void 965 intel_cpu_cacheinfo(struct cpu_info *ci) 966 { 967 const struct x86_cache_info *cai; 968 u_int descs[4]; 969 int iterations, i, j; 970 int type, level, ways, linesize, sets; 971 int caitype = -1; 972 uint8_t desc; 973 974 /* Return if the cpu is old pre-cpuid instruction cpu */ 975 if (ci->ci_cpu_type >= 0) 976 return; 977 978 if (ci->ci_max_cpuid < 2) 979 return; 980 981 /* 982 * Parse the cache info from `cpuid leaf 2', if we have it. 983 * XXX This is kinda ugly, but hey, so is the architecture... 984 */ 985 x86_cpuid(2, descs); 986 iterations = descs[0] & 0xff; 987 while (iterations-- > 0) { 988 for (i = 0; i < 4; i++) { 989 if (descs[i] & 0x80000000) 990 continue; 991 for (j = 0; j < 4; j++) { 992 /* 993 * The least significant byte in EAX 994 * ((desc[0] >> 0) & 0xff) is always 0x01 and 995 * it should be ignored. 996 */ 997 if (i == 0 && j == 0) 998 continue; 999 desc = (descs[i] >> (j * 8)) & 0xff; 1000 if (desc == 0) 1001 continue; 1002 cai = cpu_cacheinfo_lookup( 1003 intel_cpuid_cache_info, desc); 1004 if (cai != NULL) 1005 ci->ci_cinfo[cai->cai_index] = *cai; 1006 else if ((verbose != 0) && (desc != 0xff) 1007 && (desc != 0xfe)) 1008 aprint_error_dev(ci->ci_dev, "error:" 1009 " Unknown cacheinfo desc %02x\n", 1010 desc); 1011 } 1012 } 1013 x86_cpuid(2, descs); 1014 } 1015 1016 if (ci->ci_max_cpuid < 4) 1017 return; 1018 1019 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1020 cpu_dcp_cacheinfo(ci, 4); 1021 1022 if (ci->ci_max_cpuid < 0x18) 1023 return; 1024 /* Parse the TLB info from `cpuid leaf 18H', if we have it. */ 1025 x86_cpuid(0x18, descs); 1026 iterations = descs[0]; 1027 for (i = 0; i <= iterations; i++) { 1028 uint32_t pgsize; 1029 bool full; 1030 1031 x86_cpuid2(0x18, i, descs); 1032 type = __SHIFTOUT(descs[3], CPUID_DATP_TCTYPE); 1033 if (type == CPUID_DATP_TCTYPE_N) 1034 continue; 1035 level = __SHIFTOUT(descs[3], CPUID_DATP_TCLEVEL); 1036 pgsize = __SHIFTOUT(descs[1], CPUID_DATP_PGSIZE); 1037 switch (level) { 1038 case 1: 1039 if (type == CPUID_DATP_TCTYPE_I) { 1040 switch (pgsize) { 1041 case CPUID_DATP_PGSIZE_4KB: 1042 caitype = CAI_ITLB; 1043 break; 1044 case CPUID_DATP_PGSIZE_2MB 1045 | CPUID_DATP_PGSIZE_4MB: 1046 caitype = CAI_ITLB2; 1047 break; 1048 case CPUID_DATP_PGSIZE_1GB: 1049 caitype = CAI_L1_1GBITLB; 1050 break; 1051 default: 1052 aprint_error_dev(ci->ci_dev, 1053 "error: unknown ITLB size (%d)\n", 1054 pgsize); 1055 caitype = CAI_ITLB; 1056 break; 1057 } 1058 } else if (type == CPUID_DATP_TCTYPE_D) { 1059 switch (pgsize) { 1060 case CPUID_DATP_PGSIZE_4KB: 1061 caitype = CAI_DTLB; 1062 break; 1063 case CPUID_DATP_PGSIZE_2MB 1064 | CPUID_DATP_PGSIZE_4MB: 1065 caitype = CAI_DTLB2; 1066 break; 1067 case CPUID_DATP_PGSIZE_1GB: 1068 caitype = CAI_L1_1GBDTLB; 1069 break; 1070 default: 1071 aprint_error_dev(ci->ci_dev, 1072 "error: unknown DTLB size (%d)\n", 1073 pgsize); 1074 caitype = CAI_DTLB; 1075 break; 1076 } 1077 } else 1078 caitype = -1; 1079 break; 1080 case 2: 1081 if (type == CPUID_DATP_TCTYPE_I) 1082 caitype = CAI_L2_ITLB; 1083 else if (type == CPUID_DATP_TCTYPE_D) 1084 caitype = CAI_L2_DTLB; 1085 else if (type == CPUID_DATP_TCTYPE_U) { 1086 if (pgsize == CPUID_DATP_PGSIZE_4KB) 1087 caitype = CAI_L2_STLB; 1088 else if (pgsize == (CPUID_DATP_PGSIZE_4KB 1089 | CPUID_DATP_PGSIZE_2MB)) 1090 caitype = CAI_L2_STLB2; 1091 else if (pgsize == (CPUID_DATP_PGSIZE_2MB 1092 | CPUID_DATP_PGSIZE_4MB)) 1093 caitype = CAI_L2_STLB3; 1094 else if ((pgsize & CPUID_DATP_PGSIZE_1GB) 1095 != 0) { 1096 /* FIXME: 1GB max TLB */ 1097 caitype = CAI_L2_STLB3; 1098 linesize = 1024 * 1024 * 1024; 1099 } else if ((pgsize & CPUID_DATP_PGSIZE_4MB) 1100 != 0) { 1101 /* FIXME: 4MB max TLB */ 1102 caitype = CAI_L2_STLB3; 1103 linesize = 4 * 1024 * 1024; 1104 } else if ((pgsize & CPUID_DATP_PGSIZE_2MB) 1105 != 0) { 1106 /* FIXME: 2MB max TLB */ 1107 caitype = CAI_L2_STLB2; 1108 linesize = 2 * 1024 * 1024; 1109 } else { 1110 aprint_error_dev(ci->ci_dev, "error: " 1111 "unknown L2 STLB size (%d)\n", 1112 pgsize); 1113 caitype = CAI_L2_STLB; 1114 linesize = 4 * 1024; 1115 } 1116 } else 1117 caitype = -1; 1118 break; 1119 case 3: 1120 /* XXX need work for L3 TLB */ 1121 caitype = CAI_L3CACHE; 1122 break; 1123 default: 1124 caitype = -1; 1125 break; 1126 } 1127 if (caitype == -1) { 1128 aprint_error_dev(ci->ci_dev, 1129 "error: unknown TLB level&type (%d & %d)\n", 1130 level, type); 1131 continue; 1132 } 1133 switch (pgsize) { 1134 case CPUID_DATP_PGSIZE_4KB: 1135 linesize = 4 * 1024; 1136 break; 1137 case CPUID_DATP_PGSIZE_2MB: 1138 linesize = 2 * 1024 * 1024; 1139 break; 1140 case CPUID_DATP_PGSIZE_4MB: 1141 linesize = 4 * 1024 * 1024; 1142 break; 1143 case CPUID_DATP_PGSIZE_1GB: 1144 linesize = 1024 * 1024 * 1024; 1145 break; 1146 default: 1147 if ((pgsize & CPUID_DATP_PGSIZE_1GB) != 0) 1148 linesize = 1024 * 1024 * 1024; /* MAX 1G */ 1149 else if ((pgsize & CPUID_DATP_PGSIZE_4MB) != 0) 1150 linesize = 4 * 1024 * 1024; /* MAX 4M */ 1151 else if ((pgsize & CPUID_DATP_PGSIZE_2MB) != 0) 1152 linesize = 2 * 1024 * 1024; /* MAX 2M */ 1153 else 1154 linesize = 4 * 1024; /* XXX default to 4K */ 1155 aprint_error_dev(ci->ci_dev, "WARNING: Currently " 1156 "this info can't print correctly " 1157 "(level = %d, pgsize = %d)\n", 1158 level, pgsize); 1159 break; 1160 } 1161 ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS); 1162 sets = descs[2]; 1163 full = descs[3] & CPUID_DATP_FULLASSOC; 1164 ci->ci_cinfo[caitype].cai_totalsize 1165 = ways * sets; /* entries */ 1166 ci->ci_cinfo[caitype].cai_associativity 1167 = full ? 0xff : ways; 1168 ci->ci_cinfo[caitype].cai_linesize = linesize; /* pg size */ 1169 } 1170 } 1171 1172 static const struct x86_cache_info amd_cpuid_l2l3cache_assoc_info[] = 1173 AMD_L2L3CACHE_INFO; 1174 1175 static void 1176 amd_cpu_cacheinfo(struct cpu_info *ci) 1177 { 1178 const struct x86_cache_info *cp; 1179 struct x86_cache_info *cai; 1180 u_int descs[4]; 1181 u_int lfunc; 1182 1183 /* K5 model 0 has none of this info. */ 1184 if (ci->ci_family == 5 && ci->ci_model == 0) 1185 return; 1186 1187 /* Determine the largest extended function value. */ 1188 x86_cpuid(0x80000000, descs); 1189 lfunc = descs[0]; 1190 1191 if (lfunc < 0x80000005) 1192 return; 1193 1194 /* Determine L1 cache/TLB info. */ 1195 x86_cpuid(0x80000005, descs); 1196 1197 /* K6-III and higher have large page TLBs. */ 1198 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1199 cai = &ci->ci_cinfo[CAI_ITLB2]; 1200 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1201 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1202 cai->cai_linesize = largepagesize; 1203 1204 cai = &ci->ci_cinfo[CAI_DTLB2]; 1205 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1206 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1207 cai->cai_linesize = largepagesize; 1208 } 1209 1210 cai = &ci->ci_cinfo[CAI_ITLB]; 1211 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1212 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1213 cai->cai_linesize = (4 * 1024); 1214 1215 cai = &ci->ci_cinfo[CAI_DTLB]; 1216 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1217 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1218 cai->cai_linesize = (4 * 1024); 1219 1220 cai = &ci->ci_cinfo[CAI_DCACHE]; 1221 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1222 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1223 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1224 1225 cai = &ci->ci_cinfo[CAI_ICACHE]; 1226 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1227 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1228 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1229 1230 if (lfunc < 0x80000006) 1231 return; 1232 1233 /* Determine L2 cache/TLB info. */ 1234 x86_cpuid(0x80000006, descs); 1235 1236 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1237 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1238 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1239 cai->cai_linesize = (4 * 1024); 1240 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1241 cai->cai_associativity); 1242 if (cp != NULL) 1243 cai->cai_associativity = cp->cai_associativity; 1244 else 1245 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1246 1247 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1248 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1249 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1250 cai->cai_linesize = largepagesize; 1251 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1252 cai->cai_associativity); 1253 if (cp != NULL) 1254 cai->cai_associativity = cp->cai_associativity; 1255 else 1256 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1257 1258 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1259 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1260 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1261 cai->cai_linesize = (4 * 1024); 1262 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1263 cai->cai_associativity); 1264 if (cp != NULL) 1265 cai->cai_associativity = cp->cai_associativity; 1266 else 1267 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1268 1269 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1270 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1271 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1272 cai->cai_linesize = largepagesize; 1273 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1274 cai->cai_associativity); 1275 if (cp != NULL) 1276 cai->cai_associativity = cp->cai_associativity; 1277 else 1278 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1279 1280 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1281 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1282 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1283 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1284 1285 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1286 cai->cai_associativity); 1287 if (cp != NULL) 1288 cai->cai_associativity = cp->cai_associativity; 1289 else 1290 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1291 1292 /* Determine L3 cache info on AMD Family 10h and newer processors */ 1293 if (ci->ci_family >= 0x10) { 1294 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1295 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1296 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1297 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1298 1299 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1300 cai->cai_associativity); 1301 if (cp != NULL) 1302 cai->cai_associativity = cp->cai_associativity; 1303 else 1304 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1305 } 1306 1307 if (lfunc < 0x80000019) 1308 return; 1309 1310 /* Determine 1GB TLB info. */ 1311 x86_cpuid(0x80000019, descs); 1312 1313 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1314 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1315 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1316 cai->cai_linesize = (1024 * 1024 * 1024); 1317 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1318 cai->cai_associativity); 1319 if (cp != NULL) 1320 cai->cai_associativity = cp->cai_associativity; 1321 else 1322 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1323 1324 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1325 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1326 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1327 cai->cai_linesize = (1024 * 1024 * 1024); 1328 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1329 cai->cai_associativity); 1330 if (cp != NULL) 1331 cai->cai_associativity = cp->cai_associativity; 1332 else 1333 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1334 1335 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1336 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1337 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1338 cai->cai_linesize = (1024 * 1024 * 1024); 1339 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1340 cai->cai_associativity); 1341 if (cp != NULL) 1342 cai->cai_associativity = cp->cai_associativity; 1343 else 1344 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1345 1346 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1347 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1348 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1349 cai->cai_linesize = (1024 * 1024 * 1024); 1350 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1351 cai->cai_associativity); 1352 if (cp != NULL) 1353 cai->cai_associativity = cp->cai_associativity; 1354 else 1355 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1356 1357 if (lfunc < 0x8000001d) 1358 return; 1359 1360 if (ci->ci_feat_val[3] & CPUID_TOPOEXT) 1361 cpu_dcp_cacheinfo(ci, 0x8000001d); 1362 } 1363 1364 static void 1365 via_cpu_cacheinfo(struct cpu_info *ci) 1366 { 1367 struct x86_cache_info *cai; 1368 int stepping; 1369 u_int descs[4]; 1370 u_int lfunc; 1371 1372 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1373 1374 /* 1375 * Determine the largest extended function value. 1376 */ 1377 x86_cpuid(0x80000000, descs); 1378 lfunc = descs[0]; 1379 1380 /* 1381 * Determine L1 cache/TLB info. 1382 */ 1383 if (lfunc < 0x80000005) { 1384 /* No L1 cache info available. */ 1385 return; 1386 } 1387 1388 x86_cpuid(0x80000005, descs); 1389 1390 cai = &ci->ci_cinfo[CAI_ITLB]; 1391 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1392 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1393 cai->cai_linesize = (4 * 1024); 1394 1395 cai = &ci->ci_cinfo[CAI_DTLB]; 1396 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1397 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1398 cai->cai_linesize = (4 * 1024); 1399 1400 cai = &ci->ci_cinfo[CAI_DCACHE]; 1401 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1402 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1403 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1404 if (ci->ci_model == 9 && stepping == 8) { 1405 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1406 cai->cai_associativity = 2; 1407 } 1408 1409 cai = &ci->ci_cinfo[CAI_ICACHE]; 1410 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1411 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1412 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1413 if (ci->ci_model == 9 && stepping == 8) { 1414 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1415 cai->cai_associativity = 2; 1416 } 1417 1418 /* 1419 * Determine L2 cache/TLB info. 1420 */ 1421 if (lfunc < 0x80000006) { 1422 /* No L2 cache info available. */ 1423 return; 1424 } 1425 1426 x86_cpuid(0x80000006, descs); 1427 1428 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1429 if (ci->ci_model >= 9) { 1430 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1431 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1432 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1433 } else { 1434 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1435 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1436 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1437 } 1438 } 1439 1440 static void 1441 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1442 { 1443 u_int descs[4]; 1444 1445 x86_cpuid(0x80860007, descs); 1446 *frequency = descs[0]; 1447 *voltage = descs[1]; 1448 *percentage = descs[2]; 1449 } 1450 1451 static void 1452 transmeta_cpu_info(struct cpu_info *ci) 1453 { 1454 u_int descs[4], nreg; 1455 u_int frequency, voltage, percentage; 1456 1457 x86_cpuid(0x80860000, descs); 1458 nreg = descs[0]; 1459 if (nreg >= 0x80860001) { 1460 x86_cpuid(0x80860001, descs); 1461 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1462 (descs[1] >> 24) & 0xff, 1463 (descs[1] >> 16) & 0xff, 1464 (descs[1] >> 8) & 0xff, 1465 descs[1] & 0xff); 1466 } 1467 if (nreg >= 0x80860002) { 1468 x86_cpuid(0x80860002, descs); 1469 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1470 (descs[1] >> 24) & 0xff, 1471 (descs[1] >> 16) & 0xff, 1472 (descs[1] >> 8) & 0xff, 1473 descs[1] & 0xff, 1474 descs[2]); 1475 } 1476 if (nreg >= 0x80860006) { 1477 union { 1478 char text[65]; 1479 u_int descs[4][4]; 1480 } info; 1481 int i; 1482 1483 for (i=0; i<4; i++) { 1484 x86_cpuid(0x80860003 + i, info.descs[i]); 1485 } 1486 info.text[64] = '\0'; 1487 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1488 } 1489 1490 if (nreg >= 0x80860007) { 1491 tmx86_get_longrun_status(&frequency, 1492 &voltage, &percentage); 1493 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1494 frequency, voltage, percentage); 1495 } 1496 } 1497 1498 static void 1499 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1500 { 1501 u_int descs[4]; 1502 int i; 1503 uint32_t brand[12]; 1504 1505 memset(ci, 0, sizeof(*ci)); 1506 ci->ci_dev = cpuname; 1507 1508 ci->ci_cpu_type = x86_identify(); 1509 if (ci->ci_cpu_type >= 0) { 1510 /* Old pre-cpuid instruction cpu */ 1511 ci->ci_max_cpuid = -1; 1512 return; 1513 } 1514 1515 /* 1516 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1517 * function. 1518 */ 1519 1520 /* 1521 * Fn0000_0000: 1522 * - Save cpuid max level. 1523 * - Save vendor string. 1524 */ 1525 x86_cpuid(0, descs); 1526 ci->ci_max_cpuid = descs[0]; 1527 /* Save vendor string */ 1528 ci->ci_vendor[0] = descs[1]; 1529 ci->ci_vendor[2] = descs[2]; 1530 ci->ci_vendor[1] = descs[3]; 1531 ci->ci_vendor[3] = 0; 1532 1533 /* 1534 * Fn8000_0000: 1535 * - Get cpuid extended function's max level. 1536 */ 1537 x86_cpuid(0x80000000, descs); 1538 if (descs[0] >= 0x80000000) 1539 ci->ci_max_ext_cpuid = descs[0]; 1540 else { 1541 /* Set lower value than 0x80000000 */ 1542 ci->ci_max_ext_cpuid = 0; 1543 } 1544 1545 /* 1546 * Fn8000_000[2-4]: 1547 * - Save brand string. 1548 */ 1549 if (ci->ci_max_ext_cpuid >= 0x80000004) { 1550 x86_cpuid(0x80000002, brand); 1551 x86_cpuid(0x80000003, brand + 4); 1552 x86_cpuid(0x80000004, brand + 8); 1553 for (i = 0; i < 48; i++) 1554 if (((char *) brand)[i] != ' ') 1555 break; 1556 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1557 } 1558 1559 if (ci->ci_max_cpuid < 1) 1560 return; 1561 1562 /* 1563 * Fn0000_0001: 1564 * - Get CPU family, model and stepping (from eax). 1565 * - Initial local APIC ID and brand ID (from ebx) 1566 * - CPUID2 (from ecx) 1567 * - CPUID (from edx) 1568 */ 1569 x86_cpuid(1, descs); 1570 ci->ci_signature = descs[0]; 1571 1572 /* Extract full family/model values */ 1573 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1574 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1575 1576 /* Brand is low order 8 bits of ebx */ 1577 ci->ci_brand_id = __SHIFTOUT(descs[1], CPUID_BRAND_INDEX); 1578 /* Initial local APIC ID */ 1579 ci->ci_initapicid = __SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID); 1580 1581 ci->ci_feat_val[1] = descs[2]; 1582 ci->ci_feat_val[0] = descs[3]; 1583 1584 if (ci->ci_max_cpuid < 3) 1585 return; 1586 1587 /* 1588 * If the processor serial number misfeature is present and supported, 1589 * extract it here. 1590 */ 1591 if ((ci->ci_feat_val[0] & CPUID_PSN) != 0) { 1592 ci->ci_cpu_serial[0] = ci->ci_signature; 1593 x86_cpuid(3, descs); 1594 ci->ci_cpu_serial[2] = descs[2]; 1595 ci->ci_cpu_serial[1] = descs[3]; 1596 } 1597 1598 if (ci->ci_max_cpuid < 0x7) 1599 return; 1600 1601 x86_cpuid(7, descs); 1602 ci->ci_feat_val[5] = descs[1]; 1603 ci->ci_feat_val[6] = descs[2]; 1604 ci->ci_feat_val[7] = descs[3]; 1605 1606 if (ci->ci_max_cpuid < 0xd) 1607 return; 1608 1609 /* Get support XCR0 bits */ 1610 x86_cpuid2(0xd, 0, descs); 1611 ci->ci_feat_val[8] = descs[0]; /* Actually 64 bits */ 1612 ci->ci_cur_xsave = descs[1]; 1613 ci->ci_max_xsave = descs[2]; 1614 1615 /* Additional flags (eg xsaveopt support) */ 1616 x86_cpuid2(0xd, 1, descs); 1617 ci->ci_feat_val[9] = descs[0]; /* Actually 64 bits */ 1618 } 1619 1620 static void 1621 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1622 { 1623 uint32_t descs[4]; 1624 char hv_sig[13]; 1625 char *p; 1626 const char *hv_name; 1627 int i; 1628 1629 /* 1630 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1631 * http://lkml.org/lkml/2008/10/1/246 1632 * 1633 * KB1009458: Mechanisms to determine if software is running in 1634 * a VMware virtual machine 1635 * http://kb.vmware.com/kb/1009458 1636 */ 1637 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1638 x86_cpuid(0x40000000, descs); 1639 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1640 memcpy(p, &descs[i], sizeof(descs[i])); 1641 *p = '\0'; 1642 /* 1643 * HV vendor ID string 1644 * ------------+-------------- 1645 * HAXM "HAXMHAXMHAXM" 1646 * KVM "KVMKVMKVM" 1647 * Microsoft "Microsoft Hv" 1648 * QEMU(TCG) "TCGTCGTCGTCG" 1649 * VMware "VMwareVMware" 1650 * Xen "XenVMMXenVMM" 1651 * NetBSD "___ NVMM ___" 1652 */ 1653 if (strncmp(hv_sig, "HAXMHAXMHAXM", 12) == 0) 1654 hv_name = "HAXM"; 1655 else if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1656 hv_name = "KVM"; 1657 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1658 hv_name = "Hyper-V"; 1659 else if (strncmp(hv_sig, "TCGTCGTCGTCG", 12) == 0) 1660 hv_name = "QEMU(TCG)"; 1661 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1662 hv_name = "VMware"; 1663 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1664 hv_name = "Xen"; 1665 else if (strncmp(hv_sig, "___ NVMM ___", 12) == 0) 1666 hv_name = "NVMM"; 1667 else 1668 hv_name = "unknown"; 1669 1670 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1671 } 1672 } 1673 1674 static void 1675 cpu_probe_features(struct cpu_info *ci) 1676 { 1677 const struct cpu_cpuid_nameclass *cpup = NULL; 1678 unsigned int i; 1679 1680 if (ci->ci_max_cpuid < 1) 1681 return; 1682 1683 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1684 if (!strncmp((char *)ci->ci_vendor, 1685 i386_cpuid_cpus[i].cpu_id, 12)) { 1686 cpup = &i386_cpuid_cpus[i]; 1687 break; 1688 } 1689 } 1690 1691 if (cpup == NULL) 1692 return; 1693 1694 i = ci->ci_family - CPU_MINFAMILY; 1695 1696 if (i >= __arraycount(cpup->cpu_family)) 1697 i = __arraycount(cpup->cpu_family) - 1; 1698 1699 if (cpup->cpu_family[i].cpu_probe == NULL) 1700 return; 1701 1702 (*cpup->cpu_family[i].cpu_probe)(ci); 1703 } 1704 1705 static void 1706 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1707 { 1708 char buf[32 * 16]; 1709 char *bp; 1710 1711 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1712 1713 if (val == 0 || fmt == NULL) 1714 return; 1715 1716 snprintb_m(buf, sizeof(buf), fmt, val, 1717 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1718 bp = buf; 1719 while (*bp != '\0') { 1720 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1721 bp += strlen(bp) + 1; 1722 } 1723 } 1724 1725 static void 1726 dump_descs(uint32_t leafstart, uint32_t leafend, const char *cpuname, 1727 const char *blockname) 1728 { 1729 uint32_t descs[4]; 1730 uint32_t leaf; 1731 1732 aprint_verbose("%s: highest %s info %08x\n", cpuname, blockname, 1733 leafend); 1734 1735 if (verbose) { 1736 for (leaf = leafstart; leaf <= leafend; leaf++) { 1737 x86_cpuid(leaf, descs); 1738 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1739 leaf, descs[0], descs[1], descs[2], descs[3]); 1740 } 1741 } 1742 } 1743 1744 static void 1745 identifycpu_cpuids_intel_0x04(struct cpu_info *ci) 1746 { 1747 u_int lp_max = 1; /* logical processors per package */ 1748 u_int smt_max; /* smt per core */ 1749 u_int core_max = 1; /* core per package */ 1750 u_int smt_bits, core_bits; 1751 uint32_t descs[4]; 1752 1753 /* 1754 * 253668.pdf 7.10.2 1755 */ 1756 1757 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1758 x86_cpuid(1, descs); 1759 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1760 } 1761 x86_cpuid2(4, 0, descs); 1762 core_max = __SHIFTOUT(descs[0], CPUID_DCP_CORE_P_PKG) + 1; 1763 1764 assert(lp_max >= core_max); 1765 smt_max = lp_max / core_max; 1766 smt_bits = ilog2(smt_max - 1) + 1; 1767 core_bits = ilog2(core_max - 1) + 1; 1768 1769 if (smt_bits + core_bits) 1770 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1771 1772 if (core_bits) 1773 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1774 __BITS(smt_bits, smt_bits + core_bits - 1)); 1775 1776 if (smt_bits) 1777 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1778 __BITS((int)0, (int)(smt_bits - 1))); 1779 } 1780 1781 static void 1782 identifycpu_cpuids_intel_0x0b(struct cpu_info *ci) 1783 { 1784 const char *cpuname = ci->ci_dev; 1785 u_int smt_bits, core_bits, core_shift = 0, pkg_shift = 0; 1786 uint32_t descs[4]; 1787 int i; 1788 1789 x86_cpuid(0x0b, descs); 1790 if (descs[1] == 0) { 1791 identifycpu_cpuids_intel_0x04(ci); 1792 return; 1793 } 1794 1795 for (i = 0; ; i++) { 1796 unsigned int shiftnum, lvltype; 1797 x86_cpuid2(0x0b, i, descs); 1798 1799 /* On invalid level, (EAX and) EBX return 0 */ 1800 if (descs[1] == 0) 1801 break; 1802 1803 shiftnum = __SHIFTOUT(descs[0], CPUID_TOP_SHIFTNUM); 1804 lvltype = __SHIFTOUT(descs[2], CPUID_TOP_LVLTYPE); 1805 switch (lvltype) { 1806 case CPUID_TOP_LVLTYPE_SMT: 1807 core_shift = shiftnum; 1808 break; 1809 case CPUID_TOP_LVLTYPE_CORE: 1810 pkg_shift = shiftnum; 1811 break; 1812 case CPUID_TOP_LVLTYPE_INVAL: 1813 aprint_verbose("%s: Invalid level type\n", cpuname); 1814 break; 1815 default: 1816 aprint_verbose("%s: Unknown level type(%d) \n", 1817 cpuname, lvltype); 1818 break; 1819 } 1820 } 1821 1822 assert(pkg_shift >= core_shift); 1823 smt_bits = core_shift; 1824 core_bits = pkg_shift - core_shift; 1825 1826 ci->ci_packageid = ci->ci_initapicid >> pkg_shift; 1827 1828 if (core_bits) 1829 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1830 __BITS(core_shift, pkg_shift - 1)); 1831 1832 if (smt_bits) 1833 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1834 __BITS((int)0, core_shift - 1)); 1835 } 1836 1837 static void 1838 identifycpu_cpuids_intel(struct cpu_info *ci) 1839 { 1840 const char *cpuname = ci->ci_dev; 1841 1842 if (ci->ci_max_cpuid >= 0x0b) 1843 identifycpu_cpuids_intel_0x0b(ci); 1844 else if (ci->ci_max_cpuid >= 4) 1845 identifycpu_cpuids_intel_0x04(ci); 1846 1847 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1848 ci->ci_packageid); 1849 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1850 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1851 } 1852 1853 static void 1854 identifycpu_cpuids_amd(struct cpu_info *ci) 1855 { 1856 const char *cpuname = ci->ci_dev; 1857 u_int lp_max, core_max; 1858 int n, cpu_family, apic_id, smt_bits, core_bits = 0; 1859 uint32_t descs[4]; 1860 1861 apic_id = ci->ci_initapicid; 1862 cpu_family = CPUID_TO_FAMILY(ci->ci_signature); 1863 1864 if (cpu_family < 0xf) 1865 return; 1866 1867 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1868 x86_cpuid(1, descs); 1869 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1870 1871 if (cpu_family >= 0x10 && ci->ci_max_ext_cpuid >= 0x8000008) { 1872 x86_cpuid(0x8000008, descs); 1873 core_max = (descs[2] & 0xff) + 1; 1874 n = (descs[2] >> 12) & 0x0f; 1875 if (n != 0) 1876 core_bits = n; 1877 } 1878 } else { 1879 lp_max = 1; 1880 } 1881 core_max = lp_max; 1882 1883 smt_bits = ilog2((lp_max / core_max) - 1) + 1; 1884 if (core_bits == 0) 1885 core_bits = ilog2(core_max - 1) + 1; 1886 1887 #if 0 /* MSRs need kernel mode */ 1888 if (cpu_family < 0x11) { 1889 const uint64_t reg = rdmsr(MSR_NB_CFG); 1890 if ((reg & NB_CFG_INITAPICCPUIDLO) == 0) { 1891 const u_int node_id = apic_id & __BITS(0, 2); 1892 apic_id = (cpu_family == 0xf) ? 1893 (apic_id >> core_bits) | (node_id << core_bits) : 1894 (apic_id >> 5) | (node_id << 2); 1895 } 1896 } 1897 #endif 1898 1899 if (cpu_family >= 0x17) { 1900 x86_cpuid(0x8000001e, descs); 1901 const u_int threads = ((descs[1] >> 8) & 0xff) + 1; 1902 smt_bits = ilog2(threads); 1903 core_bits -= smt_bits; 1904 } 1905 1906 if (smt_bits + core_bits) { 1907 if (smt_bits + core_bits < 32) 1908 ci->ci_packageid = 0; 1909 } 1910 if (core_bits) { 1911 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1912 ci->ci_coreid = __SHIFTOUT(apic_id, core_mask); 1913 } 1914 if (smt_bits) { 1915 u_int smt_mask = __BITS(0, smt_bits - 1); 1916 ci->ci_smtid = __SHIFTOUT(apic_id, smt_mask); 1917 } 1918 1919 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1920 ci->ci_packageid); 1921 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1922 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1923 } 1924 1925 static void 1926 identifycpu_cpuids(struct cpu_info *ci) 1927 { 1928 const char *cpuname = ci->ci_dev; 1929 1930 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1931 ci->ci_packageid = ci->ci_initapicid; 1932 ci->ci_coreid = 0; 1933 ci->ci_smtid = 0; 1934 1935 if (cpu_vendor == CPUVENDOR_INTEL) 1936 identifycpu_cpuids_intel(ci); 1937 else if (cpu_vendor == CPUVENDOR_AMD) 1938 identifycpu_cpuids_amd(ci); 1939 } 1940 1941 void 1942 identifycpu(int fd, const char *cpuname) 1943 { 1944 const char *name = "", *modifier, *vendorname, *brand = ""; 1945 int class = CPUCLASS_386; 1946 unsigned int i; 1947 int modif, family; 1948 const struct cpu_cpuid_nameclass *cpup = NULL; 1949 const struct cpu_cpuid_family *cpufam; 1950 struct cpu_info *ci, cistore; 1951 u_int descs[4]; 1952 size_t sz; 1953 struct cpu_ucode_version ucode; 1954 union { 1955 struct cpu_ucode_version_amd amd; 1956 struct cpu_ucode_version_intel1 intel1; 1957 } ucvers; 1958 1959 ci = &cistore; 1960 cpu_probe_base_features(ci, cpuname); 1961 dump_descs(0x00000000, ci->ci_max_cpuid, cpuname, "basic"); 1962 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1963 x86_cpuid(0x40000000, descs); 1964 dump_descs(0x40000000, descs[0], cpuname, "hypervisor"); 1965 } 1966 dump_descs(0x80000000, ci->ci_max_ext_cpuid, cpuname, "extended"); 1967 1968 cpu_probe_hv_features(ci, cpuname); 1969 cpu_probe_features(ci); 1970 1971 if (ci->ci_cpu_type >= 0) { 1972 /* Old pre-cpuid instruction cpu */ 1973 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1974 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1975 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1976 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1977 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1978 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1979 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1980 modifier = ""; 1981 } else { 1982 /* CPU which support cpuid instruction */ 1983 modif = (ci->ci_signature >> 12) & 0x3; 1984 family = ci->ci_family; 1985 if (family < CPU_MINFAMILY) 1986 errx(1, "identifycpu: strange family value"); 1987 if (family > CPU_MAXFAMILY) 1988 family = CPU_MAXFAMILY; 1989 1990 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1991 if (!strncmp((char *)ci->ci_vendor, 1992 i386_cpuid_cpus[i].cpu_id, 12)) { 1993 cpup = &i386_cpuid_cpus[i]; 1994 break; 1995 } 1996 } 1997 1998 if (cpup == NULL) { 1999 cpu_vendor = CPUVENDOR_UNKNOWN; 2000 if (ci->ci_vendor[0] != '\0') 2001 vendorname = (char *)&ci->ci_vendor[0]; 2002 else 2003 vendorname = "Unknown"; 2004 class = family - 3; 2005 modifier = ""; 2006 name = ""; 2007 ci->ci_info = NULL; 2008 } else { 2009 cpu_vendor = cpup->cpu_vendor; 2010 vendorname = cpup->cpu_vendorname; 2011 modifier = modifiers[modif]; 2012 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 2013 name = cpufam->cpu_models[ci->ci_model]; 2014 if (name == NULL || *name == '\0') 2015 name = cpufam->cpu_model_default; 2016 class = cpufam->cpu_class; 2017 ci->ci_info = cpufam->cpu_info; 2018 2019 if (cpu_vendor == CPUVENDOR_INTEL) { 2020 if (ci->ci_family == 6 && ci->ci_model >= 5) { 2021 const char *tmp; 2022 tmp = intel_family6_name(ci); 2023 if (tmp != NULL) 2024 name = tmp; 2025 } 2026 if (ci->ci_family == 15 && 2027 ci->ci_brand_id < 2028 __arraycount(i386_intel_brand) && 2029 i386_intel_brand[ci->ci_brand_id]) 2030 name = 2031 i386_intel_brand[ci->ci_brand_id]; 2032 } 2033 2034 if (cpu_vendor == CPUVENDOR_AMD) { 2035 if (ci->ci_family == 6 && ci->ci_model >= 6) { 2036 if (ci->ci_brand_id == 1) 2037 /* 2038 * It's Duron. We override the 2039 * name, since it might have 2040 * been misidentified as Athlon. 2041 */ 2042 name = 2043 amd_brand[ci->ci_brand_id]; 2044 else 2045 brand = amd_brand_name; 2046 } 2047 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 2048 == 0xf) { 2049 /* Identify AMD64 CPU names. */ 2050 const char *tmp; 2051 tmp = amd_amd64_name(ci); 2052 if (tmp != NULL) 2053 name = tmp; 2054 } 2055 } 2056 2057 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 2058 vendorname = "VIA"; 2059 } 2060 } 2061 2062 ci->ci_cpu_class = class; 2063 2064 sz = sizeof(ci->ci_tsc_freq); 2065 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 2066 sz = sizeof(use_pae); 2067 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 2068 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 2069 2070 /* 2071 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 2072 * we try to determine from the family/model values. 2073 */ 2074 if (*cpu_brand_string != '\0') 2075 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 2076 2077 aprint_normal("%s: %s", cpuname, vendorname); 2078 if (*modifier) 2079 aprint_normal(" %s", modifier); 2080 if (*name) 2081 aprint_normal(" %s", name); 2082 if (*brand) 2083 aprint_normal(" %s", brand); 2084 aprint_normal(" (%s-class)", classnames[class]); 2085 2086 if (ci->ci_tsc_freq != 0) 2087 aprint_normal(", %ju.%02ju MHz", 2088 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 2089 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 2090 aprint_normal("\n"); 2091 2092 (void)cpu_tsc_freq_cpuid(ci); 2093 2094 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 2095 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 2096 if (ci->ci_signature != 0) 2097 aprint_normal(" (id %#x)", ci->ci_signature); 2098 aprint_normal("\n"); 2099 2100 if (ci->ci_info) 2101 (*ci->ci_info)(ci); 2102 2103 /* 2104 * display CPU feature flags 2105 */ 2106 2107 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 2108 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 2109 2110 /* These next two are actually common definitions! */ 2111 print_bits(cpuname, "features2", 2112 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 2113 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 2114 print_bits(cpuname, "features3", 2115 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 2116 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 2117 2118 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 2119 ci->ci_feat_val[4]); 2120 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2121 print_bits(cpuname, "features5", CPUID_SEF_FLAGS, 2122 ci->ci_feat_val[5]); 2123 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2124 print_bits(cpuname, "features6", CPUID_SEF_FLAGS1, 2125 ci->ci_feat_val[6]); 2126 2127 if (cpu_vendor == CPUVENDOR_INTEL) 2128 print_bits(cpuname, "features7", CPUID_SEF_FLAGS2, 2129 ci->ci_feat_val[7]); 2130 2131 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[8]); 2132 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 2133 ci->ci_feat_val[9]); 2134 2135 if (ci->ci_max_xsave != 0) { 2136 aprint_normal("%s: xsave area size: current %d, maximum %d", 2137 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 2138 aprint_normal(", xgetbv %sabled\n", 2139 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 2140 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 2141 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 2142 x86_xgetbv()); 2143 } 2144 2145 x86_print_cache_and_tlb_info(ci); 2146 2147 if (ci->ci_max_cpuid >= 3 && (ci->ci_feat_val[0] & CPUID_PSN)) { 2148 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 2149 cpuname, 2150 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 2151 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 2152 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 2153 } 2154 2155 if (ci->ci_cpu_class == CPUCLASS_386) 2156 errx(1, "NetBSD requires an 80486 or later processor"); 2157 2158 if (ci->ci_cpu_type == CPU_486DLC) { 2159 #ifndef CYRIX_CACHE_WORKS 2160 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 2161 #else 2162 #ifndef CYRIX_CACHE_REALLY_WORKS 2163 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 2164 #else 2165 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 2166 #endif 2167 #endif 2168 } 2169 2170 /* 2171 * Everything past this point requires a Pentium or later. 2172 */ 2173 if (ci->ci_max_cpuid < 0) 2174 return; 2175 2176 identifycpu_cpuids(ci); 2177 2178 if ((ci->ci_max_cpuid >= 5) 2179 && ((cpu_vendor == CPUVENDOR_INTEL) 2180 || (cpu_vendor == CPUVENDOR_AMD))) { 2181 uint16_t lmin, lmax; 2182 x86_cpuid(5, descs); 2183 2184 print_bits(cpuname, "MONITOR/MWAIT extensions", 2185 CPUID_MON_FLAGS, descs[2]); 2186 lmin = __SHIFTOUT(descs[0], CPUID_MON_MINSIZE); 2187 lmax = __SHIFTOUT(descs[1], CPUID_MON_MAXSIZE); 2188 aprint_normal("%s: monitor-line size %hu", cpuname, lmin); 2189 if (lmin != lmax) 2190 aprint_normal("-%hu", lmax); 2191 aprint_normal("\n"); 2192 2193 for (i = 0; i <= 7; i++) { 2194 unsigned int num = CPUID_MON_SUBSTATE(descs[3], i); 2195 2196 if (num != 0) 2197 aprint_normal("%s: C%u substates %u\n", 2198 cpuname, i, num); 2199 } 2200 } 2201 if ((ci->ci_max_cpuid >= 6) 2202 && ((cpu_vendor == CPUVENDOR_INTEL) 2203 || (cpu_vendor == CPUVENDOR_AMD))) { 2204 x86_cpuid(6, descs); 2205 print_bits(cpuname, "DSPM-eax", CPUID_DSPM_FLAGS, descs[0]); 2206 print_bits(cpuname, "DSPM-ecx", CPUID_DSPM_FLAGS1, descs[2]); 2207 } 2208 if ((ci->ci_max_cpuid >= 7) 2209 && ((cpu_vendor == CPUVENDOR_INTEL) 2210 || (cpu_vendor == CPUVENDOR_AMD))) { 2211 unsigned int maxsubleaf; 2212 2213 x86_cpuid(7, descs); 2214 maxsubleaf = descs[0]; 2215 aprint_verbose("%s: SEF highest subleaf %08x\n", 2216 cpuname, maxsubleaf); 2217 if (maxsubleaf >= 1) { 2218 x86_cpuid2(7, 1, descs); 2219 print_bits(cpuname, "SEF-subleaf1-eax", 2220 CPUID_SEF1_FLAGS_A, descs[0]); 2221 print_bits(cpuname, "SEF-subleaf1-ebx", 2222 CPUID_SEF1_FLAGS_B, descs[1]); 2223 print_bits(cpuname, "SEF-subleaf1-edx", 2224 CPUID_SEF1_FLAGS_D, descs[3]); 2225 } 2226 if (maxsubleaf >= 2) { 2227 x86_cpuid2(7, 2, descs); 2228 print_bits(cpuname, "SEF-subleaf2-edx", 2229 CPUID_SEF2_FLAGS_D, descs[3]); 2230 } 2231 } 2232 2233 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) { 2234 if (ci->ci_max_ext_cpuid >= 0x80000007) 2235 powernow_probe(ci); 2236 2237 if (ci->ci_max_ext_cpuid >= 0x80000008) { 2238 x86_cpuid(0x80000008, descs); 2239 print_bits(cpuname, "AMD Extended features", 2240 CPUID_CAPEX_FLAGS, descs[1]); 2241 } 2242 } 2243 2244 if (cpu_vendor == CPUVENDOR_AMD) { 2245 if (ci->ci_max_ext_cpuid >= 0x80000021) { 2246 x86_cpuid(0x80000021, descs); 2247 print_bits(cpuname, "AMD Extended features2", 2248 CPUID_AMDEXT2_FLAGS, descs[0]); 2249 } 2250 2251 if (ci->ci_max_ext_cpuid >= 0x80000007) { 2252 x86_cpuid(0x80000007, descs); 2253 print_bits(cpuname, "RAS features", 2254 CPUID_RAS_FLAGS, descs[1]); 2255 } 2256 if ((ci->ci_max_ext_cpuid >= 0x8000000a) 2257 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 2258 x86_cpuid(0x8000000a, descs); 2259 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 2260 descs[0] & 0xf); 2261 aprint_verbose("%s: SVM NASID %d\n", cpuname, 2262 descs[1]); 2263 print_bits(cpuname, "SVM features", 2264 CPUID_AMD_SVM_FLAGS, descs[3]); 2265 } 2266 if (ci->ci_max_ext_cpuid >= 0x8000001b) { 2267 x86_cpuid(0x8000001b, descs); 2268 print_bits(cpuname, "IBS features", 2269 CPUID_IBS_FLAGS, descs[0]); 2270 } 2271 if (ci->ci_max_ext_cpuid >= 0x8000001f) { 2272 x86_cpuid(0x8000001f, descs); 2273 print_bits(cpuname, "Encrypted Memory features", 2274 CPUID_AMD_ENCMEM_FLAGS, descs[0]); 2275 } 2276 if (ci->ci_max_ext_cpuid >= 0x80000022) { 2277 uint8_t ncore, nnb, nlbrs; 2278 2279 x86_cpuid(0x80000022, descs); 2280 print_bits(cpuname, "Perfmon:", 2281 CPUID_AXPERF_FLAGS, descs[0]); 2282 2283 ncore = __SHIFTOUT(descs[1], CPUID_AXPERF_NCPC); 2284 nnb = __SHIFTOUT(descs[1], CPUID_AXPERF_NNBPC); 2285 nlbrs = __SHIFTOUT(descs[1], CPUID_AXPERF_NLBRSTACK); 2286 aprint_verbose("%s: Perfmon: counters: " 2287 "Core %hhu, Northbridge %hhu\n", cpuname, 2288 ncore, nnb); 2289 aprint_verbose("%s: Perfmon: LBR Stack %hhu entries\n", 2290 cpuname, nlbrs); 2291 } 2292 } else if (cpu_vendor == CPUVENDOR_INTEL) { 2293 if (ci->ci_max_cpuid >= 0x0a) { 2294 unsigned int pmcver, ncounter, veclen; 2295 2296 x86_cpuid(0x0a, descs); 2297 pmcver = __SHIFTOUT(descs[0], CPUID_PERF_VERSION); 2298 ncounter = __SHIFTOUT(descs[0], CPUID_PERF_NGPPC); 2299 veclen = __SHIFTOUT(descs[0], CPUID_PERF_BVECLEN); 2300 aprint_verbose("%s: Perfmon: Ver. %u", 2301 cpuname, pmcver); 2302 if (((pmcver >= 3) && (pmcver <= 4)) || 2303 ((pmcver >= 5) && 2304 (descs[3] & CPUID_PERF_ANYTHREADDEPR) == 0)) 2305 aprint_verbose(" <ANYTHREAD>\n"); 2306 else 2307 aprint_verbose("\n"); 2308 2309 aprint_verbose("%s: Perfmon: General: " 2310 "bitwidth %u, %u counters\n", cpuname, 2311 (uint32_t)__SHIFTOUT(descs[0], CPUID_PERF_NBWGPPC), 2312 ncounter); 2313 /* Invert logic for the output */ 2314 descs[1] ^= __BITS(veclen - 1, 0); 2315 /* 2316 * Mask unrelated bits. An hypervisor reduces the 2317 * vector and set bit(s) out of the vector. 2318 */ 2319 descs[1] &= __BITS(veclen - 1, 0); 2320 print_bits(cpuname, "Perfmon: General: avail", 2321 CPUID_PERF_FLAGS1, descs[1]); 2322 2323 if (pmcver >= 2) { 2324 ncounter = __SHIFTOUT(descs[3], 2325 CPUID_PERF_NFFPC); 2326 aprint_verbose("%s: Perfmon: Fixed: " 2327 "bitwidth %u, %u counters\n", cpuname, 2328 (uint32_t)__SHIFTOUT(descs[3], 2329 CPUID_PERF_NBWFFPC), 2330 ncounter); 2331 if (pmcver <= 4) 2332 descs[2] = __BITS(ncounter - 1, 0); 2333 print_bits(cpuname, "Perfmon: Fixed: avail", 2334 CPUID_PERF_FLAGS2, descs[2]); 2335 } 2336 } 2337 if (ci->ci_max_cpuid >= 0x1a) { 2338 x86_cpuid(0x1a, descs); 2339 if (descs[0] != 0) { 2340 aprint_verbose("%s: Hybrid: Core type %02x, " 2341 "Native Model ID %07x\n", 2342 cpuname, 2343 (uint8_t)__SHIFTOUT(descs[0], 2344 CPUID_HYBRID_CORETYPE), 2345 (uint32_t)__SHIFTOUT(descs[0], 2346 CPUID_HYBRID_NATIVEID)); 2347 } 2348 } 2349 } 2350 2351 #ifdef INTEL_ONDEMAND_CLOCKMOD 2352 clockmod_init(); 2353 #endif 2354 2355 if (cpu_vendor == CPUVENDOR_AMD) 2356 ucode.loader_version = CPU_UCODE_LOADER_AMD; 2357 else if (cpu_vendor == CPUVENDOR_INTEL) 2358 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 2359 else 2360 return; 2361 2362 ucode.data = &ucvers; 2363 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 2364 #ifdef __i386__ 2365 struct cpu_ucode_version_64 ucode_64; 2366 if (errno != ENOTTY) 2367 return; 2368 /* Try the 64 bit ioctl */ 2369 memset(&ucode_64, 0, sizeof ucode_64); 2370 ucode_64.data = &ucvers; 2371 ucode_64.loader_version = ucode.loader_version; 2372 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 2373 return; 2374 #else 2375 return; 2376 #endif 2377 } 2378 2379 if (cpu_vendor == CPUVENDOR_AMD) 2380 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2381 else if (cpu_vendor == CPUVENDOR_INTEL) 2382 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2383 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2384 } 2385 2386 static const char * 2387 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2388 const char *sep) 2389 { 2390 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2391 char human_num[HUMAN_BUFSIZE]; 2392 2393 if (cai->cai_totalsize == 0) 2394 return sep; 2395 2396 if (sep == NULL) 2397 aprint_verbose_dev(ci->ci_dev, ""); 2398 else 2399 aprint_verbose("%s", sep); 2400 if (name != NULL) 2401 aprint_verbose("%s ", name); 2402 2403 if (cai->cai_string != NULL) { 2404 aprint_verbose("%s ", cai->cai_string); 2405 } else { 2406 (void)humanize_number(human_num, sizeof(human_num), 2407 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2408 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2409 } 2410 switch (cai->cai_associativity) { 2411 case 0: 2412 aprint_verbose("disabled"); 2413 break; 2414 case 1: 2415 aprint_verbose("direct-mapped"); 2416 break; 2417 case 0xff: 2418 aprint_verbose("fully associative"); 2419 break; 2420 default: 2421 aprint_verbose("%d-way", cai->cai_associativity); 2422 break; 2423 } 2424 return ", "; 2425 } 2426 2427 static const char * 2428 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2429 const char *sep) 2430 { 2431 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2432 char human_num[HUMAN_BUFSIZE]; 2433 2434 if (cai->cai_totalsize == 0) 2435 return sep; 2436 2437 if (sep == NULL) 2438 aprint_verbose_dev(ci->ci_dev, ""); 2439 else 2440 aprint_verbose("%s", sep); 2441 if ((name != NULL) && (sep == NULL)) 2442 aprint_verbose("%s ", name); 2443 2444 if (cai->cai_string != NULL) { 2445 aprint_verbose("%s", cai->cai_string); 2446 } else { 2447 (void)humanize_number(human_num, sizeof(human_num), 2448 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2449 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2450 human_num); 2451 switch (cai->cai_associativity) { 2452 case 0: 2453 aprint_verbose("disabled"); 2454 break; 2455 case 1: 2456 aprint_verbose("direct-mapped"); 2457 break; 2458 case 0xff: 2459 aprint_verbose("fully associative"); 2460 break; 2461 default: 2462 aprint_verbose("%d-way", cai->cai_associativity); 2463 break; 2464 } 2465 } 2466 return ", "; 2467 } 2468 2469 static void 2470 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2471 { 2472 const char *sep = NULL; 2473 2474 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2475 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2476 sep = print_cache_config(ci, CAI_ICACHE, "I-cache:", NULL); 2477 sep = print_cache_config(ci, CAI_DCACHE, "D-cache:", sep); 2478 if (sep != NULL) 2479 aprint_verbose("\n"); 2480 } 2481 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2482 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache:", NULL); 2483 if (sep != NULL) 2484 aprint_verbose("\n"); 2485 } 2486 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2487 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache:", NULL); 2488 if (sep != NULL) 2489 aprint_verbose("\n"); 2490 } 2491 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2492 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2493 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2494 if (sep != NULL) 2495 aprint_verbose("\n"); 2496 } 2497 2498 sep = print_tlb_config(ci, CAI_ITLB, "ITLB:", NULL); 2499 sep = print_tlb_config(ci, CAI_ITLB2, "ITLB:", sep); 2500 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "ITLB:", sep); 2501 if (sep != NULL) 2502 aprint_verbose("\n"); 2503 2504 sep = print_tlb_config(ci, CAI_DTLB, "DTLB:", NULL); 2505 sep = print_tlb_config(ci, CAI_DTLB2, "DTLB:", sep); 2506 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "DTLB:", sep); 2507 if (sep != NULL) 2508 aprint_verbose("\n"); 2509 2510 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB:", NULL); 2511 sep = print_tlb_config(ci, CAI_L2_ITLB2, "L2 ITLB:", sep); 2512 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 ITLB:", sep); 2513 if (sep != NULL) 2514 aprint_verbose("\n"); 2515 2516 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB:", NULL); 2517 sep = print_tlb_config(ci, CAI_L2_DTLB2, "L2 DTLB:", sep); 2518 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 DTLB:", sep); 2519 if (sep != NULL) 2520 aprint_verbose("\n"); 2521 2522 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB:", NULL); 2523 sep = print_tlb_config(ci, CAI_L2_STLB2, "L2 STLB:", sep); 2524 sep = print_tlb_config(ci, CAI_L2_STLB3, "L2 STLB:", sep); 2525 if (sep != NULL) 2526 aprint_verbose("\n"); 2527 } 2528 2529 static void 2530 powernow_probe(struct cpu_info *ci) 2531 { 2532 uint32_t regs[4]; 2533 char buf[256]; 2534 2535 x86_cpuid(0x80000007, regs); 2536 2537 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2538 aprint_normal_dev(ci->ci_dev, "Power Management features: %s\n", buf); 2539 } 2540 2541 bool 2542 identifycpu_bind(void) 2543 { 2544 2545 return true; 2546 } 2547 2548 int 2549 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2550 { 2551 struct cpu_info ci; 2552 int loader_version, res; 2553 struct cpu_ucode_version versreq; 2554 2555 cpu_probe_base_features(&ci, "unknown"); 2556 2557 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2558 loader_version = CPU_UCODE_LOADER_AMD; 2559 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2560 loader_version = CPU_UCODE_LOADER_INTEL1; 2561 else 2562 return -1; 2563 2564 /* check whether the kernel understands this loader version */ 2565 versreq.loader_version = loader_version; 2566 versreq.data = 0; 2567 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2568 if (res) 2569 return -1; 2570 2571 switch (loader_version) { 2572 case CPU_UCODE_LOADER_AMD: 2573 if (uc->cpu_nr != -1) { 2574 /* printf? */ 2575 return -1; 2576 } 2577 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2578 break; 2579 case CPU_UCODE_LOADER_INTEL1: 2580 if (uc->cpu_nr == -1) 2581 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2582 else 2583 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2584 break; 2585 default: /* can't happen */ 2586 return -1; 2587 } 2588 uc->loader_version = loader_version; 2589 return 0; 2590 } 2591
Indexes created Sat Oct 25 00:10:07 GMT 2025