i386.c revision 1.104.2.9
1 /* $NetBSD: i386.c,v 1.104.2.9 2021/12/24 12:58:14 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.104.2.9 2021/12/24 12:58:14 martin Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cpu_ucode.h> 85 86 #include "../cpuctl.h" 87 #include "cpuctl_i386.h" 88 89 /* Size of buffer for printing humanized numbers */ 90 #define HUMAN_BUFSIZE sizeof("999KB") 91 92 struct cpu_nocpuid_nameclass { 93 int cpu_vendor; 94 const char *cpu_vendorname; 95 const char *cpu_name; 96 int cpu_class; 97 void (*cpu_setup)(struct cpu_info *); 98 void (*cpu_cacheinfo)(struct cpu_info *); 99 void (*cpu_info)(struct cpu_info *); 100 }; 101 102 struct cpu_cpuid_nameclass { 103 const char *cpu_id; 104 int cpu_vendor; 105 const char *cpu_vendorname; 106 struct cpu_cpuid_family { 107 int cpu_class; 108 const char *cpu_models[256]; 109 const char *cpu_model_default; 110 void (*cpu_setup)(struct cpu_info *); 111 void (*cpu_probe)(struct cpu_info *); 112 void (*cpu_info)(struct cpu_info *); 113 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 114 }; 115 116 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 117 118 /* 119 * Map Brand ID from cpuid instruction to brand name. 120 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 121 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 122 * Architectures Software Developer's Manual, Volume 2A". 123 */ 124 static const char * const i386_intel_brand[] = { 125 "", /* Unsupported */ 126 "Celeron", /* Intel (R) Celeron (TM) processor */ 127 "Pentium III", /* Intel (R) Pentium (R) III processor */ 128 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 129 "Pentium III", /* Intel (R) Pentium (R) III processor */ 130 "", /* 0x05: Reserved */ 131 "Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */ 132 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 133 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 134 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 135 "Celeron", /* Intel (R) Celeron (TM) processor */ 136 "Xeon", /* Intel (R) Xeon (TM) processor */ 137 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 138 "", /* 0x0d: Reserved */ 139 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 140 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 141 "", /* 0x10: Reserved */ 142 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 143 "Celeron M", /* Intel (R) Celeron (R) M processor */ 144 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 145 "Celeron", /* Intel (R) Celeron (R) processor */ 146 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 147 "Pentium M", /* Intel (R) Pentium (R) M processor */ 148 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 149 }; 150 151 /* 152 * AMD processors don't have Brand IDs, so we need these names for probe. 153 */ 154 static const char * const amd_brand[] = { 155 "", 156 "Duron", /* AMD Duron(tm) */ 157 "MP", /* AMD Athlon(tm) MP */ 158 "XP", /* AMD Athlon(tm) XP */ 159 "4" /* AMD Athlon(tm) 4 */ 160 }; 161 162 int cpu_vendor; 163 static char cpu_brand_string[49]; 164 static char amd_brand_name[48]; 165 static int use_pae, largepagesize; 166 167 /* Setup functions */ 168 static void disable_tsc(struct cpu_info *); 169 static void amd_family5_setup(struct cpu_info *); 170 static void cyrix6x86_cpu_setup(struct cpu_info *); 171 static void winchip_cpu_setup(struct cpu_info *); 172 /* Brand/Model name functions */ 173 static const char *intel_family6_name(struct cpu_info *); 174 static const char *amd_amd64_name(struct cpu_info *); 175 /* Probe functions */ 176 static void amd_family6_probe(struct cpu_info *); 177 static void powernow_probe(struct cpu_info *); 178 static void intel_family_new_probe(struct cpu_info *); 179 static void via_cpu_probe(struct cpu_info *); 180 /* (Cache) Info functions */ 181 static void intel_cpu_cacheinfo(struct cpu_info *); 182 static void amd_cpu_cacheinfo(struct cpu_info *); 183 static void via_cpu_cacheinfo(struct cpu_info *); 184 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 185 static void transmeta_cpu_info(struct cpu_info *); 186 /* Common functions */ 187 static void cpu_probe_base_features(struct cpu_info *, const char *); 188 static void cpu_probe_hv_features(struct cpu_info *, const char *); 189 static void cpu_probe_features(struct cpu_info *); 190 static void print_bits(const char *, const char *, const char *, uint32_t); 191 static void identifycpu_cpuids(struct cpu_info *); 192 static const char *print_cache_config(struct cpu_info *, int, const char *, 193 const char *); 194 static const char *print_tlb_config(struct cpu_info *, int, const char *, 195 const char *); 196 static void x86_print_cache_and_tlb_info(struct cpu_info *); 197 198 /* 199 * Note: these are just the ones that may not have a cpuid instruction. 200 * We deal with the rest in a different way. 201 */ 202 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 203 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 204 NULL, NULL, NULL }, /* CPU_386SX */ 205 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 206 NULL, NULL, NULL }, /* CPU_386 */ 207 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 208 NULL, NULL, NULL }, /* CPU_486SX */ 209 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 210 NULL, NULL, NULL }, /* CPU_486 */ 211 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 212 NULL, NULL, NULL }, /* CPU_486DLC */ 213 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 214 NULL, NULL, NULL }, /* CPU_6x86 */ 215 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 216 NULL, NULL, NULL }, /* CPU_NX586 */ 217 }; 218 219 const char *classnames[] = { 220 "386", 221 "486", 222 "586", 223 "686" 224 }; 225 226 const char *modifiers[] = { 227 "", 228 "OverDrive", 229 "Dual", 230 "" 231 }; 232 233 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 234 { 235 /* 236 * For Intel processors, check Chapter 35Model-specific 237 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 238 * Software Developer's Manual, Volume 3C". 239 */ 240 "GenuineIntel", 241 CPUVENDOR_INTEL, 242 "Intel", 243 /* Family 4 */ 244 { { 245 CPUCLASS_486, 246 { 247 "486DX", "486DX", "486SX", "486DX2", "486SL", 248 "486SX2", 0, "486DX2 W/B Enhanced", 249 "486DX4", 0, 0, 0, 0, 0, 0, 0, 250 }, 251 "486", /* Default */ 252 NULL, 253 NULL, 254 intel_cpu_cacheinfo, 255 }, 256 /* Family 5 */ 257 { 258 CPUCLASS_586, 259 { 260 "Pentium (P5 A-step)", "Pentium (P5)", 261 "Pentium (P54C)", "Pentium (P24T)", 262 "Pentium/MMX", "Pentium", 0, 263 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 264 "Quark X1000", 0, 0, 0, 0, 0, 0, 265 }, 266 "Pentium", /* Default */ 267 NULL, 268 NULL, 269 intel_cpu_cacheinfo, 270 }, 271 /* Family 6 */ 272 { 273 CPUCLASS_686, 274 { 275 [0x00] = "Pentium Pro (A-step)", 276 [0x01] = "Pentium Pro", 277 [0x03] = "Pentium II (Klamath)", 278 [0x04] = "Pentium Pro", 279 [0x05] = "Pentium II/Celeron (Deschutes)", 280 [0x06] = "Celeron (Mendocino)", 281 [0x07] = "Pentium III (Katmai)", 282 [0x08] = "Pentium III (Coppermine)", 283 [0x09] = "Pentium M (Banias)", 284 [0x0a] = "Pentium III Xeon (Cascades)", 285 [0x0b] = "Pentium III (Tualatin)", 286 [0x0d] = "Pentium M (Dothan)", 287 [0x0e] = "Pentium Core Duo, Core solo", 288 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 289 "Core 2 Quad 6xxx, " 290 "Core 2 Extreme 6xxx, " 291 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 292 "and Pentium DC", 293 [0x15] = "EP80579 Integrated Processor", 294 [0x16] = "Celeron (45nm)", 295 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 296 "Core 2 Quad 8xxx and 9xxx", 297 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 298 "(Nehalem)", 299 [0x1c] = "45nm Atom Family", 300 [0x1d] = "XeonMP 74xx (Nehalem)", 301 [0x1e] = "Core i7 and i5", 302 [0x1f] = "Core i7 and i5", 303 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 304 [0x26] = "Atom Family", 305 [0x27] = "Atom Family", 306 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 307 "i3 2xxx", 308 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 309 [0x2d] = "Xeon E5 Sandy Bridge family, " 310 "Core i7-39xx Extreme", 311 [0x2e] = "Xeon 75xx & 65xx", 312 [0x2f] = "Xeon E7 family", 313 [0x35] = "Atom Family", 314 [0x36] = "Atom S1000", 315 [0x37] = "Atom E3000, Z3[67]00", 316 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 317 "Ivy Bridge", 318 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 319 "(Haswell)", 320 [0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)", 321 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 322 "Core i7-49xx Extreme", 323 [0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), " 324 "Core i7-59xx Extreme", 325 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 326 "(Haswell)", 327 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 328 "(Haswell)", 329 [0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)", 330 [0x4a] = "Atom Z3400", 331 [0x4c] = "Atom X[57]-Z8000 (Airmont)", 332 [0x4d] = "Atom C2000", 333 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 334 [0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme", 335 [0x55] = "Xeon Scalable (Skylake, Cascade Lake, Copper Lake)", 336 [0x56] = "Xeon D-1500 (Broadwell)", 337 [0x57] = "Xeon Phi [357]200 (Knights Landing)", 338 [0x5a] = "Atom E3500", 339 [0x5c] = "Atom (Goldmont)", 340 [0x5d] = "Atom X3-C3000 (Silvermont)", 341 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 342 [0x5f] = "Atom (Goldmont, Denverton)", 343 [0x66] = "8th gen Core i3 (Cannon Lake)", 344 [0x6a] = "3rd gen Xeon Scalable (Ice Lake)", 345 [0x6c] = "3rd gen Xeon Scalable (Ice Lake)", 346 [0x7a] = "Atom (Goldmont Plus)", 347 [0x7d] = "10th gen Core (Ice Lake)", 348 [0x7e] = "10th gen Core (Ice Lake)", 349 [0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)", 350 [0x86] = "Atom (Tremont)", 351 [0x8c] = "11th gen Core (Tiger Lake)", 352 [0x8d] = "11th gen Core (Tiger Lake)", 353 [0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 354 [0x96] = "Atom x6000E (Elkhart Lake)", 355 [0x9c] = "Pentium Silver N6xxx, Celeron N45xx, Celeron N51xx (Jasper Lake)", 356 [0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 357 [0xa5] = "10th gen Core (Comet Lake)", 358 [0xa6] = "10th gen Core (Comet Lake)", 359 }, 360 "Pentium Pro, II or III", /* Default */ 361 NULL, 362 intel_family_new_probe, 363 intel_cpu_cacheinfo, 364 }, 365 /* Family > 6 */ 366 { 367 CPUCLASS_686, 368 { 369 0, 0, 0, 0, 0, 0, 0, 0, 370 0, 0, 0, 0, 0, 0, 0, 0, 371 }, 372 "Pentium 4", /* Default */ 373 NULL, 374 intel_family_new_probe, 375 intel_cpu_cacheinfo, 376 } } 377 }, 378 { 379 "AuthenticAMD", 380 CPUVENDOR_AMD, 381 "AMD", 382 /* Family 4 */ 383 { { 384 CPUCLASS_486, 385 { 386 0, 0, 0, "Am486DX2 W/T", 387 0, 0, 0, "Am486DX2 W/B", 388 "Am486DX4 W/T or Am5x86 W/T 150", 389 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 390 0, 0, "Am5x86 W/T 133/160", 391 "Am5x86 W/B 133/160", 392 }, 393 "Am486 or Am5x86", /* Default */ 394 NULL, 395 NULL, 396 NULL, 397 }, 398 /* Family 5 */ 399 { 400 CPUCLASS_586, 401 { 402 "K5", "K5", "K5", "K5", 0, 0, "K6", 403 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 404 "K6-2+/III+", 0, 0, 405 }, 406 "K5 or K6", /* Default */ 407 amd_family5_setup, 408 NULL, 409 amd_cpu_cacheinfo, 410 }, 411 /* Family 6 */ 412 { 413 CPUCLASS_686, 414 { 415 0, "Athlon Model 1", "Athlon Model 2", 416 "Duron", "Athlon Model 4 (Thunderbird)", 417 0, "Athlon", "Duron", "Athlon", 0, 418 "Athlon", 0, 0, 0, 0, 0, 419 }, 420 "K7 (Athlon)", /* Default */ 421 NULL, 422 amd_family6_probe, 423 amd_cpu_cacheinfo, 424 }, 425 /* Family > 6 */ 426 { 427 CPUCLASS_686, 428 { 429 0, 0, 0, 0, 0, 0, 0, 0, 430 0, 0, 0, 0, 0, 0, 0, 0, 431 }, 432 "Unknown K8 (Athlon)", /* Default */ 433 NULL, 434 amd_family6_probe, 435 amd_cpu_cacheinfo, 436 } } 437 }, 438 { 439 "CyrixInstead", 440 CPUVENDOR_CYRIX, 441 "Cyrix", 442 /* Family 4 */ 443 { { 444 CPUCLASS_486, 445 { 446 0, 0, 0, 447 "MediaGX", 448 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 449 }, 450 "486", /* Default */ 451 cyrix6x86_cpu_setup, /* XXX ?? */ 452 NULL, 453 NULL, 454 }, 455 /* Family 5 */ 456 { 457 CPUCLASS_586, 458 { 459 0, 0, "6x86", 0, 460 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 461 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 462 }, 463 "6x86", /* Default */ 464 cyrix6x86_cpu_setup, 465 NULL, 466 NULL, 467 }, 468 /* Family 6 */ 469 { 470 CPUCLASS_686, 471 { 472 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 473 0, 0, 0, 0, 0, 0, 0, 0, 474 }, 475 "6x86MX", /* Default */ 476 cyrix6x86_cpu_setup, 477 NULL, 478 NULL, 479 }, 480 /* Family > 6 */ 481 { 482 CPUCLASS_686, 483 { 484 0, 0, 0, 0, 0, 0, 0, 0, 485 0, 0, 0, 0, 0, 0, 0, 0, 486 }, 487 "Unknown 6x86MX", /* Default */ 488 NULL, 489 NULL, 490 NULL, 491 } } 492 }, 493 { /* MediaGX is now owned by National Semiconductor */ 494 "Geode by NSC", 495 CPUVENDOR_CYRIX, /* XXX */ 496 "National Semiconductor", 497 /* Family 4, NSC never had any of these */ 498 { { 499 CPUCLASS_486, 500 { 501 0, 0, 0, 0, 0, 0, 0, 0, 502 0, 0, 0, 0, 0, 0, 0, 0, 503 }, 504 "486 compatible", /* Default */ 505 NULL, 506 NULL, 507 NULL, 508 }, 509 /* Family 5: Geode family, formerly MediaGX */ 510 { 511 CPUCLASS_586, 512 { 513 0, 0, 0, 0, 514 "Geode GX1", 515 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 516 }, 517 "Geode", /* Default */ 518 cyrix6x86_cpu_setup, 519 NULL, 520 amd_cpu_cacheinfo, 521 }, 522 /* Family 6, not yet available from NSC */ 523 { 524 CPUCLASS_686, 525 { 526 0, 0, 0, 0, 0, 0, 0, 0, 527 0, 0, 0, 0, 0, 0, 0, 0, 528 }, 529 "Pentium Pro compatible", /* Default */ 530 NULL, 531 NULL, 532 NULL, 533 }, 534 /* Family > 6, not yet available from NSC */ 535 { 536 CPUCLASS_686, 537 { 538 0, 0, 0, 0, 0, 0, 0, 0, 539 0, 0, 0, 0, 0, 0, 0, 0, 540 }, 541 "Pentium Pro compatible", /* Default */ 542 NULL, 543 NULL, 544 NULL, 545 } } 546 }, 547 { 548 "CentaurHauls", 549 CPUVENDOR_IDT, 550 "IDT", 551 /* Family 4, IDT never had any of these */ 552 { { 553 CPUCLASS_486, 554 { 555 0, 0, 0, 0, 0, 0, 0, 0, 556 0, 0, 0, 0, 0, 0, 0, 0, 557 }, 558 "486 compatible", /* Default */ 559 NULL, 560 NULL, 561 NULL, 562 }, 563 /* Family 5 */ 564 { 565 CPUCLASS_586, 566 { 567 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 568 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 569 }, 570 "WinChip", /* Default */ 571 winchip_cpu_setup, 572 NULL, 573 NULL, 574 }, 575 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 576 { 577 CPUCLASS_686, 578 { 579 0, 0, 0, 0, 0, 0, "C3 Samuel", 580 "C3 Samuel 2/Ezra", "C3 Ezra-T", 581 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 582 0, "VIA Nano", 583 }, 584 "Unknown VIA/IDT", /* Default */ 585 NULL, 586 via_cpu_probe, 587 via_cpu_cacheinfo, 588 }, 589 /* Family > 6, not yet available from VIA */ 590 { 591 CPUCLASS_686, 592 { 593 0, 0, 0, 0, 0, 0, 0, 0, 594 0, 0, 0, 0, 0, 0, 0, 0, 595 }, 596 "Pentium Pro compatible", /* Default */ 597 NULL, 598 NULL, 599 NULL, 600 } } 601 }, 602 { 603 "GenuineTMx86", 604 CPUVENDOR_TRANSMETA, 605 "Transmeta", 606 /* Family 4, Transmeta never had any of these */ 607 { { 608 CPUCLASS_486, 609 { 610 0, 0, 0, 0, 0, 0, 0, 0, 611 0, 0, 0, 0, 0, 0, 0, 0, 612 }, 613 "486 compatible", /* Default */ 614 NULL, 615 NULL, 616 NULL, 617 }, 618 /* Family 5 */ 619 { 620 CPUCLASS_586, 621 { 622 0, 0, 0, 0, 0, 0, 0, 0, 623 0, 0, 0, 0, 0, 0, 0, 0, 624 }, 625 "Crusoe", /* Default */ 626 NULL, 627 NULL, 628 transmeta_cpu_info, 629 }, 630 /* Family 6, not yet available from Transmeta */ 631 { 632 CPUCLASS_686, 633 { 634 0, 0, 0, 0, 0, 0, 0, 0, 635 0, 0, 0, 0, 0, 0, 0, 0, 636 }, 637 "Pentium Pro compatible", /* Default */ 638 NULL, 639 NULL, 640 NULL, 641 }, 642 /* Family > 6, not yet available from Transmeta */ 643 { 644 CPUCLASS_686, 645 { 646 0, 0, 0, 0, 0, 0, 0, 0, 647 0, 0, 0, 0, 0, 0, 0, 0, 648 }, 649 "Pentium Pro compatible", /* Default */ 650 NULL, 651 NULL, 652 NULL, 653 } } 654 } 655 }; 656 657 /* 658 * disable the TSC such that we don't use the TSC in microtime(9) 659 * because some CPUs got the implementation wrong. 660 */ 661 static void 662 disable_tsc(struct cpu_info *ci) 663 { 664 if (ci->ci_feat_val[0] & CPUID_TSC) { 665 ci->ci_feat_val[0] &= ~CPUID_TSC; 666 aprint_error("WARNING: broken TSC disabled\n"); 667 } 668 } 669 670 static void 671 amd_family5_setup(struct cpu_info *ci) 672 { 673 674 switch (ci->ci_model) { 675 case 0: /* AMD-K5 Model 0 */ 676 /* 677 * According to the AMD Processor Recognition App Note, 678 * the AMD-K5 Model 0 uses the wrong bit to indicate 679 * support for global PTEs, instead using bit 9 (APIC) 680 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 681 */ 682 if (ci->ci_feat_val[0] & CPUID_APIC) 683 ci->ci_feat_val[0] = 684 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 685 /* 686 * XXX But pmap_pg_g is already initialized -- need to kick 687 * XXX the pmap somehow. How does the MP branch do this? 688 */ 689 break; 690 } 691 } 692 693 static void 694 cyrix6x86_cpu_setup(struct cpu_info *ci) 695 { 696 697 /* 698 * Do not disable the TSC on the Geode GX, it's reported to 699 * work fine. 700 */ 701 if (ci->ci_signature != 0x552) 702 disable_tsc(ci); 703 } 704 705 static void 706 winchip_cpu_setup(struct cpu_info *ci) 707 { 708 switch (ci->ci_model) { 709 case 4: /* WinChip C6 */ 710 disable_tsc(ci); 711 } 712 } 713 714 715 static const char * 716 intel_family6_name(struct cpu_info *ci) 717 { 718 const char *ret = NULL; 719 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 720 721 if (ci->ci_model == 5) { 722 switch (l2cache) { 723 case 0: 724 case 128 * 1024: 725 ret = "Celeron (Covington)"; 726 break; 727 case 256 * 1024: 728 ret = "Mobile Pentium II (Dixon)"; 729 break; 730 case 512 * 1024: 731 ret = "Pentium II"; 732 break; 733 case 1 * 1024 * 1024: 734 case 2 * 1024 * 1024: 735 ret = "Pentium II Xeon"; 736 break; 737 } 738 } else if (ci->ci_model == 6) { 739 switch (l2cache) { 740 case 256 * 1024: 741 case 512 * 1024: 742 ret = "Mobile Pentium II"; 743 break; 744 } 745 } else if (ci->ci_model == 7) { 746 switch (l2cache) { 747 case 512 * 1024: 748 ret = "Pentium III"; 749 break; 750 case 1 * 1024 * 1024: 751 case 2 * 1024 * 1024: 752 ret = "Pentium III Xeon"; 753 break; 754 } 755 } else if (ci->ci_model >= 8) { 756 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 757 switch (ci->ci_brand_id) { 758 case 0x3: 759 if (ci->ci_signature == 0x6B1) 760 ret = "Celeron"; 761 break; 762 case 0x8: 763 if (ci->ci_signature >= 0xF13) 764 ret = "genuine processor"; 765 break; 766 case 0xB: 767 if (ci->ci_signature >= 0xF13) 768 ret = "Xeon MP"; 769 break; 770 case 0xE: 771 if (ci->ci_signature < 0xF13) 772 ret = "Xeon"; 773 break; 774 } 775 if (ret == NULL) 776 ret = i386_intel_brand[ci->ci_brand_id]; 777 } 778 } 779 780 return ret; 781 } 782 783 /* 784 * Identify AMD64 CPU names from cpuid. 785 * 786 * Based on: 787 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 788 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 789 * "Revision Guide for AMD NPT Family 0Fh Processors" 790 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 791 * and other miscellaneous reports. 792 * 793 * This is all rather pointless, these are cross 'brand' since the raw 794 * silicon is shared. 795 */ 796 static const char * 797 amd_amd64_name(struct cpu_info *ci) 798 { 799 static char family_str[32]; 800 801 /* Only called if family >= 15 */ 802 803 switch (ci->ci_family) { 804 case 15: 805 switch (ci->ci_model) { 806 case 0x21: /* rev JH-E1/E6 */ 807 case 0x41: /* rev JH-F2 */ 808 return "Dual-Core Opteron"; 809 case 0x23: /* rev JH-E6 (Toledo) */ 810 return "Dual-Core Opteron or Athlon 64 X2"; 811 case 0x43: /* rev JH-F2 (Windsor) */ 812 return "Athlon 64 FX or Athlon 64 X2"; 813 case 0x24: /* rev SH-E5 (Lancaster?) */ 814 return "Mobile Athlon 64 or Turion 64"; 815 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 816 return "Opteron or Athlon 64 FX"; 817 case 0x15: /* rev SH-D0 */ 818 case 0x25: /* rev SH-E4 */ 819 return "Opteron"; 820 case 0x27: /* rev DH-E4, SH-E4 */ 821 return "Athlon 64 or Athlon 64 FX or Opteron"; 822 case 0x48: /* rev BH-F2 */ 823 return "Turion 64 X2"; 824 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 825 case 0x07: /* rev SH-CG (ClawHammer) */ 826 case 0x0b: /* rev CH-CG */ 827 case 0x14: /* rev SH-D0 */ 828 case 0x17: /* rev SH-D0 */ 829 case 0x1b: /* rev CH-D0 */ 830 return "Athlon 64"; 831 case 0x2b: /* rev BH-E4 (Manchester) */ 832 case 0x4b: /* rev BH-F2 (Windsor) */ 833 return "Athlon 64 X2"; 834 case 0x6b: /* rev BH-G1 (Brisbane) */ 835 return "Athlon X2 or Athlon 64 X2"; 836 case 0x08: /* rev CH-CG */ 837 case 0x0c: /* rev DH-CG (Newcastle) */ 838 case 0x0e: /* rev DH-CG (Newcastle?) */ 839 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 840 case 0x18: /* rev CH-D0 */ 841 case 0x1c: /* rev DH-D0 (Winchester) */ 842 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 843 case 0x2c: /* rev DH-E3/E6 */ 844 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 845 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 846 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 847 case 0x6f: /* rev DH-G1 */ 848 return "Athlon 64 or Sempron"; 849 default: 850 break; 851 } 852 return "Unknown AMD64 CPU"; 853 854 #if 0 855 case 16: 856 return "Family 10h"; 857 case 17: 858 return "Family 11h"; 859 case 18: 860 return "Family 12h"; 861 case 19: 862 return "Family 14h"; 863 case 20: 864 return "Family 15h"; 865 #endif 866 867 default: 868 break; 869 } 870 871 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 872 return family_str; 873 } 874 875 static void 876 intel_family_new_probe(struct cpu_info *ci) 877 { 878 uint32_t descs[4]; 879 880 x86_cpuid(0x80000000, descs); 881 882 /* 883 * Determine extended feature flags. 884 */ 885 if (descs[0] >= 0x80000001) { 886 x86_cpuid(0x80000001, descs); 887 ci->ci_feat_val[2] |= descs[3]; 888 ci->ci_feat_val[3] |= descs[2]; 889 } 890 } 891 892 static void 893 via_cpu_probe(struct cpu_info *ci) 894 { 895 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 896 u_int descs[4]; 897 u_int lfunc; 898 899 /* 900 * Determine the largest extended function value. 901 */ 902 x86_cpuid(0x80000000, descs); 903 lfunc = descs[0]; 904 905 /* 906 * Determine the extended feature flags. 907 */ 908 if (lfunc >= 0x80000001) { 909 x86_cpuid(0x80000001, descs); 910 ci->ci_feat_val[2] |= descs[3]; 911 } 912 913 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 914 return; 915 916 /* Nehemiah or Esther */ 917 x86_cpuid(0xc0000000, descs); 918 lfunc = descs[0]; 919 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 920 return; 921 922 x86_cpuid(0xc0000001, descs); 923 lfunc = descs[3]; 924 ci->ci_feat_val[4] = lfunc; 925 } 926 927 static void 928 amd_family6_probe(struct cpu_info *ci) 929 { 930 uint32_t descs[4]; 931 char *p; 932 size_t i; 933 934 x86_cpuid(0x80000000, descs); 935 936 /* 937 * Determine the extended feature flags. 938 */ 939 if (descs[0] >= 0x80000001) { 940 x86_cpuid(0x80000001, descs); 941 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 942 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 943 } 944 945 if (*cpu_brand_string == '\0') 946 return; 947 948 for (i = 1; i < __arraycount(amd_brand); i++) 949 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 950 ci->ci_brand_id = i; 951 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 952 break; 953 } 954 } 955 956 static void 957 intel_cpu_cacheinfo(struct cpu_info *ci) 958 { 959 const struct x86_cache_info *cai; 960 u_int descs[4]; 961 int iterations, i, j; 962 int type, level, ways, linesize, sets; 963 int caitype = -1; 964 uint8_t desc; 965 966 /* Return if the cpu is old pre-cpuid instruction cpu */ 967 if (ci->ci_cpu_type >= 0) 968 return; 969 970 if (ci->ci_max_cpuid < 2) 971 return; 972 973 /* 974 * Parse the cache info from `cpuid leaf 2', if we have it. 975 * XXX This is kinda ugly, but hey, so is the architecture... 976 */ 977 x86_cpuid(2, descs); 978 iterations = descs[0] & 0xff; 979 while (iterations-- > 0) { 980 for (i = 0; i < 4; i++) { 981 if (descs[i] & 0x80000000) 982 continue; 983 for (j = 0; j < 4; j++) { 984 /* 985 * The least significant byte in EAX 986 * ((desc[0] >> 0) & 0xff) is always 0x01 and 987 * it should be ignored. 988 */ 989 if (i == 0 && j == 0) 990 continue; 991 desc = (descs[i] >> (j * 8)) & 0xff; 992 if (desc == 0) 993 continue; 994 cai = cpu_cacheinfo_lookup( 995 intel_cpuid_cache_info, desc); 996 if (cai != NULL) 997 ci->ci_cinfo[cai->cai_index] = *cai; 998 else if ((verbose != 0) && (desc != 0xff) 999 && (desc != 0xfe)) 1000 aprint_error_dev(ci->ci_dev, "error:" 1001 " Unknown cacheinfo desc %02x\n", 1002 desc); 1003 } 1004 } 1005 x86_cpuid(2, descs); 1006 } 1007 1008 if (ci->ci_max_cpuid < 4) 1009 return; 1010 1011 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1012 cpu_dcp_cacheinfo(ci, 4); 1013 1014 if (ci->ci_max_cpuid < 0x18) 1015 return; 1016 /* Parse the TLB info from `cpuid leaf 18H', if we have it. */ 1017 x86_cpuid(0x18, descs); 1018 iterations = descs[0]; 1019 for (i = 0; i <= iterations; i++) { 1020 uint32_t pgsize; 1021 bool full; 1022 1023 x86_cpuid2(0x18, i, descs); 1024 type = __SHIFTOUT(descs[3], CPUID_DATP_TCTYPE); 1025 if (type == CPUID_DATP_TCTYPE_N) 1026 continue; 1027 level = __SHIFTOUT(descs[3], CPUID_DATP_TCLEVEL); 1028 pgsize = __SHIFTOUT(descs[1], CPUID_DATP_PGSIZE); 1029 switch (level) { 1030 case 1: 1031 if (type == CPUID_DATP_TCTYPE_I) { 1032 switch (pgsize) { 1033 case CPUID_DATP_PGSIZE_4KB: 1034 caitype = CAI_ITLB; 1035 break; 1036 case CPUID_DATP_PGSIZE_2MB 1037 | CPUID_DATP_PGSIZE_4MB: 1038 caitype = CAI_ITLB2; 1039 break; 1040 case CPUID_DATP_PGSIZE_1GB: 1041 caitype = CAI_L1_1GBITLB; 1042 break; 1043 default: 1044 aprint_error_dev(ci->ci_dev, 1045 "error: unknown ITLB size (%d)\n", 1046 pgsize); 1047 caitype = CAI_ITLB; 1048 break; 1049 } 1050 } else if (type == CPUID_DATP_TCTYPE_D) { 1051 switch (pgsize) { 1052 case CPUID_DATP_PGSIZE_4KB: 1053 caitype = CAI_DTLB; 1054 break; 1055 case CPUID_DATP_PGSIZE_2MB 1056 | CPUID_DATP_PGSIZE_4MB: 1057 caitype = CAI_DTLB2; 1058 break; 1059 case CPUID_DATP_PGSIZE_1GB: 1060 caitype = CAI_L1_1GBDTLB; 1061 break; 1062 default: 1063 aprint_error_dev(ci->ci_dev, 1064 "error: unknown DTLB size (%d)\n", 1065 pgsize); 1066 caitype = CAI_DTLB; 1067 break; 1068 } 1069 } else 1070 caitype = -1; 1071 break; 1072 case 2: 1073 if (type == CPUID_DATP_TCTYPE_I) 1074 caitype = CAI_L2_ITLB; 1075 else if (type == CPUID_DATP_TCTYPE_D) 1076 caitype = CAI_L2_DTLB; 1077 else if (type == CPUID_DATP_TCTYPE_U) { 1078 if (pgsize == CPUID_DATP_PGSIZE_4KB) 1079 caitype = CAI_L2_STLB; 1080 else if (pgsize == (CPUID_DATP_PGSIZE_4KB 1081 | CPUID_DATP_PGSIZE_2MB)) 1082 caitype = CAI_L2_STLB2; 1083 else if (pgsize == (CPUID_DATP_PGSIZE_2MB 1084 | CPUID_DATP_PGSIZE_4MB)) 1085 caitype = CAI_L2_STLB3; 1086 else if ((pgsize & CPUID_DATP_PGSIZE_1GB) 1087 != 0) { 1088 /* FIXME: 1GB max TLB */ 1089 caitype = CAI_L2_STLB3; 1090 linesize = 1024 * 1024 * 1024; 1091 } else if ((pgsize & CPUID_DATP_PGSIZE_4MB) 1092 != 0) { 1093 /* FIXME: 4MB max TLB */ 1094 caitype = CAI_L2_STLB3; 1095 linesize = 4 * 1024 * 1024; 1096 } else if ((pgsize & CPUID_DATP_PGSIZE_2MB) 1097 != 0) { 1098 /* FIXME: 2MB max TLB */ 1099 caitype = CAI_L2_STLB2; 1100 linesize = 2 * 1024 * 1024; 1101 } else { 1102 aprint_error_dev(ci->ci_dev, "error: " 1103 "unknown L2 STLB size (%d)\n", 1104 pgsize); 1105 caitype = CAI_L2_STLB; 1106 linesize = 4 * 1024; 1107 } 1108 } else 1109 caitype = -1; 1110 break; 1111 case 3: 1112 /* XXX need work for L3 TLB */ 1113 caitype = CAI_L3CACHE; 1114 break; 1115 default: 1116 caitype = -1; 1117 break; 1118 } 1119 if (caitype == -1) { 1120 aprint_error_dev(ci->ci_dev, 1121 "error: unknown TLB level&type (%d & %d)\n", 1122 level, type); 1123 continue; 1124 } 1125 switch (pgsize) { 1126 case CPUID_DATP_PGSIZE_4KB: 1127 linesize = 4 * 1024; 1128 break; 1129 case CPUID_DATP_PGSIZE_2MB: 1130 linesize = 2 * 1024 * 1024; 1131 break; 1132 case CPUID_DATP_PGSIZE_4MB: 1133 linesize = 4 * 1024 * 1024; 1134 break; 1135 case CPUID_DATP_PGSIZE_1GB: 1136 linesize = 1024 * 1024 * 1024; 1137 break; 1138 default: 1139 if ((pgsize & CPUID_DATP_PGSIZE_1GB) != 0) 1140 linesize = 1024 * 1024 * 1024; /* MAX 1G */ 1141 else if ((pgsize & CPUID_DATP_PGSIZE_4MB) != 0) 1142 linesize = 4 * 1024 * 1024; /* MAX 4M */ 1143 else if ((pgsize & CPUID_DATP_PGSIZE_2MB) != 0) 1144 linesize = 2 * 1024 * 1024; /* MAX 2M */ 1145 else 1146 linesize = 4 * 1024; /* XXX default to 4K */ 1147 aprint_error_dev(ci->ci_dev, "WARNING: Currently " 1148 "this info can't print correctly " 1149 "(level = %d, pgsize = %d)\n", 1150 level, pgsize); 1151 break; 1152 } 1153 ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS); 1154 sets = descs[2]; 1155 full = descs[3] & CPUID_DATP_FULLASSOC; 1156 ci->ci_cinfo[caitype].cai_totalsize 1157 = ways * sets; /* entries */ 1158 ci->ci_cinfo[caitype].cai_associativity 1159 = full ? 0xff : ways; 1160 ci->ci_cinfo[caitype].cai_linesize = linesize; /* pg size */ 1161 } 1162 } 1163 1164 static const struct x86_cache_info amd_cpuid_l2l3cache_assoc_info[] = 1165 AMD_L2L3CACHE_INFO; 1166 1167 static void 1168 amd_cpu_cacheinfo(struct cpu_info *ci) 1169 { 1170 const struct x86_cache_info *cp; 1171 struct x86_cache_info *cai; 1172 u_int descs[4]; 1173 u_int lfunc; 1174 1175 /* K5 model 0 has none of this info. */ 1176 if (ci->ci_family == 5 && ci->ci_model == 0) 1177 return; 1178 1179 /* Determine the largest extended function value. */ 1180 x86_cpuid(0x80000000, descs); 1181 lfunc = descs[0]; 1182 1183 if (lfunc < 0x80000005) 1184 return; 1185 1186 /* Determine L1 cache/TLB info. */ 1187 x86_cpuid(0x80000005, descs); 1188 1189 /* K6-III and higher have large page TLBs. */ 1190 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1191 cai = &ci->ci_cinfo[CAI_ITLB2]; 1192 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1193 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1194 cai->cai_linesize = largepagesize; 1195 1196 cai = &ci->ci_cinfo[CAI_DTLB2]; 1197 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1198 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1199 cai->cai_linesize = largepagesize; 1200 } 1201 1202 cai = &ci->ci_cinfo[CAI_ITLB]; 1203 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1204 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1205 cai->cai_linesize = (4 * 1024); 1206 1207 cai = &ci->ci_cinfo[CAI_DTLB]; 1208 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1209 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1210 cai->cai_linesize = (4 * 1024); 1211 1212 cai = &ci->ci_cinfo[CAI_DCACHE]; 1213 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1214 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1215 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1216 1217 cai = &ci->ci_cinfo[CAI_ICACHE]; 1218 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1219 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1220 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1221 1222 if (lfunc < 0x80000006) 1223 return; 1224 1225 /* Determine L2 cache/TLB info. */ 1226 x86_cpuid(0x80000006, descs); 1227 1228 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1229 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1230 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1231 cai->cai_linesize = (4 * 1024); 1232 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1233 cai->cai_associativity); 1234 if (cp != NULL) 1235 cai->cai_associativity = cp->cai_associativity; 1236 else 1237 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1238 1239 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1240 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1241 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1242 cai->cai_linesize = largepagesize; 1243 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1244 cai->cai_associativity); 1245 if (cp != NULL) 1246 cai->cai_associativity = cp->cai_associativity; 1247 else 1248 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1249 1250 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1251 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1252 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1253 cai->cai_linesize = (4 * 1024); 1254 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1255 cai->cai_associativity); 1256 if (cp != NULL) 1257 cai->cai_associativity = cp->cai_associativity; 1258 else 1259 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1260 1261 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1262 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1263 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1264 cai->cai_linesize = largepagesize; 1265 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1266 cai->cai_associativity); 1267 if (cp != NULL) 1268 cai->cai_associativity = cp->cai_associativity; 1269 else 1270 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1271 1272 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1273 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1274 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1275 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1276 1277 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1278 cai->cai_associativity); 1279 if (cp != NULL) 1280 cai->cai_associativity = cp->cai_associativity; 1281 else 1282 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1283 1284 /* Determine L3 cache info on AMD Family 10h and newer processors */ 1285 if (ci->ci_family >= 0x10) { 1286 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1287 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1288 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1289 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1290 1291 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1292 cai->cai_associativity); 1293 if (cp != NULL) 1294 cai->cai_associativity = cp->cai_associativity; 1295 else 1296 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1297 } 1298 1299 if (lfunc < 0x80000019) 1300 return; 1301 1302 /* Determine 1GB TLB info. */ 1303 x86_cpuid(0x80000019, descs); 1304 1305 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1306 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1307 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1308 cai->cai_linesize = (1024 * 1024 * 1024); 1309 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1310 cai->cai_associativity); 1311 if (cp != NULL) 1312 cai->cai_associativity = cp->cai_associativity; 1313 else 1314 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1315 1316 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1317 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1318 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1319 cai->cai_linesize = (1024 * 1024 * 1024); 1320 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1321 cai->cai_associativity); 1322 if (cp != NULL) 1323 cai->cai_associativity = cp->cai_associativity; 1324 else 1325 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1326 1327 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1328 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1329 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1330 cai->cai_linesize = (1024 * 1024 * 1024); 1331 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1332 cai->cai_associativity); 1333 if (cp != NULL) 1334 cai->cai_associativity = cp->cai_associativity; 1335 else 1336 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1337 1338 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1339 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1340 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1341 cai->cai_linesize = (1024 * 1024 * 1024); 1342 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1343 cai->cai_associativity); 1344 if (cp != NULL) 1345 cai->cai_associativity = cp->cai_associativity; 1346 else 1347 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1348 1349 if (lfunc < 0x8000001d) 1350 return; 1351 1352 if (ci->ci_feat_val[3] & CPUID_TOPOEXT) 1353 cpu_dcp_cacheinfo(ci, 0x8000001d); 1354 } 1355 1356 static void 1357 via_cpu_cacheinfo(struct cpu_info *ci) 1358 { 1359 struct x86_cache_info *cai; 1360 int stepping; 1361 u_int descs[4]; 1362 u_int lfunc; 1363 1364 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1365 1366 /* 1367 * Determine the largest extended function value. 1368 */ 1369 x86_cpuid(0x80000000, descs); 1370 lfunc = descs[0]; 1371 1372 /* 1373 * Determine L1 cache/TLB info. 1374 */ 1375 if (lfunc < 0x80000005) { 1376 /* No L1 cache info available. */ 1377 return; 1378 } 1379 1380 x86_cpuid(0x80000005, descs); 1381 1382 cai = &ci->ci_cinfo[CAI_ITLB]; 1383 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1384 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1385 cai->cai_linesize = (4 * 1024); 1386 1387 cai = &ci->ci_cinfo[CAI_DTLB]; 1388 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1389 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1390 cai->cai_linesize = (4 * 1024); 1391 1392 cai = &ci->ci_cinfo[CAI_DCACHE]; 1393 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1394 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1395 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1396 if (ci->ci_model == 9 && stepping == 8) { 1397 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1398 cai->cai_associativity = 2; 1399 } 1400 1401 cai = &ci->ci_cinfo[CAI_ICACHE]; 1402 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1403 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1404 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1405 if (ci->ci_model == 9 && stepping == 8) { 1406 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1407 cai->cai_associativity = 2; 1408 } 1409 1410 /* 1411 * Determine L2 cache/TLB info. 1412 */ 1413 if (lfunc < 0x80000006) { 1414 /* No L2 cache info available. */ 1415 return; 1416 } 1417 1418 x86_cpuid(0x80000006, descs); 1419 1420 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1421 if (ci->ci_model >= 9) { 1422 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1423 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1424 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1425 } else { 1426 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1427 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1428 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1429 } 1430 } 1431 1432 static void 1433 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1434 { 1435 u_int descs[4]; 1436 1437 x86_cpuid(0x80860007, descs); 1438 *frequency = descs[0]; 1439 *voltage = descs[1]; 1440 *percentage = descs[2]; 1441 } 1442 1443 static void 1444 transmeta_cpu_info(struct cpu_info *ci) 1445 { 1446 u_int descs[4], nreg; 1447 u_int frequency, voltage, percentage; 1448 1449 x86_cpuid(0x80860000, descs); 1450 nreg = descs[0]; 1451 if (nreg >= 0x80860001) { 1452 x86_cpuid(0x80860001, descs); 1453 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1454 (descs[1] >> 24) & 0xff, 1455 (descs[1] >> 16) & 0xff, 1456 (descs[1] >> 8) & 0xff, 1457 descs[1] & 0xff); 1458 } 1459 if (nreg >= 0x80860002) { 1460 x86_cpuid(0x80860002, descs); 1461 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1462 (descs[1] >> 24) & 0xff, 1463 (descs[1] >> 16) & 0xff, 1464 (descs[1] >> 8) & 0xff, 1465 descs[1] & 0xff, 1466 descs[2]); 1467 } 1468 if (nreg >= 0x80860006) { 1469 union { 1470 char text[65]; 1471 u_int descs[4][4]; 1472 } info; 1473 int i; 1474 1475 for (i=0; i<4; i++) { 1476 x86_cpuid(0x80860003 + i, info.descs[i]); 1477 } 1478 info.text[64] = '\0'; 1479 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1480 } 1481 1482 if (nreg >= 0x80860007) { 1483 tmx86_get_longrun_status(&frequency, 1484 &voltage, &percentage); 1485 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1486 frequency, voltage, percentage); 1487 } 1488 } 1489 1490 static void 1491 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1492 { 1493 u_int descs[4]; 1494 int i; 1495 uint32_t brand[12]; 1496 1497 memset(ci, 0, sizeof(*ci)); 1498 ci->ci_dev = cpuname; 1499 1500 ci->ci_cpu_type = x86_identify(); 1501 if (ci->ci_cpu_type >= 0) { 1502 /* Old pre-cpuid instruction cpu */ 1503 ci->ci_max_cpuid = -1; 1504 return; 1505 } 1506 1507 /* 1508 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1509 * function. 1510 */ 1511 1512 /* 1513 * Fn0000_0000: 1514 * - Save cpuid max level. 1515 * - Save vendor string. 1516 */ 1517 x86_cpuid(0, descs); 1518 ci->ci_max_cpuid = descs[0]; 1519 /* Save vendor string */ 1520 ci->ci_vendor[0] = descs[1]; 1521 ci->ci_vendor[2] = descs[2]; 1522 ci->ci_vendor[1] = descs[3]; 1523 ci->ci_vendor[3] = 0; 1524 1525 /* 1526 * Fn8000_0000: 1527 * - Get cpuid extended function's max level. 1528 */ 1529 x86_cpuid(0x80000000, descs); 1530 if (descs[0] >= 0x80000000) 1531 ci->ci_max_ext_cpuid = descs[0]; 1532 else { 1533 /* Set lower value than 0x80000000 */ 1534 ci->ci_max_ext_cpuid = 0; 1535 } 1536 1537 /* 1538 * Fn8000_000[2-4]: 1539 * - Save brand string. 1540 */ 1541 if (ci->ci_max_ext_cpuid >= 0x80000004) { 1542 x86_cpuid(0x80000002, brand); 1543 x86_cpuid(0x80000003, brand + 4); 1544 x86_cpuid(0x80000004, brand + 8); 1545 for (i = 0; i < 48; i++) 1546 if (((char *) brand)[i] != ' ') 1547 break; 1548 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1549 } 1550 1551 if (ci->ci_max_cpuid < 1) 1552 return; 1553 1554 /* 1555 * Fn0000_0001: 1556 * - Get CPU family, model and stepping (from eax). 1557 * - Initial local APIC ID and brand ID (from ebx) 1558 * - CPUID2 (from ecx) 1559 * - CPUID (from edx) 1560 */ 1561 x86_cpuid(1, descs); 1562 ci->ci_signature = descs[0]; 1563 1564 /* Extract full family/model values */ 1565 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1566 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1567 1568 /* Brand is low order 8 bits of ebx */ 1569 ci->ci_brand_id = __SHIFTOUT(descs[1], CPUID_BRAND_INDEX); 1570 /* Initial local APIC ID */ 1571 ci->ci_initapicid = __SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID); 1572 1573 ci->ci_feat_val[1] = descs[2]; 1574 ci->ci_feat_val[0] = descs[3]; 1575 1576 if (ci->ci_max_cpuid < 3) 1577 return; 1578 1579 /* 1580 * If the processor serial number misfeature is present and supported, 1581 * extract it here. 1582 */ 1583 if ((ci->ci_feat_val[0] & CPUID_PSN) != 0) { 1584 ci->ci_cpu_serial[0] = ci->ci_signature; 1585 x86_cpuid(3, descs); 1586 ci->ci_cpu_serial[2] = descs[2]; 1587 ci->ci_cpu_serial[1] = descs[3]; 1588 } 1589 1590 if (ci->ci_max_cpuid < 0x7) 1591 return; 1592 1593 x86_cpuid(7, descs); 1594 ci->ci_feat_val[5] = descs[1]; 1595 ci->ci_feat_val[6] = descs[2]; 1596 ci->ci_feat_val[7] = descs[3]; 1597 1598 if (ci->ci_max_cpuid < 0xd) 1599 return; 1600 1601 /* Get support XCR0 bits */ 1602 x86_cpuid2(0xd, 0, descs); 1603 ci->ci_feat_val[8] = descs[0]; /* Actually 64 bits */ 1604 ci->ci_cur_xsave = descs[1]; 1605 ci->ci_max_xsave = descs[2]; 1606 1607 /* Additional flags (eg xsaveopt support) */ 1608 x86_cpuid2(0xd, 1, descs); 1609 ci->ci_feat_val[9] = descs[0]; /* Actually 64 bits */ 1610 } 1611 1612 static void 1613 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1614 { 1615 uint32_t descs[4]; 1616 char hv_sig[13]; 1617 char *p; 1618 const char *hv_name; 1619 int i; 1620 1621 /* 1622 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1623 * http://lkml.org/lkml/2008/10/1/246 1624 * 1625 * KB1009458: Mechanisms to determine if software is running in 1626 * a VMware virtual machine 1627 * http://kb.vmware.com/kb/1009458 1628 */ 1629 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1630 x86_cpuid(0x40000000, descs); 1631 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1632 memcpy(p, &descs[i], sizeof(descs[i])); 1633 *p = '\0'; 1634 /* 1635 * HV vendor ID string 1636 * ------------+-------------- 1637 * HAXM "HAXMHAXMHAXM" 1638 * KVM "KVMKVMKVM" 1639 * Microsoft "Microsoft Hv" 1640 * QEMU(TCG) "TCGTCGTCGTCG" 1641 * VMware "VMwareVMware" 1642 * Xen "XenVMMXenVMM" 1643 * NetBSD "___ NVMM ___" 1644 */ 1645 if (strncmp(hv_sig, "HAXMHAXMHAXM", 12) == 0) 1646 hv_name = "HAXM"; 1647 else if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1648 hv_name = "KVM"; 1649 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1650 hv_name = "Hyper-V"; 1651 else if (strncmp(hv_sig, "TCGTCGTCGTCG", 12) == 0) 1652 hv_name = "QEMU(TCG)"; 1653 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1654 hv_name = "VMware"; 1655 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1656 hv_name = "Xen"; 1657 else if (strncmp(hv_sig, "___ NVMM ___", 12) == 0) 1658 hv_name = "NVMM"; 1659 else 1660 hv_name = "unknown"; 1661 1662 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1663 } 1664 } 1665 1666 static void 1667 cpu_probe_features(struct cpu_info *ci) 1668 { 1669 const struct cpu_cpuid_nameclass *cpup = NULL; 1670 unsigned int i; 1671 1672 if (ci->ci_max_cpuid < 1) 1673 return; 1674 1675 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1676 if (!strncmp((char *)ci->ci_vendor, 1677 i386_cpuid_cpus[i].cpu_id, 12)) { 1678 cpup = &i386_cpuid_cpus[i]; 1679 break; 1680 } 1681 } 1682 1683 if (cpup == NULL) 1684 return; 1685 1686 i = ci->ci_family - CPU_MINFAMILY; 1687 1688 if (i >= __arraycount(cpup->cpu_family)) 1689 i = __arraycount(cpup->cpu_family) - 1; 1690 1691 if (cpup->cpu_family[i].cpu_probe == NULL) 1692 return; 1693 1694 (*cpup->cpu_family[i].cpu_probe)(ci); 1695 } 1696 1697 static void 1698 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1699 { 1700 char buf[32 * 16]; 1701 char *bp; 1702 1703 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1704 1705 if (val == 0 || fmt == NULL) 1706 return; 1707 1708 snprintb_m(buf, sizeof(buf), fmt, val, 1709 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1710 bp = buf; 1711 while (*bp != '\0') { 1712 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1713 bp += strlen(bp) + 1; 1714 } 1715 } 1716 1717 static void 1718 dump_descs(uint32_t leafstart, uint32_t leafend, const char *cpuname, 1719 const char *blockname) 1720 { 1721 uint32_t descs[4]; 1722 uint32_t leaf; 1723 1724 aprint_verbose("%s: highest %s info %08x\n", cpuname, blockname, 1725 leafend); 1726 1727 if (verbose) { 1728 for (leaf = leafstart; leaf <= leafend; leaf++) { 1729 x86_cpuid(leaf, descs); 1730 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1731 leaf, descs[0], descs[1], descs[2], descs[3]); 1732 } 1733 } 1734 } 1735 1736 static void 1737 identifycpu_cpuids_intel_0x04(struct cpu_info *ci) 1738 { 1739 u_int lp_max = 1; /* logical processors per package */ 1740 u_int smt_max; /* smt per core */ 1741 u_int core_max = 1; /* core per package */ 1742 u_int smt_bits, core_bits; 1743 uint32_t descs[4]; 1744 1745 /* 1746 * 253668.pdf 7.10.2 1747 */ 1748 1749 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1750 x86_cpuid(1, descs); 1751 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1752 } 1753 x86_cpuid2(4, 0, descs); 1754 core_max = __SHIFTOUT(descs[0], CPUID_DCP_CORE_P_PKG) + 1; 1755 1756 assert(lp_max >= core_max); 1757 smt_max = lp_max / core_max; 1758 smt_bits = ilog2(smt_max - 1) + 1; 1759 core_bits = ilog2(core_max - 1) + 1; 1760 1761 if (smt_bits + core_bits) 1762 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1763 1764 if (core_bits) 1765 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1766 __BITS(smt_bits, smt_bits + core_bits - 1)); 1767 1768 if (smt_bits) 1769 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1770 __BITS((int)0, (int)(smt_bits - 1))); 1771 } 1772 1773 static void 1774 identifycpu_cpuids_intel_0x0b(struct cpu_info *ci) 1775 { 1776 const char *cpuname = ci->ci_dev; 1777 u_int smt_bits, core_bits, core_shift = 0, pkg_shift = 0; 1778 uint32_t descs[4]; 1779 int i; 1780 1781 x86_cpuid(0x0b, descs); 1782 if (descs[1] == 0) { 1783 identifycpu_cpuids_intel_0x04(ci); 1784 return; 1785 } 1786 1787 for (i = 0; ; i++) { 1788 unsigned int shiftnum, lvltype; 1789 x86_cpuid2(0x0b, i, descs); 1790 1791 /* On invalid level, (EAX and) EBX return 0 */ 1792 if (descs[1] == 0) 1793 break; 1794 1795 shiftnum = __SHIFTOUT(descs[0], CPUID_TOP_SHIFTNUM); 1796 lvltype = __SHIFTOUT(descs[2], CPUID_TOP_LVLTYPE); 1797 switch (lvltype) { 1798 case CPUID_TOP_LVLTYPE_SMT: 1799 core_shift = shiftnum; 1800 break; 1801 case CPUID_TOP_LVLTYPE_CORE: 1802 pkg_shift = shiftnum; 1803 break; 1804 case CPUID_TOP_LVLTYPE_INVAL: 1805 aprint_verbose("%s: Invalid level type\n", cpuname); 1806 break; 1807 default: 1808 aprint_verbose("%s: Unknown level type(%d) \n", 1809 cpuname, lvltype); 1810 break; 1811 } 1812 } 1813 1814 assert(pkg_shift >= core_shift); 1815 smt_bits = core_shift; 1816 core_bits = pkg_shift - core_shift; 1817 1818 ci->ci_packageid = ci->ci_initapicid >> pkg_shift; 1819 1820 if (core_bits) 1821 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1822 __BITS(core_shift, pkg_shift - 1)); 1823 1824 if (smt_bits) 1825 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1826 __BITS((int)0, core_shift - 1)); 1827 } 1828 1829 static void 1830 identifycpu_cpuids_intel(struct cpu_info *ci) 1831 { 1832 const char *cpuname = ci->ci_dev; 1833 1834 if (ci->ci_max_cpuid >= 0x0b) 1835 identifycpu_cpuids_intel_0x0b(ci); 1836 else if (ci->ci_max_cpuid >= 4) 1837 identifycpu_cpuids_intel_0x04(ci); 1838 1839 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1840 ci->ci_packageid); 1841 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1842 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1843 } 1844 1845 static void 1846 identifycpu_cpuids_amd(struct cpu_info *ci) 1847 { 1848 const char *cpuname = ci->ci_dev; 1849 u_int lp_max, core_max; 1850 int n, cpu_family, apic_id, smt_bits, core_bits = 0; 1851 uint32_t descs[4]; 1852 1853 apic_id = ci->ci_initapicid; 1854 cpu_family = CPUID_TO_FAMILY(ci->ci_signature); 1855 1856 if (cpu_family < 0xf) 1857 return; 1858 1859 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1860 x86_cpuid(1, descs); 1861 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1862 1863 if (cpu_family >= 0x10 && ci->ci_max_ext_cpuid >= 0x8000008) { 1864 x86_cpuid(0x8000008, descs); 1865 core_max = (descs[2] & 0xff) + 1; 1866 n = (descs[2] >> 12) & 0x0f; 1867 if (n != 0) 1868 core_bits = n; 1869 } 1870 } else { 1871 lp_max = 1; 1872 } 1873 core_max = lp_max; 1874 1875 smt_bits = ilog2((lp_max / core_max) - 1) + 1; 1876 if (core_bits == 0) 1877 core_bits = ilog2(core_max - 1) + 1; 1878 1879 #if 0 /* MSRs need kernel mode */ 1880 if (cpu_family < 0x11) { 1881 const uint64_t reg = rdmsr(MSR_NB_CFG); 1882 if ((reg & NB_CFG_INITAPICCPUIDLO) == 0) { 1883 const u_int node_id = apic_id & __BITS(0, 2); 1884 apic_id = (cpu_family == 0xf) ? 1885 (apic_id >> core_bits) | (node_id << core_bits) : 1886 (apic_id >> 5) | (node_id << 2); 1887 } 1888 } 1889 #endif 1890 1891 if (cpu_family >= 0x17) { 1892 x86_cpuid(0x8000001e, descs); 1893 const u_int threads = ((descs[1] >> 8) & 0xff) + 1; 1894 smt_bits = ilog2(threads); 1895 core_bits -= smt_bits; 1896 } 1897 1898 if (smt_bits + core_bits) { 1899 if (smt_bits + core_bits < 32) 1900 ci->ci_packageid = 0; 1901 } 1902 if (core_bits) { 1903 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1904 ci->ci_coreid = __SHIFTOUT(apic_id, core_mask); 1905 } 1906 if (smt_bits) { 1907 u_int smt_mask = __BITS(0, smt_bits - 1); 1908 ci->ci_smtid = __SHIFTOUT(apic_id, smt_mask); 1909 } 1910 1911 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1912 ci->ci_packageid); 1913 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1914 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1915 } 1916 1917 static void 1918 identifycpu_cpuids(struct cpu_info *ci) 1919 { 1920 const char *cpuname = ci->ci_dev; 1921 1922 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1923 ci->ci_packageid = ci->ci_initapicid; 1924 ci->ci_coreid = 0; 1925 ci->ci_smtid = 0; 1926 1927 if (cpu_vendor == CPUVENDOR_INTEL) 1928 identifycpu_cpuids_intel(ci); 1929 else if (cpu_vendor == CPUVENDOR_AMD) 1930 identifycpu_cpuids_amd(ci); 1931 } 1932 1933 void 1934 identifycpu(int fd, const char *cpuname) 1935 { 1936 const char *name = "", *modifier, *vendorname, *brand = ""; 1937 int class = CPUCLASS_386; 1938 unsigned int i; 1939 int modif, family; 1940 const struct cpu_cpuid_nameclass *cpup = NULL; 1941 const struct cpu_cpuid_family *cpufam; 1942 struct cpu_info *ci, cistore; 1943 u_int descs[4]; 1944 size_t sz; 1945 struct cpu_ucode_version ucode; 1946 union { 1947 struct cpu_ucode_version_amd amd; 1948 struct cpu_ucode_version_intel1 intel1; 1949 } ucvers; 1950 1951 ci = &cistore; 1952 cpu_probe_base_features(ci, cpuname); 1953 dump_descs(0x00000000, ci->ci_max_cpuid, cpuname, "basic"); 1954 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1955 x86_cpuid(0x40000000, descs); 1956 dump_descs(0x40000000, descs[0], cpuname, "hypervisor"); 1957 } 1958 dump_descs(0x80000000, ci->ci_max_ext_cpuid, cpuname, "extended"); 1959 1960 cpu_probe_hv_features(ci, cpuname); 1961 cpu_probe_features(ci); 1962 1963 if (ci->ci_cpu_type >= 0) { 1964 /* Old pre-cpuid instruction cpu */ 1965 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1966 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1967 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1968 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1969 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1970 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1971 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1972 modifier = ""; 1973 } else { 1974 /* CPU which support cpuid instruction */ 1975 modif = (ci->ci_signature >> 12) & 0x3; 1976 family = ci->ci_family; 1977 if (family < CPU_MINFAMILY) 1978 errx(1, "identifycpu: strange family value"); 1979 if (family > CPU_MAXFAMILY) 1980 family = CPU_MAXFAMILY; 1981 1982 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1983 if (!strncmp((char *)ci->ci_vendor, 1984 i386_cpuid_cpus[i].cpu_id, 12)) { 1985 cpup = &i386_cpuid_cpus[i]; 1986 break; 1987 } 1988 } 1989 1990 if (cpup == NULL) { 1991 cpu_vendor = CPUVENDOR_UNKNOWN; 1992 if (ci->ci_vendor[0] != '\0') 1993 vendorname = (char *)&ci->ci_vendor[0]; 1994 else 1995 vendorname = "Unknown"; 1996 class = family - 3; 1997 modifier = ""; 1998 name = ""; 1999 ci->ci_info = NULL; 2000 } else { 2001 cpu_vendor = cpup->cpu_vendor; 2002 vendorname = cpup->cpu_vendorname; 2003 modifier = modifiers[modif]; 2004 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 2005 name = cpufam->cpu_models[ci->ci_model]; 2006 if (name == NULL || *name == '\0') 2007 name = cpufam->cpu_model_default; 2008 class = cpufam->cpu_class; 2009 ci->ci_info = cpufam->cpu_info; 2010 2011 if (cpu_vendor == CPUVENDOR_INTEL) { 2012 if (ci->ci_family == 6 && ci->ci_model >= 5) { 2013 const char *tmp; 2014 tmp = intel_family6_name(ci); 2015 if (tmp != NULL) 2016 name = tmp; 2017 } 2018 if (ci->ci_family == 15 && 2019 ci->ci_brand_id < 2020 __arraycount(i386_intel_brand) && 2021 i386_intel_brand[ci->ci_brand_id]) 2022 name = 2023 i386_intel_brand[ci->ci_brand_id]; 2024 } 2025 2026 if (cpu_vendor == CPUVENDOR_AMD) { 2027 if (ci->ci_family == 6 && ci->ci_model >= 6) { 2028 if (ci->ci_brand_id == 1) 2029 /* 2030 * It's Duron. We override the 2031 * name, since it might have 2032 * been misidentified as Athlon. 2033 */ 2034 name = 2035 amd_brand[ci->ci_brand_id]; 2036 else 2037 brand = amd_brand_name; 2038 } 2039 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 2040 == 0xf) { 2041 /* Identify AMD64 CPU names. */ 2042 const char *tmp; 2043 tmp = amd_amd64_name(ci); 2044 if (tmp != NULL) 2045 name = tmp; 2046 } 2047 } 2048 2049 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 2050 vendorname = "VIA"; 2051 } 2052 } 2053 2054 ci->ci_cpu_class = class; 2055 2056 sz = sizeof(ci->ci_tsc_freq); 2057 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 2058 sz = sizeof(use_pae); 2059 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 2060 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 2061 2062 /* 2063 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 2064 * we try to determine from the family/model values. 2065 */ 2066 if (*cpu_brand_string != '\0') 2067 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 2068 2069 aprint_normal("%s: %s", cpuname, vendorname); 2070 if (*modifier) 2071 aprint_normal(" %s", modifier); 2072 if (*name) 2073 aprint_normal(" %s", name); 2074 if (*brand) 2075 aprint_normal(" %s", brand); 2076 aprint_normal(" (%s-class)", classnames[class]); 2077 2078 if (ci->ci_tsc_freq != 0) 2079 aprint_normal(", %ju.%02ju MHz", 2080 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 2081 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 2082 aprint_normal("\n"); 2083 2084 (void)cpu_tsc_freq_cpuid(ci); 2085 2086 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 2087 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 2088 if (ci->ci_signature != 0) 2089 aprint_normal(" (id %#x)", ci->ci_signature); 2090 aprint_normal("\n"); 2091 2092 if (ci->ci_info) 2093 (*ci->ci_info)(ci); 2094 2095 /* 2096 * display CPU feature flags 2097 */ 2098 2099 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 2100 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 2101 2102 /* These next two are actually common definitions! */ 2103 print_bits(cpuname, "features2", 2104 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 2105 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 2106 print_bits(cpuname, "features3", 2107 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 2108 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 2109 2110 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 2111 ci->ci_feat_val[4]); 2112 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2113 print_bits(cpuname, "features5", CPUID_SEF_FLAGS, 2114 ci->ci_feat_val[5]); 2115 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2116 print_bits(cpuname, "features6", CPUID_SEF_FLAGS1, 2117 ci->ci_feat_val[6]); 2118 2119 if (cpu_vendor == CPUVENDOR_INTEL) 2120 print_bits(cpuname, "features7", CPUID_SEF_FLAGS2, 2121 ci->ci_feat_val[7]); 2122 2123 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[8]); 2124 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 2125 ci->ci_feat_val[9]); 2126 2127 if (ci->ci_max_xsave != 0) { 2128 aprint_normal("%s: xsave area size: current %d, maximum %d", 2129 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 2130 aprint_normal(", xgetbv %sabled\n", 2131 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 2132 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 2133 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 2134 x86_xgetbv()); 2135 } 2136 2137 x86_print_cache_and_tlb_info(ci); 2138 2139 if (ci->ci_max_cpuid >= 3 && (ci->ci_feat_val[0] & CPUID_PSN)) { 2140 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 2141 cpuname, 2142 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 2143 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 2144 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 2145 } 2146 2147 if (ci->ci_cpu_class == CPUCLASS_386) 2148 errx(1, "NetBSD requires an 80486 or later processor"); 2149 2150 if (ci->ci_cpu_type == CPU_486DLC) { 2151 #ifndef CYRIX_CACHE_WORKS 2152 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 2153 #else 2154 #ifndef CYRIX_CACHE_REALLY_WORKS 2155 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 2156 #else 2157 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 2158 #endif 2159 #endif 2160 } 2161 2162 /* 2163 * Everything past this point requires a Pentium or later. 2164 */ 2165 if (ci->ci_max_cpuid < 0) 2166 return; 2167 2168 identifycpu_cpuids(ci); 2169 2170 if ((ci->ci_max_cpuid >= 5) 2171 && ((cpu_vendor == CPUVENDOR_INTEL) 2172 || (cpu_vendor == CPUVENDOR_AMD))) { 2173 uint16_t lmin, lmax; 2174 x86_cpuid(5, descs); 2175 2176 print_bits(cpuname, "MONITOR/MWAIT extensions", 2177 CPUID_MON_FLAGS, descs[2]); 2178 lmin = __SHIFTOUT(descs[0], CPUID_MON_MINSIZE); 2179 lmax = __SHIFTOUT(descs[1], CPUID_MON_MAXSIZE); 2180 aprint_normal("%s: monitor-line size %hu", cpuname, lmin); 2181 if (lmin != lmax) 2182 aprint_normal("-%hu", lmax); 2183 aprint_normal("\n"); 2184 2185 for (i = 0; i <= 7; i++) { 2186 unsigned int num = CPUID_MON_SUBSTATE(descs[3], i); 2187 2188 if (num != 0) 2189 aprint_normal("%s: C%u substates %u\n", 2190 cpuname, i, num); 2191 } 2192 } 2193 if ((ci->ci_max_cpuid >= 6) 2194 && ((cpu_vendor == CPUVENDOR_INTEL) 2195 || (cpu_vendor == CPUVENDOR_AMD))) { 2196 x86_cpuid(6, descs); 2197 print_bits(cpuname, "DSPM-eax", CPUID_DSPM_FLAGS, descs[0]); 2198 print_bits(cpuname, "DSPM-ecx", CPUID_DSPM_FLAGS1, descs[2]); 2199 } 2200 if ((ci->ci_max_cpuid >= 7) 2201 && ((cpu_vendor == CPUVENDOR_INTEL) 2202 || (cpu_vendor == CPUVENDOR_AMD))) { 2203 x86_cpuid(7, descs); 2204 aprint_verbose("%s: SEF highest subleaf %08x\n", 2205 cpuname, descs[0]); 2206 if (descs[0] >= 1) { 2207 x86_cpuid2(7, 1, descs); 2208 print_bits(cpuname, "SEF-subleaf1-eax", 2209 CPUID_SEF1_FLAGS_A, descs[0]); 2210 } 2211 } 2212 2213 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) { 2214 if (ci->ci_max_ext_cpuid >= 0x80000007) 2215 powernow_probe(ci); 2216 2217 if (ci->ci_max_ext_cpuid >= 0x80000008) { 2218 x86_cpuid(0x80000008, descs); 2219 print_bits(cpuname, "AMD Extended features", 2220 CPUID_CAPEX_FLAGS, descs[1]); 2221 } 2222 } 2223 2224 if (cpu_vendor == CPUVENDOR_AMD) { 2225 if ((ci->ci_max_ext_cpuid >= 0x8000000a) 2226 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 2227 x86_cpuid(0x8000000a, descs); 2228 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 2229 descs[0] & 0xf); 2230 aprint_verbose("%s: SVM NASID %d\n", cpuname, 2231 descs[1]); 2232 print_bits(cpuname, "SVM features", 2233 CPUID_AMD_SVM_FLAGS, descs[3]); 2234 } 2235 if (ci->ci_max_ext_cpuid >= 0x8000001f) { 2236 x86_cpuid(0x8000001f, descs); 2237 print_bits(cpuname, "Encrypted Memory features", 2238 CPUID_AMD_ENCMEM_FLAGS, descs[0]); 2239 } 2240 } else if (cpu_vendor == CPUVENDOR_INTEL) { 2241 int32_t bi_index; 2242 2243 for (bi_index = 1; bi_index <= ci->ci_max_cpuid; bi_index++) { 2244 x86_cpuid(bi_index, descs); 2245 switch (bi_index) { 2246 case 0x0a: 2247 print_bits(cpuname, "Perfmon-eax", 2248 CPUID_PERF_FLAGS0, descs[0]); 2249 print_bits(cpuname, "Perfmon-ebx", 2250 CPUID_PERF_FLAGS1, descs[1]); 2251 print_bits(cpuname, "Perfmon-edx", 2252 CPUID_PERF_FLAGS3, descs[3]); 2253 break; 2254 default: 2255 #if 0 2256 aprint_verbose("%s: basic %08x-eax %08x\n", 2257 cpuname, bi_index, descs[0]); 2258 aprint_verbose("%s: basic %08x-ebx %08x\n", 2259 cpuname, bi_index, descs[1]); 2260 aprint_verbose("%s: basic %08x-ecx %08x\n", 2261 cpuname, bi_index, descs[2]); 2262 aprint_verbose("%s: basic %08x-edx %08x\n", 2263 cpuname, bi_index, descs[3]); 2264 #endif 2265 break; 2266 } 2267 } 2268 } 2269 2270 #ifdef INTEL_ONDEMAND_CLOCKMOD 2271 clockmod_init(); 2272 #endif 2273 2274 if (cpu_vendor == CPUVENDOR_AMD) 2275 ucode.loader_version = CPU_UCODE_LOADER_AMD; 2276 else if (cpu_vendor == CPUVENDOR_INTEL) 2277 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 2278 else 2279 return; 2280 2281 ucode.data = &ucvers; 2282 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 2283 #ifdef __i386__ 2284 struct cpu_ucode_version_64 ucode_64; 2285 if (errno != ENOTTY) 2286 return; 2287 /* Try the 64 bit ioctl */ 2288 memset(&ucode_64, 0, sizeof ucode_64); 2289 ucode_64.data = &ucvers; 2290 ucode_64.loader_version = ucode.loader_version; 2291 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 2292 return; 2293 #else 2294 return; 2295 #endif 2296 } 2297 2298 if (cpu_vendor == CPUVENDOR_AMD) 2299 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2300 else if (cpu_vendor == CPUVENDOR_INTEL) 2301 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2302 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2303 } 2304 2305 static const char * 2306 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2307 const char *sep) 2308 { 2309 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2310 char human_num[HUMAN_BUFSIZE]; 2311 2312 if (cai->cai_totalsize == 0) 2313 return sep; 2314 2315 if (sep == NULL) 2316 aprint_verbose_dev(ci->ci_dev, ""); 2317 else 2318 aprint_verbose("%s", sep); 2319 if (name != NULL) 2320 aprint_verbose("%s ", name); 2321 2322 if (cai->cai_string != NULL) { 2323 aprint_verbose("%s ", cai->cai_string); 2324 } else { 2325 (void)humanize_number(human_num, sizeof(human_num), 2326 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2327 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2328 } 2329 switch (cai->cai_associativity) { 2330 case 0: 2331 aprint_verbose("disabled"); 2332 break; 2333 case 1: 2334 aprint_verbose("direct-mapped"); 2335 break; 2336 case 0xff: 2337 aprint_verbose("fully associative"); 2338 break; 2339 default: 2340 aprint_verbose("%d-way", cai->cai_associativity); 2341 break; 2342 } 2343 return ", "; 2344 } 2345 2346 static const char * 2347 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2348 const char *sep) 2349 { 2350 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2351 char human_num[HUMAN_BUFSIZE]; 2352 2353 if (cai->cai_totalsize == 0) 2354 return sep; 2355 2356 if (sep == NULL) 2357 aprint_verbose_dev(ci->ci_dev, ""); 2358 else 2359 aprint_verbose("%s", sep); 2360 if ((name != NULL) && (sep == NULL)) 2361 aprint_verbose("%s ", name); 2362 2363 if (cai->cai_string != NULL) { 2364 aprint_verbose("%s", cai->cai_string); 2365 } else { 2366 (void)humanize_number(human_num, sizeof(human_num), 2367 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2368 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2369 human_num); 2370 switch (cai->cai_associativity) { 2371 case 0: 2372 aprint_verbose("disabled"); 2373 break; 2374 case 1: 2375 aprint_verbose("direct-mapped"); 2376 break; 2377 case 0xff: 2378 aprint_verbose("fully associative"); 2379 break; 2380 default: 2381 aprint_verbose("%d-way", cai->cai_associativity); 2382 break; 2383 } 2384 } 2385 return ", "; 2386 } 2387 2388 static void 2389 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2390 { 2391 const char *sep = NULL; 2392 2393 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2394 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2395 sep = print_cache_config(ci, CAI_ICACHE, "I-cache:", NULL); 2396 sep = print_cache_config(ci, CAI_DCACHE, "D-cache:", sep); 2397 if (sep != NULL) 2398 aprint_verbose("\n"); 2399 } 2400 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2401 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache:", NULL); 2402 if (sep != NULL) 2403 aprint_verbose("\n"); 2404 } 2405 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2406 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache:", NULL); 2407 if (sep != NULL) 2408 aprint_verbose("\n"); 2409 } 2410 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2411 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2412 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2413 if (sep != NULL) 2414 aprint_verbose("\n"); 2415 } 2416 2417 sep = print_tlb_config(ci, CAI_ITLB, "ITLB:", NULL); 2418 sep = print_tlb_config(ci, CAI_ITLB2, "ITLB:", sep); 2419 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "ITLB:", sep); 2420 if (sep != NULL) 2421 aprint_verbose("\n"); 2422 2423 sep = print_tlb_config(ci, CAI_DTLB, "DTLB:", NULL); 2424 sep = print_tlb_config(ci, CAI_DTLB2, "DTLB:", sep); 2425 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "DTLB:", sep); 2426 if (sep != NULL) 2427 aprint_verbose("\n"); 2428 2429 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB:", NULL); 2430 sep = print_tlb_config(ci, CAI_L2_ITLB2, "L2 ITLB:", sep); 2431 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 ITLB:", sep); 2432 if (sep != NULL) 2433 aprint_verbose("\n"); 2434 2435 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB:", NULL); 2436 sep = print_tlb_config(ci, CAI_L2_DTLB2, "L2 DTLB:", sep); 2437 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 DTLB:", sep); 2438 if (sep != NULL) 2439 aprint_verbose("\n"); 2440 2441 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB:", NULL); 2442 sep = print_tlb_config(ci, CAI_L2_STLB2, "L2 STLB:", sep); 2443 sep = print_tlb_config(ci, CAI_L2_STLB3, "L2 STLB:", sep); 2444 if (sep != NULL) 2445 aprint_verbose("\n"); 2446 } 2447 2448 static void 2449 powernow_probe(struct cpu_info *ci) 2450 { 2451 uint32_t regs[4]; 2452 char buf[256]; 2453 2454 x86_cpuid(0x80000007, regs); 2455 2456 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2457 aprint_normal_dev(ci->ci_dev, "Power Management features: %s\n", buf); 2458 } 2459 2460 bool 2461 identifycpu_bind(void) 2462 { 2463 2464 return true; 2465 } 2466 2467 int 2468 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2469 { 2470 struct cpu_info ci; 2471 int loader_version, res; 2472 struct cpu_ucode_version versreq; 2473 2474 cpu_probe_base_features(&ci, "unknown"); 2475 2476 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2477 loader_version = CPU_UCODE_LOADER_AMD; 2478 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2479 loader_version = CPU_UCODE_LOADER_INTEL1; 2480 else 2481 return -1; 2482 2483 /* check whether the kernel understands this loader version */ 2484 versreq.loader_version = loader_version; 2485 versreq.data = 0; 2486 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2487 if (res) 2488 return -1; 2489 2490 switch (loader_version) { 2491 case CPU_UCODE_LOADER_AMD: 2492 if (uc->cpu_nr != -1) { 2493 /* printf? */ 2494 return -1; 2495 } 2496 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2497 break; 2498 case CPU_UCODE_LOADER_INTEL1: 2499 if (uc->cpu_nr == -1) 2500 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2501 else 2502 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2503 break; 2504 default: /* can't happen */ 2505 return -1; 2506 } 2507 uc->loader_version = loader_version; 2508 return 0; 2509 } 2510
Indexes created Sat Oct 25 16:10:12 GMT 2025