i386.c revision 1.113
1 /* $NetBSD: i386.c,v 1.113 2020/06/01 08:33:40 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.113 2020/06/01 08:33:40 msaitoh Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cpu_ucode.h> 85 86 #include "../cpuctl.h" 87 #include "cpuctl_i386.h" 88 89 /* Size of buffer for printing humanized numbers */ 90 #define HUMAN_BUFSIZE sizeof("999KB") 91 92 struct cpu_nocpuid_nameclass { 93 int cpu_vendor; 94 const char *cpu_vendorname; 95 const char *cpu_name; 96 int cpu_class; 97 void (*cpu_setup)(struct cpu_info *); 98 void (*cpu_cacheinfo)(struct cpu_info *); 99 void (*cpu_info)(struct cpu_info *); 100 }; 101 102 struct cpu_cpuid_nameclass { 103 const char *cpu_id; 104 int cpu_vendor; 105 const char *cpu_vendorname; 106 struct cpu_cpuid_family { 107 int cpu_class; 108 const char *cpu_models[256]; 109 const char *cpu_model_default; 110 void (*cpu_setup)(struct cpu_info *); 111 void (*cpu_probe)(struct cpu_info *); 112 void (*cpu_info)(struct cpu_info *); 113 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 114 }; 115 116 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 117 118 /* 119 * Map Brand ID from cpuid instruction to brand name. 120 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 121 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 122 * Architectures Software Developer's Manual, Volume 2A". 123 */ 124 static const char * const i386_intel_brand[] = { 125 "", /* Unsupported */ 126 "Celeron", /* Intel (R) Celeron (TM) processor */ 127 "Pentium III", /* Intel (R) Pentium (R) III processor */ 128 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 129 "Pentium III", /* Intel (R) Pentium (R) III processor */ 130 "", /* 0x05: Reserved */ 131 "Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */ 132 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 133 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 134 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 135 "Celeron", /* Intel (R) Celeron (TM) processor */ 136 "Xeon", /* Intel (R) Xeon (TM) processor */ 137 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 138 "", /* 0x0d: Reserved */ 139 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 140 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 141 "", /* 0x10: Reserved */ 142 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 143 "Celeron M", /* Intel (R) Celeron (R) M processor */ 144 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 145 "Celeron", /* Intel (R) Celeron (R) processor */ 146 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 147 "Pentium M", /* Intel (R) Pentium (R) M processor */ 148 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 149 }; 150 151 /* 152 * AMD processors don't have Brand IDs, so we need these names for probe. 153 */ 154 static const char * const amd_brand[] = { 155 "", 156 "Duron", /* AMD Duron(tm) */ 157 "MP", /* AMD Athlon(tm) MP */ 158 "XP", /* AMD Athlon(tm) XP */ 159 "4" /* AMD Athlon(tm) 4 */ 160 }; 161 162 int cpu_vendor; 163 static char cpu_brand_string[49]; 164 static char amd_brand_name[48]; 165 static int use_pae, largepagesize; 166 167 /* Setup functions */ 168 static void disable_tsc(struct cpu_info *); 169 static void amd_family5_setup(struct cpu_info *); 170 static void cyrix6x86_cpu_setup(struct cpu_info *); 171 static void winchip_cpu_setup(struct cpu_info *); 172 /* Brand/Model name functions */ 173 static const char *intel_family6_name(struct cpu_info *); 174 static const char *amd_amd64_name(struct cpu_info *); 175 /* Probe functions */ 176 static void amd_family6_probe(struct cpu_info *); 177 static void powernow_probe(struct cpu_info *); 178 static void intel_family_new_probe(struct cpu_info *); 179 static void via_cpu_probe(struct cpu_info *); 180 /* (Cache) Info functions */ 181 static void cpu_dcp_cacheinfo(struct cpu_info *, uint32_t); 182 static void intel_cpu_cacheinfo(struct cpu_info *); 183 static void amd_cpu_cacheinfo(struct cpu_info *); 184 static void via_cpu_cacheinfo(struct cpu_info *); 185 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 186 static void transmeta_cpu_info(struct cpu_info *); 187 /* Common functions */ 188 static void cpu_probe_base_features(struct cpu_info *, const char *); 189 static void cpu_probe_hv_features(struct cpu_info *, const char *); 190 static void cpu_probe_features(struct cpu_info *); 191 static void print_bits(const char *, const char *, const char *, uint32_t); 192 static void identifycpu_cpuids(struct cpu_info *); 193 static const struct x86_cache_info *cache_info_lookup( 194 const struct x86_cache_info *, uint8_t); 195 static const char *print_cache_config(struct cpu_info *, int, const char *, 196 const char *); 197 static const char *print_tlb_config(struct cpu_info *, int, const char *, 198 const char *); 199 static void x86_print_cache_and_tlb_info(struct cpu_info *); 200 201 /* 202 * Note: these are just the ones that may not have a cpuid instruction. 203 * We deal with the rest in a different way. 204 */ 205 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 206 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 207 NULL, NULL, NULL }, /* CPU_386SX */ 208 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 209 NULL, NULL, NULL }, /* CPU_386 */ 210 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 211 NULL, NULL, NULL }, /* CPU_486SX */ 212 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 213 NULL, NULL, NULL }, /* CPU_486 */ 214 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 215 NULL, NULL, NULL }, /* CPU_486DLC */ 216 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 217 NULL, NULL, NULL }, /* CPU_6x86 */ 218 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 219 NULL, NULL, NULL }, /* CPU_NX586 */ 220 }; 221 222 const char *classnames[] = { 223 "386", 224 "486", 225 "586", 226 "686" 227 }; 228 229 const char *modifiers[] = { 230 "", 231 "OverDrive", 232 "Dual", 233 "" 234 }; 235 236 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 237 { 238 /* 239 * For Intel processors, check Chapter 35Model-specific 240 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 241 * Software Developer's Manual, Volume 3C". 242 */ 243 "GenuineIntel", 244 CPUVENDOR_INTEL, 245 "Intel", 246 /* Family 4 */ 247 { { 248 CPUCLASS_486, 249 { 250 "486DX", "486DX", "486SX", "486DX2", "486SL", 251 "486SX2", 0, "486DX2 W/B Enhanced", 252 "486DX4", 0, 0, 0, 0, 0, 0, 0, 253 }, 254 "486", /* Default */ 255 NULL, 256 NULL, 257 intel_cpu_cacheinfo, 258 }, 259 /* Family 5 */ 260 { 261 CPUCLASS_586, 262 { 263 "Pentium (P5 A-step)", "Pentium (P5)", 264 "Pentium (P54C)", "Pentium (P24T)", 265 "Pentium/MMX", "Pentium", 0, 266 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 267 "Quark X1000", 0, 0, 0, 0, 0, 0, 268 }, 269 "Pentium", /* Default */ 270 NULL, 271 NULL, 272 intel_cpu_cacheinfo, 273 }, 274 /* Family 6 */ 275 { 276 CPUCLASS_686, 277 { 278 [0x00] = "Pentium Pro (A-step)", 279 [0x01] = "Pentium Pro", 280 [0x03] = "Pentium II (Klamath)", 281 [0x04] = "Pentium Pro", 282 [0x05] = "Pentium II/Celeron (Deschutes)", 283 [0x06] = "Celeron (Mendocino)", 284 [0x07] = "Pentium III (Katmai)", 285 [0x08] = "Pentium III (Coppermine)", 286 [0x09] = "Pentium M (Banias)", 287 [0x0a] = "Pentium III Xeon (Cascades)", 288 [0x0b] = "Pentium III (Tualatin)", 289 [0x0d] = "Pentium M (Dothan)", 290 [0x0e] = "Pentium Core Duo, Core solo", 291 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 292 "Core 2 Quad 6xxx, " 293 "Core 2 Extreme 6xxx, " 294 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 295 "and Pentium DC", 296 [0x15] = "EP80579 Integrated Processor", 297 [0x16] = "Celeron (45nm)", 298 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 299 "Core 2 Quad 8xxx and 9xxx", 300 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 301 "(Nehalem)", 302 [0x1c] = "45nm Atom Family", 303 [0x1d] = "XeonMP 74xx (Nehalem)", 304 [0x1e] = "Core i7 and i5", 305 [0x1f] = "Core i7 and i5", 306 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 307 [0x26] = "Atom Family", 308 [0x27] = "Atom Family", 309 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 310 "i3 2xxx", 311 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 312 [0x2d] = "Xeon E5 Sandy Bridge family, " 313 "Core i7-39xx Extreme", 314 [0x2e] = "Xeon 75xx & 65xx", 315 [0x2f] = "Xeon E7 family", 316 [0x35] = "Atom Family", 317 [0x36] = "Atom S1000", 318 [0x37] = "Atom E3000, Z3[67]00", 319 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 320 "Ivy Bridge", 321 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 322 "(Haswell)", 323 [0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)", 324 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 325 "Core i7-49xx Extreme", 326 [0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), " 327 "Core i7-59xx Extreme", 328 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 329 "(Haswell)", 330 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 331 "(Haswell)", 332 [0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)", 333 [0x4a] = "Atom Z3400", 334 [0x4c] = "Atom X[57]-Z8000 (Airmont)", 335 [0x4d] = "Atom C2000", 336 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 337 [0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme", 338 [0x55] = "Xeon Scalable (Skylake, Cascade Lake, Copper Lake)", 339 [0x56] = "Xeon D-1500 (Broadwell)", 340 [0x57] = "Xeon Phi [357]200 (Knights Landing)", 341 [0x5a] = "Atom E3500", 342 [0x5c] = "Atom (Goldmont)", 343 [0x5d] = "Atom X3-C3000 (Silvermont)", 344 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 345 [0x5f] = "Atom (Goldmont, Denverton)", 346 [0x66] = "8th gen Core i3 (Cannon Lake)", 347 [0x6a] = "Future Xeon (Ice Lake)", 348 [0x6c] = "Future Xeon (Ice Lake)", 349 [0x7a] = "Atom (Goldmont Plus)", 350 [0x7d] = "10th gen Core (Ice Lake)", 351 [0x7e] = "10th gen Core (Ice Lake)", 352 [0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)", 353 [0x86] = "Atom (Tremont)", 354 [0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 355 [0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 356 [0xa5] = "10th gen Core (Comet Lake)", 357 [0xa6] = "10th gen Core (Comet Lake)", 358 }, 359 "Pentium Pro, II or III", /* Default */ 360 NULL, 361 intel_family_new_probe, 362 intel_cpu_cacheinfo, 363 }, 364 /* Family > 6 */ 365 { 366 CPUCLASS_686, 367 { 368 0, 0, 0, 0, 0, 0, 0, 0, 369 0, 0, 0, 0, 0, 0, 0, 0, 370 }, 371 "Pentium 4", /* Default */ 372 NULL, 373 intel_family_new_probe, 374 intel_cpu_cacheinfo, 375 } } 376 }, 377 { 378 "AuthenticAMD", 379 CPUVENDOR_AMD, 380 "AMD", 381 /* Family 4 */ 382 { { 383 CPUCLASS_486, 384 { 385 0, 0, 0, "Am486DX2 W/T", 386 0, 0, 0, "Am486DX2 W/B", 387 "Am486DX4 W/T or Am5x86 W/T 150", 388 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 389 0, 0, "Am5x86 W/T 133/160", 390 "Am5x86 W/B 133/160", 391 }, 392 "Am486 or Am5x86", /* Default */ 393 NULL, 394 NULL, 395 NULL, 396 }, 397 /* Family 5 */ 398 { 399 CPUCLASS_586, 400 { 401 "K5", "K5", "K5", "K5", 0, 0, "K6", 402 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 403 "K6-2+/III+", 0, 0, 404 }, 405 "K5 or K6", /* Default */ 406 amd_family5_setup, 407 NULL, 408 amd_cpu_cacheinfo, 409 }, 410 /* Family 6 */ 411 { 412 CPUCLASS_686, 413 { 414 0, "Athlon Model 1", "Athlon Model 2", 415 "Duron", "Athlon Model 4 (Thunderbird)", 416 0, "Athlon", "Duron", "Athlon", 0, 417 "Athlon", 0, 0, 0, 0, 0, 418 }, 419 "K7 (Athlon)", /* Default */ 420 NULL, 421 amd_family6_probe, 422 amd_cpu_cacheinfo, 423 }, 424 /* Family > 6 */ 425 { 426 CPUCLASS_686, 427 { 428 0, 0, 0, 0, 0, 0, 0, 0, 429 0, 0, 0, 0, 0, 0, 0, 0, 430 }, 431 "Unknown K8 (Athlon)", /* Default */ 432 NULL, 433 amd_family6_probe, 434 amd_cpu_cacheinfo, 435 } } 436 }, 437 { 438 "CyrixInstead", 439 CPUVENDOR_CYRIX, 440 "Cyrix", 441 /* Family 4 */ 442 { { 443 CPUCLASS_486, 444 { 445 0, 0, 0, 446 "MediaGX", 447 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 448 }, 449 "486", /* Default */ 450 cyrix6x86_cpu_setup, /* XXX ?? */ 451 NULL, 452 NULL, 453 }, 454 /* Family 5 */ 455 { 456 CPUCLASS_586, 457 { 458 0, 0, "6x86", 0, 459 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 460 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 461 }, 462 "6x86", /* Default */ 463 cyrix6x86_cpu_setup, 464 NULL, 465 NULL, 466 }, 467 /* Family 6 */ 468 { 469 CPUCLASS_686, 470 { 471 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 472 0, 0, 0, 0, 0, 0, 0, 0, 473 }, 474 "6x86MX", /* Default */ 475 cyrix6x86_cpu_setup, 476 NULL, 477 NULL, 478 }, 479 /* Family > 6 */ 480 { 481 CPUCLASS_686, 482 { 483 0, 0, 0, 0, 0, 0, 0, 0, 484 0, 0, 0, 0, 0, 0, 0, 0, 485 }, 486 "Unknown 6x86MX", /* Default */ 487 NULL, 488 NULL, 489 NULL, 490 } } 491 }, 492 { /* MediaGX is now owned by National Semiconductor */ 493 "Geode by NSC", 494 CPUVENDOR_CYRIX, /* XXX */ 495 "National Semiconductor", 496 /* Family 4, NSC never had any of these */ 497 { { 498 CPUCLASS_486, 499 { 500 0, 0, 0, 0, 0, 0, 0, 0, 501 0, 0, 0, 0, 0, 0, 0, 0, 502 }, 503 "486 compatible", /* Default */ 504 NULL, 505 NULL, 506 NULL, 507 }, 508 /* Family 5: Geode family, formerly MediaGX */ 509 { 510 CPUCLASS_586, 511 { 512 0, 0, 0, 0, 513 "Geode GX1", 514 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 515 }, 516 "Geode", /* Default */ 517 cyrix6x86_cpu_setup, 518 NULL, 519 amd_cpu_cacheinfo, 520 }, 521 /* Family 6, not yet available from NSC */ 522 { 523 CPUCLASS_686, 524 { 525 0, 0, 0, 0, 0, 0, 0, 0, 526 0, 0, 0, 0, 0, 0, 0, 0, 527 }, 528 "Pentium Pro compatible", /* Default */ 529 NULL, 530 NULL, 531 NULL, 532 }, 533 /* Family > 6, not yet available from NSC */ 534 { 535 CPUCLASS_686, 536 { 537 0, 0, 0, 0, 0, 0, 0, 0, 538 0, 0, 0, 0, 0, 0, 0, 0, 539 }, 540 "Pentium Pro compatible", /* Default */ 541 NULL, 542 NULL, 543 NULL, 544 } } 545 }, 546 { 547 "CentaurHauls", 548 CPUVENDOR_IDT, 549 "IDT", 550 /* Family 4, IDT never had any of these */ 551 { { 552 CPUCLASS_486, 553 { 554 0, 0, 0, 0, 0, 0, 0, 0, 555 0, 0, 0, 0, 0, 0, 0, 0, 556 }, 557 "486 compatible", /* Default */ 558 NULL, 559 NULL, 560 NULL, 561 }, 562 /* Family 5 */ 563 { 564 CPUCLASS_586, 565 { 566 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 567 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 568 }, 569 "WinChip", /* Default */ 570 winchip_cpu_setup, 571 NULL, 572 NULL, 573 }, 574 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 575 { 576 CPUCLASS_686, 577 { 578 0, 0, 0, 0, 0, 0, "C3 Samuel", 579 "C3 Samuel 2/Ezra", "C3 Ezra-T", 580 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 581 0, "VIA Nano", 582 }, 583 "Unknown VIA/IDT", /* Default */ 584 NULL, 585 via_cpu_probe, 586 via_cpu_cacheinfo, 587 }, 588 /* Family > 6, not yet available from VIA */ 589 { 590 CPUCLASS_686, 591 { 592 0, 0, 0, 0, 0, 0, 0, 0, 593 0, 0, 0, 0, 0, 0, 0, 0, 594 }, 595 "Pentium Pro compatible", /* Default */ 596 NULL, 597 NULL, 598 NULL, 599 } } 600 }, 601 { 602 "GenuineTMx86", 603 CPUVENDOR_TRANSMETA, 604 "Transmeta", 605 /* Family 4, Transmeta never had any of these */ 606 { { 607 CPUCLASS_486, 608 { 609 0, 0, 0, 0, 0, 0, 0, 0, 610 0, 0, 0, 0, 0, 0, 0, 0, 611 }, 612 "486 compatible", /* Default */ 613 NULL, 614 NULL, 615 NULL, 616 }, 617 /* Family 5 */ 618 { 619 CPUCLASS_586, 620 { 621 0, 0, 0, 0, 0, 0, 0, 0, 622 0, 0, 0, 0, 0, 0, 0, 0, 623 }, 624 "Crusoe", /* Default */ 625 NULL, 626 NULL, 627 transmeta_cpu_info, 628 }, 629 /* Family 6, not yet available from Transmeta */ 630 { 631 CPUCLASS_686, 632 { 633 0, 0, 0, 0, 0, 0, 0, 0, 634 0, 0, 0, 0, 0, 0, 0, 0, 635 }, 636 "Pentium Pro compatible", /* Default */ 637 NULL, 638 NULL, 639 NULL, 640 }, 641 /* Family > 6, not yet available from Transmeta */ 642 { 643 CPUCLASS_686, 644 { 645 0, 0, 0, 0, 0, 0, 0, 0, 646 0, 0, 0, 0, 0, 0, 0, 0, 647 }, 648 "Pentium Pro compatible", /* Default */ 649 NULL, 650 NULL, 651 NULL, 652 } } 653 } 654 }; 655 656 /* 657 * disable the TSC such that we don't use the TSC in microtime(9) 658 * because some CPUs got the implementation wrong. 659 */ 660 static void 661 disable_tsc(struct cpu_info *ci) 662 { 663 if (ci->ci_feat_val[0] & CPUID_TSC) { 664 ci->ci_feat_val[0] &= ~CPUID_TSC; 665 aprint_error("WARNING: broken TSC disabled\n"); 666 } 667 } 668 669 static void 670 amd_family5_setup(struct cpu_info *ci) 671 { 672 673 switch (ci->ci_model) { 674 case 0: /* AMD-K5 Model 0 */ 675 /* 676 * According to the AMD Processor Recognition App Note, 677 * the AMD-K5 Model 0 uses the wrong bit to indicate 678 * support for global PTEs, instead using bit 9 (APIC) 679 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 680 */ 681 if (ci->ci_feat_val[0] & CPUID_APIC) 682 ci->ci_feat_val[0] = 683 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 684 /* 685 * XXX But pmap_pg_g is already initialized -- need to kick 686 * XXX the pmap somehow. How does the MP branch do this? 687 */ 688 break; 689 } 690 } 691 692 static void 693 cyrix6x86_cpu_setup(struct cpu_info *ci) 694 { 695 696 /* 697 * Do not disable the TSC on the Geode GX, it's reported to 698 * work fine. 699 */ 700 if (ci->ci_signature != 0x552) 701 disable_tsc(ci); 702 } 703 704 static void 705 winchip_cpu_setup(struct cpu_info *ci) 706 { 707 switch (ci->ci_model) { 708 case 4: /* WinChip C6 */ 709 disable_tsc(ci); 710 } 711 } 712 713 714 static const char * 715 intel_family6_name(struct cpu_info *ci) 716 { 717 const char *ret = NULL; 718 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 719 720 if (ci->ci_model == 5) { 721 switch (l2cache) { 722 case 0: 723 case 128 * 1024: 724 ret = "Celeron (Covington)"; 725 break; 726 case 256 * 1024: 727 ret = "Mobile Pentium II (Dixon)"; 728 break; 729 case 512 * 1024: 730 ret = "Pentium II"; 731 break; 732 case 1 * 1024 * 1024: 733 case 2 * 1024 * 1024: 734 ret = "Pentium II Xeon"; 735 break; 736 } 737 } else if (ci->ci_model == 6) { 738 switch (l2cache) { 739 case 256 * 1024: 740 case 512 * 1024: 741 ret = "Mobile Pentium II"; 742 break; 743 } 744 } else if (ci->ci_model == 7) { 745 switch (l2cache) { 746 case 512 * 1024: 747 ret = "Pentium III"; 748 break; 749 case 1 * 1024 * 1024: 750 case 2 * 1024 * 1024: 751 ret = "Pentium III Xeon"; 752 break; 753 } 754 } else if (ci->ci_model >= 8) { 755 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 756 switch (ci->ci_brand_id) { 757 case 0x3: 758 if (ci->ci_signature == 0x6B1) 759 ret = "Celeron"; 760 break; 761 case 0x8: 762 if (ci->ci_signature >= 0xF13) 763 ret = "genuine processor"; 764 break; 765 case 0xB: 766 if (ci->ci_signature >= 0xF13) 767 ret = "Xeon MP"; 768 break; 769 case 0xE: 770 if (ci->ci_signature < 0xF13) 771 ret = "Xeon"; 772 break; 773 } 774 if (ret == NULL) 775 ret = i386_intel_brand[ci->ci_brand_id]; 776 } 777 } 778 779 return ret; 780 } 781 782 /* 783 * Identify AMD64 CPU names from cpuid. 784 * 785 * Based on: 786 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 787 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 788 * "Revision Guide for AMD NPT Family 0Fh Processors" 789 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 790 * and other miscellaneous reports. 791 * 792 * This is all rather pointless, these are cross 'brand' since the raw 793 * silicon is shared. 794 */ 795 static const char * 796 amd_amd64_name(struct cpu_info *ci) 797 { 798 static char family_str[32]; 799 800 /* Only called if family >= 15 */ 801 802 switch (ci->ci_family) { 803 case 15: 804 switch (ci->ci_model) { 805 case 0x21: /* rev JH-E1/E6 */ 806 case 0x41: /* rev JH-F2 */ 807 return "Dual-Core Opteron"; 808 case 0x23: /* rev JH-E6 (Toledo) */ 809 return "Dual-Core Opteron or Athlon 64 X2"; 810 case 0x43: /* rev JH-F2 (Windsor) */ 811 return "Athlon 64 FX or Athlon 64 X2"; 812 case 0x24: /* rev SH-E5 (Lancaster?) */ 813 return "Mobile Athlon 64 or Turion 64"; 814 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 815 return "Opteron or Athlon 64 FX"; 816 case 0x15: /* rev SH-D0 */ 817 case 0x25: /* rev SH-E4 */ 818 return "Opteron"; 819 case 0x27: /* rev DH-E4, SH-E4 */ 820 return "Athlon 64 or Athlon 64 FX or Opteron"; 821 case 0x48: /* rev BH-F2 */ 822 return "Turion 64 X2"; 823 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 824 case 0x07: /* rev SH-CG (ClawHammer) */ 825 case 0x0b: /* rev CH-CG */ 826 case 0x14: /* rev SH-D0 */ 827 case 0x17: /* rev SH-D0 */ 828 case 0x1b: /* rev CH-D0 */ 829 return "Athlon 64"; 830 case 0x2b: /* rev BH-E4 (Manchester) */ 831 case 0x4b: /* rev BH-F2 (Windsor) */ 832 return "Athlon 64 X2"; 833 case 0x6b: /* rev BH-G1 (Brisbane) */ 834 return "Athlon X2 or Athlon 64 X2"; 835 case 0x08: /* rev CH-CG */ 836 case 0x0c: /* rev DH-CG (Newcastle) */ 837 case 0x0e: /* rev DH-CG (Newcastle?) */ 838 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 839 case 0x18: /* rev CH-D0 */ 840 case 0x1c: /* rev DH-D0 (Winchester) */ 841 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 842 case 0x2c: /* rev DH-E3/E6 */ 843 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 844 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 845 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 846 case 0x6f: /* rev DH-G1 */ 847 return "Athlon 64 or Sempron"; 848 default: 849 break; 850 } 851 return "Unknown AMD64 CPU"; 852 853 #if 0 854 case 16: 855 return "Family 10h"; 856 case 17: 857 return "Family 11h"; 858 case 18: 859 return "Family 12h"; 860 case 19: 861 return "Family 14h"; 862 case 20: 863 return "Family 15h"; 864 #endif 865 866 default: 867 break; 868 } 869 870 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 871 return family_str; 872 } 873 874 static void 875 intel_family_new_probe(struct cpu_info *ci) 876 { 877 uint32_t descs[4]; 878 879 x86_cpuid(0x80000000, descs); 880 881 /* 882 * Determine extended feature flags. 883 */ 884 if (descs[0] >= 0x80000001) { 885 x86_cpuid(0x80000001, descs); 886 ci->ci_feat_val[2] |= descs[3]; 887 ci->ci_feat_val[3] |= descs[2]; 888 } 889 } 890 891 static void 892 via_cpu_probe(struct cpu_info *ci) 893 { 894 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 895 u_int descs[4]; 896 u_int lfunc; 897 898 /* 899 * Determine the largest extended function value. 900 */ 901 x86_cpuid(0x80000000, descs); 902 lfunc = descs[0]; 903 904 /* 905 * Determine the extended feature flags. 906 */ 907 if (lfunc >= 0x80000001) { 908 x86_cpuid(0x80000001, descs); 909 ci->ci_feat_val[2] |= descs[3]; 910 } 911 912 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 913 return; 914 915 /* Nehemiah or Esther */ 916 x86_cpuid(0xc0000000, descs); 917 lfunc = descs[0]; 918 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 919 return; 920 921 x86_cpuid(0xc0000001, descs); 922 lfunc = descs[3]; 923 ci->ci_feat_val[4] = lfunc; 924 } 925 926 static void 927 amd_family6_probe(struct cpu_info *ci) 928 { 929 uint32_t descs[4]; 930 char *p; 931 size_t i; 932 933 x86_cpuid(0x80000000, descs); 934 935 /* 936 * Determine the extended feature flags. 937 */ 938 if (descs[0] >= 0x80000001) { 939 x86_cpuid(0x80000001, descs); 940 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 941 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 942 } 943 944 if (*cpu_brand_string == '\0') 945 return; 946 947 for (i = 1; i < __arraycount(amd_brand); i++) 948 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 949 ci->ci_brand_id = i; 950 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 951 break; 952 } 953 } 954 955 /* 956 * Get cache info from one of the following: 957 * Intel Deterministic Cache Parameter Leaf (0x04) 958 * AMD Cache Topology Information Leaf (0x8000001d) 959 */ 960 static void 961 cpu_dcp_cacheinfo(struct cpu_info *ci, uint32_t leaf) 962 { 963 u_int descs[4]; 964 int type, level, ways, partitions, linesize, sets, totalsize; 965 int caitype = -1; 966 int i; 967 968 for (i = 0; ; i++) { 969 x86_cpuid2(leaf, i, descs); 970 type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE); 971 if (type == CPUID_DCP_CACHETYPE_N) 972 break; 973 level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL); 974 switch (level) { 975 case 1: 976 if (type == CPUID_DCP_CACHETYPE_I) 977 caitype = CAI_ICACHE; 978 else if (type == CPUID_DCP_CACHETYPE_D) 979 caitype = CAI_DCACHE; 980 else 981 caitype = -1; 982 break; 983 case 2: 984 if (type == CPUID_DCP_CACHETYPE_U) 985 caitype = CAI_L2CACHE; 986 else 987 caitype = -1; 988 break; 989 case 3: 990 if (type == CPUID_DCP_CACHETYPE_U) 991 caitype = CAI_L3CACHE; 992 else 993 caitype = -1; 994 break; 995 default: 996 caitype = -1; 997 break; 998 } 999 if (caitype == -1) { 1000 aprint_error_dev(ci->ci_dev, 1001 "error: unknown cache level&type (%d & %d)\n", 1002 level, type); 1003 continue; 1004 } 1005 ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1; 1006 partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS) 1007 + 1; 1008 linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE) 1009 + 1; 1010 sets = descs[2] + 1; 1011 totalsize = ways * partitions * linesize * sets; 1012 ci->ci_cinfo[caitype].cai_totalsize = totalsize; 1013 ci->ci_cinfo[caitype].cai_associativity = ways; 1014 ci->ci_cinfo[caitype].cai_linesize = linesize; 1015 } 1016 } 1017 1018 static void 1019 intel_cpu_cacheinfo(struct cpu_info *ci) 1020 { 1021 const struct x86_cache_info *cai; 1022 u_int descs[4]; 1023 int iterations, i, j; 1024 int type, level, ways, linesize, sets; 1025 int caitype = -1; 1026 uint8_t desc; 1027 1028 /* Return if the cpu is old pre-cpuid instruction cpu */ 1029 if (ci->ci_cpu_type >= 0) 1030 return; 1031 1032 if (ci->ci_max_cpuid < 2) 1033 return; 1034 1035 /* 1036 * Parse the cache info from `cpuid leaf 2', if we have it. 1037 * XXX This is kinda ugly, but hey, so is the architecture... 1038 */ 1039 x86_cpuid(2, descs); 1040 iterations = descs[0] & 0xff; 1041 while (iterations-- > 0) { 1042 for (i = 0; i < 4; i++) { 1043 if (descs[i] & 0x80000000) 1044 continue; 1045 for (j = 0; j < 4; j++) { 1046 /* 1047 * The least significant byte in EAX 1048 * ((desc[0] >> 0) & 0xff) is always 0x01 and 1049 * it should be ignored. 1050 */ 1051 if (i == 0 && j == 0) 1052 continue; 1053 desc = (descs[i] >> (j * 8)) & 0xff; 1054 if (desc == 0) 1055 continue; 1056 cai = cache_info_lookup(intel_cpuid_cache_info, 1057 desc); 1058 if (cai != NULL) 1059 ci->ci_cinfo[cai->cai_index] = *cai; 1060 else if ((verbose != 0) && (desc != 0xff) 1061 && (desc != 0xfe)) 1062 aprint_error_dev(ci->ci_dev, "error:" 1063 " Unknown cacheinfo desc %02x\n", 1064 desc); 1065 } 1066 } 1067 x86_cpuid(2, descs); 1068 } 1069 1070 if (ci->ci_max_cpuid < 4) 1071 return; 1072 1073 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1074 cpu_dcp_cacheinfo(ci, 4); 1075 1076 if (ci->ci_max_cpuid < 0x18) 1077 return; 1078 /* Parse the TLB info from `cpuid leaf 18H', if we have it. */ 1079 x86_cpuid(0x18, descs); 1080 iterations = descs[0]; 1081 for (i = 0; i <= iterations; i++) { 1082 uint32_t pgsize; 1083 bool full; 1084 1085 x86_cpuid2(0x18, i, descs); 1086 type = __SHIFTOUT(descs[3], CPUID_DATP_TCTYPE); 1087 if (type == CPUID_DATP_TCTYPE_N) 1088 continue; 1089 level = __SHIFTOUT(descs[3], CPUID_DATP_TCLEVEL); 1090 pgsize = __SHIFTOUT(descs[1], CPUID_DATP_PGSIZE); 1091 switch (level) { 1092 case 1: 1093 if (type == CPUID_DATP_TCTYPE_I) { 1094 switch (pgsize) { 1095 case CPUID_DATP_PGSIZE_4KB: 1096 caitype = CAI_ITLB; 1097 break; 1098 case CPUID_DATP_PGSIZE_2MB 1099 | CPUID_DATP_PGSIZE_4MB: 1100 caitype = CAI_ITLB2; 1101 break; 1102 case CPUID_DATP_PGSIZE_1GB: 1103 caitype = CAI_L1_1GBITLB; 1104 break; 1105 default: 1106 aprint_error_dev(ci->ci_dev, 1107 "error: unknown ITLB size (%d)\n", 1108 pgsize); 1109 caitype = CAI_ITLB; 1110 break; 1111 } 1112 } else if (type == CPUID_DATP_TCTYPE_D) { 1113 switch (pgsize) { 1114 case CPUID_DATP_PGSIZE_4KB: 1115 caitype = CAI_DTLB; 1116 break; 1117 case CPUID_DATP_PGSIZE_2MB 1118 | CPUID_DATP_PGSIZE_4MB: 1119 caitype = CAI_DTLB2; 1120 break; 1121 case CPUID_DATP_PGSIZE_1GB: 1122 caitype = CAI_L1_1GBDTLB; 1123 break; 1124 default: 1125 aprint_error_dev(ci->ci_dev, 1126 "error: unknown DTLB size (%d)\n", 1127 pgsize); 1128 caitype = CAI_DTLB; 1129 break; 1130 } 1131 } else 1132 caitype = -1; 1133 break; 1134 case 2: 1135 if (type == CPUID_DATP_TCTYPE_I) 1136 caitype = CAI_L2_ITLB; 1137 else if (type == CPUID_DATP_TCTYPE_D) 1138 caitype = CAI_L2_DTLB; 1139 else if (type == CPUID_DATP_TCTYPE_U) { 1140 switch (pgsize) { 1141 case CPUID_DATP_PGSIZE_4KB: 1142 caitype = CAI_L2_STLB; 1143 break; 1144 case CPUID_DATP_PGSIZE_4KB 1145 | CPUID_DATP_PGSIZE_2MB: 1146 caitype = CAI_L2_STLB2; 1147 break; 1148 case CPUID_DATP_PGSIZE_2MB 1149 | CPUID_DATP_PGSIZE_4MB: 1150 caitype = CAI_L2_STLB3; 1151 break; 1152 default: 1153 aprint_error_dev(ci->ci_dev, 1154 "error: unknown L2 STLB size (%d)\n", 1155 pgsize); 1156 caitype = CAI_DTLB; 1157 break; 1158 } 1159 } else 1160 caitype = -1; 1161 break; 1162 case 3: 1163 /* XXX need work for L3 TLB */ 1164 caitype = CAI_L3CACHE; 1165 break; 1166 default: 1167 caitype = -1; 1168 break; 1169 } 1170 if (caitype == -1) { 1171 aprint_error_dev(ci->ci_dev, 1172 "error: unknown TLB level&type (%d & %d)\n", 1173 level, type); 1174 continue; 1175 } 1176 switch (pgsize) { 1177 case CPUID_DATP_PGSIZE_4KB: 1178 linesize = 4 * 1024; 1179 break; 1180 case CPUID_DATP_PGSIZE_2MB: 1181 linesize = 2 * 1024 * 1024; 1182 break; 1183 case CPUID_DATP_PGSIZE_4MB: 1184 linesize = 4 * 1024 * 1024; 1185 break; 1186 case CPUID_DATP_PGSIZE_1GB: 1187 linesize = 1024 * 1024 * 1024; 1188 break; 1189 case CPUID_DATP_PGSIZE_2MB | CPUID_DATP_PGSIZE_4MB: 1190 aprint_error_dev(ci->ci_dev, 1191 "WARINING: Currently 2M/4M info can't print correctly\n"); 1192 linesize = 4 * 1024 * 1024; 1193 break; 1194 default: 1195 aprint_error_dev(ci->ci_dev, 1196 "error: Unknown size combination\n"); 1197 linesize = 4 * 1024; 1198 break; 1199 } 1200 ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS); 1201 sets = descs[2]; 1202 full = descs[3] & CPUID_DATP_FULLASSOC; 1203 ci->ci_cinfo[caitype].cai_totalsize 1204 = ways * sets; /* entries */ 1205 ci->ci_cinfo[caitype].cai_associativity 1206 = full ? 0xff : ways; 1207 ci->ci_cinfo[caitype].cai_linesize = linesize; /* pg size */ 1208 } 1209 } 1210 1211 static const struct x86_cache_info amd_cpuid_l2l3cache_assoc_info[] = 1212 AMD_L2L3CACHE_INFO; 1213 1214 static void 1215 amd_cpu_cacheinfo(struct cpu_info *ci) 1216 { 1217 const struct x86_cache_info *cp; 1218 struct x86_cache_info *cai; 1219 u_int descs[4]; 1220 u_int lfunc; 1221 1222 /* K5 model 0 has none of this info. */ 1223 if (ci->ci_family == 5 && ci->ci_model == 0) 1224 return; 1225 1226 /* Determine the largest extended function value. */ 1227 x86_cpuid(0x80000000, descs); 1228 lfunc = descs[0]; 1229 1230 if (lfunc < 0x80000005) 1231 return; 1232 1233 /* Determine L1 cache/TLB info. */ 1234 x86_cpuid(0x80000005, descs); 1235 1236 /* K6-III and higher have large page TLBs. */ 1237 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1238 cai = &ci->ci_cinfo[CAI_ITLB2]; 1239 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1240 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1241 cai->cai_linesize = largepagesize; 1242 1243 cai = &ci->ci_cinfo[CAI_DTLB2]; 1244 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1245 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1246 cai->cai_linesize = largepagesize; 1247 } 1248 1249 cai = &ci->ci_cinfo[CAI_ITLB]; 1250 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1251 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1252 cai->cai_linesize = (4 * 1024); 1253 1254 cai = &ci->ci_cinfo[CAI_DTLB]; 1255 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1256 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1257 cai->cai_linesize = (4 * 1024); 1258 1259 cai = &ci->ci_cinfo[CAI_DCACHE]; 1260 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1261 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1262 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1263 1264 cai = &ci->ci_cinfo[CAI_ICACHE]; 1265 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1266 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1267 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1268 1269 if (lfunc < 0x80000006) 1270 return; 1271 1272 /* Determine L2 cache/TLB info. */ 1273 x86_cpuid(0x80000006, descs); 1274 1275 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1276 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1277 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1278 cai->cai_linesize = (4 * 1024); 1279 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1280 cai->cai_associativity); 1281 if (cp != NULL) 1282 cai->cai_associativity = cp->cai_associativity; 1283 else 1284 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1285 1286 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1287 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1288 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1289 cai->cai_linesize = largepagesize; 1290 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1291 cai->cai_associativity); 1292 if (cp != NULL) 1293 cai->cai_associativity = cp->cai_associativity; 1294 else 1295 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1296 1297 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1298 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1299 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1300 cai->cai_linesize = (4 * 1024); 1301 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1302 cai->cai_associativity); 1303 if (cp != NULL) 1304 cai->cai_associativity = cp->cai_associativity; 1305 else 1306 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1307 1308 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1309 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1310 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1311 cai->cai_linesize = largepagesize; 1312 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1313 cai->cai_associativity); 1314 if (cp != NULL) 1315 cai->cai_associativity = cp->cai_associativity; 1316 else 1317 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1318 1319 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1320 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1321 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1322 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1323 1324 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1325 cai->cai_associativity); 1326 if (cp != NULL) 1327 cai->cai_associativity = cp->cai_associativity; 1328 else 1329 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1330 1331 /* Determine L3 cache info on AMD Family 10h and newer processors */ 1332 if (ci->ci_family >= 0x10) { 1333 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1334 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1335 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1336 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1337 1338 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1339 cai->cai_associativity); 1340 if (cp != NULL) 1341 cai->cai_associativity = cp->cai_associativity; 1342 else 1343 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1344 } 1345 1346 if (lfunc < 0x80000019) 1347 return; 1348 1349 /* Determine 1GB TLB info. */ 1350 x86_cpuid(0x80000019, descs); 1351 1352 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1353 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1354 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1355 cai->cai_linesize = (1024 * 1024 * 1024); 1356 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1357 cai->cai_associativity); 1358 if (cp != NULL) 1359 cai->cai_associativity = cp->cai_associativity; 1360 else 1361 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1362 1363 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1364 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1365 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1366 cai->cai_linesize = (1024 * 1024 * 1024); 1367 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1368 cai->cai_associativity); 1369 if (cp != NULL) 1370 cai->cai_associativity = cp->cai_associativity; 1371 else 1372 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1373 1374 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1375 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1376 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1377 cai->cai_linesize = (1024 * 1024 * 1024); 1378 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1379 cai->cai_associativity); 1380 if (cp != NULL) 1381 cai->cai_associativity = cp->cai_associativity; 1382 else 1383 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1384 1385 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1386 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1387 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1388 cai->cai_linesize = (1024 * 1024 * 1024); 1389 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1390 cai->cai_associativity); 1391 if (cp != NULL) 1392 cai->cai_associativity = cp->cai_associativity; 1393 else 1394 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1395 1396 if (lfunc < 0x8000001d) 1397 return; 1398 1399 if (ci->ci_feat_val[3] & CPUID_TOPOEXT) 1400 cpu_dcp_cacheinfo(ci, 0x8000001d); 1401 } 1402 1403 static void 1404 via_cpu_cacheinfo(struct cpu_info *ci) 1405 { 1406 struct x86_cache_info *cai; 1407 int stepping; 1408 u_int descs[4]; 1409 u_int lfunc; 1410 1411 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1412 1413 /* 1414 * Determine the largest extended function value. 1415 */ 1416 x86_cpuid(0x80000000, descs); 1417 lfunc = descs[0]; 1418 1419 /* 1420 * Determine L1 cache/TLB info. 1421 */ 1422 if (lfunc < 0x80000005) { 1423 /* No L1 cache info available. */ 1424 return; 1425 } 1426 1427 x86_cpuid(0x80000005, descs); 1428 1429 cai = &ci->ci_cinfo[CAI_ITLB]; 1430 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1431 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1432 cai->cai_linesize = (4 * 1024); 1433 1434 cai = &ci->ci_cinfo[CAI_DTLB]; 1435 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1436 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1437 cai->cai_linesize = (4 * 1024); 1438 1439 cai = &ci->ci_cinfo[CAI_DCACHE]; 1440 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1441 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1442 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1443 if (ci->ci_model == 9 && stepping == 8) { 1444 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1445 cai->cai_associativity = 2; 1446 } 1447 1448 cai = &ci->ci_cinfo[CAI_ICACHE]; 1449 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1450 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1451 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1452 if (ci->ci_model == 9 && stepping == 8) { 1453 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1454 cai->cai_associativity = 2; 1455 } 1456 1457 /* 1458 * Determine L2 cache/TLB info. 1459 */ 1460 if (lfunc < 0x80000006) { 1461 /* No L2 cache info available. */ 1462 return; 1463 } 1464 1465 x86_cpuid(0x80000006, descs); 1466 1467 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1468 if (ci->ci_model >= 9) { 1469 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1470 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1471 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1472 } else { 1473 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1474 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1475 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1476 } 1477 } 1478 1479 static void 1480 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1481 { 1482 u_int descs[4]; 1483 1484 x86_cpuid(0x80860007, descs); 1485 *frequency = descs[0]; 1486 *voltage = descs[1]; 1487 *percentage = descs[2]; 1488 } 1489 1490 static void 1491 transmeta_cpu_info(struct cpu_info *ci) 1492 { 1493 u_int descs[4], nreg; 1494 u_int frequency, voltage, percentage; 1495 1496 x86_cpuid(0x80860000, descs); 1497 nreg = descs[0]; 1498 if (nreg >= 0x80860001) { 1499 x86_cpuid(0x80860001, descs); 1500 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1501 (descs[1] >> 24) & 0xff, 1502 (descs[1] >> 16) & 0xff, 1503 (descs[1] >> 8) & 0xff, 1504 descs[1] & 0xff); 1505 } 1506 if (nreg >= 0x80860002) { 1507 x86_cpuid(0x80860002, descs); 1508 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1509 (descs[1] >> 24) & 0xff, 1510 (descs[1] >> 16) & 0xff, 1511 (descs[1] >> 8) & 0xff, 1512 descs[1] & 0xff, 1513 descs[2]); 1514 } 1515 if (nreg >= 0x80860006) { 1516 union { 1517 char text[65]; 1518 u_int descs[4][4]; 1519 } info; 1520 int i; 1521 1522 for (i=0; i<4; i++) { 1523 x86_cpuid(0x80860003 + i, info.descs[i]); 1524 } 1525 info.text[64] = '\0'; 1526 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1527 } 1528 1529 if (nreg >= 0x80860007) { 1530 tmx86_get_longrun_status(&frequency, 1531 &voltage, &percentage); 1532 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1533 frequency, voltage, percentage); 1534 } 1535 } 1536 1537 static void 1538 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1539 { 1540 u_int descs[4]; 1541 int i; 1542 uint32_t brand[12]; 1543 1544 memset(ci, 0, sizeof(*ci)); 1545 ci->ci_dev = cpuname; 1546 1547 ci->ci_cpu_type = x86_identify(); 1548 if (ci->ci_cpu_type >= 0) { 1549 /* Old pre-cpuid instruction cpu */ 1550 ci->ci_max_cpuid = -1; 1551 return; 1552 } 1553 1554 /* 1555 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1556 * function. 1557 */ 1558 1559 /* 1560 * Fn0000_0000: 1561 * - Save cpuid max level. 1562 * - Save vendor string. 1563 */ 1564 x86_cpuid(0, descs); 1565 ci->ci_max_cpuid = descs[0]; 1566 /* Save vendor string */ 1567 ci->ci_vendor[0] = descs[1]; 1568 ci->ci_vendor[2] = descs[2]; 1569 ci->ci_vendor[1] = descs[3]; 1570 ci->ci_vendor[3] = 0; 1571 1572 /* 1573 * Fn8000_0000: 1574 * - Get cpuid extended function's max level. 1575 */ 1576 x86_cpuid(0x80000000, descs); 1577 if (descs[0] >= 0x80000000) 1578 ci->ci_max_ext_cpuid = descs[0]; 1579 else { 1580 /* Set lower value than 0x80000000 */ 1581 ci->ci_max_ext_cpuid = 0; 1582 } 1583 1584 /* 1585 * Fn8000_000[2-4]: 1586 * - Save brand string. 1587 */ 1588 if (ci->ci_max_ext_cpuid >= 0x80000004) { 1589 x86_cpuid(0x80000002, brand); 1590 x86_cpuid(0x80000003, brand + 4); 1591 x86_cpuid(0x80000004, brand + 8); 1592 for (i = 0; i < 48; i++) 1593 if (((char *) brand)[i] != ' ') 1594 break; 1595 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1596 } 1597 1598 if (ci->ci_max_cpuid < 1) 1599 return; 1600 1601 /* 1602 * Fn0000_0001: 1603 * - Get CPU family, model and stepping (from eax). 1604 * - Initial local APIC ID and brand ID (from ebx) 1605 * - CPUID2 (from ecx) 1606 * - CPUID (from edx) 1607 */ 1608 x86_cpuid(1, descs); 1609 ci->ci_signature = descs[0]; 1610 1611 /* Extract full family/model values */ 1612 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1613 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1614 1615 /* Brand is low order 8 bits of ebx */ 1616 ci->ci_brand_id = __SHIFTOUT(descs[1], CPUID_BRAND_INDEX); 1617 /* Initial local APIC ID */ 1618 ci->ci_initapicid = __SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID); 1619 1620 ci->ci_feat_val[1] = descs[2]; 1621 ci->ci_feat_val[0] = descs[3]; 1622 1623 if (ci->ci_max_cpuid < 3) 1624 return; 1625 1626 /* 1627 * If the processor serial number misfeature is present and supported, 1628 * extract it here. 1629 */ 1630 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1631 ci->ci_cpu_serial[0] = ci->ci_signature; 1632 x86_cpuid(3, descs); 1633 ci->ci_cpu_serial[2] = descs[2]; 1634 ci->ci_cpu_serial[1] = descs[3]; 1635 } 1636 1637 if (ci->ci_max_cpuid < 0x7) 1638 return; 1639 1640 x86_cpuid(7, descs); 1641 ci->ci_feat_val[5] = descs[1]; 1642 ci->ci_feat_val[6] = descs[2]; 1643 ci->ci_feat_val[7] = descs[3]; 1644 1645 if (ci->ci_max_cpuid < 0xd) 1646 return; 1647 1648 /* Get support XCR0 bits */ 1649 x86_cpuid2(0xd, 0, descs); 1650 ci->ci_feat_val[8] = descs[0]; /* Actually 64 bits */ 1651 ci->ci_cur_xsave = descs[1]; 1652 ci->ci_max_xsave = descs[2]; 1653 1654 /* Additional flags (eg xsaveopt support) */ 1655 x86_cpuid2(0xd, 1, descs); 1656 ci->ci_feat_val[9] = descs[0]; /* Actually 64 bits */ 1657 } 1658 1659 static void 1660 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1661 { 1662 uint32_t descs[4]; 1663 char hv_sig[13]; 1664 char *p; 1665 const char *hv_name; 1666 int i; 1667 1668 /* 1669 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1670 * http://lkml.org/lkml/2008/10/1/246 1671 * 1672 * KB1009458: Mechanisms to determine if software is running in 1673 * a VMware virtual machine 1674 * http://kb.vmware.com/kb/1009458 1675 */ 1676 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1677 x86_cpuid(0x40000000, descs); 1678 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1679 memcpy(p, &descs[i], sizeof(descs[i])); 1680 *p = '\0'; 1681 /* 1682 * HV vendor ID string 1683 * ------------+-------------- 1684 * HAXM "HAXMHAXMHAXM" 1685 * KVM "KVMKVMKVM" 1686 * Microsoft "Microsoft Hv" 1687 * QEMU(TCG) "TCGTCGTCGTCG" 1688 * VMware "VMwareVMware" 1689 * Xen "XenVMMXenVMM" 1690 * NetBSD "___ NVMM ___" 1691 */ 1692 if (strncmp(hv_sig, "HAXMHAXMHAXM", 12) == 0) 1693 hv_name = "HAXM"; 1694 else if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1695 hv_name = "KVM"; 1696 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1697 hv_name = "Hyper-V"; 1698 else if (strncmp(hv_sig, "TCGTCGTCGTCG", 12) == 0) 1699 hv_name = "QEMU(TCG)"; 1700 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1701 hv_name = "VMware"; 1702 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1703 hv_name = "Xen"; 1704 else if (strncmp(hv_sig, "___ NVMM ___", 12) == 0) 1705 hv_name = "NVMM"; 1706 else 1707 hv_name = "unknown"; 1708 1709 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1710 } 1711 } 1712 1713 static void 1714 cpu_probe_features(struct cpu_info *ci) 1715 { 1716 const struct cpu_cpuid_nameclass *cpup = NULL; 1717 unsigned int i; 1718 1719 if (ci->ci_max_cpuid < 1) 1720 return; 1721 1722 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1723 if (!strncmp((char *)ci->ci_vendor, 1724 i386_cpuid_cpus[i].cpu_id, 12)) { 1725 cpup = &i386_cpuid_cpus[i]; 1726 break; 1727 } 1728 } 1729 1730 if (cpup == NULL) 1731 return; 1732 1733 i = ci->ci_family - CPU_MINFAMILY; 1734 1735 if (i >= __arraycount(cpup->cpu_family)) 1736 i = __arraycount(cpup->cpu_family) - 1; 1737 1738 if (cpup->cpu_family[i].cpu_probe == NULL) 1739 return; 1740 1741 (*cpup->cpu_family[i].cpu_probe)(ci); 1742 } 1743 1744 static void 1745 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1746 { 1747 char buf[32 * 16]; 1748 char *bp; 1749 1750 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1751 1752 if (val == 0 || fmt == NULL) 1753 return; 1754 1755 snprintb_m(buf, sizeof(buf), fmt, val, 1756 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1757 bp = buf; 1758 while (*bp != '\0') { 1759 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1760 bp += strlen(bp) + 1; 1761 } 1762 } 1763 1764 static void 1765 dump_descs(uint32_t leafstart, uint32_t leafend, const char *cpuname, 1766 const char *blockname) 1767 { 1768 uint32_t descs[4]; 1769 uint32_t leaf; 1770 1771 aprint_verbose("%s: highest %s info %08x\n", cpuname, blockname, 1772 leafend); 1773 1774 if (verbose) { 1775 for (leaf = leafstart; leaf <= leafend; leaf++) { 1776 x86_cpuid(leaf, descs); 1777 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1778 leaf, descs[0], descs[1], descs[2], descs[3]); 1779 } 1780 } 1781 } 1782 1783 static void 1784 identifycpu_cpuids_intel_0x04(struct cpu_info *ci) 1785 { 1786 u_int lp_max = 1; /* logical processors per package */ 1787 u_int smt_max; /* smt per core */ 1788 u_int core_max = 1; /* core per package */ 1789 u_int smt_bits, core_bits; 1790 uint32_t descs[4]; 1791 1792 /* 1793 * 253668.pdf 7.10.2 1794 */ 1795 1796 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1797 x86_cpuid(1, descs); 1798 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1799 } 1800 x86_cpuid2(4, 0, descs); 1801 core_max = __SHIFTOUT(descs[0], CPUID_DCP_CORE_P_PKG) + 1; 1802 1803 assert(lp_max >= core_max); 1804 smt_max = lp_max / core_max; 1805 smt_bits = ilog2(smt_max - 1) + 1; 1806 core_bits = ilog2(core_max - 1) + 1; 1807 1808 if (smt_bits + core_bits) 1809 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1810 1811 if (core_bits) 1812 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1813 __BITS(smt_bits, smt_bits + core_bits - 1)); 1814 1815 if (smt_bits) 1816 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1817 __BITS((int)0, (int)(smt_bits - 1))); 1818 } 1819 1820 static void 1821 identifycpu_cpuids_intel_0x0b(struct cpu_info *ci) 1822 { 1823 const char *cpuname = ci->ci_dev; 1824 u_int smt_bits, core_bits, core_shift = 0, pkg_shift = 0; 1825 uint32_t descs[4]; 1826 int i; 1827 1828 x86_cpuid(0x0b, descs); 1829 if (descs[1] == 0) { 1830 identifycpu_cpuids_intel_0x04(ci); 1831 return; 1832 } 1833 1834 for (i = 0; ; i++) { 1835 unsigned int shiftnum, lvltype; 1836 x86_cpuid2(0x0b, i, descs); 1837 1838 /* On invalid level, (EAX and) EBX return 0 */ 1839 if (descs[1] == 0) 1840 break; 1841 1842 shiftnum = __SHIFTOUT(descs[0], CPUID_TOP_SHIFTNUM); 1843 lvltype = __SHIFTOUT(descs[2], CPUID_TOP_LVLTYPE); 1844 switch (lvltype) { 1845 case CPUID_TOP_LVLTYPE_SMT: 1846 core_shift = shiftnum; 1847 break; 1848 case CPUID_TOP_LVLTYPE_CORE: 1849 pkg_shift = shiftnum; 1850 break; 1851 case CPUID_TOP_LVLTYPE_INVAL: 1852 aprint_verbose("%s: Invalid level type\n", cpuname); 1853 break; 1854 default: 1855 aprint_verbose("%s: Unknown level type(%d) \n", 1856 cpuname, lvltype); 1857 break; 1858 } 1859 } 1860 1861 assert(pkg_shift >= core_shift); 1862 smt_bits = core_shift; 1863 core_bits = pkg_shift - core_shift; 1864 1865 ci->ci_packageid = ci->ci_initapicid >> pkg_shift; 1866 1867 if (core_bits) 1868 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1869 __BITS(core_shift, pkg_shift - 1)); 1870 1871 if (smt_bits) 1872 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1873 __BITS((int)0, core_shift - 1)); 1874 } 1875 1876 static void 1877 identifycpu_cpuids_intel(struct cpu_info *ci) 1878 { 1879 const char *cpuname = ci->ci_dev; 1880 1881 if (ci->ci_max_cpuid >= 0x0b) 1882 identifycpu_cpuids_intel_0x0b(ci); 1883 else if (ci->ci_max_cpuid >= 4) 1884 identifycpu_cpuids_intel_0x04(ci); 1885 1886 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1887 ci->ci_packageid); 1888 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1889 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1890 } 1891 1892 static void 1893 identifycpu_cpuids_amd(struct cpu_info *ci) 1894 { 1895 const char *cpuname = ci->ci_dev; 1896 u_int lp_max, core_max; 1897 int n, cpu_family, apic_id, smt_bits, core_bits = 0; 1898 uint32_t descs[4]; 1899 1900 apic_id = ci->ci_initapicid; 1901 cpu_family = CPUID_TO_FAMILY(ci->ci_signature); 1902 1903 if (cpu_family < 0xf) 1904 return; 1905 1906 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1907 x86_cpuid(1, descs); 1908 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1909 1910 if (cpu_family >= 0x10 && ci->ci_max_ext_cpuid >= 0x8000008) { 1911 x86_cpuid(0x8000008, descs); 1912 core_max = (descs[2] & 0xff) + 1; 1913 n = (descs[2] >> 12) & 0x0f; 1914 if (n != 0) 1915 core_bits = n; 1916 } 1917 } else { 1918 lp_max = 1; 1919 } 1920 core_max = lp_max; 1921 1922 smt_bits = ilog2((lp_max / core_max) - 1) + 1; 1923 if (core_bits == 0) 1924 core_bits = ilog2(core_max - 1) + 1; 1925 1926 #if 0 /* MSRs need kernel mode */ 1927 if (cpu_family < 0x11) { 1928 const uint64_t reg = rdmsr(MSR_NB_CFG); 1929 if ((reg & NB_CFG_INITAPICCPUIDLO) == 0) { 1930 const u_int node_id = apic_id & __BITS(0, 2); 1931 apic_id = (cpu_family == 0xf) ? 1932 (apic_id >> core_bits) | (node_id << core_bits) : 1933 (apic_id >> 5) | (node_id << 2); 1934 } 1935 } 1936 #endif 1937 1938 if (cpu_family == 0x17) { 1939 x86_cpuid(0x8000001e, descs); 1940 const u_int threads = ((descs[1] >> 8) & 0xff) + 1; 1941 smt_bits = ilog2(threads); 1942 core_bits -= smt_bits; 1943 } 1944 1945 if (smt_bits + core_bits) { 1946 if (smt_bits + core_bits < 32) 1947 ci->ci_packageid = 0; 1948 } 1949 if (core_bits) { 1950 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1951 ci->ci_coreid = __SHIFTOUT(apic_id, core_mask); 1952 } 1953 if (smt_bits) { 1954 u_int smt_mask = __BITS(0, smt_bits - 1); 1955 ci->ci_smtid = __SHIFTOUT(apic_id, smt_mask); 1956 } 1957 1958 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1959 ci->ci_packageid); 1960 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1961 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1962 } 1963 1964 static void 1965 identifycpu_cpuids(struct cpu_info *ci) 1966 { 1967 const char *cpuname = ci->ci_dev; 1968 1969 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1970 ci->ci_packageid = ci->ci_initapicid; 1971 ci->ci_coreid = 0; 1972 ci->ci_smtid = 0; 1973 1974 if (cpu_vendor == CPUVENDOR_INTEL) 1975 identifycpu_cpuids_intel(ci); 1976 else if (cpu_vendor == CPUVENDOR_AMD) 1977 identifycpu_cpuids_amd(ci); 1978 } 1979 1980 void 1981 identifycpu(int fd, const char *cpuname) 1982 { 1983 const char *name = "", *modifier, *vendorname, *brand = ""; 1984 int class = CPUCLASS_386; 1985 unsigned int i; 1986 int modif, family; 1987 const struct cpu_cpuid_nameclass *cpup = NULL; 1988 const struct cpu_cpuid_family *cpufam; 1989 struct cpu_info *ci, cistore; 1990 u_int descs[4]; 1991 size_t sz; 1992 struct cpu_ucode_version ucode; 1993 union { 1994 struct cpu_ucode_version_amd amd; 1995 struct cpu_ucode_version_intel1 intel1; 1996 } ucvers; 1997 1998 ci = &cistore; 1999 cpu_probe_base_features(ci, cpuname); 2000 dump_descs(0x00000000, ci->ci_max_cpuid, cpuname, "basic"); 2001 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 2002 x86_cpuid(0x40000000, descs); 2003 dump_descs(0x40000000, descs[0], cpuname, "hypervisor"); 2004 } 2005 dump_descs(0x80000000, ci->ci_max_ext_cpuid, cpuname, "extended"); 2006 2007 cpu_probe_hv_features(ci, cpuname); 2008 cpu_probe_features(ci); 2009 2010 if (ci->ci_cpu_type >= 0) { 2011 /* Old pre-cpuid instruction cpu */ 2012 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 2013 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 2014 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 2015 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 2016 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 2017 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 2018 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 2019 modifier = ""; 2020 } else { 2021 /* CPU which support cpuid instruction */ 2022 modif = (ci->ci_signature >> 12) & 0x3; 2023 family = ci->ci_family; 2024 if (family < CPU_MINFAMILY) 2025 errx(1, "identifycpu: strange family value"); 2026 if (family > CPU_MAXFAMILY) 2027 family = CPU_MAXFAMILY; 2028 2029 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 2030 if (!strncmp((char *)ci->ci_vendor, 2031 i386_cpuid_cpus[i].cpu_id, 12)) { 2032 cpup = &i386_cpuid_cpus[i]; 2033 break; 2034 } 2035 } 2036 2037 if (cpup == NULL) { 2038 cpu_vendor = CPUVENDOR_UNKNOWN; 2039 if (ci->ci_vendor[0] != '\0') 2040 vendorname = (char *)&ci->ci_vendor[0]; 2041 else 2042 vendorname = "Unknown"; 2043 class = family - 3; 2044 modifier = ""; 2045 name = ""; 2046 ci->ci_info = NULL; 2047 } else { 2048 cpu_vendor = cpup->cpu_vendor; 2049 vendorname = cpup->cpu_vendorname; 2050 modifier = modifiers[modif]; 2051 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 2052 name = cpufam->cpu_models[ci->ci_model]; 2053 if (name == NULL || *name == '\0') 2054 name = cpufam->cpu_model_default; 2055 class = cpufam->cpu_class; 2056 ci->ci_info = cpufam->cpu_info; 2057 2058 if (cpu_vendor == CPUVENDOR_INTEL) { 2059 if (ci->ci_family == 6 && ci->ci_model >= 5) { 2060 const char *tmp; 2061 tmp = intel_family6_name(ci); 2062 if (tmp != NULL) 2063 name = tmp; 2064 } 2065 if (ci->ci_family == 15 && 2066 ci->ci_brand_id < 2067 __arraycount(i386_intel_brand) && 2068 i386_intel_brand[ci->ci_brand_id]) 2069 name = 2070 i386_intel_brand[ci->ci_brand_id]; 2071 } 2072 2073 if (cpu_vendor == CPUVENDOR_AMD) { 2074 if (ci->ci_family == 6 && ci->ci_model >= 6) { 2075 if (ci->ci_brand_id == 1) 2076 /* 2077 * It's Duron. We override the 2078 * name, since it might have 2079 * been misidentified as Athlon. 2080 */ 2081 name = 2082 amd_brand[ci->ci_brand_id]; 2083 else 2084 brand = amd_brand_name; 2085 } 2086 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 2087 == 0xf) { 2088 /* Identify AMD64 CPU names. */ 2089 const char *tmp; 2090 tmp = amd_amd64_name(ci); 2091 if (tmp != NULL) 2092 name = tmp; 2093 } 2094 } 2095 2096 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 2097 vendorname = "VIA"; 2098 } 2099 } 2100 2101 ci->ci_cpu_class = class; 2102 2103 sz = sizeof(ci->ci_tsc_freq); 2104 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 2105 sz = sizeof(use_pae); 2106 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 2107 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 2108 2109 /* 2110 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 2111 * we try to determine from the family/model values. 2112 */ 2113 if (*cpu_brand_string != '\0') 2114 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 2115 2116 aprint_normal("%s: %s", cpuname, vendorname); 2117 if (*modifier) 2118 aprint_normal(" %s", modifier); 2119 if (*name) 2120 aprint_normal(" %s", name); 2121 if (*brand) 2122 aprint_normal(" %s", brand); 2123 aprint_normal(" (%s-class)", classnames[class]); 2124 2125 if (ci->ci_tsc_freq != 0) 2126 aprint_normal(", %ju.%02ju MHz", 2127 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 2128 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 2129 aprint_normal("\n"); 2130 2131 (void)cpu_tsc_freq_cpuid(ci); 2132 2133 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 2134 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 2135 if (ci->ci_signature != 0) 2136 aprint_normal(" (id %#x)", ci->ci_signature); 2137 aprint_normal("\n"); 2138 2139 if (ci->ci_info) 2140 (*ci->ci_info)(ci); 2141 2142 /* 2143 * display CPU feature flags 2144 */ 2145 2146 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 2147 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 2148 2149 /* These next two are actually common definitions! */ 2150 print_bits(cpuname, "features2", 2151 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 2152 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 2153 print_bits(cpuname, "features3", 2154 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 2155 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 2156 2157 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 2158 ci->ci_feat_val[4]); 2159 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2160 print_bits(cpuname, "features5", CPUID_SEF_FLAGS, 2161 ci->ci_feat_val[5]); 2162 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2163 print_bits(cpuname, "features6", CPUID_SEF_FLAGS1, 2164 ci->ci_feat_val[6]); 2165 2166 if (cpu_vendor == CPUVENDOR_INTEL) 2167 print_bits(cpuname, "features7", CPUID_SEF_FLAGS2, 2168 ci->ci_feat_val[7]); 2169 2170 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[8]); 2171 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 2172 ci->ci_feat_val[9]); 2173 2174 if (ci->ci_max_xsave != 0) { 2175 aprint_normal("%s: xsave area size: current %d, maximum %d", 2176 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 2177 aprint_normal(", xgetbv %sabled\n", 2178 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 2179 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 2180 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 2181 x86_xgetbv()); 2182 } 2183 2184 x86_print_cache_and_tlb_info(ci); 2185 2186 if (ci->ci_max_cpuid >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 2187 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 2188 cpuname, 2189 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 2190 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 2191 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 2192 } 2193 2194 if (ci->ci_cpu_class == CPUCLASS_386) 2195 errx(1, "NetBSD requires an 80486 or later processor"); 2196 2197 if (ci->ci_cpu_type == CPU_486DLC) { 2198 #ifndef CYRIX_CACHE_WORKS 2199 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 2200 #else 2201 #ifndef CYRIX_CACHE_REALLY_WORKS 2202 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 2203 #else 2204 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 2205 #endif 2206 #endif 2207 } 2208 2209 /* 2210 * Everything past this point requires a Pentium or later. 2211 */ 2212 if (ci->ci_max_cpuid < 0) 2213 return; 2214 2215 identifycpu_cpuids(ci); 2216 2217 if ((ci->ci_max_cpuid >= 5) 2218 && ((cpu_vendor == CPUVENDOR_INTEL) 2219 || (cpu_vendor == CPUVENDOR_AMD))) { 2220 uint16_t lmin, lmax; 2221 x86_cpuid(5, descs); 2222 2223 print_bits(cpuname, "MONITOR/MWAIT extensions", 2224 CPUID_MON_FLAGS, descs[2]); 2225 lmin = __SHIFTOUT(descs[0], CPUID_MON_MINSIZE); 2226 lmax = __SHIFTOUT(descs[1], CPUID_MON_MAXSIZE); 2227 aprint_normal("%s: monitor-line size %hu", cpuname, lmin); 2228 if (lmin != lmax) 2229 aprint_normal("-%hu", lmax); 2230 aprint_normal("\n"); 2231 2232 for (i = 0; i <= 7; i++) { 2233 unsigned int num = CPUID_MON_SUBSTATE(descs[3], i); 2234 2235 if (num != 0) 2236 aprint_normal("%s: C%u substates %u\n", 2237 cpuname, i, num); 2238 } 2239 } 2240 if ((ci->ci_max_cpuid >= 6) 2241 && ((cpu_vendor == CPUVENDOR_INTEL) 2242 || (cpu_vendor == CPUVENDOR_AMD))) { 2243 x86_cpuid(6, descs); 2244 print_bits(cpuname, "DSPM-eax", CPUID_DSPM_FLAGS, descs[0]); 2245 print_bits(cpuname, "DSPM-ecx", CPUID_DSPM_FLAGS1, descs[2]); 2246 } 2247 if ((ci->ci_max_cpuid >= 7) 2248 && ((cpu_vendor == CPUVENDOR_INTEL) 2249 || (cpu_vendor == CPUVENDOR_AMD))) { 2250 x86_cpuid(7, descs); 2251 aprint_verbose("%s: SEF highest subleaf %08x\n", 2252 cpuname, descs[0]); 2253 } 2254 2255 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2256 if (ci->ci_max_ext_cpuid >= 0x80000007) 2257 powernow_probe(ci); 2258 2259 if (cpu_vendor == CPUVENDOR_AMD) { 2260 if (ci->ci_max_ext_cpuid >= 0x80000008) { 2261 x86_cpuid(0x80000008, descs); 2262 print_bits(cpuname, "AMD Extended features", 2263 CPUID_CAPEX_FLAGS, descs[1]); 2264 } 2265 2266 if ((ci->ci_max_ext_cpuid >= 0x8000000a) 2267 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 2268 x86_cpuid(0x8000000a, descs); 2269 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 2270 descs[0] & 0xf); 2271 aprint_verbose("%s: SVM NASID %d\n", cpuname, 2272 descs[1]); 2273 print_bits(cpuname, "SVM features", 2274 CPUID_AMD_SVM_FLAGS, descs[3]); 2275 } 2276 if (ci->ci_max_ext_cpuid >= 0x8000001f) { 2277 x86_cpuid(0x8000001f, descs); 2278 print_bits(cpuname, "Encrypted Memory features", 2279 CPUID_AMD_ENCMEM_FLAGS, descs[0]); 2280 } 2281 } else if (cpu_vendor == CPUVENDOR_INTEL) { 2282 int32_t bi_index; 2283 2284 for (bi_index = 1; bi_index <= ci->ci_max_cpuid; bi_index++) { 2285 x86_cpuid(bi_index, descs); 2286 switch (bi_index) { 2287 case 0x0a: 2288 print_bits(cpuname, "Perfmon-eax", 2289 CPUID_PERF_FLAGS0, descs[0]); 2290 print_bits(cpuname, "Perfmon-ebx", 2291 CPUID_PERF_FLAGS1, descs[1]); 2292 print_bits(cpuname, "Perfmon-edx", 2293 CPUID_PERF_FLAGS3, descs[3]); 2294 break; 2295 default: 2296 #if 0 2297 aprint_verbose("%s: basic %08x-eax %08x\n", 2298 cpuname, bi_index, descs[0]); 2299 aprint_verbose("%s: basic %08x-ebx %08x\n", 2300 cpuname, bi_index, descs[1]); 2301 aprint_verbose("%s: basic %08x-ecx %08x\n", 2302 cpuname, bi_index, descs[2]); 2303 aprint_verbose("%s: basic %08x-edx %08x\n", 2304 cpuname, bi_index, descs[3]); 2305 #endif 2306 break; 2307 } 2308 } 2309 } 2310 2311 #ifdef INTEL_ONDEMAND_CLOCKMOD 2312 clockmod_init(); 2313 #endif 2314 2315 if (cpu_vendor == CPUVENDOR_AMD) 2316 ucode.loader_version = CPU_UCODE_LOADER_AMD; 2317 else if (cpu_vendor == CPUVENDOR_INTEL) 2318 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 2319 else 2320 return; 2321 2322 ucode.data = &ucvers; 2323 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 2324 #ifdef __i386__ 2325 struct cpu_ucode_version_64 ucode_64; 2326 if (errno != ENOTTY) 2327 return; 2328 /* Try the 64 bit ioctl */ 2329 memset(&ucode_64, 0, sizeof ucode_64); 2330 ucode_64.data = &ucvers; 2331 ucode_64.loader_version = ucode.loader_version; 2332 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 2333 return; 2334 #else 2335 return; 2336 #endif 2337 } 2338 2339 if (cpu_vendor == CPUVENDOR_AMD) 2340 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2341 else if (cpu_vendor == CPUVENDOR_INTEL) 2342 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2343 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2344 } 2345 2346 static const struct x86_cache_info * 2347 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 2348 { 2349 int i; 2350 2351 for (i = 0; cai[i].cai_desc != 0; i++) { 2352 if (cai[i].cai_desc == desc) 2353 return (&cai[i]); 2354 } 2355 2356 return (NULL); 2357 } 2358 2359 static const char * 2360 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2361 const char *sep) 2362 { 2363 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2364 char human_num[HUMAN_BUFSIZE]; 2365 2366 if (cai->cai_totalsize == 0) 2367 return sep; 2368 2369 if (sep == NULL) 2370 aprint_verbose_dev(ci->ci_dev, ""); 2371 else 2372 aprint_verbose("%s", sep); 2373 if (name != NULL) 2374 aprint_verbose("%s ", name); 2375 2376 if (cai->cai_string != NULL) { 2377 aprint_verbose("%s ", cai->cai_string); 2378 } else { 2379 (void)humanize_number(human_num, sizeof(human_num), 2380 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2381 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2382 } 2383 switch (cai->cai_associativity) { 2384 case 0: 2385 aprint_verbose("disabled"); 2386 break; 2387 case 1: 2388 aprint_verbose("direct-mapped"); 2389 break; 2390 case 0xff: 2391 aprint_verbose("fully associative"); 2392 break; 2393 default: 2394 aprint_verbose("%d-way", cai->cai_associativity); 2395 break; 2396 } 2397 return ", "; 2398 } 2399 2400 static const char * 2401 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2402 const char *sep) 2403 { 2404 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2405 char human_num[HUMAN_BUFSIZE]; 2406 2407 if (cai->cai_totalsize == 0) 2408 return sep; 2409 2410 if (sep == NULL) 2411 aprint_verbose_dev(ci->ci_dev, ""); 2412 else 2413 aprint_verbose("%s", sep); 2414 if (name != NULL) 2415 aprint_verbose("%s ", name); 2416 2417 if (cai->cai_string != NULL) { 2418 aprint_verbose("%s", cai->cai_string); 2419 } else { 2420 (void)humanize_number(human_num, sizeof(human_num), 2421 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2422 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2423 human_num); 2424 switch (cai->cai_associativity) { 2425 case 0: 2426 aprint_verbose("disabled"); 2427 break; 2428 case 1: 2429 aprint_verbose("direct-mapped"); 2430 break; 2431 case 0xff: 2432 aprint_verbose("fully associative"); 2433 break; 2434 default: 2435 aprint_verbose("%d-way", cai->cai_associativity); 2436 break; 2437 } 2438 } 2439 return ", "; 2440 } 2441 2442 static void 2443 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2444 { 2445 const char *sep = NULL; 2446 2447 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2448 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2449 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 2450 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 2451 if (sep != NULL) 2452 aprint_verbose("\n"); 2453 } 2454 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2455 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 2456 if (sep != NULL) 2457 aprint_verbose("\n"); 2458 } 2459 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2460 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 2461 if (sep != NULL) 2462 aprint_verbose("\n"); 2463 } 2464 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2465 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2466 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2467 if (sep != NULL) 2468 aprint_verbose("\n"); 2469 } 2470 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 2471 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 2472 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 2473 if (sep != NULL) 2474 aprint_verbose("\n"); 2475 } 2476 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 2477 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 2478 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 2479 if (sep != NULL) 2480 aprint_verbose("\n"); 2481 } 2482 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 2483 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 2484 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 2485 if (sep != NULL) 2486 aprint_verbose("\n"); 2487 } 2488 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 2489 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 2490 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 2491 if (sep != NULL) 2492 aprint_verbose("\n"); 2493 } 2494 if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) { 2495 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL); 2496 sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep); 2497 sep = print_tlb_config(ci, CAI_L2_STLB3, NULL, sep); 2498 if (sep != NULL) 2499 aprint_verbose("\n"); 2500 } 2501 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 2502 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", 2503 NULL); 2504 if (sep != NULL) 2505 aprint_verbose("\n"); 2506 } 2507 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 2508 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", 2509 NULL); 2510 if (sep != NULL) 2511 aprint_verbose("\n"); 2512 } 2513 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 2514 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", 2515 NULL); 2516 if (sep != NULL) 2517 aprint_verbose("\n"); 2518 } 2519 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 2520 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", 2521 NULL); 2522 if (sep != NULL) 2523 aprint_verbose("\n"); 2524 } 2525 } 2526 2527 static void 2528 powernow_probe(struct cpu_info *ci) 2529 { 2530 uint32_t regs[4]; 2531 char buf[256]; 2532 2533 x86_cpuid(0x80000007, regs); 2534 2535 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2536 aprint_normal_dev(ci->ci_dev, "Power Management features: %s\n", buf); 2537 } 2538 2539 bool 2540 identifycpu_bind(void) 2541 { 2542 2543 return true; 2544 } 2545 2546 int 2547 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2548 { 2549 struct cpu_info ci; 2550 int loader_version, res; 2551 struct cpu_ucode_version versreq; 2552 2553 cpu_probe_base_features(&ci, "unknown"); 2554 2555 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2556 loader_version = CPU_UCODE_LOADER_AMD; 2557 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2558 loader_version = CPU_UCODE_LOADER_INTEL1; 2559 else 2560 return -1; 2561 2562 /* check whether the kernel understands this loader version */ 2563 versreq.loader_version = loader_version; 2564 versreq.data = 0; 2565 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2566 if (res) 2567 return -1; 2568 2569 switch (loader_version) { 2570 case CPU_UCODE_LOADER_AMD: 2571 if (uc->cpu_nr != -1) { 2572 /* printf? */ 2573 return -1; 2574 } 2575 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2576 break; 2577 case CPU_UCODE_LOADER_INTEL1: 2578 if (uc->cpu_nr == -1) 2579 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2580 else 2581 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2582 break; 2583 default: /* can't happen */ 2584 return -1; 2585 } 2586 uc->loader_version = loader_version; 2587 return 0; 2588 } 2589
Indexes created Fri Sep 26 20:09:58 GMT 2025