i386.c revision 1.115
1 /* $NetBSD: i386.c,v 1.115 2020/11/24 00:48:39 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.115 2020/11/24 00:48:39 msaitoh Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cpu_ucode.h> 85 86 #include "../cpuctl.h" 87 #include "cpuctl_i386.h" 88 89 /* Size of buffer for printing humanized numbers */ 90 #define HUMAN_BUFSIZE sizeof("999KB") 91 92 struct cpu_nocpuid_nameclass { 93 int cpu_vendor; 94 const char *cpu_vendorname; 95 const char *cpu_name; 96 int cpu_class; 97 void (*cpu_setup)(struct cpu_info *); 98 void (*cpu_cacheinfo)(struct cpu_info *); 99 void (*cpu_info)(struct cpu_info *); 100 }; 101 102 struct cpu_cpuid_nameclass { 103 const char *cpu_id; 104 int cpu_vendor; 105 const char *cpu_vendorname; 106 struct cpu_cpuid_family { 107 int cpu_class; 108 const char *cpu_models[256]; 109 const char *cpu_model_default; 110 void (*cpu_setup)(struct cpu_info *); 111 void (*cpu_probe)(struct cpu_info *); 112 void (*cpu_info)(struct cpu_info *); 113 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 114 }; 115 116 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 117 118 /* 119 * Map Brand ID from cpuid instruction to brand name. 120 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 121 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 122 * Architectures Software Developer's Manual, Volume 2A". 123 */ 124 static const char * const i386_intel_brand[] = { 125 "", /* Unsupported */ 126 "Celeron", /* Intel (R) Celeron (TM) processor */ 127 "Pentium III", /* Intel (R) Pentium (R) III processor */ 128 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 129 "Pentium III", /* Intel (R) Pentium (R) III processor */ 130 "", /* 0x05: Reserved */ 131 "Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */ 132 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 133 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 134 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 135 "Celeron", /* Intel (R) Celeron (TM) processor */ 136 "Xeon", /* Intel (R) Xeon (TM) processor */ 137 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 138 "", /* 0x0d: Reserved */ 139 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 140 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 141 "", /* 0x10: Reserved */ 142 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 143 "Celeron M", /* Intel (R) Celeron (R) M processor */ 144 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 145 "Celeron", /* Intel (R) Celeron (R) processor */ 146 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 147 "Pentium M", /* Intel (R) Pentium (R) M processor */ 148 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 149 }; 150 151 /* 152 * AMD processors don't have Brand IDs, so we need these names for probe. 153 */ 154 static const char * const amd_brand[] = { 155 "", 156 "Duron", /* AMD Duron(tm) */ 157 "MP", /* AMD Athlon(tm) MP */ 158 "XP", /* AMD Athlon(tm) XP */ 159 "4" /* AMD Athlon(tm) 4 */ 160 }; 161 162 int cpu_vendor; 163 static char cpu_brand_string[49]; 164 static char amd_brand_name[48]; 165 static int use_pae, largepagesize; 166 167 /* Setup functions */ 168 static void disable_tsc(struct cpu_info *); 169 static void amd_family5_setup(struct cpu_info *); 170 static void cyrix6x86_cpu_setup(struct cpu_info *); 171 static void winchip_cpu_setup(struct cpu_info *); 172 /* Brand/Model name functions */ 173 static const char *intel_family6_name(struct cpu_info *); 174 static const char *amd_amd64_name(struct cpu_info *); 175 /* Probe functions */ 176 static void amd_family6_probe(struct cpu_info *); 177 static void powernow_probe(struct cpu_info *); 178 static void intel_family_new_probe(struct cpu_info *); 179 static void via_cpu_probe(struct cpu_info *); 180 /* (Cache) Info functions */ 181 static void cpu_dcp_cacheinfo(struct cpu_info *, uint32_t); 182 static void intel_cpu_cacheinfo(struct cpu_info *); 183 static void amd_cpu_cacheinfo(struct cpu_info *); 184 static void via_cpu_cacheinfo(struct cpu_info *); 185 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 186 static void transmeta_cpu_info(struct cpu_info *); 187 /* Common functions */ 188 static void cpu_probe_base_features(struct cpu_info *, const char *); 189 static void cpu_probe_hv_features(struct cpu_info *, const char *); 190 static void cpu_probe_features(struct cpu_info *); 191 static void print_bits(const char *, const char *, const char *, uint32_t); 192 static void identifycpu_cpuids(struct cpu_info *); 193 static const struct x86_cache_info *cache_info_lookup( 194 const struct x86_cache_info *, uint8_t); 195 static const char *print_cache_config(struct cpu_info *, int, const char *, 196 const char *); 197 static const char *print_tlb_config(struct cpu_info *, int, const char *, 198 const char *); 199 static void x86_print_cache_and_tlb_info(struct cpu_info *); 200 201 /* 202 * Note: these are just the ones that may not have a cpuid instruction. 203 * We deal with the rest in a different way. 204 */ 205 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 206 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 207 NULL, NULL, NULL }, /* CPU_386SX */ 208 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 209 NULL, NULL, NULL }, /* CPU_386 */ 210 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 211 NULL, NULL, NULL }, /* CPU_486SX */ 212 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 213 NULL, NULL, NULL }, /* CPU_486 */ 214 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 215 NULL, NULL, NULL }, /* CPU_486DLC */ 216 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 217 NULL, NULL, NULL }, /* CPU_6x86 */ 218 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 219 NULL, NULL, NULL }, /* CPU_NX586 */ 220 }; 221 222 const char *classnames[] = { 223 "386", 224 "486", 225 "586", 226 "686" 227 }; 228 229 const char *modifiers[] = { 230 "", 231 "OverDrive", 232 "Dual", 233 "" 234 }; 235 236 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 237 { 238 /* 239 * For Intel processors, check Chapter 35Model-specific 240 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 241 * Software Developer's Manual, Volume 3C". 242 */ 243 "GenuineIntel", 244 CPUVENDOR_INTEL, 245 "Intel", 246 /* Family 4 */ 247 { { 248 CPUCLASS_486, 249 { 250 "486DX", "486DX", "486SX", "486DX2", "486SL", 251 "486SX2", 0, "486DX2 W/B Enhanced", 252 "486DX4", 0, 0, 0, 0, 0, 0, 0, 253 }, 254 "486", /* Default */ 255 NULL, 256 NULL, 257 intel_cpu_cacheinfo, 258 }, 259 /* Family 5 */ 260 { 261 CPUCLASS_586, 262 { 263 "Pentium (P5 A-step)", "Pentium (P5)", 264 "Pentium (P54C)", "Pentium (P24T)", 265 "Pentium/MMX", "Pentium", 0, 266 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 267 "Quark X1000", 0, 0, 0, 0, 0, 0, 268 }, 269 "Pentium", /* Default */ 270 NULL, 271 NULL, 272 intel_cpu_cacheinfo, 273 }, 274 /* Family 6 */ 275 { 276 CPUCLASS_686, 277 { 278 [0x00] = "Pentium Pro (A-step)", 279 [0x01] = "Pentium Pro", 280 [0x03] = "Pentium II (Klamath)", 281 [0x04] = "Pentium Pro", 282 [0x05] = "Pentium II/Celeron (Deschutes)", 283 [0x06] = "Celeron (Mendocino)", 284 [0x07] = "Pentium III (Katmai)", 285 [0x08] = "Pentium III (Coppermine)", 286 [0x09] = "Pentium M (Banias)", 287 [0x0a] = "Pentium III Xeon (Cascades)", 288 [0x0b] = "Pentium III (Tualatin)", 289 [0x0d] = "Pentium M (Dothan)", 290 [0x0e] = "Pentium Core Duo, Core solo", 291 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 292 "Core 2 Quad 6xxx, " 293 "Core 2 Extreme 6xxx, " 294 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 295 "and Pentium DC", 296 [0x15] = "EP80579 Integrated Processor", 297 [0x16] = "Celeron (45nm)", 298 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 299 "Core 2 Quad 8xxx and 9xxx", 300 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 301 "(Nehalem)", 302 [0x1c] = "45nm Atom Family", 303 [0x1d] = "XeonMP 74xx (Nehalem)", 304 [0x1e] = "Core i7 and i5", 305 [0x1f] = "Core i7 and i5", 306 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 307 [0x26] = "Atom Family", 308 [0x27] = "Atom Family", 309 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 310 "i3 2xxx", 311 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 312 [0x2d] = "Xeon E5 Sandy Bridge family, " 313 "Core i7-39xx Extreme", 314 [0x2e] = "Xeon 75xx & 65xx", 315 [0x2f] = "Xeon E7 family", 316 [0x35] = "Atom Family", 317 [0x36] = "Atom S1000", 318 [0x37] = "Atom E3000, Z3[67]00", 319 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 320 "Ivy Bridge", 321 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 322 "(Haswell)", 323 [0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)", 324 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 325 "Core i7-49xx Extreme", 326 [0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), " 327 "Core i7-59xx Extreme", 328 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 329 "(Haswell)", 330 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 331 "(Haswell)", 332 [0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)", 333 [0x4a] = "Atom Z3400", 334 [0x4c] = "Atom X[57]-Z8000 (Airmont)", 335 [0x4d] = "Atom C2000", 336 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 337 [0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme", 338 [0x55] = "Xeon Scalable (Skylake, Cascade Lake, Copper Lake)", 339 [0x56] = "Xeon D-1500 (Broadwell)", 340 [0x57] = "Xeon Phi [357]200 (Knights Landing)", 341 [0x5a] = "Atom E3500", 342 [0x5c] = "Atom (Goldmont)", 343 [0x5d] = "Atom X3-C3000 (Silvermont)", 344 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 345 [0x5f] = "Atom (Goldmont, Denverton)", 346 [0x66] = "8th gen Core i3 (Cannon Lake)", 347 [0x6a] = "Future Xeon (Ice Lake)", 348 [0x6c] = "Future Xeon (Ice Lake)", 349 [0x7a] = "Atom (Goldmont Plus)", 350 [0x7d] = "10th gen Core (Ice Lake)", 351 [0x7e] = "10th gen Core (Ice Lake)", 352 [0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)", 353 [0x86] = "Atom (Tremont)", 354 [0x8c] = "11th gen Core (Tiger Lake)", 355 [0x8d] = "11th gen Core (Tiger Lake)", 356 [0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 357 [0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 358 [0xa5] = "10th gen Core (Comet Lake)", 359 [0xa6] = "10th gen Core (Comet Lake)", 360 }, 361 "Pentium Pro, II or III", /* Default */ 362 NULL, 363 intel_family_new_probe, 364 intel_cpu_cacheinfo, 365 }, 366 /* Family > 6 */ 367 { 368 CPUCLASS_686, 369 { 370 0, 0, 0, 0, 0, 0, 0, 0, 371 0, 0, 0, 0, 0, 0, 0, 0, 372 }, 373 "Pentium 4", /* Default */ 374 NULL, 375 intel_family_new_probe, 376 intel_cpu_cacheinfo, 377 } } 378 }, 379 { 380 "AuthenticAMD", 381 CPUVENDOR_AMD, 382 "AMD", 383 /* Family 4 */ 384 { { 385 CPUCLASS_486, 386 { 387 0, 0, 0, "Am486DX2 W/T", 388 0, 0, 0, "Am486DX2 W/B", 389 "Am486DX4 W/T or Am5x86 W/T 150", 390 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 391 0, 0, "Am5x86 W/T 133/160", 392 "Am5x86 W/B 133/160", 393 }, 394 "Am486 or Am5x86", /* Default */ 395 NULL, 396 NULL, 397 NULL, 398 }, 399 /* Family 5 */ 400 { 401 CPUCLASS_586, 402 { 403 "K5", "K5", "K5", "K5", 0, 0, "K6", 404 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 405 "K6-2+/III+", 0, 0, 406 }, 407 "K5 or K6", /* Default */ 408 amd_family5_setup, 409 NULL, 410 amd_cpu_cacheinfo, 411 }, 412 /* Family 6 */ 413 { 414 CPUCLASS_686, 415 { 416 0, "Athlon Model 1", "Athlon Model 2", 417 "Duron", "Athlon Model 4 (Thunderbird)", 418 0, "Athlon", "Duron", "Athlon", 0, 419 "Athlon", 0, 0, 0, 0, 0, 420 }, 421 "K7 (Athlon)", /* Default */ 422 NULL, 423 amd_family6_probe, 424 amd_cpu_cacheinfo, 425 }, 426 /* Family > 6 */ 427 { 428 CPUCLASS_686, 429 { 430 0, 0, 0, 0, 0, 0, 0, 0, 431 0, 0, 0, 0, 0, 0, 0, 0, 432 }, 433 "Unknown K8 (Athlon)", /* Default */ 434 NULL, 435 amd_family6_probe, 436 amd_cpu_cacheinfo, 437 } } 438 }, 439 { 440 "CyrixInstead", 441 CPUVENDOR_CYRIX, 442 "Cyrix", 443 /* Family 4 */ 444 { { 445 CPUCLASS_486, 446 { 447 0, 0, 0, 448 "MediaGX", 449 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 450 }, 451 "486", /* Default */ 452 cyrix6x86_cpu_setup, /* XXX ?? */ 453 NULL, 454 NULL, 455 }, 456 /* Family 5 */ 457 { 458 CPUCLASS_586, 459 { 460 0, 0, "6x86", 0, 461 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 462 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 463 }, 464 "6x86", /* Default */ 465 cyrix6x86_cpu_setup, 466 NULL, 467 NULL, 468 }, 469 /* Family 6 */ 470 { 471 CPUCLASS_686, 472 { 473 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 474 0, 0, 0, 0, 0, 0, 0, 0, 475 }, 476 "6x86MX", /* Default */ 477 cyrix6x86_cpu_setup, 478 NULL, 479 NULL, 480 }, 481 /* Family > 6 */ 482 { 483 CPUCLASS_686, 484 { 485 0, 0, 0, 0, 0, 0, 0, 0, 486 0, 0, 0, 0, 0, 0, 0, 0, 487 }, 488 "Unknown 6x86MX", /* Default */ 489 NULL, 490 NULL, 491 NULL, 492 } } 493 }, 494 { /* MediaGX is now owned by National Semiconductor */ 495 "Geode by NSC", 496 CPUVENDOR_CYRIX, /* XXX */ 497 "National Semiconductor", 498 /* Family 4, NSC never had any of these */ 499 { { 500 CPUCLASS_486, 501 { 502 0, 0, 0, 0, 0, 0, 0, 0, 503 0, 0, 0, 0, 0, 0, 0, 0, 504 }, 505 "486 compatible", /* Default */ 506 NULL, 507 NULL, 508 NULL, 509 }, 510 /* Family 5: Geode family, formerly MediaGX */ 511 { 512 CPUCLASS_586, 513 { 514 0, 0, 0, 0, 515 "Geode GX1", 516 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 517 }, 518 "Geode", /* Default */ 519 cyrix6x86_cpu_setup, 520 NULL, 521 amd_cpu_cacheinfo, 522 }, 523 /* Family 6, not yet available from NSC */ 524 { 525 CPUCLASS_686, 526 { 527 0, 0, 0, 0, 0, 0, 0, 0, 528 0, 0, 0, 0, 0, 0, 0, 0, 529 }, 530 "Pentium Pro compatible", /* Default */ 531 NULL, 532 NULL, 533 NULL, 534 }, 535 /* Family > 6, not yet available from NSC */ 536 { 537 CPUCLASS_686, 538 { 539 0, 0, 0, 0, 0, 0, 0, 0, 540 0, 0, 0, 0, 0, 0, 0, 0, 541 }, 542 "Pentium Pro compatible", /* Default */ 543 NULL, 544 NULL, 545 NULL, 546 } } 547 }, 548 { 549 "CentaurHauls", 550 CPUVENDOR_IDT, 551 "IDT", 552 /* Family 4, IDT never had any of these */ 553 { { 554 CPUCLASS_486, 555 { 556 0, 0, 0, 0, 0, 0, 0, 0, 557 0, 0, 0, 0, 0, 0, 0, 0, 558 }, 559 "486 compatible", /* Default */ 560 NULL, 561 NULL, 562 NULL, 563 }, 564 /* Family 5 */ 565 { 566 CPUCLASS_586, 567 { 568 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 569 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 570 }, 571 "WinChip", /* Default */ 572 winchip_cpu_setup, 573 NULL, 574 NULL, 575 }, 576 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 577 { 578 CPUCLASS_686, 579 { 580 0, 0, 0, 0, 0, 0, "C3 Samuel", 581 "C3 Samuel 2/Ezra", "C3 Ezra-T", 582 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 583 0, "VIA Nano", 584 }, 585 "Unknown VIA/IDT", /* Default */ 586 NULL, 587 via_cpu_probe, 588 via_cpu_cacheinfo, 589 }, 590 /* Family > 6, not yet available from VIA */ 591 { 592 CPUCLASS_686, 593 { 594 0, 0, 0, 0, 0, 0, 0, 0, 595 0, 0, 0, 0, 0, 0, 0, 0, 596 }, 597 "Pentium Pro compatible", /* Default */ 598 NULL, 599 NULL, 600 NULL, 601 } } 602 }, 603 { 604 "GenuineTMx86", 605 CPUVENDOR_TRANSMETA, 606 "Transmeta", 607 /* Family 4, Transmeta never had any of these */ 608 { { 609 CPUCLASS_486, 610 { 611 0, 0, 0, 0, 0, 0, 0, 0, 612 0, 0, 0, 0, 0, 0, 0, 0, 613 }, 614 "486 compatible", /* Default */ 615 NULL, 616 NULL, 617 NULL, 618 }, 619 /* Family 5 */ 620 { 621 CPUCLASS_586, 622 { 623 0, 0, 0, 0, 0, 0, 0, 0, 624 0, 0, 0, 0, 0, 0, 0, 0, 625 }, 626 "Crusoe", /* Default */ 627 NULL, 628 NULL, 629 transmeta_cpu_info, 630 }, 631 /* Family 6, not yet available from Transmeta */ 632 { 633 CPUCLASS_686, 634 { 635 0, 0, 0, 0, 0, 0, 0, 0, 636 0, 0, 0, 0, 0, 0, 0, 0, 637 }, 638 "Pentium Pro compatible", /* Default */ 639 NULL, 640 NULL, 641 NULL, 642 }, 643 /* Family > 6, not yet available from Transmeta */ 644 { 645 CPUCLASS_686, 646 { 647 0, 0, 0, 0, 0, 0, 0, 0, 648 0, 0, 0, 0, 0, 0, 0, 0, 649 }, 650 "Pentium Pro compatible", /* Default */ 651 NULL, 652 NULL, 653 NULL, 654 } } 655 } 656 }; 657 658 /* 659 * disable the TSC such that we don't use the TSC in microtime(9) 660 * because some CPUs got the implementation wrong. 661 */ 662 static void 663 disable_tsc(struct cpu_info *ci) 664 { 665 if (ci->ci_feat_val[0] & CPUID_TSC) { 666 ci->ci_feat_val[0] &= ~CPUID_TSC; 667 aprint_error("WARNING: broken TSC disabled\n"); 668 } 669 } 670 671 static void 672 amd_family5_setup(struct cpu_info *ci) 673 { 674 675 switch (ci->ci_model) { 676 case 0: /* AMD-K5 Model 0 */ 677 /* 678 * According to the AMD Processor Recognition App Note, 679 * the AMD-K5 Model 0 uses the wrong bit to indicate 680 * support for global PTEs, instead using bit 9 (APIC) 681 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 682 */ 683 if (ci->ci_feat_val[0] & CPUID_APIC) 684 ci->ci_feat_val[0] = 685 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 686 /* 687 * XXX But pmap_pg_g is already initialized -- need to kick 688 * XXX the pmap somehow. How does the MP branch do this? 689 */ 690 break; 691 } 692 } 693 694 static void 695 cyrix6x86_cpu_setup(struct cpu_info *ci) 696 { 697 698 /* 699 * Do not disable the TSC on the Geode GX, it's reported to 700 * work fine. 701 */ 702 if (ci->ci_signature != 0x552) 703 disable_tsc(ci); 704 } 705 706 static void 707 winchip_cpu_setup(struct cpu_info *ci) 708 { 709 switch (ci->ci_model) { 710 case 4: /* WinChip C6 */ 711 disable_tsc(ci); 712 } 713 } 714 715 716 static const char * 717 intel_family6_name(struct cpu_info *ci) 718 { 719 const char *ret = NULL; 720 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 721 722 if (ci->ci_model == 5) { 723 switch (l2cache) { 724 case 0: 725 case 128 * 1024: 726 ret = "Celeron (Covington)"; 727 break; 728 case 256 * 1024: 729 ret = "Mobile Pentium II (Dixon)"; 730 break; 731 case 512 * 1024: 732 ret = "Pentium II"; 733 break; 734 case 1 * 1024 * 1024: 735 case 2 * 1024 * 1024: 736 ret = "Pentium II Xeon"; 737 break; 738 } 739 } else if (ci->ci_model == 6) { 740 switch (l2cache) { 741 case 256 * 1024: 742 case 512 * 1024: 743 ret = "Mobile Pentium II"; 744 break; 745 } 746 } else if (ci->ci_model == 7) { 747 switch (l2cache) { 748 case 512 * 1024: 749 ret = "Pentium III"; 750 break; 751 case 1 * 1024 * 1024: 752 case 2 * 1024 * 1024: 753 ret = "Pentium III Xeon"; 754 break; 755 } 756 } else if (ci->ci_model >= 8) { 757 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 758 switch (ci->ci_brand_id) { 759 case 0x3: 760 if (ci->ci_signature == 0x6B1) 761 ret = "Celeron"; 762 break; 763 case 0x8: 764 if (ci->ci_signature >= 0xF13) 765 ret = "genuine processor"; 766 break; 767 case 0xB: 768 if (ci->ci_signature >= 0xF13) 769 ret = "Xeon MP"; 770 break; 771 case 0xE: 772 if (ci->ci_signature < 0xF13) 773 ret = "Xeon"; 774 break; 775 } 776 if (ret == NULL) 777 ret = i386_intel_brand[ci->ci_brand_id]; 778 } 779 } 780 781 return ret; 782 } 783 784 /* 785 * Identify AMD64 CPU names from cpuid. 786 * 787 * Based on: 788 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 789 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 790 * "Revision Guide for AMD NPT Family 0Fh Processors" 791 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 792 * and other miscellaneous reports. 793 * 794 * This is all rather pointless, these are cross 'brand' since the raw 795 * silicon is shared. 796 */ 797 static const char * 798 amd_amd64_name(struct cpu_info *ci) 799 { 800 static char family_str[32]; 801 802 /* Only called if family >= 15 */ 803 804 switch (ci->ci_family) { 805 case 15: 806 switch (ci->ci_model) { 807 case 0x21: /* rev JH-E1/E6 */ 808 case 0x41: /* rev JH-F2 */ 809 return "Dual-Core Opteron"; 810 case 0x23: /* rev JH-E6 (Toledo) */ 811 return "Dual-Core Opteron or Athlon 64 X2"; 812 case 0x43: /* rev JH-F2 (Windsor) */ 813 return "Athlon 64 FX or Athlon 64 X2"; 814 case 0x24: /* rev SH-E5 (Lancaster?) */ 815 return "Mobile Athlon 64 or Turion 64"; 816 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 817 return "Opteron or Athlon 64 FX"; 818 case 0x15: /* rev SH-D0 */ 819 case 0x25: /* rev SH-E4 */ 820 return "Opteron"; 821 case 0x27: /* rev DH-E4, SH-E4 */ 822 return "Athlon 64 or Athlon 64 FX or Opteron"; 823 case 0x48: /* rev BH-F2 */ 824 return "Turion 64 X2"; 825 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 826 case 0x07: /* rev SH-CG (ClawHammer) */ 827 case 0x0b: /* rev CH-CG */ 828 case 0x14: /* rev SH-D0 */ 829 case 0x17: /* rev SH-D0 */ 830 case 0x1b: /* rev CH-D0 */ 831 return "Athlon 64"; 832 case 0x2b: /* rev BH-E4 (Manchester) */ 833 case 0x4b: /* rev BH-F2 (Windsor) */ 834 return "Athlon 64 X2"; 835 case 0x6b: /* rev BH-G1 (Brisbane) */ 836 return "Athlon X2 or Athlon 64 X2"; 837 case 0x08: /* rev CH-CG */ 838 case 0x0c: /* rev DH-CG (Newcastle) */ 839 case 0x0e: /* rev DH-CG (Newcastle?) */ 840 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 841 case 0x18: /* rev CH-D0 */ 842 case 0x1c: /* rev DH-D0 (Winchester) */ 843 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 844 case 0x2c: /* rev DH-E3/E6 */ 845 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 846 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 847 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 848 case 0x6f: /* rev DH-G1 */ 849 return "Athlon 64 or Sempron"; 850 default: 851 break; 852 } 853 return "Unknown AMD64 CPU"; 854 855 #if 0 856 case 16: 857 return "Family 10h"; 858 case 17: 859 return "Family 11h"; 860 case 18: 861 return "Family 12h"; 862 case 19: 863 return "Family 14h"; 864 case 20: 865 return "Family 15h"; 866 #endif 867 868 default: 869 break; 870 } 871 872 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 873 return family_str; 874 } 875 876 static void 877 intel_family_new_probe(struct cpu_info *ci) 878 { 879 uint32_t descs[4]; 880 881 x86_cpuid(0x80000000, descs); 882 883 /* 884 * Determine extended feature flags. 885 */ 886 if (descs[0] >= 0x80000001) { 887 x86_cpuid(0x80000001, descs); 888 ci->ci_feat_val[2] |= descs[3]; 889 ci->ci_feat_val[3] |= descs[2]; 890 } 891 } 892 893 static void 894 via_cpu_probe(struct cpu_info *ci) 895 { 896 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 897 u_int descs[4]; 898 u_int lfunc; 899 900 /* 901 * Determine the largest extended function value. 902 */ 903 x86_cpuid(0x80000000, descs); 904 lfunc = descs[0]; 905 906 /* 907 * Determine the extended feature flags. 908 */ 909 if (lfunc >= 0x80000001) { 910 x86_cpuid(0x80000001, descs); 911 ci->ci_feat_val[2] |= descs[3]; 912 } 913 914 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 915 return; 916 917 /* Nehemiah or Esther */ 918 x86_cpuid(0xc0000000, descs); 919 lfunc = descs[0]; 920 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 921 return; 922 923 x86_cpuid(0xc0000001, descs); 924 lfunc = descs[3]; 925 ci->ci_feat_val[4] = lfunc; 926 } 927 928 static void 929 amd_family6_probe(struct cpu_info *ci) 930 { 931 uint32_t descs[4]; 932 char *p; 933 size_t i; 934 935 x86_cpuid(0x80000000, descs); 936 937 /* 938 * Determine the extended feature flags. 939 */ 940 if (descs[0] >= 0x80000001) { 941 x86_cpuid(0x80000001, descs); 942 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 943 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 944 } 945 946 if (*cpu_brand_string == '\0') 947 return; 948 949 for (i = 1; i < __arraycount(amd_brand); i++) 950 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 951 ci->ci_brand_id = i; 952 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 953 break; 954 } 955 } 956 957 /* 958 * Get cache info from one of the following: 959 * Intel Deterministic Cache Parameter Leaf (0x04) 960 * AMD Cache Topology Information Leaf (0x8000001d) 961 */ 962 static void 963 cpu_dcp_cacheinfo(struct cpu_info *ci, uint32_t leaf) 964 { 965 u_int descs[4]; 966 int type, level, ways, partitions, linesize, sets, totalsize; 967 int caitype = -1; 968 int i; 969 970 for (i = 0; ; i++) { 971 x86_cpuid2(leaf, i, descs); 972 type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE); 973 if (type == CPUID_DCP_CACHETYPE_N) 974 break; 975 level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL); 976 switch (level) { 977 case 1: 978 if (type == CPUID_DCP_CACHETYPE_I) 979 caitype = CAI_ICACHE; 980 else if (type == CPUID_DCP_CACHETYPE_D) 981 caitype = CAI_DCACHE; 982 else 983 caitype = -1; 984 break; 985 case 2: 986 if (type == CPUID_DCP_CACHETYPE_U) 987 caitype = CAI_L2CACHE; 988 else 989 caitype = -1; 990 break; 991 case 3: 992 if (type == CPUID_DCP_CACHETYPE_U) 993 caitype = CAI_L3CACHE; 994 else 995 caitype = -1; 996 break; 997 default: 998 caitype = -1; 999 break; 1000 } 1001 if (caitype == -1) { 1002 aprint_error_dev(ci->ci_dev, 1003 "error: unknown cache level&type (%d & %d)\n", 1004 level, type); 1005 continue; 1006 } 1007 ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1; 1008 partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS) 1009 + 1; 1010 linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE) 1011 + 1; 1012 sets = descs[2] + 1; 1013 totalsize = ways * partitions * linesize * sets; 1014 ci->ci_cinfo[caitype].cai_totalsize = totalsize; 1015 ci->ci_cinfo[caitype].cai_associativity = ways; 1016 ci->ci_cinfo[caitype].cai_linesize = linesize; 1017 } 1018 } 1019 1020 static void 1021 intel_cpu_cacheinfo(struct cpu_info *ci) 1022 { 1023 const struct x86_cache_info *cai; 1024 u_int descs[4]; 1025 int iterations, i, j; 1026 int type, level, ways, linesize, sets; 1027 int caitype = -1; 1028 uint8_t desc; 1029 1030 /* Return if the cpu is old pre-cpuid instruction cpu */ 1031 if (ci->ci_cpu_type >= 0) 1032 return; 1033 1034 if (ci->ci_max_cpuid < 2) 1035 return; 1036 1037 /* 1038 * Parse the cache info from `cpuid leaf 2', if we have it. 1039 * XXX This is kinda ugly, but hey, so is the architecture... 1040 */ 1041 x86_cpuid(2, descs); 1042 iterations = descs[0] & 0xff; 1043 while (iterations-- > 0) { 1044 for (i = 0; i < 4; i++) { 1045 if (descs[i] & 0x80000000) 1046 continue; 1047 for (j = 0; j < 4; j++) { 1048 /* 1049 * The least significant byte in EAX 1050 * ((desc[0] >> 0) & 0xff) is always 0x01 and 1051 * it should be ignored. 1052 */ 1053 if (i == 0 && j == 0) 1054 continue; 1055 desc = (descs[i] >> (j * 8)) & 0xff; 1056 if (desc == 0) 1057 continue; 1058 cai = cache_info_lookup(intel_cpuid_cache_info, 1059 desc); 1060 if (cai != NULL) 1061 ci->ci_cinfo[cai->cai_index] = *cai; 1062 else if ((verbose != 0) && (desc != 0xff) 1063 && (desc != 0xfe)) 1064 aprint_error_dev(ci->ci_dev, "error:" 1065 " Unknown cacheinfo desc %02x\n", 1066 desc); 1067 } 1068 } 1069 x86_cpuid(2, descs); 1070 } 1071 1072 if (ci->ci_max_cpuid < 4) 1073 return; 1074 1075 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1076 cpu_dcp_cacheinfo(ci, 4); 1077 1078 if (ci->ci_max_cpuid < 0x18) 1079 return; 1080 /* Parse the TLB info from `cpuid leaf 18H', if we have it. */ 1081 x86_cpuid(0x18, descs); 1082 iterations = descs[0]; 1083 for (i = 0; i <= iterations; i++) { 1084 uint32_t pgsize; 1085 bool full; 1086 1087 x86_cpuid2(0x18, i, descs); 1088 type = __SHIFTOUT(descs[3], CPUID_DATP_TCTYPE); 1089 if (type == CPUID_DATP_TCTYPE_N) 1090 continue; 1091 level = __SHIFTOUT(descs[3], CPUID_DATP_TCLEVEL); 1092 pgsize = __SHIFTOUT(descs[1], CPUID_DATP_PGSIZE); 1093 switch (level) { 1094 case 1: 1095 if (type == CPUID_DATP_TCTYPE_I) { 1096 switch (pgsize) { 1097 case CPUID_DATP_PGSIZE_4KB: 1098 caitype = CAI_ITLB; 1099 break; 1100 case CPUID_DATP_PGSIZE_2MB 1101 | CPUID_DATP_PGSIZE_4MB: 1102 caitype = CAI_ITLB2; 1103 break; 1104 case CPUID_DATP_PGSIZE_1GB: 1105 caitype = CAI_L1_1GBITLB; 1106 break; 1107 default: 1108 aprint_error_dev(ci->ci_dev, 1109 "error: unknown ITLB size (%d)\n", 1110 pgsize); 1111 caitype = CAI_ITLB; 1112 break; 1113 } 1114 } else if (type == CPUID_DATP_TCTYPE_D) { 1115 switch (pgsize) { 1116 case CPUID_DATP_PGSIZE_4KB: 1117 caitype = CAI_DTLB; 1118 break; 1119 case CPUID_DATP_PGSIZE_2MB 1120 | CPUID_DATP_PGSIZE_4MB: 1121 caitype = CAI_DTLB2; 1122 break; 1123 case CPUID_DATP_PGSIZE_1GB: 1124 caitype = CAI_L1_1GBDTLB; 1125 break; 1126 default: 1127 aprint_error_dev(ci->ci_dev, 1128 "error: unknown DTLB size (%d)\n", 1129 pgsize); 1130 caitype = CAI_DTLB; 1131 break; 1132 } 1133 } else 1134 caitype = -1; 1135 break; 1136 case 2: 1137 if (type == CPUID_DATP_TCTYPE_I) 1138 caitype = CAI_L2_ITLB; 1139 else if (type == CPUID_DATP_TCTYPE_D) 1140 caitype = CAI_L2_DTLB; 1141 else if (type == CPUID_DATP_TCTYPE_U) { 1142 switch (pgsize) { 1143 case CPUID_DATP_PGSIZE_4KB: 1144 caitype = CAI_L2_STLB; 1145 break; 1146 case CPUID_DATP_PGSIZE_4KB 1147 | CPUID_DATP_PGSIZE_2MB: 1148 caitype = CAI_L2_STLB2; 1149 break; 1150 case CPUID_DATP_PGSIZE_2MB 1151 | CPUID_DATP_PGSIZE_4MB: 1152 caitype = CAI_L2_STLB3; 1153 break; 1154 default: 1155 aprint_error_dev(ci->ci_dev, 1156 "error: unknown L2 STLB size (%d)\n", 1157 pgsize); 1158 caitype = CAI_DTLB; 1159 break; 1160 } 1161 } else 1162 caitype = -1; 1163 break; 1164 case 3: 1165 /* XXX need work for L3 TLB */ 1166 caitype = CAI_L3CACHE; 1167 break; 1168 default: 1169 caitype = -1; 1170 break; 1171 } 1172 if (caitype == -1) { 1173 aprint_error_dev(ci->ci_dev, 1174 "error: unknown TLB level&type (%d & %d)\n", 1175 level, type); 1176 continue; 1177 } 1178 switch (pgsize) { 1179 case CPUID_DATP_PGSIZE_4KB: 1180 linesize = 4 * 1024; 1181 break; 1182 case CPUID_DATP_PGSIZE_2MB: 1183 linesize = 2 * 1024 * 1024; 1184 break; 1185 case CPUID_DATP_PGSIZE_4MB: 1186 linesize = 4 * 1024 * 1024; 1187 break; 1188 case CPUID_DATP_PGSIZE_1GB: 1189 linesize = 1024 * 1024 * 1024; 1190 break; 1191 case CPUID_DATP_PGSIZE_2MB | CPUID_DATP_PGSIZE_4MB: 1192 aprint_error_dev(ci->ci_dev, 1193 "WARINING: Currently 2M/4M info can't print correctly\n"); 1194 linesize = 4 * 1024 * 1024; 1195 break; 1196 default: 1197 aprint_error_dev(ci->ci_dev, 1198 "error: Unknown size combination\n"); 1199 linesize = 4 * 1024; 1200 break; 1201 } 1202 ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS); 1203 sets = descs[2]; 1204 full = descs[3] & CPUID_DATP_FULLASSOC; 1205 ci->ci_cinfo[caitype].cai_totalsize 1206 = ways * sets; /* entries */ 1207 ci->ci_cinfo[caitype].cai_associativity 1208 = full ? 0xff : ways; 1209 ci->ci_cinfo[caitype].cai_linesize = linesize; /* pg size */ 1210 } 1211 } 1212 1213 static const struct x86_cache_info amd_cpuid_l2l3cache_assoc_info[] = 1214 AMD_L2L3CACHE_INFO; 1215 1216 static void 1217 amd_cpu_cacheinfo(struct cpu_info *ci) 1218 { 1219 const struct x86_cache_info *cp; 1220 struct x86_cache_info *cai; 1221 u_int descs[4]; 1222 u_int lfunc; 1223 1224 /* K5 model 0 has none of this info. */ 1225 if (ci->ci_family == 5 && ci->ci_model == 0) 1226 return; 1227 1228 /* Determine the largest extended function value. */ 1229 x86_cpuid(0x80000000, descs); 1230 lfunc = descs[0]; 1231 1232 if (lfunc < 0x80000005) 1233 return; 1234 1235 /* Determine L1 cache/TLB info. */ 1236 x86_cpuid(0x80000005, descs); 1237 1238 /* K6-III and higher have large page TLBs. */ 1239 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1240 cai = &ci->ci_cinfo[CAI_ITLB2]; 1241 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1242 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1243 cai->cai_linesize = largepagesize; 1244 1245 cai = &ci->ci_cinfo[CAI_DTLB2]; 1246 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1247 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1248 cai->cai_linesize = largepagesize; 1249 } 1250 1251 cai = &ci->ci_cinfo[CAI_ITLB]; 1252 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1253 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1254 cai->cai_linesize = (4 * 1024); 1255 1256 cai = &ci->ci_cinfo[CAI_DTLB]; 1257 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1258 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1259 cai->cai_linesize = (4 * 1024); 1260 1261 cai = &ci->ci_cinfo[CAI_DCACHE]; 1262 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1263 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1264 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1265 1266 cai = &ci->ci_cinfo[CAI_ICACHE]; 1267 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1268 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1269 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1270 1271 if (lfunc < 0x80000006) 1272 return; 1273 1274 /* Determine L2 cache/TLB info. */ 1275 x86_cpuid(0x80000006, descs); 1276 1277 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1278 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1279 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1280 cai->cai_linesize = (4 * 1024); 1281 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1282 cai->cai_associativity); 1283 if (cp != NULL) 1284 cai->cai_associativity = cp->cai_associativity; 1285 else 1286 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1287 1288 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1289 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1290 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1291 cai->cai_linesize = largepagesize; 1292 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1293 cai->cai_associativity); 1294 if (cp != NULL) 1295 cai->cai_associativity = cp->cai_associativity; 1296 else 1297 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1298 1299 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1300 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1301 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1302 cai->cai_linesize = (4 * 1024); 1303 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1304 cai->cai_associativity); 1305 if (cp != NULL) 1306 cai->cai_associativity = cp->cai_associativity; 1307 else 1308 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1309 1310 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1311 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1312 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1313 cai->cai_linesize = largepagesize; 1314 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1315 cai->cai_associativity); 1316 if (cp != NULL) 1317 cai->cai_associativity = cp->cai_associativity; 1318 else 1319 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1320 1321 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1322 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1323 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1324 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1325 1326 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1327 cai->cai_associativity); 1328 if (cp != NULL) 1329 cai->cai_associativity = cp->cai_associativity; 1330 else 1331 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1332 1333 /* Determine L3 cache info on AMD Family 10h and newer processors */ 1334 if (ci->ci_family >= 0x10) { 1335 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1336 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1337 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1338 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1339 1340 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1341 cai->cai_associativity); 1342 if (cp != NULL) 1343 cai->cai_associativity = cp->cai_associativity; 1344 else 1345 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1346 } 1347 1348 if (lfunc < 0x80000019) 1349 return; 1350 1351 /* Determine 1GB TLB info. */ 1352 x86_cpuid(0x80000019, descs); 1353 1354 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1355 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1356 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1357 cai->cai_linesize = (1024 * 1024 * 1024); 1358 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1359 cai->cai_associativity); 1360 if (cp != NULL) 1361 cai->cai_associativity = cp->cai_associativity; 1362 else 1363 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1364 1365 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1366 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1367 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1368 cai->cai_linesize = (1024 * 1024 * 1024); 1369 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1370 cai->cai_associativity); 1371 if (cp != NULL) 1372 cai->cai_associativity = cp->cai_associativity; 1373 else 1374 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1375 1376 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1377 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1378 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1379 cai->cai_linesize = (1024 * 1024 * 1024); 1380 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1381 cai->cai_associativity); 1382 if (cp != NULL) 1383 cai->cai_associativity = cp->cai_associativity; 1384 else 1385 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1386 1387 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1388 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1389 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1390 cai->cai_linesize = (1024 * 1024 * 1024); 1391 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1392 cai->cai_associativity); 1393 if (cp != NULL) 1394 cai->cai_associativity = cp->cai_associativity; 1395 else 1396 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1397 1398 if (lfunc < 0x8000001d) 1399 return; 1400 1401 if (ci->ci_feat_val[3] & CPUID_TOPOEXT) 1402 cpu_dcp_cacheinfo(ci, 0x8000001d); 1403 } 1404 1405 static void 1406 via_cpu_cacheinfo(struct cpu_info *ci) 1407 { 1408 struct x86_cache_info *cai; 1409 int stepping; 1410 u_int descs[4]; 1411 u_int lfunc; 1412 1413 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1414 1415 /* 1416 * Determine the largest extended function value. 1417 */ 1418 x86_cpuid(0x80000000, descs); 1419 lfunc = descs[0]; 1420 1421 /* 1422 * Determine L1 cache/TLB info. 1423 */ 1424 if (lfunc < 0x80000005) { 1425 /* No L1 cache info available. */ 1426 return; 1427 } 1428 1429 x86_cpuid(0x80000005, descs); 1430 1431 cai = &ci->ci_cinfo[CAI_ITLB]; 1432 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1433 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1434 cai->cai_linesize = (4 * 1024); 1435 1436 cai = &ci->ci_cinfo[CAI_DTLB]; 1437 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1438 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1439 cai->cai_linesize = (4 * 1024); 1440 1441 cai = &ci->ci_cinfo[CAI_DCACHE]; 1442 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1443 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1444 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1445 if (ci->ci_model == 9 && stepping == 8) { 1446 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1447 cai->cai_associativity = 2; 1448 } 1449 1450 cai = &ci->ci_cinfo[CAI_ICACHE]; 1451 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1452 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1453 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1454 if (ci->ci_model == 9 && stepping == 8) { 1455 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1456 cai->cai_associativity = 2; 1457 } 1458 1459 /* 1460 * Determine L2 cache/TLB info. 1461 */ 1462 if (lfunc < 0x80000006) { 1463 /* No L2 cache info available. */ 1464 return; 1465 } 1466 1467 x86_cpuid(0x80000006, descs); 1468 1469 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1470 if (ci->ci_model >= 9) { 1471 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1472 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1473 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1474 } else { 1475 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1476 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1477 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1478 } 1479 } 1480 1481 static void 1482 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1483 { 1484 u_int descs[4]; 1485 1486 x86_cpuid(0x80860007, descs); 1487 *frequency = descs[0]; 1488 *voltage = descs[1]; 1489 *percentage = descs[2]; 1490 } 1491 1492 static void 1493 transmeta_cpu_info(struct cpu_info *ci) 1494 { 1495 u_int descs[4], nreg; 1496 u_int frequency, voltage, percentage; 1497 1498 x86_cpuid(0x80860000, descs); 1499 nreg = descs[0]; 1500 if (nreg >= 0x80860001) { 1501 x86_cpuid(0x80860001, descs); 1502 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1503 (descs[1] >> 24) & 0xff, 1504 (descs[1] >> 16) & 0xff, 1505 (descs[1] >> 8) & 0xff, 1506 descs[1] & 0xff); 1507 } 1508 if (nreg >= 0x80860002) { 1509 x86_cpuid(0x80860002, descs); 1510 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1511 (descs[1] >> 24) & 0xff, 1512 (descs[1] >> 16) & 0xff, 1513 (descs[1] >> 8) & 0xff, 1514 descs[1] & 0xff, 1515 descs[2]); 1516 } 1517 if (nreg >= 0x80860006) { 1518 union { 1519 char text[65]; 1520 u_int descs[4][4]; 1521 } info; 1522 int i; 1523 1524 for (i=0; i<4; i++) { 1525 x86_cpuid(0x80860003 + i, info.descs[i]); 1526 } 1527 info.text[64] = '\0'; 1528 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1529 } 1530 1531 if (nreg >= 0x80860007) { 1532 tmx86_get_longrun_status(&frequency, 1533 &voltage, &percentage); 1534 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1535 frequency, voltage, percentage); 1536 } 1537 } 1538 1539 static void 1540 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1541 { 1542 u_int descs[4]; 1543 int i; 1544 uint32_t brand[12]; 1545 1546 memset(ci, 0, sizeof(*ci)); 1547 ci->ci_dev = cpuname; 1548 1549 ci->ci_cpu_type = x86_identify(); 1550 if (ci->ci_cpu_type >= 0) { 1551 /* Old pre-cpuid instruction cpu */ 1552 ci->ci_max_cpuid = -1; 1553 return; 1554 } 1555 1556 /* 1557 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1558 * function. 1559 */ 1560 1561 /* 1562 * Fn0000_0000: 1563 * - Save cpuid max level. 1564 * - Save vendor string. 1565 */ 1566 x86_cpuid(0, descs); 1567 ci->ci_max_cpuid = descs[0]; 1568 /* Save vendor string */ 1569 ci->ci_vendor[0] = descs[1]; 1570 ci->ci_vendor[2] = descs[2]; 1571 ci->ci_vendor[1] = descs[3]; 1572 ci->ci_vendor[3] = 0; 1573 1574 /* 1575 * Fn8000_0000: 1576 * - Get cpuid extended function's max level. 1577 */ 1578 x86_cpuid(0x80000000, descs); 1579 if (descs[0] >= 0x80000000) 1580 ci->ci_max_ext_cpuid = descs[0]; 1581 else { 1582 /* Set lower value than 0x80000000 */ 1583 ci->ci_max_ext_cpuid = 0; 1584 } 1585 1586 /* 1587 * Fn8000_000[2-4]: 1588 * - Save brand string. 1589 */ 1590 if (ci->ci_max_ext_cpuid >= 0x80000004) { 1591 x86_cpuid(0x80000002, brand); 1592 x86_cpuid(0x80000003, brand + 4); 1593 x86_cpuid(0x80000004, brand + 8); 1594 for (i = 0; i < 48; i++) 1595 if (((char *) brand)[i] != ' ') 1596 break; 1597 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1598 } 1599 1600 if (ci->ci_max_cpuid < 1) 1601 return; 1602 1603 /* 1604 * Fn0000_0001: 1605 * - Get CPU family, model and stepping (from eax). 1606 * - Initial local APIC ID and brand ID (from ebx) 1607 * - CPUID2 (from ecx) 1608 * - CPUID (from edx) 1609 */ 1610 x86_cpuid(1, descs); 1611 ci->ci_signature = descs[0]; 1612 1613 /* Extract full family/model values */ 1614 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1615 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1616 1617 /* Brand is low order 8 bits of ebx */ 1618 ci->ci_brand_id = __SHIFTOUT(descs[1], CPUID_BRAND_INDEX); 1619 /* Initial local APIC ID */ 1620 ci->ci_initapicid = __SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID); 1621 1622 ci->ci_feat_val[1] = descs[2]; 1623 ci->ci_feat_val[0] = descs[3]; 1624 1625 if (ci->ci_max_cpuid < 3) 1626 return; 1627 1628 /* 1629 * If the processor serial number misfeature is present and supported, 1630 * extract it here. 1631 */ 1632 if ((ci->ci_feat_val[0] & CPUID_PSN) != 0) { 1633 ci->ci_cpu_serial[0] = ci->ci_signature; 1634 x86_cpuid(3, descs); 1635 ci->ci_cpu_serial[2] = descs[2]; 1636 ci->ci_cpu_serial[1] = descs[3]; 1637 } 1638 1639 if (ci->ci_max_cpuid < 0x7) 1640 return; 1641 1642 x86_cpuid(7, descs); 1643 ci->ci_feat_val[5] = descs[1]; 1644 ci->ci_feat_val[6] = descs[2]; 1645 ci->ci_feat_val[7] = descs[3]; 1646 1647 if (ci->ci_max_cpuid < 0xd) 1648 return; 1649 1650 /* Get support XCR0 bits */ 1651 x86_cpuid2(0xd, 0, descs); 1652 ci->ci_feat_val[8] = descs[0]; /* Actually 64 bits */ 1653 ci->ci_cur_xsave = descs[1]; 1654 ci->ci_max_xsave = descs[2]; 1655 1656 /* Additional flags (eg xsaveopt support) */ 1657 x86_cpuid2(0xd, 1, descs); 1658 ci->ci_feat_val[9] = descs[0]; /* Actually 64 bits */ 1659 } 1660 1661 static void 1662 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1663 { 1664 uint32_t descs[4]; 1665 char hv_sig[13]; 1666 char *p; 1667 const char *hv_name; 1668 int i; 1669 1670 /* 1671 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1672 * http://lkml.org/lkml/2008/10/1/246 1673 * 1674 * KB1009458: Mechanisms to determine if software is running in 1675 * a VMware virtual machine 1676 * http://kb.vmware.com/kb/1009458 1677 */ 1678 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1679 x86_cpuid(0x40000000, descs); 1680 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1681 memcpy(p, &descs[i], sizeof(descs[i])); 1682 *p = '\0'; 1683 /* 1684 * HV vendor ID string 1685 * ------------+-------------- 1686 * HAXM "HAXMHAXMHAXM" 1687 * KVM "KVMKVMKVM" 1688 * Microsoft "Microsoft Hv" 1689 * QEMU(TCG) "TCGTCGTCGTCG" 1690 * VMware "VMwareVMware" 1691 * Xen "XenVMMXenVMM" 1692 * NetBSD "___ NVMM ___" 1693 */ 1694 if (strncmp(hv_sig, "HAXMHAXMHAXM", 12) == 0) 1695 hv_name = "HAXM"; 1696 else if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1697 hv_name = "KVM"; 1698 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1699 hv_name = "Hyper-V"; 1700 else if (strncmp(hv_sig, "TCGTCGTCGTCG", 12) == 0) 1701 hv_name = "QEMU(TCG)"; 1702 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1703 hv_name = "VMware"; 1704 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1705 hv_name = "Xen"; 1706 else if (strncmp(hv_sig, "___ NVMM ___", 12) == 0) 1707 hv_name = "NVMM"; 1708 else 1709 hv_name = "unknown"; 1710 1711 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1712 } 1713 } 1714 1715 static void 1716 cpu_probe_features(struct cpu_info *ci) 1717 { 1718 const struct cpu_cpuid_nameclass *cpup = NULL; 1719 unsigned int i; 1720 1721 if (ci->ci_max_cpuid < 1) 1722 return; 1723 1724 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1725 if (!strncmp((char *)ci->ci_vendor, 1726 i386_cpuid_cpus[i].cpu_id, 12)) { 1727 cpup = &i386_cpuid_cpus[i]; 1728 break; 1729 } 1730 } 1731 1732 if (cpup == NULL) 1733 return; 1734 1735 i = ci->ci_family - CPU_MINFAMILY; 1736 1737 if (i >= __arraycount(cpup->cpu_family)) 1738 i = __arraycount(cpup->cpu_family) - 1; 1739 1740 if (cpup->cpu_family[i].cpu_probe == NULL) 1741 return; 1742 1743 (*cpup->cpu_family[i].cpu_probe)(ci); 1744 } 1745 1746 static void 1747 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1748 { 1749 char buf[32 * 16]; 1750 char *bp; 1751 1752 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1753 1754 if (val == 0 || fmt == NULL) 1755 return; 1756 1757 snprintb_m(buf, sizeof(buf), fmt, val, 1758 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1759 bp = buf; 1760 while (*bp != '\0') { 1761 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1762 bp += strlen(bp) + 1; 1763 } 1764 } 1765 1766 static void 1767 dump_descs(uint32_t leafstart, uint32_t leafend, const char *cpuname, 1768 const char *blockname) 1769 { 1770 uint32_t descs[4]; 1771 uint32_t leaf; 1772 1773 aprint_verbose("%s: highest %s info %08x\n", cpuname, blockname, 1774 leafend); 1775 1776 if (verbose) { 1777 for (leaf = leafstart; leaf <= leafend; leaf++) { 1778 x86_cpuid(leaf, descs); 1779 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1780 leaf, descs[0], descs[1], descs[2], descs[3]); 1781 } 1782 } 1783 } 1784 1785 static void 1786 identifycpu_cpuids_intel_0x04(struct cpu_info *ci) 1787 { 1788 u_int lp_max = 1; /* logical processors per package */ 1789 u_int smt_max; /* smt per core */ 1790 u_int core_max = 1; /* core per package */ 1791 u_int smt_bits, core_bits; 1792 uint32_t descs[4]; 1793 1794 /* 1795 * 253668.pdf 7.10.2 1796 */ 1797 1798 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1799 x86_cpuid(1, descs); 1800 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1801 } 1802 x86_cpuid2(4, 0, descs); 1803 core_max = __SHIFTOUT(descs[0], CPUID_DCP_CORE_P_PKG) + 1; 1804 1805 assert(lp_max >= core_max); 1806 smt_max = lp_max / core_max; 1807 smt_bits = ilog2(smt_max - 1) + 1; 1808 core_bits = ilog2(core_max - 1) + 1; 1809 1810 if (smt_bits + core_bits) 1811 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1812 1813 if (core_bits) 1814 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1815 __BITS(smt_bits, smt_bits + core_bits - 1)); 1816 1817 if (smt_bits) 1818 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1819 __BITS((int)0, (int)(smt_bits - 1))); 1820 } 1821 1822 static void 1823 identifycpu_cpuids_intel_0x0b(struct cpu_info *ci) 1824 { 1825 const char *cpuname = ci->ci_dev; 1826 u_int smt_bits, core_bits, core_shift = 0, pkg_shift = 0; 1827 uint32_t descs[4]; 1828 int i; 1829 1830 x86_cpuid(0x0b, descs); 1831 if (descs[1] == 0) { 1832 identifycpu_cpuids_intel_0x04(ci); 1833 return; 1834 } 1835 1836 for (i = 0; ; i++) { 1837 unsigned int shiftnum, lvltype; 1838 x86_cpuid2(0x0b, i, descs); 1839 1840 /* On invalid level, (EAX and) EBX return 0 */ 1841 if (descs[1] == 0) 1842 break; 1843 1844 shiftnum = __SHIFTOUT(descs[0], CPUID_TOP_SHIFTNUM); 1845 lvltype = __SHIFTOUT(descs[2], CPUID_TOP_LVLTYPE); 1846 switch (lvltype) { 1847 case CPUID_TOP_LVLTYPE_SMT: 1848 core_shift = shiftnum; 1849 break; 1850 case CPUID_TOP_LVLTYPE_CORE: 1851 pkg_shift = shiftnum; 1852 break; 1853 case CPUID_TOP_LVLTYPE_INVAL: 1854 aprint_verbose("%s: Invalid level type\n", cpuname); 1855 break; 1856 default: 1857 aprint_verbose("%s: Unknown level type(%d) \n", 1858 cpuname, lvltype); 1859 break; 1860 } 1861 } 1862 1863 assert(pkg_shift >= core_shift); 1864 smt_bits = core_shift; 1865 core_bits = pkg_shift - core_shift; 1866 1867 ci->ci_packageid = ci->ci_initapicid >> pkg_shift; 1868 1869 if (core_bits) 1870 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1871 __BITS(core_shift, pkg_shift - 1)); 1872 1873 if (smt_bits) 1874 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1875 __BITS((int)0, core_shift - 1)); 1876 } 1877 1878 static void 1879 identifycpu_cpuids_intel(struct cpu_info *ci) 1880 { 1881 const char *cpuname = ci->ci_dev; 1882 1883 if (ci->ci_max_cpuid >= 0x0b) 1884 identifycpu_cpuids_intel_0x0b(ci); 1885 else if (ci->ci_max_cpuid >= 4) 1886 identifycpu_cpuids_intel_0x04(ci); 1887 1888 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1889 ci->ci_packageid); 1890 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1891 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1892 } 1893 1894 static void 1895 identifycpu_cpuids_amd(struct cpu_info *ci) 1896 { 1897 const char *cpuname = ci->ci_dev; 1898 u_int lp_max, core_max; 1899 int n, cpu_family, apic_id, smt_bits, core_bits = 0; 1900 uint32_t descs[4]; 1901 1902 apic_id = ci->ci_initapicid; 1903 cpu_family = CPUID_TO_FAMILY(ci->ci_signature); 1904 1905 if (cpu_family < 0xf) 1906 return; 1907 1908 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1909 x86_cpuid(1, descs); 1910 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1911 1912 if (cpu_family >= 0x10 && ci->ci_max_ext_cpuid >= 0x8000008) { 1913 x86_cpuid(0x8000008, descs); 1914 core_max = (descs[2] & 0xff) + 1; 1915 n = (descs[2] >> 12) & 0x0f; 1916 if (n != 0) 1917 core_bits = n; 1918 } 1919 } else { 1920 lp_max = 1; 1921 } 1922 core_max = lp_max; 1923 1924 smt_bits = ilog2((lp_max / core_max) - 1) + 1; 1925 if (core_bits == 0) 1926 core_bits = ilog2(core_max - 1) + 1; 1927 1928 #if 0 /* MSRs need kernel mode */ 1929 if (cpu_family < 0x11) { 1930 const uint64_t reg = rdmsr(MSR_NB_CFG); 1931 if ((reg & NB_CFG_INITAPICCPUIDLO) == 0) { 1932 const u_int node_id = apic_id & __BITS(0, 2); 1933 apic_id = (cpu_family == 0xf) ? 1934 (apic_id >> core_bits) | (node_id << core_bits) : 1935 (apic_id >> 5) | (node_id << 2); 1936 } 1937 } 1938 #endif 1939 1940 if (cpu_family == 0x17) { 1941 x86_cpuid(0x8000001e, descs); 1942 const u_int threads = ((descs[1] >> 8) & 0xff) + 1; 1943 smt_bits = ilog2(threads); 1944 core_bits -= smt_bits; 1945 } 1946 1947 if (smt_bits + core_bits) { 1948 if (smt_bits + core_bits < 32) 1949 ci->ci_packageid = 0; 1950 } 1951 if (core_bits) { 1952 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1953 ci->ci_coreid = __SHIFTOUT(apic_id, core_mask); 1954 } 1955 if (smt_bits) { 1956 u_int smt_mask = __BITS(0, smt_bits - 1); 1957 ci->ci_smtid = __SHIFTOUT(apic_id, smt_mask); 1958 } 1959 1960 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1961 ci->ci_packageid); 1962 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1963 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1964 } 1965 1966 static void 1967 identifycpu_cpuids(struct cpu_info *ci) 1968 { 1969 const char *cpuname = ci->ci_dev; 1970 1971 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1972 ci->ci_packageid = ci->ci_initapicid; 1973 ci->ci_coreid = 0; 1974 ci->ci_smtid = 0; 1975 1976 if (cpu_vendor == CPUVENDOR_INTEL) 1977 identifycpu_cpuids_intel(ci); 1978 else if (cpu_vendor == CPUVENDOR_AMD) 1979 identifycpu_cpuids_amd(ci); 1980 } 1981 1982 void 1983 identifycpu(int fd, const char *cpuname) 1984 { 1985 const char *name = "", *modifier, *vendorname, *brand = ""; 1986 int class = CPUCLASS_386; 1987 unsigned int i; 1988 int modif, family; 1989 const struct cpu_cpuid_nameclass *cpup = NULL; 1990 const struct cpu_cpuid_family *cpufam; 1991 struct cpu_info *ci, cistore; 1992 u_int descs[4]; 1993 size_t sz; 1994 struct cpu_ucode_version ucode; 1995 union { 1996 struct cpu_ucode_version_amd amd; 1997 struct cpu_ucode_version_intel1 intel1; 1998 } ucvers; 1999 2000 ci = &cistore; 2001 cpu_probe_base_features(ci, cpuname); 2002 dump_descs(0x00000000, ci->ci_max_cpuid, cpuname, "basic"); 2003 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 2004 x86_cpuid(0x40000000, descs); 2005 dump_descs(0x40000000, descs[0], cpuname, "hypervisor"); 2006 } 2007 dump_descs(0x80000000, ci->ci_max_ext_cpuid, cpuname, "extended"); 2008 2009 cpu_probe_hv_features(ci, cpuname); 2010 cpu_probe_features(ci); 2011 2012 if (ci->ci_cpu_type >= 0) { 2013 /* Old pre-cpuid instruction cpu */ 2014 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 2015 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 2016 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 2017 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 2018 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 2019 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 2020 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 2021 modifier = ""; 2022 } else { 2023 /* CPU which support cpuid instruction */ 2024 modif = (ci->ci_signature >> 12) & 0x3; 2025 family = ci->ci_family; 2026 if (family < CPU_MINFAMILY) 2027 errx(1, "identifycpu: strange family value"); 2028 if (family > CPU_MAXFAMILY) 2029 family = CPU_MAXFAMILY; 2030 2031 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 2032 if (!strncmp((char *)ci->ci_vendor, 2033 i386_cpuid_cpus[i].cpu_id, 12)) { 2034 cpup = &i386_cpuid_cpus[i]; 2035 break; 2036 } 2037 } 2038 2039 if (cpup == NULL) { 2040 cpu_vendor = CPUVENDOR_UNKNOWN; 2041 if (ci->ci_vendor[0] != '\0') 2042 vendorname = (char *)&ci->ci_vendor[0]; 2043 else 2044 vendorname = "Unknown"; 2045 class = family - 3; 2046 modifier = ""; 2047 name = ""; 2048 ci->ci_info = NULL; 2049 } else { 2050 cpu_vendor = cpup->cpu_vendor; 2051 vendorname = cpup->cpu_vendorname; 2052 modifier = modifiers[modif]; 2053 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 2054 name = cpufam->cpu_models[ci->ci_model]; 2055 if (name == NULL || *name == '\0') 2056 name = cpufam->cpu_model_default; 2057 class = cpufam->cpu_class; 2058 ci->ci_info = cpufam->cpu_info; 2059 2060 if (cpu_vendor == CPUVENDOR_INTEL) { 2061 if (ci->ci_family == 6 && ci->ci_model >= 5) { 2062 const char *tmp; 2063 tmp = intel_family6_name(ci); 2064 if (tmp != NULL) 2065 name = tmp; 2066 } 2067 if (ci->ci_family == 15 && 2068 ci->ci_brand_id < 2069 __arraycount(i386_intel_brand) && 2070 i386_intel_brand[ci->ci_brand_id]) 2071 name = 2072 i386_intel_brand[ci->ci_brand_id]; 2073 } 2074 2075 if (cpu_vendor == CPUVENDOR_AMD) { 2076 if (ci->ci_family == 6 && ci->ci_model >= 6) { 2077 if (ci->ci_brand_id == 1) 2078 /* 2079 * It's Duron. We override the 2080 * name, since it might have 2081 * been misidentified as Athlon. 2082 */ 2083 name = 2084 amd_brand[ci->ci_brand_id]; 2085 else 2086 brand = amd_brand_name; 2087 } 2088 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 2089 == 0xf) { 2090 /* Identify AMD64 CPU names. */ 2091 const char *tmp; 2092 tmp = amd_amd64_name(ci); 2093 if (tmp != NULL) 2094 name = tmp; 2095 } 2096 } 2097 2098 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 2099 vendorname = "VIA"; 2100 } 2101 } 2102 2103 ci->ci_cpu_class = class; 2104 2105 sz = sizeof(ci->ci_tsc_freq); 2106 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 2107 sz = sizeof(use_pae); 2108 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 2109 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 2110 2111 /* 2112 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 2113 * we try to determine from the family/model values. 2114 */ 2115 if (*cpu_brand_string != '\0') 2116 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 2117 2118 aprint_normal("%s: %s", cpuname, vendorname); 2119 if (*modifier) 2120 aprint_normal(" %s", modifier); 2121 if (*name) 2122 aprint_normal(" %s", name); 2123 if (*brand) 2124 aprint_normal(" %s", brand); 2125 aprint_normal(" (%s-class)", classnames[class]); 2126 2127 if (ci->ci_tsc_freq != 0) 2128 aprint_normal(", %ju.%02ju MHz", 2129 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 2130 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 2131 aprint_normal("\n"); 2132 2133 (void)cpu_tsc_freq_cpuid(ci); 2134 2135 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 2136 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 2137 if (ci->ci_signature != 0) 2138 aprint_normal(" (id %#x)", ci->ci_signature); 2139 aprint_normal("\n"); 2140 2141 if (ci->ci_info) 2142 (*ci->ci_info)(ci); 2143 2144 /* 2145 * display CPU feature flags 2146 */ 2147 2148 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 2149 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 2150 2151 /* These next two are actually common definitions! */ 2152 print_bits(cpuname, "features2", 2153 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 2154 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 2155 print_bits(cpuname, "features3", 2156 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 2157 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 2158 2159 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 2160 ci->ci_feat_val[4]); 2161 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2162 print_bits(cpuname, "features5", CPUID_SEF_FLAGS, 2163 ci->ci_feat_val[5]); 2164 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2165 print_bits(cpuname, "features6", CPUID_SEF_FLAGS1, 2166 ci->ci_feat_val[6]); 2167 2168 if (cpu_vendor == CPUVENDOR_INTEL) 2169 print_bits(cpuname, "features7", CPUID_SEF_FLAGS2, 2170 ci->ci_feat_val[7]); 2171 2172 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[8]); 2173 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 2174 ci->ci_feat_val[9]); 2175 2176 if (ci->ci_max_xsave != 0) { 2177 aprint_normal("%s: xsave area size: current %d, maximum %d", 2178 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 2179 aprint_normal(", xgetbv %sabled\n", 2180 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 2181 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 2182 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 2183 x86_xgetbv()); 2184 } 2185 2186 x86_print_cache_and_tlb_info(ci); 2187 2188 if (ci->ci_max_cpuid >= 3 && (ci->ci_feat_val[0] & CPUID_PSN)) { 2189 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 2190 cpuname, 2191 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 2192 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 2193 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 2194 } 2195 2196 if (ci->ci_cpu_class == CPUCLASS_386) 2197 errx(1, "NetBSD requires an 80486 or later processor"); 2198 2199 if (ci->ci_cpu_type == CPU_486DLC) { 2200 #ifndef CYRIX_CACHE_WORKS 2201 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 2202 #else 2203 #ifndef CYRIX_CACHE_REALLY_WORKS 2204 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 2205 #else 2206 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 2207 #endif 2208 #endif 2209 } 2210 2211 /* 2212 * Everything past this point requires a Pentium or later. 2213 */ 2214 if (ci->ci_max_cpuid < 0) 2215 return; 2216 2217 identifycpu_cpuids(ci); 2218 2219 if ((ci->ci_max_cpuid >= 5) 2220 && ((cpu_vendor == CPUVENDOR_INTEL) 2221 || (cpu_vendor == CPUVENDOR_AMD))) { 2222 uint16_t lmin, lmax; 2223 x86_cpuid(5, descs); 2224 2225 print_bits(cpuname, "MONITOR/MWAIT extensions", 2226 CPUID_MON_FLAGS, descs[2]); 2227 lmin = __SHIFTOUT(descs[0], CPUID_MON_MINSIZE); 2228 lmax = __SHIFTOUT(descs[1], CPUID_MON_MAXSIZE); 2229 aprint_normal("%s: monitor-line size %hu", cpuname, lmin); 2230 if (lmin != lmax) 2231 aprint_normal("-%hu", lmax); 2232 aprint_normal("\n"); 2233 2234 for (i = 0; i <= 7; i++) { 2235 unsigned int num = CPUID_MON_SUBSTATE(descs[3], i); 2236 2237 if (num != 0) 2238 aprint_normal("%s: C%u substates %u\n", 2239 cpuname, i, num); 2240 } 2241 } 2242 if ((ci->ci_max_cpuid >= 6) 2243 && ((cpu_vendor == CPUVENDOR_INTEL) 2244 || (cpu_vendor == CPUVENDOR_AMD))) { 2245 x86_cpuid(6, descs); 2246 print_bits(cpuname, "DSPM-eax", CPUID_DSPM_FLAGS, descs[0]); 2247 print_bits(cpuname, "DSPM-ecx", CPUID_DSPM_FLAGS1, descs[2]); 2248 } 2249 if ((ci->ci_max_cpuid >= 7) 2250 && ((cpu_vendor == CPUVENDOR_INTEL) 2251 || (cpu_vendor == CPUVENDOR_AMD))) { 2252 x86_cpuid(7, descs); 2253 aprint_verbose("%s: SEF highest subleaf %08x\n", 2254 cpuname, descs[0]); 2255 if (descs[0] >= 1) { 2256 x86_cpuid2(7, 1, descs); 2257 print_bits(cpuname, "SEF-subleaf1-eax", 2258 CPUID_SEF1_FLAGS_A, descs[0]); 2259 } 2260 } 2261 2262 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) { 2263 if (ci->ci_max_ext_cpuid >= 0x80000007) 2264 powernow_probe(ci); 2265 2266 if (ci->ci_max_ext_cpuid >= 0x80000008) { 2267 x86_cpuid(0x80000008, descs); 2268 print_bits(cpuname, "AMD Extended features", 2269 CPUID_CAPEX_FLAGS, descs[1]); 2270 } 2271 } 2272 2273 if (cpu_vendor == CPUVENDOR_AMD) { 2274 if ((ci->ci_max_ext_cpuid >= 0x8000000a) 2275 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 2276 x86_cpuid(0x8000000a, descs); 2277 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 2278 descs[0] & 0xf); 2279 aprint_verbose("%s: SVM NASID %d\n", cpuname, 2280 descs[1]); 2281 print_bits(cpuname, "SVM features", 2282 CPUID_AMD_SVM_FLAGS, descs[3]); 2283 } 2284 if (ci->ci_max_ext_cpuid >= 0x8000001f) { 2285 x86_cpuid(0x8000001f, descs); 2286 print_bits(cpuname, "Encrypted Memory features", 2287 CPUID_AMD_ENCMEM_FLAGS, descs[0]); 2288 } 2289 } else if (cpu_vendor == CPUVENDOR_INTEL) { 2290 int32_t bi_index; 2291 2292 for (bi_index = 1; bi_index <= ci->ci_max_cpuid; bi_index++) { 2293 x86_cpuid(bi_index, descs); 2294 switch (bi_index) { 2295 case 0x0a: 2296 print_bits(cpuname, "Perfmon-eax", 2297 CPUID_PERF_FLAGS0, descs[0]); 2298 print_bits(cpuname, "Perfmon-ebx", 2299 CPUID_PERF_FLAGS1, descs[1]); 2300 print_bits(cpuname, "Perfmon-edx", 2301 CPUID_PERF_FLAGS3, descs[3]); 2302 break; 2303 default: 2304 #if 0 2305 aprint_verbose("%s: basic %08x-eax %08x\n", 2306 cpuname, bi_index, descs[0]); 2307 aprint_verbose("%s: basic %08x-ebx %08x\n", 2308 cpuname, bi_index, descs[1]); 2309 aprint_verbose("%s: basic %08x-ecx %08x\n", 2310 cpuname, bi_index, descs[2]); 2311 aprint_verbose("%s: basic %08x-edx %08x\n", 2312 cpuname, bi_index, descs[3]); 2313 #endif 2314 break; 2315 } 2316 } 2317 } 2318 2319 #ifdef INTEL_ONDEMAND_CLOCKMOD 2320 clockmod_init(); 2321 #endif 2322 2323 if (cpu_vendor == CPUVENDOR_AMD) 2324 ucode.loader_version = CPU_UCODE_LOADER_AMD; 2325 else if (cpu_vendor == CPUVENDOR_INTEL) 2326 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 2327 else 2328 return; 2329 2330 ucode.data = &ucvers; 2331 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 2332 #ifdef __i386__ 2333 struct cpu_ucode_version_64 ucode_64; 2334 if (errno != ENOTTY) 2335 return; 2336 /* Try the 64 bit ioctl */ 2337 memset(&ucode_64, 0, sizeof ucode_64); 2338 ucode_64.data = &ucvers; 2339 ucode_64.loader_version = ucode.loader_version; 2340 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 2341 return; 2342 #else 2343 return; 2344 #endif 2345 } 2346 2347 if (cpu_vendor == CPUVENDOR_AMD) 2348 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2349 else if (cpu_vendor == CPUVENDOR_INTEL) 2350 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2351 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2352 } 2353 2354 static const struct x86_cache_info * 2355 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 2356 { 2357 int i; 2358 2359 for (i = 0; cai[i].cai_desc != 0; i++) { 2360 if (cai[i].cai_desc == desc) 2361 return (&cai[i]); 2362 } 2363 2364 return (NULL); 2365 } 2366 2367 static const char * 2368 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2369 const char *sep) 2370 { 2371 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2372 char human_num[HUMAN_BUFSIZE]; 2373 2374 if (cai->cai_totalsize == 0) 2375 return sep; 2376 2377 if (sep == NULL) 2378 aprint_verbose_dev(ci->ci_dev, ""); 2379 else 2380 aprint_verbose("%s", sep); 2381 if (name != NULL) 2382 aprint_verbose("%s ", name); 2383 2384 if (cai->cai_string != NULL) { 2385 aprint_verbose("%s ", cai->cai_string); 2386 } else { 2387 (void)humanize_number(human_num, sizeof(human_num), 2388 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2389 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2390 } 2391 switch (cai->cai_associativity) { 2392 case 0: 2393 aprint_verbose("disabled"); 2394 break; 2395 case 1: 2396 aprint_verbose("direct-mapped"); 2397 break; 2398 case 0xff: 2399 aprint_verbose("fully associative"); 2400 break; 2401 default: 2402 aprint_verbose("%d-way", cai->cai_associativity); 2403 break; 2404 } 2405 return ", "; 2406 } 2407 2408 static const char * 2409 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2410 const char *sep) 2411 { 2412 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2413 char human_num[HUMAN_BUFSIZE]; 2414 2415 if (cai->cai_totalsize == 0) 2416 return sep; 2417 2418 if (sep == NULL) 2419 aprint_verbose_dev(ci->ci_dev, ""); 2420 else 2421 aprint_verbose("%s", sep); 2422 if (name != NULL) 2423 aprint_verbose("%s ", name); 2424 2425 if (cai->cai_string != NULL) { 2426 aprint_verbose("%s", cai->cai_string); 2427 } else { 2428 (void)humanize_number(human_num, sizeof(human_num), 2429 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2430 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2431 human_num); 2432 switch (cai->cai_associativity) { 2433 case 0: 2434 aprint_verbose("disabled"); 2435 break; 2436 case 1: 2437 aprint_verbose("direct-mapped"); 2438 break; 2439 case 0xff: 2440 aprint_verbose("fully associative"); 2441 break; 2442 default: 2443 aprint_verbose("%d-way", cai->cai_associativity); 2444 break; 2445 } 2446 } 2447 return ", "; 2448 } 2449 2450 static void 2451 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2452 { 2453 const char *sep = NULL; 2454 2455 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2456 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2457 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 2458 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 2459 if (sep != NULL) 2460 aprint_verbose("\n"); 2461 } 2462 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2463 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 2464 if (sep != NULL) 2465 aprint_verbose("\n"); 2466 } 2467 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2468 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 2469 if (sep != NULL) 2470 aprint_verbose("\n"); 2471 } 2472 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2473 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2474 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2475 if (sep != NULL) 2476 aprint_verbose("\n"); 2477 } 2478 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 2479 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 2480 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 2481 if (sep != NULL) 2482 aprint_verbose("\n"); 2483 } 2484 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 2485 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 2486 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 2487 if (sep != NULL) 2488 aprint_verbose("\n"); 2489 } 2490 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 2491 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 2492 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 2493 if (sep != NULL) 2494 aprint_verbose("\n"); 2495 } 2496 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 2497 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 2498 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 2499 if (sep != NULL) 2500 aprint_verbose("\n"); 2501 } 2502 if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) { 2503 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL); 2504 sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep); 2505 sep = print_tlb_config(ci, CAI_L2_STLB3, NULL, sep); 2506 if (sep != NULL) 2507 aprint_verbose("\n"); 2508 } 2509 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 2510 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", 2511 NULL); 2512 if (sep != NULL) 2513 aprint_verbose("\n"); 2514 } 2515 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 2516 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", 2517 NULL); 2518 if (sep != NULL) 2519 aprint_verbose("\n"); 2520 } 2521 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 2522 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", 2523 NULL); 2524 if (sep != NULL) 2525 aprint_verbose("\n"); 2526 } 2527 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 2528 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", 2529 NULL); 2530 if (sep != NULL) 2531 aprint_verbose("\n"); 2532 } 2533 } 2534 2535 static void 2536 powernow_probe(struct cpu_info *ci) 2537 { 2538 uint32_t regs[4]; 2539 char buf[256]; 2540 2541 x86_cpuid(0x80000007, regs); 2542 2543 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2544 aprint_normal_dev(ci->ci_dev, "Power Management features: %s\n", buf); 2545 } 2546 2547 bool 2548 identifycpu_bind(void) 2549 { 2550 2551 return true; 2552 } 2553 2554 int 2555 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2556 { 2557 struct cpu_info ci; 2558 int loader_version, res; 2559 struct cpu_ucode_version versreq; 2560 2561 cpu_probe_base_features(&ci, "unknown"); 2562 2563 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2564 loader_version = CPU_UCODE_LOADER_AMD; 2565 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2566 loader_version = CPU_UCODE_LOADER_INTEL1; 2567 else 2568 return -1; 2569 2570 /* check whether the kernel understands this loader version */ 2571 versreq.loader_version = loader_version; 2572 versreq.data = 0; 2573 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2574 if (res) 2575 return -1; 2576 2577 switch (loader_version) { 2578 case CPU_UCODE_LOADER_AMD: 2579 if (uc->cpu_nr != -1) { 2580 /* printf? */ 2581 return -1; 2582 } 2583 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2584 break; 2585 case CPU_UCODE_LOADER_INTEL1: 2586 if (uc->cpu_nr == -1) 2587 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2588 else 2589 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2590 break; 2591 default: /* can't happen */ 2592 return -1; 2593 } 2594 uc->loader_version = loader_version; 2595 return 0; 2596 } 2597
Indexes created Fri Sep 26 20:09:58 GMT 2025