i386.c revision 1.119
1 /* $NetBSD: i386.c,v 1.119 2021/09/27 16:47:15 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.119 2021/09/27 16:47:15 msaitoh Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cpu_ucode.h> 85 86 #include "../cpuctl.h" 87 #include "cpuctl_i386.h" 88 89 /* Size of buffer for printing humanized numbers */ 90 #define HUMAN_BUFSIZE sizeof("999KB") 91 92 struct cpu_nocpuid_nameclass { 93 int cpu_vendor; 94 const char *cpu_vendorname; 95 const char *cpu_name; 96 int cpu_class; 97 void (*cpu_setup)(struct cpu_info *); 98 void (*cpu_cacheinfo)(struct cpu_info *); 99 void (*cpu_info)(struct cpu_info *); 100 }; 101 102 struct cpu_cpuid_nameclass { 103 const char *cpu_id; 104 int cpu_vendor; 105 const char *cpu_vendorname; 106 struct cpu_cpuid_family { 107 int cpu_class; 108 const char *cpu_models[256]; 109 const char *cpu_model_default; 110 void (*cpu_setup)(struct cpu_info *); 111 void (*cpu_probe)(struct cpu_info *); 112 void (*cpu_info)(struct cpu_info *); 113 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 114 }; 115 116 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 117 118 /* 119 * Map Brand ID from cpuid instruction to brand name. 120 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 121 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 122 * Architectures Software Developer's Manual, Volume 2A". 123 */ 124 static const char * const i386_intel_brand[] = { 125 "", /* Unsupported */ 126 "Celeron", /* Intel (R) Celeron (TM) processor */ 127 "Pentium III", /* Intel (R) Pentium (R) III processor */ 128 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 129 "Pentium III", /* Intel (R) Pentium (R) III processor */ 130 "", /* 0x05: Reserved */ 131 "Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */ 132 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 133 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 134 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 135 "Celeron", /* Intel (R) Celeron (TM) processor */ 136 "Xeon", /* Intel (R) Xeon (TM) processor */ 137 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 138 "", /* 0x0d: Reserved */ 139 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 140 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 141 "", /* 0x10: Reserved */ 142 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 143 "Celeron M", /* Intel (R) Celeron (R) M processor */ 144 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 145 "Celeron", /* Intel (R) Celeron (R) processor */ 146 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 147 "Pentium M", /* Intel (R) Pentium (R) M processor */ 148 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 149 }; 150 151 /* 152 * AMD processors don't have Brand IDs, so we need these names for probe. 153 */ 154 static const char * const amd_brand[] = { 155 "", 156 "Duron", /* AMD Duron(tm) */ 157 "MP", /* AMD Athlon(tm) MP */ 158 "XP", /* AMD Athlon(tm) XP */ 159 "4" /* AMD Athlon(tm) 4 */ 160 }; 161 162 int cpu_vendor; 163 static char cpu_brand_string[49]; 164 static char amd_brand_name[48]; 165 static int use_pae, largepagesize; 166 167 /* Setup functions */ 168 static void disable_tsc(struct cpu_info *); 169 static void amd_family5_setup(struct cpu_info *); 170 static void cyrix6x86_cpu_setup(struct cpu_info *); 171 static void winchip_cpu_setup(struct cpu_info *); 172 /* Brand/Model name functions */ 173 static const char *intel_family6_name(struct cpu_info *); 174 static const char *amd_amd64_name(struct cpu_info *); 175 /* Probe functions */ 176 static void amd_family6_probe(struct cpu_info *); 177 static void powernow_probe(struct cpu_info *); 178 static void intel_family_new_probe(struct cpu_info *); 179 static void via_cpu_probe(struct cpu_info *); 180 /* (Cache) Info functions */ 181 static void cpu_dcp_cacheinfo(struct cpu_info *, uint32_t); 182 static void intel_cpu_cacheinfo(struct cpu_info *); 183 static void amd_cpu_cacheinfo(struct cpu_info *); 184 static void via_cpu_cacheinfo(struct cpu_info *); 185 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 186 static void transmeta_cpu_info(struct cpu_info *); 187 /* Common functions */ 188 static void cpu_probe_base_features(struct cpu_info *, const char *); 189 static void cpu_probe_hv_features(struct cpu_info *, const char *); 190 static void cpu_probe_features(struct cpu_info *); 191 static void print_bits(const char *, const char *, const char *, uint32_t); 192 static void identifycpu_cpuids(struct cpu_info *); 193 static const struct x86_cache_info *cache_info_lookup( 194 const struct x86_cache_info *, uint8_t); 195 static const char *print_cache_config(struct cpu_info *, int, const char *, 196 const char *); 197 static const char *print_tlb_config(struct cpu_info *, int, const char *, 198 const char *); 199 static void x86_print_cache_and_tlb_info(struct cpu_info *); 200 201 /* 202 * Note: these are just the ones that may not have a cpuid instruction. 203 * We deal with the rest in a different way. 204 */ 205 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 206 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 207 NULL, NULL, NULL }, /* CPU_386SX */ 208 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 209 NULL, NULL, NULL }, /* CPU_386 */ 210 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 211 NULL, NULL, NULL }, /* CPU_486SX */ 212 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 213 NULL, NULL, NULL }, /* CPU_486 */ 214 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 215 NULL, NULL, NULL }, /* CPU_486DLC */ 216 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 217 NULL, NULL, NULL }, /* CPU_6x86 */ 218 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 219 NULL, NULL, NULL }, /* CPU_NX586 */ 220 }; 221 222 const char *classnames[] = { 223 "386", 224 "486", 225 "586", 226 "686" 227 }; 228 229 const char *modifiers[] = { 230 "", 231 "OverDrive", 232 "Dual", 233 "" 234 }; 235 236 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 237 { 238 /* 239 * For Intel processors, check Chapter 35Model-specific 240 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 241 * Software Developer's Manual, Volume 3C". 242 */ 243 "GenuineIntel", 244 CPUVENDOR_INTEL, 245 "Intel", 246 /* Family 4 */ 247 { { 248 CPUCLASS_486, 249 { 250 "486DX", "486DX", "486SX", "486DX2", "486SL", 251 "486SX2", 0, "486DX2 W/B Enhanced", 252 "486DX4", 0, 0, 0, 0, 0, 0, 0, 253 }, 254 "486", /* Default */ 255 NULL, 256 NULL, 257 intel_cpu_cacheinfo, 258 }, 259 /* Family 5 */ 260 { 261 CPUCLASS_586, 262 { 263 "Pentium (P5 A-step)", "Pentium (P5)", 264 "Pentium (P54C)", "Pentium (P24T)", 265 "Pentium/MMX", "Pentium", 0, 266 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 267 "Quark X1000", 0, 0, 0, 0, 0, 0, 268 }, 269 "Pentium", /* Default */ 270 NULL, 271 NULL, 272 intel_cpu_cacheinfo, 273 }, 274 /* Family 6 */ 275 { 276 CPUCLASS_686, 277 { 278 [0x00] = "Pentium Pro (A-step)", 279 [0x01] = "Pentium Pro", 280 [0x03] = "Pentium II (Klamath)", 281 [0x04] = "Pentium Pro", 282 [0x05] = "Pentium II/Celeron (Deschutes)", 283 [0x06] = "Celeron (Mendocino)", 284 [0x07] = "Pentium III (Katmai)", 285 [0x08] = "Pentium III (Coppermine)", 286 [0x09] = "Pentium M (Banias)", 287 [0x0a] = "Pentium III Xeon (Cascades)", 288 [0x0b] = "Pentium III (Tualatin)", 289 [0x0d] = "Pentium M (Dothan)", 290 [0x0e] = "Pentium Core Duo, Core solo", 291 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 292 "Core 2 Quad 6xxx, " 293 "Core 2 Extreme 6xxx, " 294 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 295 "and Pentium DC", 296 [0x15] = "EP80579 Integrated Processor", 297 [0x16] = "Celeron (45nm)", 298 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 299 "Core 2 Quad 8xxx and 9xxx", 300 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 301 "(Nehalem)", 302 [0x1c] = "45nm Atom Family", 303 [0x1d] = "XeonMP 74xx (Nehalem)", 304 [0x1e] = "Core i7 and i5", 305 [0x1f] = "Core i7 and i5", 306 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 307 [0x26] = "Atom Family", 308 [0x27] = "Atom Family", 309 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 310 "i3 2xxx", 311 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 312 [0x2d] = "Xeon E5 Sandy Bridge family, " 313 "Core i7-39xx Extreme", 314 [0x2e] = "Xeon 75xx & 65xx", 315 [0x2f] = "Xeon E7 family", 316 [0x35] = "Atom Family", 317 [0x36] = "Atom S1000", 318 [0x37] = "Atom E3000, Z3[67]00", 319 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 320 "Ivy Bridge", 321 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 322 "(Haswell)", 323 [0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)", 324 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 325 "Core i7-49xx Extreme", 326 [0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), " 327 "Core i7-59xx Extreme", 328 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 329 "(Haswell)", 330 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 331 "(Haswell)", 332 [0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)", 333 [0x4a] = "Atom Z3400", 334 [0x4c] = "Atom X[57]-Z8000 (Airmont)", 335 [0x4d] = "Atom C2000", 336 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 337 [0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme", 338 [0x55] = "Xeon Scalable (Skylake, Cascade Lake, Copper Lake)", 339 [0x56] = "Xeon D-1500 (Broadwell)", 340 [0x57] = "Xeon Phi [357]200 (Knights Landing)", 341 [0x5a] = "Atom E3500", 342 [0x5c] = "Atom (Goldmont)", 343 [0x5d] = "Atom X3-C3000 (Silvermont)", 344 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 345 [0x5f] = "Atom (Goldmont, Denverton)", 346 [0x66] = "8th gen Core i3 (Cannon Lake)", 347 [0x6a] = "3rd gen Xeon Scalable (Ice Lake)", 348 [0x6c] = "3rd gen Xeon Scalable (Ice Lake)", 349 [0x7a] = "Atom (Goldmont Plus)", 350 [0x7d] = "10th gen Core (Ice Lake)", 351 [0x7e] = "10th gen Core (Ice Lake)", 352 [0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)", 353 [0x86] = "Atom (Tremont)", 354 [0x8c] = "11th gen Core (Tiger Lake)", 355 [0x8d] = "11th gen Core (Tiger Lake)", 356 [0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 357 [0x96] = "Atom x6000E (Elkhart Lake)", 358 [0x9c] = "Pentium Silver N6xxx, Celeron N45xx, Celeron N51xx (Jasper Lake)", 359 [0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 360 [0xa5] = "10th gen Core (Comet Lake)", 361 [0xa6] = "10th gen Core (Comet Lake)", 362 }, 363 "Pentium Pro, II or III", /* Default */ 364 NULL, 365 intel_family_new_probe, 366 intel_cpu_cacheinfo, 367 }, 368 /* Family > 6 */ 369 { 370 CPUCLASS_686, 371 { 372 0, 0, 0, 0, 0, 0, 0, 0, 373 0, 0, 0, 0, 0, 0, 0, 0, 374 }, 375 "Pentium 4", /* Default */ 376 NULL, 377 intel_family_new_probe, 378 intel_cpu_cacheinfo, 379 } } 380 }, 381 { 382 "AuthenticAMD", 383 CPUVENDOR_AMD, 384 "AMD", 385 /* Family 4 */ 386 { { 387 CPUCLASS_486, 388 { 389 0, 0, 0, "Am486DX2 W/T", 390 0, 0, 0, "Am486DX2 W/B", 391 "Am486DX4 W/T or Am5x86 W/T 150", 392 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 393 0, 0, "Am5x86 W/T 133/160", 394 "Am5x86 W/B 133/160", 395 }, 396 "Am486 or Am5x86", /* Default */ 397 NULL, 398 NULL, 399 NULL, 400 }, 401 /* Family 5 */ 402 { 403 CPUCLASS_586, 404 { 405 "K5", "K5", "K5", "K5", 0, 0, "K6", 406 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 407 "K6-2+/III+", 0, 0, 408 }, 409 "K5 or K6", /* Default */ 410 amd_family5_setup, 411 NULL, 412 amd_cpu_cacheinfo, 413 }, 414 /* Family 6 */ 415 { 416 CPUCLASS_686, 417 { 418 0, "Athlon Model 1", "Athlon Model 2", 419 "Duron", "Athlon Model 4 (Thunderbird)", 420 0, "Athlon", "Duron", "Athlon", 0, 421 "Athlon", 0, 0, 0, 0, 0, 422 }, 423 "K7 (Athlon)", /* Default */ 424 NULL, 425 amd_family6_probe, 426 amd_cpu_cacheinfo, 427 }, 428 /* Family > 6 */ 429 { 430 CPUCLASS_686, 431 { 432 0, 0, 0, 0, 0, 0, 0, 0, 433 0, 0, 0, 0, 0, 0, 0, 0, 434 }, 435 "Unknown K8 (Athlon)", /* Default */ 436 NULL, 437 amd_family6_probe, 438 amd_cpu_cacheinfo, 439 } } 440 }, 441 { 442 "CyrixInstead", 443 CPUVENDOR_CYRIX, 444 "Cyrix", 445 /* Family 4 */ 446 { { 447 CPUCLASS_486, 448 { 449 0, 0, 0, 450 "MediaGX", 451 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 452 }, 453 "486", /* Default */ 454 cyrix6x86_cpu_setup, /* XXX ?? */ 455 NULL, 456 NULL, 457 }, 458 /* Family 5 */ 459 { 460 CPUCLASS_586, 461 { 462 0, 0, "6x86", 0, 463 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 464 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 465 }, 466 "6x86", /* Default */ 467 cyrix6x86_cpu_setup, 468 NULL, 469 NULL, 470 }, 471 /* Family 6 */ 472 { 473 CPUCLASS_686, 474 { 475 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 476 0, 0, 0, 0, 0, 0, 0, 0, 477 }, 478 "6x86MX", /* Default */ 479 cyrix6x86_cpu_setup, 480 NULL, 481 NULL, 482 }, 483 /* Family > 6 */ 484 { 485 CPUCLASS_686, 486 { 487 0, 0, 0, 0, 0, 0, 0, 0, 488 0, 0, 0, 0, 0, 0, 0, 0, 489 }, 490 "Unknown 6x86MX", /* Default */ 491 NULL, 492 NULL, 493 NULL, 494 } } 495 }, 496 { /* MediaGX is now owned by National Semiconductor */ 497 "Geode by NSC", 498 CPUVENDOR_CYRIX, /* XXX */ 499 "National Semiconductor", 500 /* Family 4, NSC never had any of these */ 501 { { 502 CPUCLASS_486, 503 { 504 0, 0, 0, 0, 0, 0, 0, 0, 505 0, 0, 0, 0, 0, 0, 0, 0, 506 }, 507 "486 compatible", /* Default */ 508 NULL, 509 NULL, 510 NULL, 511 }, 512 /* Family 5: Geode family, formerly MediaGX */ 513 { 514 CPUCLASS_586, 515 { 516 0, 0, 0, 0, 517 "Geode GX1", 518 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 519 }, 520 "Geode", /* Default */ 521 cyrix6x86_cpu_setup, 522 NULL, 523 amd_cpu_cacheinfo, 524 }, 525 /* Family 6, not yet available from NSC */ 526 { 527 CPUCLASS_686, 528 { 529 0, 0, 0, 0, 0, 0, 0, 0, 530 0, 0, 0, 0, 0, 0, 0, 0, 531 }, 532 "Pentium Pro compatible", /* Default */ 533 NULL, 534 NULL, 535 NULL, 536 }, 537 /* Family > 6, not yet available from NSC */ 538 { 539 CPUCLASS_686, 540 { 541 0, 0, 0, 0, 0, 0, 0, 0, 542 0, 0, 0, 0, 0, 0, 0, 0, 543 }, 544 "Pentium Pro compatible", /* Default */ 545 NULL, 546 NULL, 547 NULL, 548 } } 549 }, 550 { 551 "CentaurHauls", 552 CPUVENDOR_IDT, 553 "IDT", 554 /* Family 4, IDT never had any of these */ 555 { { 556 CPUCLASS_486, 557 { 558 0, 0, 0, 0, 0, 0, 0, 0, 559 0, 0, 0, 0, 0, 0, 0, 0, 560 }, 561 "486 compatible", /* Default */ 562 NULL, 563 NULL, 564 NULL, 565 }, 566 /* Family 5 */ 567 { 568 CPUCLASS_586, 569 { 570 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 571 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 572 }, 573 "WinChip", /* Default */ 574 winchip_cpu_setup, 575 NULL, 576 NULL, 577 }, 578 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 579 { 580 CPUCLASS_686, 581 { 582 0, 0, 0, 0, 0, 0, "C3 Samuel", 583 "C3 Samuel 2/Ezra", "C3 Ezra-T", 584 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 585 0, "VIA Nano", 586 }, 587 "Unknown VIA/IDT", /* Default */ 588 NULL, 589 via_cpu_probe, 590 via_cpu_cacheinfo, 591 }, 592 /* Family > 6, not yet available from VIA */ 593 { 594 CPUCLASS_686, 595 { 596 0, 0, 0, 0, 0, 0, 0, 0, 597 0, 0, 0, 0, 0, 0, 0, 0, 598 }, 599 "Pentium Pro compatible", /* Default */ 600 NULL, 601 NULL, 602 NULL, 603 } } 604 }, 605 { 606 "GenuineTMx86", 607 CPUVENDOR_TRANSMETA, 608 "Transmeta", 609 /* Family 4, Transmeta never had any of these */ 610 { { 611 CPUCLASS_486, 612 { 613 0, 0, 0, 0, 0, 0, 0, 0, 614 0, 0, 0, 0, 0, 0, 0, 0, 615 }, 616 "486 compatible", /* Default */ 617 NULL, 618 NULL, 619 NULL, 620 }, 621 /* Family 5 */ 622 { 623 CPUCLASS_586, 624 { 625 0, 0, 0, 0, 0, 0, 0, 0, 626 0, 0, 0, 0, 0, 0, 0, 0, 627 }, 628 "Crusoe", /* Default */ 629 NULL, 630 NULL, 631 transmeta_cpu_info, 632 }, 633 /* Family 6, not yet available from Transmeta */ 634 { 635 CPUCLASS_686, 636 { 637 0, 0, 0, 0, 0, 0, 0, 0, 638 0, 0, 0, 0, 0, 0, 0, 0, 639 }, 640 "Pentium Pro compatible", /* Default */ 641 NULL, 642 NULL, 643 NULL, 644 }, 645 /* Family > 6, not yet available from Transmeta */ 646 { 647 CPUCLASS_686, 648 { 649 0, 0, 0, 0, 0, 0, 0, 0, 650 0, 0, 0, 0, 0, 0, 0, 0, 651 }, 652 "Pentium Pro compatible", /* Default */ 653 NULL, 654 NULL, 655 NULL, 656 } } 657 } 658 }; 659 660 /* 661 * disable the TSC such that we don't use the TSC in microtime(9) 662 * because some CPUs got the implementation wrong. 663 */ 664 static void 665 disable_tsc(struct cpu_info *ci) 666 { 667 if (ci->ci_feat_val[0] & CPUID_TSC) { 668 ci->ci_feat_val[0] &= ~CPUID_TSC; 669 aprint_error("WARNING: broken TSC disabled\n"); 670 } 671 } 672 673 static void 674 amd_family5_setup(struct cpu_info *ci) 675 { 676 677 switch (ci->ci_model) { 678 case 0: /* AMD-K5 Model 0 */ 679 /* 680 * According to the AMD Processor Recognition App Note, 681 * the AMD-K5 Model 0 uses the wrong bit to indicate 682 * support for global PTEs, instead using bit 9 (APIC) 683 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 684 */ 685 if (ci->ci_feat_val[0] & CPUID_APIC) 686 ci->ci_feat_val[0] = 687 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 688 /* 689 * XXX But pmap_pg_g is already initialized -- need to kick 690 * XXX the pmap somehow. How does the MP branch do this? 691 */ 692 break; 693 } 694 } 695 696 static void 697 cyrix6x86_cpu_setup(struct cpu_info *ci) 698 { 699 700 /* 701 * Do not disable the TSC on the Geode GX, it's reported to 702 * work fine. 703 */ 704 if (ci->ci_signature != 0x552) 705 disable_tsc(ci); 706 } 707 708 static void 709 winchip_cpu_setup(struct cpu_info *ci) 710 { 711 switch (ci->ci_model) { 712 case 4: /* WinChip C6 */ 713 disable_tsc(ci); 714 } 715 } 716 717 718 static const char * 719 intel_family6_name(struct cpu_info *ci) 720 { 721 const char *ret = NULL; 722 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 723 724 if (ci->ci_model == 5) { 725 switch (l2cache) { 726 case 0: 727 case 128 * 1024: 728 ret = "Celeron (Covington)"; 729 break; 730 case 256 * 1024: 731 ret = "Mobile Pentium II (Dixon)"; 732 break; 733 case 512 * 1024: 734 ret = "Pentium II"; 735 break; 736 case 1 * 1024 * 1024: 737 case 2 * 1024 * 1024: 738 ret = "Pentium II Xeon"; 739 break; 740 } 741 } else if (ci->ci_model == 6) { 742 switch (l2cache) { 743 case 256 * 1024: 744 case 512 * 1024: 745 ret = "Mobile Pentium II"; 746 break; 747 } 748 } else if (ci->ci_model == 7) { 749 switch (l2cache) { 750 case 512 * 1024: 751 ret = "Pentium III"; 752 break; 753 case 1 * 1024 * 1024: 754 case 2 * 1024 * 1024: 755 ret = "Pentium III Xeon"; 756 break; 757 } 758 } else if (ci->ci_model >= 8) { 759 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 760 switch (ci->ci_brand_id) { 761 case 0x3: 762 if (ci->ci_signature == 0x6B1) 763 ret = "Celeron"; 764 break; 765 case 0x8: 766 if (ci->ci_signature >= 0xF13) 767 ret = "genuine processor"; 768 break; 769 case 0xB: 770 if (ci->ci_signature >= 0xF13) 771 ret = "Xeon MP"; 772 break; 773 case 0xE: 774 if (ci->ci_signature < 0xF13) 775 ret = "Xeon"; 776 break; 777 } 778 if (ret == NULL) 779 ret = i386_intel_brand[ci->ci_brand_id]; 780 } 781 } 782 783 return ret; 784 } 785 786 /* 787 * Identify AMD64 CPU names from cpuid. 788 * 789 * Based on: 790 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 791 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 792 * "Revision Guide for AMD NPT Family 0Fh Processors" 793 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 794 * and other miscellaneous reports. 795 * 796 * This is all rather pointless, these are cross 'brand' since the raw 797 * silicon is shared. 798 */ 799 static const char * 800 amd_amd64_name(struct cpu_info *ci) 801 { 802 static char family_str[32]; 803 804 /* Only called if family >= 15 */ 805 806 switch (ci->ci_family) { 807 case 15: 808 switch (ci->ci_model) { 809 case 0x21: /* rev JH-E1/E6 */ 810 case 0x41: /* rev JH-F2 */ 811 return "Dual-Core Opteron"; 812 case 0x23: /* rev JH-E6 (Toledo) */ 813 return "Dual-Core Opteron or Athlon 64 X2"; 814 case 0x43: /* rev JH-F2 (Windsor) */ 815 return "Athlon 64 FX or Athlon 64 X2"; 816 case 0x24: /* rev SH-E5 (Lancaster?) */ 817 return "Mobile Athlon 64 or Turion 64"; 818 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 819 return "Opteron or Athlon 64 FX"; 820 case 0x15: /* rev SH-D0 */ 821 case 0x25: /* rev SH-E4 */ 822 return "Opteron"; 823 case 0x27: /* rev DH-E4, SH-E4 */ 824 return "Athlon 64 or Athlon 64 FX or Opteron"; 825 case 0x48: /* rev BH-F2 */ 826 return "Turion 64 X2"; 827 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 828 case 0x07: /* rev SH-CG (ClawHammer) */ 829 case 0x0b: /* rev CH-CG */ 830 case 0x14: /* rev SH-D0 */ 831 case 0x17: /* rev SH-D0 */ 832 case 0x1b: /* rev CH-D0 */ 833 return "Athlon 64"; 834 case 0x2b: /* rev BH-E4 (Manchester) */ 835 case 0x4b: /* rev BH-F2 (Windsor) */ 836 return "Athlon 64 X2"; 837 case 0x6b: /* rev BH-G1 (Brisbane) */ 838 return "Athlon X2 or Athlon 64 X2"; 839 case 0x08: /* rev CH-CG */ 840 case 0x0c: /* rev DH-CG (Newcastle) */ 841 case 0x0e: /* rev DH-CG (Newcastle?) */ 842 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 843 case 0x18: /* rev CH-D0 */ 844 case 0x1c: /* rev DH-D0 (Winchester) */ 845 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 846 case 0x2c: /* rev DH-E3/E6 */ 847 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 848 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 849 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 850 case 0x6f: /* rev DH-G1 */ 851 return "Athlon 64 or Sempron"; 852 default: 853 break; 854 } 855 return "Unknown AMD64 CPU"; 856 857 #if 0 858 case 16: 859 return "Family 10h"; 860 case 17: 861 return "Family 11h"; 862 case 18: 863 return "Family 12h"; 864 case 19: 865 return "Family 14h"; 866 case 20: 867 return "Family 15h"; 868 #endif 869 870 default: 871 break; 872 } 873 874 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 875 return family_str; 876 } 877 878 static void 879 intel_family_new_probe(struct cpu_info *ci) 880 { 881 uint32_t descs[4]; 882 883 x86_cpuid(0x80000000, descs); 884 885 /* 886 * Determine extended feature flags. 887 */ 888 if (descs[0] >= 0x80000001) { 889 x86_cpuid(0x80000001, descs); 890 ci->ci_feat_val[2] |= descs[3]; 891 ci->ci_feat_val[3] |= descs[2]; 892 } 893 } 894 895 static void 896 via_cpu_probe(struct cpu_info *ci) 897 { 898 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 899 u_int descs[4]; 900 u_int lfunc; 901 902 /* 903 * Determine the largest extended function value. 904 */ 905 x86_cpuid(0x80000000, descs); 906 lfunc = descs[0]; 907 908 /* 909 * Determine the extended feature flags. 910 */ 911 if (lfunc >= 0x80000001) { 912 x86_cpuid(0x80000001, descs); 913 ci->ci_feat_val[2] |= descs[3]; 914 } 915 916 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 917 return; 918 919 /* Nehemiah or Esther */ 920 x86_cpuid(0xc0000000, descs); 921 lfunc = descs[0]; 922 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 923 return; 924 925 x86_cpuid(0xc0000001, descs); 926 lfunc = descs[3]; 927 ci->ci_feat_val[4] = lfunc; 928 } 929 930 static void 931 amd_family6_probe(struct cpu_info *ci) 932 { 933 uint32_t descs[4]; 934 char *p; 935 size_t i; 936 937 x86_cpuid(0x80000000, descs); 938 939 /* 940 * Determine the extended feature flags. 941 */ 942 if (descs[0] >= 0x80000001) { 943 x86_cpuid(0x80000001, descs); 944 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 945 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 946 } 947 948 if (*cpu_brand_string == '\0') 949 return; 950 951 for (i = 1; i < __arraycount(amd_brand); i++) 952 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 953 ci->ci_brand_id = i; 954 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 955 break; 956 } 957 } 958 959 /* 960 * Get cache info from one of the following: 961 * Intel Deterministic Cache Parameter Leaf (0x04) 962 * AMD Cache Topology Information Leaf (0x8000001d) 963 */ 964 static void 965 cpu_dcp_cacheinfo(struct cpu_info *ci, uint32_t leaf) 966 { 967 u_int descs[4]; 968 int type, level, ways, partitions, linesize, sets, totalsize; 969 int caitype = -1; 970 int i; 971 972 for (i = 0; ; i++) { 973 x86_cpuid2(leaf, i, descs); 974 type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE); 975 if (type == CPUID_DCP_CACHETYPE_N) 976 break; 977 level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL); 978 switch (level) { 979 case 1: 980 if (type == CPUID_DCP_CACHETYPE_I) 981 caitype = CAI_ICACHE; 982 else if (type == CPUID_DCP_CACHETYPE_D) 983 caitype = CAI_DCACHE; 984 else 985 caitype = -1; 986 break; 987 case 2: 988 if (type == CPUID_DCP_CACHETYPE_U) 989 caitype = CAI_L2CACHE; 990 else 991 caitype = -1; 992 break; 993 case 3: 994 if (type == CPUID_DCP_CACHETYPE_U) 995 caitype = CAI_L3CACHE; 996 else 997 caitype = -1; 998 break; 999 default: 1000 caitype = -1; 1001 break; 1002 } 1003 if (caitype == -1) { 1004 aprint_error_dev(ci->ci_dev, 1005 "error: unknown cache level&type (%d & %d)\n", 1006 level, type); 1007 continue; 1008 } 1009 ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1; 1010 partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS) 1011 + 1; 1012 linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE) 1013 + 1; 1014 sets = descs[2] + 1; 1015 totalsize = ways * partitions * linesize * sets; 1016 ci->ci_cinfo[caitype].cai_totalsize = totalsize; 1017 ci->ci_cinfo[caitype].cai_associativity = ways; 1018 ci->ci_cinfo[caitype].cai_linesize = linesize; 1019 } 1020 } 1021 1022 static void 1023 intel_cpu_cacheinfo(struct cpu_info *ci) 1024 { 1025 const struct x86_cache_info *cai; 1026 u_int descs[4]; 1027 int iterations, i, j; 1028 int type, level, ways, linesize, sets; 1029 int caitype = -1; 1030 uint8_t desc; 1031 1032 /* Return if the cpu is old pre-cpuid instruction cpu */ 1033 if (ci->ci_cpu_type >= 0) 1034 return; 1035 1036 if (ci->ci_max_cpuid < 2) 1037 return; 1038 1039 /* 1040 * Parse the cache info from `cpuid leaf 2', if we have it. 1041 * XXX This is kinda ugly, but hey, so is the architecture... 1042 */ 1043 x86_cpuid(2, descs); 1044 iterations = descs[0] & 0xff; 1045 while (iterations-- > 0) { 1046 for (i = 0; i < 4; i++) { 1047 if (descs[i] & 0x80000000) 1048 continue; 1049 for (j = 0; j < 4; j++) { 1050 /* 1051 * The least significant byte in EAX 1052 * ((desc[0] >> 0) & 0xff) is always 0x01 and 1053 * it should be ignored. 1054 */ 1055 if (i == 0 && j == 0) 1056 continue; 1057 desc = (descs[i] >> (j * 8)) & 0xff; 1058 if (desc == 0) 1059 continue; 1060 cai = cache_info_lookup(intel_cpuid_cache_info, 1061 desc); 1062 if (cai != NULL) 1063 ci->ci_cinfo[cai->cai_index] = *cai; 1064 else if ((verbose != 0) && (desc != 0xff) 1065 && (desc != 0xfe)) 1066 aprint_error_dev(ci->ci_dev, "error:" 1067 " Unknown cacheinfo desc %02x\n", 1068 desc); 1069 } 1070 } 1071 x86_cpuid(2, descs); 1072 } 1073 1074 if (ci->ci_max_cpuid < 4) 1075 return; 1076 1077 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1078 cpu_dcp_cacheinfo(ci, 4); 1079 1080 if (ci->ci_max_cpuid < 0x18) 1081 return; 1082 /* Parse the TLB info from `cpuid leaf 18H', if we have it. */ 1083 x86_cpuid(0x18, descs); 1084 iterations = descs[0]; 1085 for (i = 0; i <= iterations; i++) { 1086 uint32_t pgsize; 1087 bool full; 1088 1089 x86_cpuid2(0x18, i, descs); 1090 type = __SHIFTOUT(descs[3], CPUID_DATP_TCTYPE); 1091 if (type == CPUID_DATP_TCTYPE_N) 1092 continue; 1093 level = __SHIFTOUT(descs[3], CPUID_DATP_TCLEVEL); 1094 pgsize = __SHIFTOUT(descs[1], CPUID_DATP_PGSIZE); 1095 switch (level) { 1096 case 1: 1097 if (type == CPUID_DATP_TCTYPE_I) { 1098 switch (pgsize) { 1099 case CPUID_DATP_PGSIZE_4KB: 1100 caitype = CAI_ITLB; 1101 break; 1102 case CPUID_DATP_PGSIZE_2MB 1103 | CPUID_DATP_PGSIZE_4MB: 1104 caitype = CAI_ITLB2; 1105 break; 1106 case CPUID_DATP_PGSIZE_1GB: 1107 caitype = CAI_L1_1GBITLB; 1108 break; 1109 default: 1110 aprint_error_dev(ci->ci_dev, 1111 "error: unknown ITLB size (%d)\n", 1112 pgsize); 1113 caitype = CAI_ITLB; 1114 break; 1115 } 1116 } else if (type == CPUID_DATP_TCTYPE_D) { 1117 switch (pgsize) { 1118 case CPUID_DATP_PGSIZE_4KB: 1119 caitype = CAI_DTLB; 1120 break; 1121 case CPUID_DATP_PGSIZE_2MB 1122 | CPUID_DATP_PGSIZE_4MB: 1123 caitype = CAI_DTLB2; 1124 break; 1125 case CPUID_DATP_PGSIZE_1GB: 1126 caitype = CAI_L1_1GBDTLB; 1127 break; 1128 default: 1129 aprint_error_dev(ci->ci_dev, 1130 "error: unknown DTLB size (%d)\n", 1131 pgsize); 1132 caitype = CAI_DTLB; 1133 break; 1134 } 1135 } else 1136 caitype = -1; 1137 break; 1138 case 2: 1139 if (type == CPUID_DATP_TCTYPE_I) 1140 caitype = CAI_L2_ITLB; 1141 else if (type == CPUID_DATP_TCTYPE_D) 1142 caitype = CAI_L2_DTLB; 1143 else if (type == CPUID_DATP_TCTYPE_U) { 1144 switch (pgsize) { 1145 case CPUID_DATP_PGSIZE_4KB: 1146 caitype = CAI_L2_STLB; 1147 break; 1148 case CPUID_DATP_PGSIZE_4KB 1149 | CPUID_DATP_PGSIZE_2MB: 1150 caitype = CAI_L2_STLB2; 1151 break; 1152 case CPUID_DATP_PGSIZE_2MB 1153 | CPUID_DATP_PGSIZE_4MB: 1154 caitype = CAI_L2_STLB3; 1155 break; 1156 default: 1157 aprint_error_dev(ci->ci_dev, 1158 "error: unknown L2 STLB size (%d)\n", 1159 pgsize); 1160 caitype = CAI_DTLB; 1161 break; 1162 } 1163 } else 1164 caitype = -1; 1165 break; 1166 case 3: 1167 /* XXX need work for L3 TLB */ 1168 caitype = CAI_L3CACHE; 1169 break; 1170 default: 1171 caitype = -1; 1172 break; 1173 } 1174 if (caitype == -1) { 1175 aprint_error_dev(ci->ci_dev, 1176 "error: unknown TLB level&type (%d & %d)\n", 1177 level, type); 1178 continue; 1179 } 1180 switch (pgsize) { 1181 case CPUID_DATP_PGSIZE_4KB: 1182 linesize = 4 * 1024; 1183 break; 1184 case CPUID_DATP_PGSIZE_2MB: 1185 linesize = 2 * 1024 * 1024; 1186 break; 1187 case CPUID_DATP_PGSIZE_4MB: 1188 linesize = 4 * 1024 * 1024; 1189 break; 1190 case CPUID_DATP_PGSIZE_1GB: 1191 linesize = 1024 * 1024 * 1024; 1192 break; 1193 case CPUID_DATP_PGSIZE_2MB | CPUID_DATP_PGSIZE_4MB: 1194 aprint_error_dev(ci->ci_dev, 1195 "WARINING: Currently 2M/4M info can't print correctly\n"); 1196 linesize = 4 * 1024 * 1024; 1197 break; 1198 default: 1199 aprint_error_dev(ci->ci_dev, 1200 "error: Unknown size combination\n"); 1201 linesize = 4 * 1024; 1202 break; 1203 } 1204 ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS); 1205 sets = descs[2]; 1206 full = descs[3] & CPUID_DATP_FULLASSOC; 1207 ci->ci_cinfo[caitype].cai_totalsize 1208 = ways * sets; /* entries */ 1209 ci->ci_cinfo[caitype].cai_associativity 1210 = full ? 0xff : ways; 1211 ci->ci_cinfo[caitype].cai_linesize = linesize; /* pg size */ 1212 } 1213 } 1214 1215 static const struct x86_cache_info amd_cpuid_l2l3cache_assoc_info[] = 1216 AMD_L2L3CACHE_INFO; 1217 1218 static void 1219 amd_cpu_cacheinfo(struct cpu_info *ci) 1220 { 1221 const struct x86_cache_info *cp; 1222 struct x86_cache_info *cai; 1223 u_int descs[4]; 1224 u_int lfunc; 1225 1226 /* K5 model 0 has none of this info. */ 1227 if (ci->ci_family == 5 && ci->ci_model == 0) 1228 return; 1229 1230 /* Determine the largest extended function value. */ 1231 x86_cpuid(0x80000000, descs); 1232 lfunc = descs[0]; 1233 1234 if (lfunc < 0x80000005) 1235 return; 1236 1237 /* Determine L1 cache/TLB info. */ 1238 x86_cpuid(0x80000005, descs); 1239 1240 /* K6-III and higher have large page TLBs. */ 1241 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1242 cai = &ci->ci_cinfo[CAI_ITLB2]; 1243 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1244 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1245 cai->cai_linesize = largepagesize; 1246 1247 cai = &ci->ci_cinfo[CAI_DTLB2]; 1248 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1249 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1250 cai->cai_linesize = largepagesize; 1251 } 1252 1253 cai = &ci->ci_cinfo[CAI_ITLB]; 1254 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1255 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1256 cai->cai_linesize = (4 * 1024); 1257 1258 cai = &ci->ci_cinfo[CAI_DTLB]; 1259 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1260 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1261 cai->cai_linesize = (4 * 1024); 1262 1263 cai = &ci->ci_cinfo[CAI_DCACHE]; 1264 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1265 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1266 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1267 1268 cai = &ci->ci_cinfo[CAI_ICACHE]; 1269 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1270 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1271 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1272 1273 if (lfunc < 0x80000006) 1274 return; 1275 1276 /* Determine L2 cache/TLB info. */ 1277 x86_cpuid(0x80000006, descs); 1278 1279 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1280 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1281 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1282 cai->cai_linesize = (4 * 1024); 1283 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1284 cai->cai_associativity); 1285 if (cp != NULL) 1286 cai->cai_associativity = cp->cai_associativity; 1287 else 1288 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1289 1290 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1291 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1292 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1293 cai->cai_linesize = largepagesize; 1294 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1295 cai->cai_associativity); 1296 if (cp != NULL) 1297 cai->cai_associativity = cp->cai_associativity; 1298 else 1299 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1300 1301 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1302 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1303 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1304 cai->cai_linesize = (4 * 1024); 1305 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1306 cai->cai_associativity); 1307 if (cp != NULL) 1308 cai->cai_associativity = cp->cai_associativity; 1309 else 1310 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1311 1312 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1313 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1314 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1315 cai->cai_linesize = largepagesize; 1316 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1317 cai->cai_associativity); 1318 if (cp != NULL) 1319 cai->cai_associativity = cp->cai_associativity; 1320 else 1321 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1322 1323 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1324 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1325 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1326 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1327 1328 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1329 cai->cai_associativity); 1330 if (cp != NULL) 1331 cai->cai_associativity = cp->cai_associativity; 1332 else 1333 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1334 1335 /* Determine L3 cache info on AMD Family 10h and newer processors */ 1336 if (ci->ci_family >= 0x10) { 1337 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1338 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1339 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1340 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1341 1342 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1343 cai->cai_associativity); 1344 if (cp != NULL) 1345 cai->cai_associativity = cp->cai_associativity; 1346 else 1347 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1348 } 1349 1350 if (lfunc < 0x80000019) 1351 return; 1352 1353 /* Determine 1GB TLB info. */ 1354 x86_cpuid(0x80000019, descs); 1355 1356 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1357 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1358 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1359 cai->cai_linesize = (1024 * 1024 * 1024); 1360 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1361 cai->cai_associativity); 1362 if (cp != NULL) 1363 cai->cai_associativity = cp->cai_associativity; 1364 else 1365 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1366 1367 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1368 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1369 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1370 cai->cai_linesize = (1024 * 1024 * 1024); 1371 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1372 cai->cai_associativity); 1373 if (cp != NULL) 1374 cai->cai_associativity = cp->cai_associativity; 1375 else 1376 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1377 1378 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1379 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1380 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1381 cai->cai_linesize = (1024 * 1024 * 1024); 1382 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1383 cai->cai_associativity); 1384 if (cp != NULL) 1385 cai->cai_associativity = cp->cai_associativity; 1386 else 1387 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1388 1389 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1390 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1391 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1392 cai->cai_linesize = (1024 * 1024 * 1024); 1393 cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info, 1394 cai->cai_associativity); 1395 if (cp != NULL) 1396 cai->cai_associativity = cp->cai_associativity; 1397 else 1398 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1399 1400 if (lfunc < 0x8000001d) 1401 return; 1402 1403 if (ci->ci_feat_val[3] & CPUID_TOPOEXT) 1404 cpu_dcp_cacheinfo(ci, 0x8000001d); 1405 } 1406 1407 static void 1408 via_cpu_cacheinfo(struct cpu_info *ci) 1409 { 1410 struct x86_cache_info *cai; 1411 int stepping; 1412 u_int descs[4]; 1413 u_int lfunc; 1414 1415 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1416 1417 /* 1418 * Determine the largest extended function value. 1419 */ 1420 x86_cpuid(0x80000000, descs); 1421 lfunc = descs[0]; 1422 1423 /* 1424 * Determine L1 cache/TLB info. 1425 */ 1426 if (lfunc < 0x80000005) { 1427 /* No L1 cache info available. */ 1428 return; 1429 } 1430 1431 x86_cpuid(0x80000005, descs); 1432 1433 cai = &ci->ci_cinfo[CAI_ITLB]; 1434 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1435 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1436 cai->cai_linesize = (4 * 1024); 1437 1438 cai = &ci->ci_cinfo[CAI_DTLB]; 1439 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1440 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1441 cai->cai_linesize = (4 * 1024); 1442 1443 cai = &ci->ci_cinfo[CAI_DCACHE]; 1444 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1445 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1446 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1447 if (ci->ci_model == 9 && stepping == 8) { 1448 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1449 cai->cai_associativity = 2; 1450 } 1451 1452 cai = &ci->ci_cinfo[CAI_ICACHE]; 1453 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1454 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1455 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1456 if (ci->ci_model == 9 && stepping == 8) { 1457 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1458 cai->cai_associativity = 2; 1459 } 1460 1461 /* 1462 * Determine L2 cache/TLB info. 1463 */ 1464 if (lfunc < 0x80000006) { 1465 /* No L2 cache info available. */ 1466 return; 1467 } 1468 1469 x86_cpuid(0x80000006, descs); 1470 1471 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1472 if (ci->ci_model >= 9) { 1473 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1474 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1475 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1476 } else { 1477 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1478 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1479 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1480 } 1481 } 1482 1483 static void 1484 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1485 { 1486 u_int descs[4]; 1487 1488 x86_cpuid(0x80860007, descs); 1489 *frequency = descs[0]; 1490 *voltage = descs[1]; 1491 *percentage = descs[2]; 1492 } 1493 1494 static void 1495 transmeta_cpu_info(struct cpu_info *ci) 1496 { 1497 u_int descs[4], nreg; 1498 u_int frequency, voltage, percentage; 1499 1500 x86_cpuid(0x80860000, descs); 1501 nreg = descs[0]; 1502 if (nreg >= 0x80860001) { 1503 x86_cpuid(0x80860001, descs); 1504 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1505 (descs[1] >> 24) & 0xff, 1506 (descs[1] >> 16) & 0xff, 1507 (descs[1] >> 8) & 0xff, 1508 descs[1] & 0xff); 1509 } 1510 if (nreg >= 0x80860002) { 1511 x86_cpuid(0x80860002, descs); 1512 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1513 (descs[1] >> 24) & 0xff, 1514 (descs[1] >> 16) & 0xff, 1515 (descs[1] >> 8) & 0xff, 1516 descs[1] & 0xff, 1517 descs[2]); 1518 } 1519 if (nreg >= 0x80860006) { 1520 union { 1521 char text[65]; 1522 u_int descs[4][4]; 1523 } info; 1524 int i; 1525 1526 for (i=0; i<4; i++) { 1527 x86_cpuid(0x80860003 + i, info.descs[i]); 1528 } 1529 info.text[64] = '\0'; 1530 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1531 } 1532 1533 if (nreg >= 0x80860007) { 1534 tmx86_get_longrun_status(&frequency, 1535 &voltage, &percentage); 1536 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1537 frequency, voltage, percentage); 1538 } 1539 } 1540 1541 static void 1542 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1543 { 1544 u_int descs[4]; 1545 int i; 1546 uint32_t brand[12]; 1547 1548 memset(ci, 0, sizeof(*ci)); 1549 ci->ci_dev = cpuname; 1550 1551 ci->ci_cpu_type = x86_identify(); 1552 if (ci->ci_cpu_type >= 0) { 1553 /* Old pre-cpuid instruction cpu */ 1554 ci->ci_max_cpuid = -1; 1555 return; 1556 } 1557 1558 /* 1559 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1560 * function. 1561 */ 1562 1563 /* 1564 * Fn0000_0000: 1565 * - Save cpuid max level. 1566 * - Save vendor string. 1567 */ 1568 x86_cpuid(0, descs); 1569 ci->ci_max_cpuid = descs[0]; 1570 /* Save vendor string */ 1571 ci->ci_vendor[0] = descs[1]; 1572 ci->ci_vendor[2] = descs[2]; 1573 ci->ci_vendor[1] = descs[3]; 1574 ci->ci_vendor[3] = 0; 1575 1576 /* 1577 * Fn8000_0000: 1578 * - Get cpuid extended function's max level. 1579 */ 1580 x86_cpuid(0x80000000, descs); 1581 if (descs[0] >= 0x80000000) 1582 ci->ci_max_ext_cpuid = descs[0]; 1583 else { 1584 /* Set lower value than 0x80000000 */ 1585 ci->ci_max_ext_cpuid = 0; 1586 } 1587 1588 /* 1589 * Fn8000_000[2-4]: 1590 * - Save brand string. 1591 */ 1592 if (ci->ci_max_ext_cpuid >= 0x80000004) { 1593 x86_cpuid(0x80000002, brand); 1594 x86_cpuid(0x80000003, brand + 4); 1595 x86_cpuid(0x80000004, brand + 8); 1596 for (i = 0; i < 48; i++) 1597 if (((char *) brand)[i] != ' ') 1598 break; 1599 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1600 } 1601 1602 if (ci->ci_max_cpuid < 1) 1603 return; 1604 1605 /* 1606 * Fn0000_0001: 1607 * - Get CPU family, model and stepping (from eax). 1608 * - Initial local APIC ID and brand ID (from ebx) 1609 * - CPUID2 (from ecx) 1610 * - CPUID (from edx) 1611 */ 1612 x86_cpuid(1, descs); 1613 ci->ci_signature = descs[0]; 1614 1615 /* Extract full family/model values */ 1616 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1617 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1618 1619 /* Brand is low order 8 bits of ebx */ 1620 ci->ci_brand_id = __SHIFTOUT(descs[1], CPUID_BRAND_INDEX); 1621 /* Initial local APIC ID */ 1622 ci->ci_initapicid = __SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID); 1623 1624 ci->ci_feat_val[1] = descs[2]; 1625 ci->ci_feat_val[0] = descs[3]; 1626 1627 if (ci->ci_max_cpuid < 3) 1628 return; 1629 1630 /* 1631 * If the processor serial number misfeature is present and supported, 1632 * extract it here. 1633 */ 1634 if ((ci->ci_feat_val[0] & CPUID_PSN) != 0) { 1635 ci->ci_cpu_serial[0] = ci->ci_signature; 1636 x86_cpuid(3, descs); 1637 ci->ci_cpu_serial[2] = descs[2]; 1638 ci->ci_cpu_serial[1] = descs[3]; 1639 } 1640 1641 if (ci->ci_max_cpuid < 0x7) 1642 return; 1643 1644 x86_cpuid(7, descs); 1645 ci->ci_feat_val[5] = descs[1]; 1646 ci->ci_feat_val[6] = descs[2]; 1647 ci->ci_feat_val[7] = descs[3]; 1648 1649 if (ci->ci_max_cpuid < 0xd) 1650 return; 1651 1652 /* Get support XCR0 bits */ 1653 x86_cpuid2(0xd, 0, descs); 1654 ci->ci_feat_val[8] = descs[0]; /* Actually 64 bits */ 1655 ci->ci_cur_xsave = descs[1]; 1656 ci->ci_max_xsave = descs[2]; 1657 1658 /* Additional flags (eg xsaveopt support) */ 1659 x86_cpuid2(0xd, 1, descs); 1660 ci->ci_feat_val[9] = descs[0]; /* Actually 64 bits */ 1661 } 1662 1663 static void 1664 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1665 { 1666 uint32_t descs[4]; 1667 char hv_sig[13]; 1668 char *p; 1669 const char *hv_name; 1670 int i; 1671 1672 /* 1673 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1674 * http://lkml.org/lkml/2008/10/1/246 1675 * 1676 * KB1009458: Mechanisms to determine if software is running in 1677 * a VMware virtual machine 1678 * http://kb.vmware.com/kb/1009458 1679 */ 1680 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1681 x86_cpuid(0x40000000, descs); 1682 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1683 memcpy(p, &descs[i], sizeof(descs[i])); 1684 *p = '\0'; 1685 /* 1686 * HV vendor ID string 1687 * ------------+-------------- 1688 * HAXM "HAXMHAXMHAXM" 1689 * KVM "KVMKVMKVM" 1690 * Microsoft "Microsoft Hv" 1691 * QEMU(TCG) "TCGTCGTCGTCG" 1692 * VMware "VMwareVMware" 1693 * Xen "XenVMMXenVMM" 1694 * NetBSD "___ NVMM ___" 1695 */ 1696 if (strncmp(hv_sig, "HAXMHAXMHAXM", 12) == 0) 1697 hv_name = "HAXM"; 1698 else if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1699 hv_name = "KVM"; 1700 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1701 hv_name = "Hyper-V"; 1702 else if (strncmp(hv_sig, "TCGTCGTCGTCG", 12) == 0) 1703 hv_name = "QEMU(TCG)"; 1704 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1705 hv_name = "VMware"; 1706 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1707 hv_name = "Xen"; 1708 else if (strncmp(hv_sig, "___ NVMM ___", 12) == 0) 1709 hv_name = "NVMM"; 1710 else 1711 hv_name = "unknown"; 1712 1713 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1714 } 1715 } 1716 1717 static void 1718 cpu_probe_features(struct cpu_info *ci) 1719 { 1720 const struct cpu_cpuid_nameclass *cpup = NULL; 1721 unsigned int i; 1722 1723 if (ci->ci_max_cpuid < 1) 1724 return; 1725 1726 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1727 if (!strncmp((char *)ci->ci_vendor, 1728 i386_cpuid_cpus[i].cpu_id, 12)) { 1729 cpup = &i386_cpuid_cpus[i]; 1730 break; 1731 } 1732 } 1733 1734 if (cpup == NULL) 1735 return; 1736 1737 i = ci->ci_family - CPU_MINFAMILY; 1738 1739 if (i >= __arraycount(cpup->cpu_family)) 1740 i = __arraycount(cpup->cpu_family) - 1; 1741 1742 if (cpup->cpu_family[i].cpu_probe == NULL) 1743 return; 1744 1745 (*cpup->cpu_family[i].cpu_probe)(ci); 1746 } 1747 1748 static void 1749 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1750 { 1751 char buf[32 * 16]; 1752 char *bp; 1753 1754 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1755 1756 if (val == 0 || fmt == NULL) 1757 return; 1758 1759 snprintb_m(buf, sizeof(buf), fmt, val, 1760 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1761 bp = buf; 1762 while (*bp != '\0') { 1763 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1764 bp += strlen(bp) + 1; 1765 } 1766 } 1767 1768 static void 1769 dump_descs(uint32_t leafstart, uint32_t leafend, const char *cpuname, 1770 const char *blockname) 1771 { 1772 uint32_t descs[4]; 1773 uint32_t leaf; 1774 1775 aprint_verbose("%s: highest %s info %08x\n", cpuname, blockname, 1776 leafend); 1777 1778 if (verbose) { 1779 for (leaf = leafstart; leaf <= leafend; leaf++) { 1780 x86_cpuid(leaf, descs); 1781 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1782 leaf, descs[0], descs[1], descs[2], descs[3]); 1783 } 1784 } 1785 } 1786 1787 static void 1788 identifycpu_cpuids_intel_0x04(struct cpu_info *ci) 1789 { 1790 u_int lp_max = 1; /* logical processors per package */ 1791 u_int smt_max; /* smt per core */ 1792 u_int core_max = 1; /* core per package */ 1793 u_int smt_bits, core_bits; 1794 uint32_t descs[4]; 1795 1796 /* 1797 * 253668.pdf 7.10.2 1798 */ 1799 1800 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1801 x86_cpuid(1, descs); 1802 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1803 } 1804 x86_cpuid2(4, 0, descs); 1805 core_max = __SHIFTOUT(descs[0], CPUID_DCP_CORE_P_PKG) + 1; 1806 1807 assert(lp_max >= core_max); 1808 smt_max = lp_max / core_max; 1809 smt_bits = ilog2(smt_max - 1) + 1; 1810 core_bits = ilog2(core_max - 1) + 1; 1811 1812 if (smt_bits + core_bits) 1813 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1814 1815 if (core_bits) 1816 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1817 __BITS(smt_bits, smt_bits + core_bits - 1)); 1818 1819 if (smt_bits) 1820 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1821 __BITS((int)0, (int)(smt_bits - 1))); 1822 } 1823 1824 static void 1825 identifycpu_cpuids_intel_0x0b(struct cpu_info *ci) 1826 { 1827 const char *cpuname = ci->ci_dev; 1828 u_int smt_bits, core_bits, core_shift = 0, pkg_shift = 0; 1829 uint32_t descs[4]; 1830 int i; 1831 1832 x86_cpuid(0x0b, descs); 1833 if (descs[1] == 0) { 1834 identifycpu_cpuids_intel_0x04(ci); 1835 return; 1836 } 1837 1838 for (i = 0; ; i++) { 1839 unsigned int shiftnum, lvltype; 1840 x86_cpuid2(0x0b, i, descs); 1841 1842 /* On invalid level, (EAX and) EBX return 0 */ 1843 if (descs[1] == 0) 1844 break; 1845 1846 shiftnum = __SHIFTOUT(descs[0], CPUID_TOP_SHIFTNUM); 1847 lvltype = __SHIFTOUT(descs[2], CPUID_TOP_LVLTYPE); 1848 switch (lvltype) { 1849 case CPUID_TOP_LVLTYPE_SMT: 1850 core_shift = shiftnum; 1851 break; 1852 case CPUID_TOP_LVLTYPE_CORE: 1853 pkg_shift = shiftnum; 1854 break; 1855 case CPUID_TOP_LVLTYPE_INVAL: 1856 aprint_verbose("%s: Invalid level type\n", cpuname); 1857 break; 1858 default: 1859 aprint_verbose("%s: Unknown level type(%d) \n", 1860 cpuname, lvltype); 1861 break; 1862 } 1863 } 1864 1865 assert(pkg_shift >= core_shift); 1866 smt_bits = core_shift; 1867 core_bits = pkg_shift - core_shift; 1868 1869 ci->ci_packageid = ci->ci_initapicid >> pkg_shift; 1870 1871 if (core_bits) 1872 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1873 __BITS(core_shift, pkg_shift - 1)); 1874 1875 if (smt_bits) 1876 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1877 __BITS((int)0, core_shift - 1)); 1878 } 1879 1880 static void 1881 identifycpu_cpuids_intel(struct cpu_info *ci) 1882 { 1883 const char *cpuname = ci->ci_dev; 1884 1885 if (ci->ci_max_cpuid >= 0x0b) 1886 identifycpu_cpuids_intel_0x0b(ci); 1887 else if (ci->ci_max_cpuid >= 4) 1888 identifycpu_cpuids_intel_0x04(ci); 1889 1890 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1891 ci->ci_packageid); 1892 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1893 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1894 } 1895 1896 static void 1897 identifycpu_cpuids_amd(struct cpu_info *ci) 1898 { 1899 const char *cpuname = ci->ci_dev; 1900 u_int lp_max, core_max; 1901 int n, cpu_family, apic_id, smt_bits, core_bits = 0; 1902 uint32_t descs[4]; 1903 1904 apic_id = ci->ci_initapicid; 1905 cpu_family = CPUID_TO_FAMILY(ci->ci_signature); 1906 1907 if (cpu_family < 0xf) 1908 return; 1909 1910 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1911 x86_cpuid(1, descs); 1912 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1913 1914 if (cpu_family >= 0x10 && ci->ci_max_ext_cpuid >= 0x8000008) { 1915 x86_cpuid(0x8000008, descs); 1916 core_max = (descs[2] & 0xff) + 1; 1917 n = (descs[2] >> 12) & 0x0f; 1918 if (n != 0) 1919 core_bits = n; 1920 } 1921 } else { 1922 lp_max = 1; 1923 } 1924 core_max = lp_max; 1925 1926 smt_bits = ilog2((lp_max / core_max) - 1) + 1; 1927 if (core_bits == 0) 1928 core_bits = ilog2(core_max - 1) + 1; 1929 1930 #if 0 /* MSRs need kernel mode */ 1931 if (cpu_family < 0x11) { 1932 const uint64_t reg = rdmsr(MSR_NB_CFG); 1933 if ((reg & NB_CFG_INITAPICCPUIDLO) == 0) { 1934 const u_int node_id = apic_id & __BITS(0, 2); 1935 apic_id = (cpu_family == 0xf) ? 1936 (apic_id >> core_bits) | (node_id << core_bits) : 1937 (apic_id >> 5) | (node_id << 2); 1938 } 1939 } 1940 #endif 1941 1942 if (cpu_family == 0x17) { 1943 x86_cpuid(0x8000001e, descs); 1944 const u_int threads = ((descs[1] >> 8) & 0xff) + 1; 1945 smt_bits = ilog2(threads); 1946 core_bits -= smt_bits; 1947 } 1948 1949 if (smt_bits + core_bits) { 1950 if (smt_bits + core_bits < 32) 1951 ci->ci_packageid = 0; 1952 } 1953 if (core_bits) { 1954 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1955 ci->ci_coreid = __SHIFTOUT(apic_id, core_mask); 1956 } 1957 if (smt_bits) { 1958 u_int smt_mask = __BITS(0, smt_bits - 1); 1959 ci->ci_smtid = __SHIFTOUT(apic_id, smt_mask); 1960 } 1961 1962 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1963 ci->ci_packageid); 1964 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1965 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1966 } 1967 1968 static void 1969 identifycpu_cpuids(struct cpu_info *ci) 1970 { 1971 const char *cpuname = ci->ci_dev; 1972 1973 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1974 ci->ci_packageid = ci->ci_initapicid; 1975 ci->ci_coreid = 0; 1976 ci->ci_smtid = 0; 1977 1978 if (cpu_vendor == CPUVENDOR_INTEL) 1979 identifycpu_cpuids_intel(ci); 1980 else if (cpu_vendor == CPUVENDOR_AMD) 1981 identifycpu_cpuids_amd(ci); 1982 } 1983 1984 void 1985 identifycpu(int fd, const char *cpuname) 1986 { 1987 const char *name = "", *modifier, *vendorname, *brand = ""; 1988 int class = CPUCLASS_386; 1989 unsigned int i; 1990 int modif, family; 1991 const struct cpu_cpuid_nameclass *cpup = NULL; 1992 const struct cpu_cpuid_family *cpufam; 1993 struct cpu_info *ci, cistore; 1994 u_int descs[4]; 1995 size_t sz; 1996 struct cpu_ucode_version ucode; 1997 union { 1998 struct cpu_ucode_version_amd amd; 1999 struct cpu_ucode_version_intel1 intel1; 2000 } ucvers; 2001 2002 ci = &cistore; 2003 cpu_probe_base_features(ci, cpuname); 2004 dump_descs(0x00000000, ci->ci_max_cpuid, cpuname, "basic"); 2005 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 2006 x86_cpuid(0x40000000, descs); 2007 dump_descs(0x40000000, descs[0], cpuname, "hypervisor"); 2008 } 2009 dump_descs(0x80000000, ci->ci_max_ext_cpuid, cpuname, "extended"); 2010 2011 cpu_probe_hv_features(ci, cpuname); 2012 cpu_probe_features(ci); 2013 2014 if (ci->ci_cpu_type >= 0) { 2015 /* Old pre-cpuid instruction cpu */ 2016 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 2017 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 2018 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 2019 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 2020 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 2021 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 2022 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 2023 modifier = ""; 2024 } else { 2025 /* CPU which support cpuid instruction */ 2026 modif = (ci->ci_signature >> 12) & 0x3; 2027 family = ci->ci_family; 2028 if (family < CPU_MINFAMILY) 2029 errx(1, "identifycpu: strange family value"); 2030 if (family > CPU_MAXFAMILY) 2031 family = CPU_MAXFAMILY; 2032 2033 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 2034 if (!strncmp((char *)ci->ci_vendor, 2035 i386_cpuid_cpus[i].cpu_id, 12)) { 2036 cpup = &i386_cpuid_cpus[i]; 2037 break; 2038 } 2039 } 2040 2041 if (cpup == NULL) { 2042 cpu_vendor = CPUVENDOR_UNKNOWN; 2043 if (ci->ci_vendor[0] != '\0') 2044 vendorname = (char *)&ci->ci_vendor[0]; 2045 else 2046 vendorname = "Unknown"; 2047 class = family - 3; 2048 modifier = ""; 2049 name = ""; 2050 ci->ci_info = NULL; 2051 } else { 2052 cpu_vendor = cpup->cpu_vendor; 2053 vendorname = cpup->cpu_vendorname; 2054 modifier = modifiers[modif]; 2055 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 2056 name = cpufam->cpu_models[ci->ci_model]; 2057 if (name == NULL || *name == '\0') 2058 name = cpufam->cpu_model_default; 2059 class = cpufam->cpu_class; 2060 ci->ci_info = cpufam->cpu_info; 2061 2062 if (cpu_vendor == CPUVENDOR_INTEL) { 2063 if (ci->ci_family == 6 && ci->ci_model >= 5) { 2064 const char *tmp; 2065 tmp = intel_family6_name(ci); 2066 if (tmp != NULL) 2067 name = tmp; 2068 } 2069 if (ci->ci_family == 15 && 2070 ci->ci_brand_id < 2071 __arraycount(i386_intel_brand) && 2072 i386_intel_brand[ci->ci_brand_id]) 2073 name = 2074 i386_intel_brand[ci->ci_brand_id]; 2075 } 2076 2077 if (cpu_vendor == CPUVENDOR_AMD) { 2078 if (ci->ci_family == 6 && ci->ci_model >= 6) { 2079 if (ci->ci_brand_id == 1) 2080 /* 2081 * It's Duron. We override the 2082 * name, since it might have 2083 * been misidentified as Athlon. 2084 */ 2085 name = 2086 amd_brand[ci->ci_brand_id]; 2087 else 2088 brand = amd_brand_name; 2089 } 2090 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 2091 == 0xf) { 2092 /* Identify AMD64 CPU names. */ 2093 const char *tmp; 2094 tmp = amd_amd64_name(ci); 2095 if (tmp != NULL) 2096 name = tmp; 2097 } 2098 } 2099 2100 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 2101 vendorname = "VIA"; 2102 } 2103 } 2104 2105 ci->ci_cpu_class = class; 2106 2107 sz = sizeof(ci->ci_tsc_freq); 2108 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 2109 sz = sizeof(use_pae); 2110 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 2111 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 2112 2113 /* 2114 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 2115 * we try to determine from the family/model values. 2116 */ 2117 if (*cpu_brand_string != '\0') 2118 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 2119 2120 aprint_normal("%s: %s", cpuname, vendorname); 2121 if (*modifier) 2122 aprint_normal(" %s", modifier); 2123 if (*name) 2124 aprint_normal(" %s", name); 2125 if (*brand) 2126 aprint_normal(" %s", brand); 2127 aprint_normal(" (%s-class)", classnames[class]); 2128 2129 if (ci->ci_tsc_freq != 0) 2130 aprint_normal(", %ju.%02ju MHz", 2131 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 2132 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 2133 aprint_normal("\n"); 2134 2135 (void)cpu_tsc_freq_cpuid(ci); 2136 2137 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 2138 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 2139 if (ci->ci_signature != 0) 2140 aprint_normal(" (id %#x)", ci->ci_signature); 2141 aprint_normal("\n"); 2142 2143 if (ci->ci_info) 2144 (*ci->ci_info)(ci); 2145 2146 /* 2147 * display CPU feature flags 2148 */ 2149 2150 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 2151 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 2152 2153 /* These next two are actually common definitions! */ 2154 print_bits(cpuname, "features2", 2155 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 2156 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 2157 print_bits(cpuname, "features3", 2158 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 2159 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 2160 2161 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 2162 ci->ci_feat_val[4]); 2163 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2164 print_bits(cpuname, "features5", CPUID_SEF_FLAGS, 2165 ci->ci_feat_val[5]); 2166 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2167 print_bits(cpuname, "features6", CPUID_SEF_FLAGS1, 2168 ci->ci_feat_val[6]); 2169 2170 if (cpu_vendor == CPUVENDOR_INTEL) 2171 print_bits(cpuname, "features7", CPUID_SEF_FLAGS2, 2172 ci->ci_feat_val[7]); 2173 2174 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[8]); 2175 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 2176 ci->ci_feat_val[9]); 2177 2178 if (ci->ci_max_xsave != 0) { 2179 aprint_normal("%s: xsave area size: current %d, maximum %d", 2180 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 2181 aprint_normal(", xgetbv %sabled\n", 2182 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 2183 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 2184 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 2185 x86_xgetbv()); 2186 } 2187 2188 x86_print_cache_and_tlb_info(ci); 2189 2190 if (ci->ci_max_cpuid >= 3 && (ci->ci_feat_val[0] & CPUID_PSN)) { 2191 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 2192 cpuname, 2193 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 2194 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 2195 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 2196 } 2197 2198 if (ci->ci_cpu_class == CPUCLASS_386) 2199 errx(1, "NetBSD requires an 80486 or later processor"); 2200 2201 if (ci->ci_cpu_type == CPU_486DLC) { 2202 #ifndef CYRIX_CACHE_WORKS 2203 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 2204 #else 2205 #ifndef CYRIX_CACHE_REALLY_WORKS 2206 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 2207 #else 2208 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 2209 #endif 2210 #endif 2211 } 2212 2213 /* 2214 * Everything past this point requires a Pentium or later. 2215 */ 2216 if (ci->ci_max_cpuid < 0) 2217 return; 2218 2219 identifycpu_cpuids(ci); 2220 2221 if ((ci->ci_max_cpuid >= 5) 2222 && ((cpu_vendor == CPUVENDOR_INTEL) 2223 || (cpu_vendor == CPUVENDOR_AMD))) { 2224 uint16_t lmin, lmax; 2225 x86_cpuid(5, descs); 2226 2227 print_bits(cpuname, "MONITOR/MWAIT extensions", 2228 CPUID_MON_FLAGS, descs[2]); 2229 lmin = __SHIFTOUT(descs[0], CPUID_MON_MINSIZE); 2230 lmax = __SHIFTOUT(descs[1], CPUID_MON_MAXSIZE); 2231 aprint_normal("%s: monitor-line size %hu", cpuname, lmin); 2232 if (lmin != lmax) 2233 aprint_normal("-%hu", lmax); 2234 aprint_normal("\n"); 2235 2236 for (i = 0; i <= 7; i++) { 2237 unsigned int num = CPUID_MON_SUBSTATE(descs[3], i); 2238 2239 if (num != 0) 2240 aprint_normal("%s: C%u substates %u\n", 2241 cpuname, i, num); 2242 } 2243 } 2244 if ((ci->ci_max_cpuid >= 6) 2245 && ((cpu_vendor == CPUVENDOR_INTEL) 2246 || (cpu_vendor == CPUVENDOR_AMD))) { 2247 x86_cpuid(6, descs); 2248 print_bits(cpuname, "DSPM-eax", CPUID_DSPM_FLAGS, descs[0]); 2249 print_bits(cpuname, "DSPM-ecx", CPUID_DSPM_FLAGS1, descs[2]); 2250 } 2251 if ((ci->ci_max_cpuid >= 7) 2252 && ((cpu_vendor == CPUVENDOR_INTEL) 2253 || (cpu_vendor == CPUVENDOR_AMD))) { 2254 x86_cpuid(7, descs); 2255 aprint_verbose("%s: SEF highest subleaf %08x\n", 2256 cpuname, descs[0]); 2257 if (descs[0] >= 1) { 2258 x86_cpuid2(7, 1, descs); 2259 print_bits(cpuname, "SEF-subleaf1-eax", 2260 CPUID_SEF1_FLAGS_A, descs[0]); 2261 } 2262 } 2263 2264 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) { 2265 if (ci->ci_max_ext_cpuid >= 0x80000007) 2266 powernow_probe(ci); 2267 2268 if (ci->ci_max_ext_cpuid >= 0x80000008) { 2269 x86_cpuid(0x80000008, descs); 2270 print_bits(cpuname, "AMD Extended features", 2271 CPUID_CAPEX_FLAGS, descs[1]); 2272 } 2273 } 2274 2275 if (cpu_vendor == CPUVENDOR_AMD) { 2276 if ((ci->ci_max_ext_cpuid >= 0x8000000a) 2277 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 2278 x86_cpuid(0x8000000a, descs); 2279 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 2280 descs[0] & 0xf); 2281 aprint_verbose("%s: SVM NASID %d\n", cpuname, 2282 descs[1]); 2283 print_bits(cpuname, "SVM features", 2284 CPUID_AMD_SVM_FLAGS, descs[3]); 2285 } 2286 if (ci->ci_max_ext_cpuid >= 0x8000001f) { 2287 x86_cpuid(0x8000001f, descs); 2288 print_bits(cpuname, "Encrypted Memory features", 2289 CPUID_AMD_ENCMEM_FLAGS, descs[0]); 2290 } 2291 } else if (cpu_vendor == CPUVENDOR_INTEL) { 2292 int32_t bi_index; 2293 2294 for (bi_index = 1; bi_index <= ci->ci_max_cpuid; bi_index++) { 2295 x86_cpuid(bi_index, descs); 2296 switch (bi_index) { 2297 case 0x0a: 2298 print_bits(cpuname, "Perfmon-eax", 2299 CPUID_PERF_FLAGS0, descs[0]); 2300 print_bits(cpuname, "Perfmon-ebx", 2301 CPUID_PERF_FLAGS1, descs[1]); 2302 print_bits(cpuname, "Perfmon-edx", 2303 CPUID_PERF_FLAGS3, descs[3]); 2304 break; 2305 default: 2306 #if 0 2307 aprint_verbose("%s: basic %08x-eax %08x\n", 2308 cpuname, bi_index, descs[0]); 2309 aprint_verbose("%s: basic %08x-ebx %08x\n", 2310 cpuname, bi_index, descs[1]); 2311 aprint_verbose("%s: basic %08x-ecx %08x\n", 2312 cpuname, bi_index, descs[2]); 2313 aprint_verbose("%s: basic %08x-edx %08x\n", 2314 cpuname, bi_index, descs[3]); 2315 #endif 2316 break; 2317 } 2318 } 2319 } 2320 2321 #ifdef INTEL_ONDEMAND_CLOCKMOD 2322 clockmod_init(); 2323 #endif 2324 2325 if (cpu_vendor == CPUVENDOR_AMD) 2326 ucode.loader_version = CPU_UCODE_LOADER_AMD; 2327 else if (cpu_vendor == CPUVENDOR_INTEL) 2328 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 2329 else 2330 return; 2331 2332 ucode.data = &ucvers; 2333 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 2334 #ifdef __i386__ 2335 struct cpu_ucode_version_64 ucode_64; 2336 if (errno != ENOTTY) 2337 return; 2338 /* Try the 64 bit ioctl */ 2339 memset(&ucode_64, 0, sizeof ucode_64); 2340 ucode_64.data = &ucvers; 2341 ucode_64.loader_version = ucode.loader_version; 2342 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 2343 return; 2344 #else 2345 return; 2346 #endif 2347 } 2348 2349 if (cpu_vendor == CPUVENDOR_AMD) 2350 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2351 else if (cpu_vendor == CPUVENDOR_INTEL) 2352 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2353 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2354 } 2355 2356 static const struct x86_cache_info * 2357 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 2358 { 2359 int i; 2360 2361 for (i = 0; cai[i].cai_desc != 0; i++) { 2362 if (cai[i].cai_desc == desc) 2363 return (&cai[i]); 2364 } 2365 2366 return (NULL); 2367 } 2368 2369 static const char * 2370 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2371 const char *sep) 2372 { 2373 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2374 char human_num[HUMAN_BUFSIZE]; 2375 2376 if (cai->cai_totalsize == 0) 2377 return sep; 2378 2379 if (sep == NULL) 2380 aprint_verbose_dev(ci->ci_dev, ""); 2381 else 2382 aprint_verbose("%s", sep); 2383 if (name != NULL) 2384 aprint_verbose("%s ", name); 2385 2386 if (cai->cai_string != NULL) { 2387 aprint_verbose("%s ", cai->cai_string); 2388 } else { 2389 (void)humanize_number(human_num, sizeof(human_num), 2390 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2391 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2392 } 2393 switch (cai->cai_associativity) { 2394 case 0: 2395 aprint_verbose("disabled"); 2396 break; 2397 case 1: 2398 aprint_verbose("direct-mapped"); 2399 break; 2400 case 0xff: 2401 aprint_verbose("fully associative"); 2402 break; 2403 default: 2404 aprint_verbose("%d-way", cai->cai_associativity); 2405 break; 2406 } 2407 return ", "; 2408 } 2409 2410 static const char * 2411 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2412 const char *sep) 2413 { 2414 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2415 char human_num[HUMAN_BUFSIZE]; 2416 2417 if (cai->cai_totalsize == 0) 2418 return sep; 2419 2420 if (sep == NULL) 2421 aprint_verbose_dev(ci->ci_dev, ""); 2422 else 2423 aprint_verbose("%s", sep); 2424 if ((name != NULL) && (sep == NULL)) 2425 aprint_verbose("%s ", name); 2426 2427 if (cai->cai_string != NULL) { 2428 aprint_verbose("%s", cai->cai_string); 2429 } else { 2430 (void)humanize_number(human_num, sizeof(human_num), 2431 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2432 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2433 human_num); 2434 switch (cai->cai_associativity) { 2435 case 0: 2436 aprint_verbose("disabled"); 2437 break; 2438 case 1: 2439 aprint_verbose("direct-mapped"); 2440 break; 2441 case 0xff: 2442 aprint_verbose("fully associative"); 2443 break; 2444 default: 2445 aprint_verbose("%d-way", cai->cai_associativity); 2446 break; 2447 } 2448 } 2449 return ", "; 2450 } 2451 2452 static void 2453 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2454 { 2455 const char *sep = NULL; 2456 2457 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2458 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2459 sep = print_cache_config(ci, CAI_ICACHE, "I-cache:", NULL); 2460 sep = print_cache_config(ci, CAI_DCACHE, "D-cache:", sep); 2461 if (sep != NULL) 2462 aprint_verbose("\n"); 2463 } 2464 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2465 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache:", NULL); 2466 if (sep != NULL) 2467 aprint_verbose("\n"); 2468 } 2469 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2470 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache:", NULL); 2471 if (sep != NULL) 2472 aprint_verbose("\n"); 2473 } 2474 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2475 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2476 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2477 if (sep != NULL) 2478 aprint_verbose("\n"); 2479 } 2480 2481 sep = print_tlb_config(ci, CAI_ITLB, "ITLB:", NULL); 2482 sep = print_tlb_config(ci, CAI_ITLB2, "ITLB:", sep); 2483 if (sep != NULL) 2484 aprint_verbose("\n"); 2485 2486 sep = print_tlb_config(ci, CAI_DTLB, "DTLB:", NULL); 2487 sep = print_tlb_config(ci, CAI_DTLB2, "DTLB:", sep); 2488 if (sep != NULL) 2489 aprint_verbose("\n"); 2490 2491 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB:", NULL); 2492 sep = print_tlb_config(ci, CAI_L2_ITLB2, "L2 ITLB:", sep); 2493 if (sep != NULL) 2494 aprint_verbose("\n"); 2495 2496 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB:", NULL); 2497 sep = print_tlb_config(ci, CAI_L2_DTLB2, "L2 DTLB:", sep); 2498 if (sep != NULL) 2499 aprint_verbose("\n"); 2500 2501 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB:", NULL); 2502 sep = print_tlb_config(ci, CAI_L2_STLB2, "L2 STLB:", sep); 2503 sep = print_tlb_config(ci, CAI_L2_STLB3, "L2 STLB:", sep); 2504 if (sep != NULL) 2505 aprint_verbose("\n"); 2506 2507 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB:", NULL); 2508 if (sep != NULL) 2509 aprint_verbose("\n"); 2510 2511 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB:", NULL); 2512 if (sep != NULL) 2513 aprint_verbose("\n"); 2514 2515 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB:", NULL); 2516 if (sep != NULL) 2517 aprint_verbose("\n"); 2518 2519 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB:", NULL); 2520 if (sep != NULL) 2521 aprint_verbose("\n"); 2522 } 2523 2524 static void 2525 powernow_probe(struct cpu_info *ci) 2526 { 2527 uint32_t regs[4]; 2528 char buf[256]; 2529 2530 x86_cpuid(0x80000007, regs); 2531 2532 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2533 aprint_normal_dev(ci->ci_dev, "Power Management features: %s\n", buf); 2534 } 2535 2536 bool 2537 identifycpu_bind(void) 2538 { 2539 2540 return true; 2541 } 2542 2543 int 2544 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2545 { 2546 struct cpu_info ci; 2547 int loader_version, res; 2548 struct cpu_ucode_version versreq; 2549 2550 cpu_probe_base_features(&ci, "unknown"); 2551 2552 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2553 loader_version = CPU_UCODE_LOADER_AMD; 2554 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2555 loader_version = CPU_UCODE_LOADER_INTEL1; 2556 else 2557 return -1; 2558 2559 /* check whether the kernel understands this loader version */ 2560 versreq.loader_version = loader_version; 2561 versreq.data = 0; 2562 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2563 if (res) 2564 return -1; 2565 2566 switch (loader_version) { 2567 case CPU_UCODE_LOADER_AMD: 2568 if (uc->cpu_nr != -1) { 2569 /* printf? */ 2570 return -1; 2571 } 2572 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2573 break; 2574 case CPU_UCODE_LOADER_INTEL1: 2575 if (uc->cpu_nr == -1) 2576 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2577 else 2578 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2579 break; 2580 default: /* can't happen */ 2581 return -1; 2582 } 2583 uc->loader_version = loader_version; 2584 return 0; 2585 } 2586
Indexes created Fri Sep 26 08:10:20 GMT 2025