i386.c revision 1.12
1 /* $NetBSD: i386.c,v 1.12 2008/10/13 21:11:46 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.12 2008/10/13 21:11:46 cegger Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 68 #include <string.h> 69 #include <stdio.h> 70 #include <stdlib.h> 71 #include <err.h> 72 #include <assert.h> 73 #include <math.h> 74 75 #include <machine/specialreg.h> 76 #include <machine/cpu.h> 77 78 #include <x86/cpuvar.h> 79 #include <x86/cputypes.h> 80 #include <x86/cacheinfo.h> 81 82 #include "../cpuctl.h" 83 84 /* Size of buffer for printing humanized numbers */ 85 #define HUMAN_BUFSIZE 5 86 87 #define x86_cpuid(a,b) x86_cpuid2((a),0,(b)) 88 89 void x86_cpuid2(uint32_t, uint32_t, uint32_t *); 90 void x86_identify(void); 91 92 struct cpu_info { 93 const char *ci_dev; 94 int32_t ci_cpuid_level; 95 uint32_t ci_signature; /* X86 cpuid type */ 96 uint32_t ci_feature_flags;/* X86 %edx CPUID feature bits */ 97 uint32_t ci_feature2_flags;/* X86 %ecx CPUID feature bits */ 98 uint32_t ci_feature3_flags;/* X86 extended %edx feature bits */ 99 uint32_t ci_feature4_flags;/* X86 extended %ecx feature bits */ 100 uint32_t ci_padlock_flags;/* VIA PadLock feature bits */ 101 uint32_t ci_cpu_class; /* CPU class */ 102 uint32_t ci_brand_id; /* Intel brand id */ 103 uint32_t ci_vendor[4]; /* vendor string */ 104 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 105 uint64_t ci_tsc_freq; /* cpu cycles/second */ 106 uint8_t ci_packageid; 107 uint8_t ci_coreid; 108 uint8_t ci_smtid; 109 uint32_t ci_initapicid; 110 struct x86_cache_info ci_cinfo[CAI_COUNT]; 111 void (*ci_info)(struct cpu_info *); 112 }; 113 114 struct cpu_nocpuid_nameclass { 115 int cpu_vendor; 116 const char *cpu_vendorname; 117 const char *cpu_name; 118 int cpu_class; 119 void (*cpu_setup)(struct cpu_info *); 120 void (*cpu_cacheinfo)(struct cpu_info *); 121 void (*cpu_info)(struct cpu_info *); 122 }; 123 124 125 struct cpu_cpuid_nameclass { 126 const char *cpu_id; 127 int cpu_vendor; 128 const char *cpu_vendorname; 129 struct cpu_cpuid_family { 130 int cpu_class; 131 const char *cpu_models[CPU_MAXMODEL+2]; 132 void (*cpu_setup)(struct cpu_info *); 133 void (*cpu_probe)(struct cpu_info *); 134 void (*cpu_info)(struct cpu_info *); 135 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 136 }; 137 138 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 139 140 /* 141 * Map Brand ID from cpuid instruction to brand name. 142 * Source: Intel Processor Identification and the CPUID Instruction, AP-485 143 */ 144 static const char * const i386_intel_brand[] = { 145 "", /* Unsupported */ 146 "Celeron", /* Intel (R) Celeron (TM) processor */ 147 "Pentium III", /* Intel (R) Pentium (R) III processor */ 148 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 149 "Pentium III", /* Intel (R) Pentium (R) III processor */ 150 "", /* Reserved */ 151 "Mobile Pentium III", /* Mobile Intel (R) Pentium (R) III processor-M */ 152 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 153 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 154 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 155 "Celeron", /* Intel (R) Celeron (TM) processor */ 156 "Xeon", /* Intel (R) Xeon (TM) processor */ 157 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 158 "", /* Reserved */ 159 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 160 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 161 }; 162 163 /* 164 * AMD processors don't have Brand IDs, so we need these names for probe. 165 */ 166 static const char * const amd_brand[] = { 167 "", 168 "Duron", /* AMD Duron(tm) */ 169 "MP", /* AMD Athlon(tm) MP */ 170 "XP", /* AMD Athlon(tm) XP */ 171 "4" /* AMD Athlon(tm) 4 */ 172 }; 173 174 static int cpu_vendor; 175 static char cpu_brand_string[49]; 176 static char amd_brand_name[48]; 177 178 static void via_cpu_probe(struct cpu_info *); 179 static void amd_family6_probe(struct cpu_info *); 180 static void intel_family_new_probe(struct cpu_info *); 181 static const char *intel_family6_name(struct cpu_info *); 182 static const char *amd_amd64_name(struct cpu_info *); 183 static void amd_family5_setup(struct cpu_info *); 184 static void transmeta_cpu_info(struct cpu_info *); 185 static const char *print_cache_config(struct cpu_info *, int, const char *, 186 const char *); 187 static const char *print_tlb_config(struct cpu_info *, int, const char *, 188 const char *); 189 static void amd_cpu_cacheinfo(struct cpu_info *); 190 static void via_cpu_cacheinfo(struct cpu_info *); 191 static void x86_print_cacheinfo(struct cpu_info *); 192 static const struct x86_cache_info *cache_info_lookup( 193 const struct x86_cache_info *, uint8_t); 194 static void cyrix6x86_cpu_setup(struct cpu_info *); 195 static void winchip_cpu_setup(struct cpu_info *); 196 static void amd_family5_setup(struct cpu_info *); 197 static void powernow_probe(struct cpu_info *); 198 199 /* 200 * Info for CTL_HW 201 */ 202 static char cpu_model[120]; 203 204 /* 205 * Note: these are just the ones that may not have a cpuid instruction. 206 * We deal with the rest in a different way. 207 */ 208 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 209 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 210 NULL, NULL, NULL }, /* CPU_386SX */ 211 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 212 NULL, NULL, NULL }, /* CPU_386 */ 213 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 214 NULL, NULL, NULL }, /* CPU_486SX */ 215 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 216 NULL, NULL, NULL }, /* CPU_486 */ 217 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 218 NULL, NULL, NULL }, /* CPU_486DLC */ 219 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 220 NULL, NULL, NULL }, /* CPU_6x86 */ 221 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 222 NULL, NULL, NULL }, /* CPU_NX586 */ 223 }; 224 225 const char *classnames[] = { 226 "386", 227 "486", 228 "586", 229 "686" 230 }; 231 232 const char *modifiers[] = { 233 "", 234 "OverDrive", 235 "Dual", 236 "" 237 }; 238 239 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 240 { 241 "GenuineIntel", 242 CPUVENDOR_INTEL, 243 "Intel", 244 /* Family 4 */ 245 { { 246 CPUCLASS_486, 247 { 248 "486DX", "486DX", "486SX", "486DX2", "486SL", 249 "486SX2", 0, "486DX2 W/B Enhanced", 250 "486DX4", 0, 0, 0, 0, 0, 0, 0, 251 "486" /* Default */ 252 }, 253 NULL, 254 NULL, 255 NULL, 256 }, 257 /* Family 5 */ 258 { 259 CPUCLASS_586, 260 { 261 "Pentium (P5 A-step)", "Pentium (P5)", 262 "Pentium (P54C)", "Pentium (P24T)", 263 "Pentium/MMX", "Pentium", 0, 264 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 265 0, 0, 0, 0, 0, 0, 0, 266 "Pentium" /* Default */ 267 }, 268 NULL, 269 NULL, 270 NULL, 271 }, 272 /* Family 6 */ 273 { 274 CPUCLASS_686, 275 { 276 "Pentium Pro (A-step)", "Pentium Pro", 0, 277 "Pentium II (Klamath)", "Pentium Pro", 278 "Pentium II/Celeron (Deschutes)", 279 "Celeron (Mendocino)", 280 "Pentium III (Katmai)", 281 "Pentium III (Coppermine)", 282 "Pentium M (Banias)", 283 "Pentium III Xeon (Cascades)", 284 "Pentium III (Tualatin)", 0, 285 "Pentium M (Dothan)", 286 "Pentium M (Yonah)", 287 "Core 2 (Merom)", 288 "Pentium Pro, II or III" /* Default */ 289 }, 290 NULL, 291 intel_family_new_probe, 292 NULL, 293 }, 294 /* Family > 6 */ 295 { 296 CPUCLASS_686, 297 { 298 0, 0, 0, 0, 0, 0, 0, 0, 299 0, 0, 0, 0, 0, 0, 0, 0, 300 "Pentium 4" /* Default */ 301 }, 302 NULL, 303 intel_family_new_probe, 304 NULL, 305 } } 306 }, 307 { 308 "AuthenticAMD", 309 CPUVENDOR_AMD, 310 "AMD", 311 /* Family 4 */ 312 { { 313 CPUCLASS_486, 314 { 315 0, 0, 0, "Am486DX2 W/T", 316 0, 0, 0, "Am486DX2 W/B", 317 "Am486DX4 W/T or Am5x86 W/T 150", 318 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 319 0, 0, "Am5x86 W/T 133/160", 320 "Am5x86 W/B 133/160", 321 "Am486 or Am5x86" /* Default */ 322 }, 323 NULL, 324 NULL, 325 NULL, 326 }, 327 /* Family 5 */ 328 { 329 CPUCLASS_586, 330 { 331 "K5", "K5", "K5", "K5", 0, 0, "K6", 332 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 333 "K6-2+/III+", 0, 0, 334 "K5 or K6" /* Default */ 335 }, 336 amd_family5_setup, 337 NULL, 338 amd_cpu_cacheinfo, 339 }, 340 /* Family 6 */ 341 { 342 CPUCLASS_686, 343 { 344 0, "Athlon Model 1", "Athlon Model 2", 345 "Duron", "Athlon Model 4 (Thunderbird)", 346 0, "Athlon", "Duron", "Athlon", 0, 347 "Athlon", 0, 0, 0, 0, 0, 348 "K7 (Athlon)" /* Default */ 349 }, 350 NULL, 351 amd_family6_probe, 352 amd_cpu_cacheinfo, 353 }, 354 /* Family > 6 */ 355 { 356 CPUCLASS_686, 357 { 358 0, 0, 0, 0, 0, 0, 0, 0, 359 0, 0, 0, 0, 0, 0, 0, 0, 360 "Unknown K8 (Athlon)" /* Default */ 361 }, 362 NULL, 363 amd_family6_probe, 364 amd_cpu_cacheinfo, 365 } } 366 }, 367 { 368 "CyrixInstead", 369 CPUVENDOR_CYRIX, 370 "Cyrix", 371 /* Family 4 */ 372 { { 373 CPUCLASS_486, 374 { 375 0, 0, 0, 376 "MediaGX", 377 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 378 "486" /* Default */ 379 }, 380 cyrix6x86_cpu_setup, /* XXX ?? */ 381 NULL, 382 NULL, 383 }, 384 /* Family 5 */ 385 { 386 CPUCLASS_586, 387 { 388 0, 0, "6x86", 0, 389 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 390 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 391 "6x86" /* Default */ 392 }, 393 cyrix6x86_cpu_setup, 394 NULL, 395 NULL, 396 }, 397 /* Family 6 */ 398 { 399 CPUCLASS_686, 400 { 401 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 402 0, 0, 0, 0, 0, 0, 0, 0, 403 "6x86MX" /* Default */ 404 }, 405 cyrix6x86_cpu_setup, 406 NULL, 407 NULL, 408 }, 409 /* Family > 6 */ 410 { 411 CPUCLASS_686, 412 { 413 0, 0, 0, 0, 0, 0, 0, 0, 414 0, 0, 0, 0, 0, 0, 0, 0, 415 "Unknown 6x86MX" /* Default */ 416 }, 417 NULL, 418 NULL, 419 NULL, 420 } } 421 }, 422 { /* MediaGX is now owned by National Semiconductor */ 423 "Geode by NSC", 424 CPUVENDOR_CYRIX, /* XXX */ 425 "National Semiconductor", 426 /* Family 4, NSC never had any of these */ 427 { { 428 CPUCLASS_486, 429 { 430 0, 0, 0, 0, 0, 0, 0, 0, 431 0, 0, 0, 0, 0, 0, 0, 0, 432 "486 compatible" /* Default */ 433 }, 434 NULL, 435 NULL, 436 NULL, 437 }, 438 /* Family 5: Geode family, formerly MediaGX */ 439 { 440 CPUCLASS_586, 441 { 442 0, 0, 0, 0, 443 "Geode GX1", 444 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 445 "Geode" /* Default */ 446 }, 447 cyrix6x86_cpu_setup, 448 NULL, 449 amd_cpu_cacheinfo, 450 }, 451 /* Family 6, not yet available from NSC */ 452 { 453 CPUCLASS_686, 454 { 455 0, 0, 0, 0, 0, 0, 0, 0, 456 0, 0, 0, 0, 0, 0, 0, 0, 457 "Pentium Pro compatible" /* Default */ 458 }, 459 NULL, 460 NULL, 461 NULL, 462 }, 463 /* Family > 6, not yet available from NSC */ 464 { 465 CPUCLASS_686, 466 { 467 0, 0, 0, 0, 0, 0, 0, 0, 468 0, 0, 0, 0, 0, 0, 0, 0, 469 "Pentium Pro compatible" /* Default */ 470 }, 471 NULL, 472 NULL, 473 NULL, 474 } } 475 }, 476 { 477 "CentaurHauls", 478 CPUVENDOR_IDT, 479 "IDT", 480 /* Family 4, IDT never had any of these */ 481 { { 482 CPUCLASS_486, 483 { 484 0, 0, 0, 0, 0, 0, 0, 0, 485 0, 0, 0, 0, 0, 0, 0, 0, 486 "486 compatible" /* Default */ 487 }, 488 NULL, 489 NULL, 490 NULL, 491 }, 492 /* Family 5 */ 493 { 494 CPUCLASS_586, 495 { 496 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 497 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 498 "WinChip" /* Default */ 499 }, 500 winchip_cpu_setup, 501 NULL, 502 NULL, 503 }, 504 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 505 { 506 CPUCLASS_686, 507 { 508 0, 0, 0, 0, 0, 0, "C3 Samuel", 509 "C3 Samuel 2/Ezra", "C3 Ezra-T", 510 "C3 Nehemiah", "C7 Esther", 0, 0, 0, 0, 0, 511 "C3" /* Default */ 512 }, 513 NULL, 514 via_cpu_probe, 515 via_cpu_cacheinfo, 516 }, 517 /* Family > 6, not yet available from VIA */ 518 { 519 CPUCLASS_686, 520 { 521 0, 0, 0, 0, 0, 0, 0, 0, 522 0, 0, 0, 0, 0, 0, 0, 0, 523 "Pentium Pro compatible" /* Default */ 524 }, 525 NULL, 526 NULL, 527 NULL, 528 } } 529 }, 530 { 531 "GenuineTMx86", 532 CPUVENDOR_TRANSMETA, 533 "Transmeta", 534 /* Family 4, Transmeta never had any of these */ 535 { { 536 CPUCLASS_486, 537 { 538 0, 0, 0, 0, 0, 0, 0, 0, 539 0, 0, 0, 0, 0, 0, 0, 0, 540 "486 compatible" /* Default */ 541 }, 542 NULL, 543 NULL, 544 NULL, 545 }, 546 /* Family 5 */ 547 { 548 CPUCLASS_586, 549 { 550 0, 0, 0, 0, 0, 0, 0, 0, 551 0, 0, 0, 0, 0, 0, 0, 0, 552 "Crusoe" /* Default */ 553 }, 554 NULL, 555 NULL, 556 transmeta_cpu_info, 557 }, 558 /* Family 6, not yet available from Transmeta */ 559 { 560 CPUCLASS_686, 561 { 562 0, 0, 0, 0, 0, 0, 0, 0, 563 0, 0, 0, 0, 0, 0, 0, 0, 564 "Pentium Pro compatible" /* Default */ 565 }, 566 NULL, 567 NULL, 568 NULL, 569 }, 570 /* Family > 6, not yet available from Transmeta */ 571 { 572 CPUCLASS_686, 573 { 574 0, 0, 0, 0, 0, 0, 0, 0, 575 0, 0, 0, 0, 0, 0, 0, 0, 576 "Pentium Pro compatible" /* Default */ 577 }, 578 NULL, 579 NULL, 580 NULL, 581 } } 582 } 583 }; 584 585 /* 586 * disable the TSC such that we don't use the TSC in microtime(9) 587 * because some CPUs got the implementation wrong. 588 */ 589 static void 590 disable_tsc(struct cpu_info *ci) 591 { 592 if (ci->ci_feature_flags & CPUID_TSC) { 593 ci->ci_feature_flags &= ~CPUID_TSC; 594 aprint_error("WARNING: broken TSC disabled\n"); 595 } 596 } 597 598 static void 599 cyrix6x86_cpu_setup(struct cpu_info *ci) 600 { 601 602 /* 603 * Do not disable the TSC on the Geode GX, it's reported to 604 * work fine. 605 */ 606 if (ci->ci_signature != 0x552) 607 disable_tsc(ci); 608 } 609 610 void 611 winchip_cpu_setup(struct cpu_info *ci) 612 { 613 switch (CPUID2MODEL(ci->ci_signature)) { /* model */ 614 case 4: /* WinChip C6 */ 615 disable_tsc(ci); 616 } 617 } 618 619 620 static void 621 identifycpu_cpuids(struct cpu_info *ci) 622 { 623 const char *cpuname = ci->ci_dev; 624 u_int lp_max = 1; /* logical processors per package */ 625 u_int smt_max; /* smt per core */ 626 u_int core_max = 1; /* core per package */ 627 int smt_bits, core_bits; 628 uint32_t descs[4]; 629 630 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 631 ci->ci_packageid = ci->ci_initapicid; 632 ci->ci_coreid = 0; 633 ci->ci_smtid = 0; 634 if (cpu_vendor != CPUVENDOR_INTEL) { 635 return; 636 } 637 638 /* 639 * 253668.pdf 7.10.2 640 */ 641 642 if ((ci->ci_feature_flags & CPUID_HTT) != 0) { 643 x86_cpuid(1, descs); 644 lp_max = (descs[1] >> 16) & 0xff; 645 } 646 x86_cpuid(0, descs); 647 if (descs[0] >= 4) { 648 x86_cpuid2(4, 0, descs); 649 core_max = (descs[0] >> 26) + 1; 650 } 651 assert(lp_max >= core_max); 652 smt_max = lp_max / core_max; 653 smt_bits = ilog2(smt_max - 1) + 1; 654 core_bits = ilog2(core_max - 1) + 1; 655 if (smt_bits + core_bits) { 656 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 657 } 658 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 659 ci->ci_packageid); 660 if (core_bits) { 661 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 662 663 ci->ci_coreid = 664 __SHIFTOUT(ci->ci_initapicid, core_mask); 665 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 666 } 667 if (smt_bits) { 668 u_int smt_mask = __BITS(0, smt_bits - 1); 669 670 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, smt_mask); 671 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 672 } 673 } 674 675 static void 676 via_cpu_probe(struct cpu_info *ci) 677 { 678 u_int model = CPUID2MODEL(ci->ci_signature); 679 u_int stepping = CPUID2STEPPING(ci->ci_signature); 680 u_int descs[4]; 681 u_int lfunc; 682 683 /* 684 * Determine the largest extended function value. 685 */ 686 x86_cpuid(0x80000000, descs); 687 lfunc = descs[0]; 688 689 /* 690 * Determine the extended feature flags. 691 */ 692 if (lfunc >= 0x80000001) { 693 x86_cpuid(0x80000001, descs); 694 ci->ci_feature3_flags |= descs[3]; 695 } 696 697 if (model < 0x9) 698 return; 699 700 /* Nehemiah or Esther */ 701 x86_cpuid(0xc0000000, descs); 702 lfunc = descs[0]; 703 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 704 return; 705 706 x86_cpuid(0xc0000001, descs); 707 lfunc = descs[3]; 708 if (model > 0x9 || stepping >= 8) { /* ACE */ 709 if (lfunc & CPUID_VIA_HAS_ACE) { 710 ci->ci_padlock_flags = lfunc; 711 } 712 } 713 } 714 715 static const char * 716 intel_family6_name(struct cpu_info *ci) 717 { 718 int model = CPUID2MODEL(ci->ci_signature); 719 const char *ret = NULL; 720 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 721 722 if (model == 5) { 723 switch (l2cache) { 724 case 0: 725 case 128 * 1024: 726 ret = "Celeron (Covington)"; 727 break; 728 case 256 * 1024: 729 ret = "Mobile Pentium II (Dixon)"; 730 break; 731 case 512 * 1024: 732 ret = "Pentium II"; 733 break; 734 case 1 * 1024 * 1024: 735 case 2 * 1024 * 1024: 736 ret = "Pentium II Xeon"; 737 break; 738 } 739 } else if (model == 6) { 740 switch (l2cache) { 741 case 256 * 1024: 742 case 512 * 1024: 743 ret = "Mobile Pentium II"; 744 break; 745 } 746 } else if (model == 7) { 747 switch (l2cache) { 748 case 512 * 1024: 749 ret = "Pentium III"; 750 break; 751 case 1 * 1024 * 1024: 752 case 2 * 1024 * 1024: 753 ret = "Pentium III Xeon"; 754 break; 755 } 756 } else if (model >= 8) { 757 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 758 switch (ci->ci_brand_id) { 759 case 0x3: 760 if (ci->ci_signature == 0x6B1) 761 ret = "Celeron"; 762 break; 763 case 0x8: 764 if (ci->ci_signature >= 0xF13) 765 ret = "genuine processor"; 766 break; 767 case 0xB: 768 if (ci->ci_signature >= 0xF13) 769 ret = "Xeon MP"; 770 break; 771 case 0xE: 772 if (ci->ci_signature < 0xF13) 773 ret = "Xeon"; 774 break; 775 } 776 if (ret == NULL) 777 ret = i386_intel_brand[ci->ci_brand_id]; 778 } 779 } 780 781 return ret; 782 } 783 784 /* 785 * Identify AMD64 CPU names from cpuid. 786 * 787 * Based on: 788 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 789 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 790 * "Revision Guide for AMD NPT Family 0Fh Processors" 791 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 792 * and other miscellaneous reports. 793 */ 794 static const char * 795 amd_amd64_name(struct cpu_info *ci) 796 { 797 int extfamily, extmodel, model; 798 const char *ret = NULL; 799 800 model = CPUID2MODEL(ci->ci_signature); 801 extfamily = CPUID2EXTFAMILY(ci->ci_signature); 802 extmodel = CPUID2EXTMODEL(ci->ci_signature); 803 804 switch (extfamily) { 805 case 0x00: 806 switch (model) { 807 case 0x1: 808 switch (extmodel) { 809 case 0x2: /* rev JH-E1/E6 */ 810 case 0x4: /* rev JH-F2 */ 811 ret = "Dual-Core Opteron"; 812 break; 813 } 814 break; 815 case 0x3: 816 switch (extmodel) { 817 case 0x2: /* rev JH-E6 (Toledo) */ 818 ret = "Dual-Core Opteron or Athlon 64 X2"; 819 break; 820 case 0x4: /* rev JH-F2 (Windsor) */ 821 ret = "Athlon 64 FX or Athlon 64 X2"; 822 break; 823 } 824 break; 825 case 0x4: 826 switch (extmodel) { 827 case 0x0: /* rev SH-B0/C0/CG (ClawHammer) */ 828 case 0x1: /* rev SH-D0 */ 829 ret = "Athlon 64"; 830 break; 831 case 0x2: /* rev SH-E5 (Lancaster?) */ 832 ret = "Mobile Athlon 64 or Turion 64"; 833 break; 834 } 835 break; 836 case 0x5: 837 switch (extmodel) { 838 case 0x0: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 839 ret = "Opteron or Athlon 64 FX"; 840 break; 841 case 0x1: /* rev SH-D0 */ 842 case 0x2: /* rev SH-E4 */ 843 ret = "Opteron"; 844 break; 845 } 846 break; 847 case 0x7: 848 switch (extmodel) { 849 case 0x0: /* rev SH-CG (ClawHammer) */ 850 case 0x1: /* rev SH-D0 */ 851 ret = "Athlon 64"; 852 break; 853 case 0x2: /* rev DH-E4, SH-E4 */ 854 ret = "Athlon 64 or Athlon 64 FX or Opteron"; 855 break; 856 } 857 break; 858 case 0x8: 859 switch (extmodel) { 860 case 0x0: /* rev CH-CG */ 861 case 0x1: /* rev CH-D0 */ 862 ret = "Athlon 64 or Sempron"; 863 break; 864 case 0x4: /* rev BH-F2 */ 865 ret = "Turion 64 X2"; 866 break; 867 } 868 break; 869 case 0xb: 870 switch (extmodel) { 871 case 0x0: /* rev CH-CG */ 872 case 0x1: /* rev CH-D0 */ 873 ret = "Athlon 64"; 874 break; 875 case 0x2: /* rev BH-E4 (Manchester) */ 876 case 0x4: /* rev BH-F2 (Windsor) */ 877 ret = "Athlon 64 X2"; 878 break; 879 case 0x6: /* rev BH-G1 (Brisbane) */ 880 ret = "Athlon X2 or Athlon 64 X2"; 881 break; 882 } 883 break; 884 case 0xc: 885 switch (extmodel) { 886 case 0x0: /* rev DH-CG (Newcastle) */ 887 case 0x1: /* rev DH-D0 (Winchester) */ 888 case 0x2: /* rev DH-E3/E6 */ 889 ret = "Athlon 64 or Sempron"; 890 break; 891 } 892 break; 893 case 0xe: 894 switch (extmodel) { 895 case 0x0: /* rev DH-CG (Newcastle?) */ 896 ret = "Athlon 64 or Sempron"; 897 break; 898 } 899 break; 900 case 0xf: 901 switch (extmodel) { 902 case 0x0: /* rev DH-CG (Newcastle/Paris) */ 903 case 0x1: /* rev DH-D0 (Winchester/Victoria) */ 904 case 0x2: /* rev DH-E3/E6 (Venice/Palermo) */ 905 case 0x4: /* rev DH-F2 (Orleans/Manila) */ 906 case 0x5: /* rev DH-F2 (Orleans/Manila) */ 907 case 0x6: /* rev DH-G1 */ 908 ret = "Athlon 64 or Sempron"; 909 break; 910 } 911 break; 912 default: 913 ret = "Unknown AMD64 CPU"; 914 } 915 break; 916 case 0x01: 917 switch (model) { 918 case 0x02: 919 ret = "Family 10h"; 920 break; 921 default: 922 ret = "Unknown AMD64 CPU"; 923 break; 924 } 925 break; 926 } 927 928 return ret; 929 } 930 931 static void 932 cpu_probe_base_features(struct cpu_info *ci) 933 { 934 const struct x86_cache_info *cai; 935 u_int descs[4]; 936 int iterations, i, j; 937 uint8_t desc; 938 uint32_t miscbytes; 939 uint32_t brand[12]; 940 941 if (ci->ci_cpuid_level < 0) 942 return; 943 944 x86_cpuid(0, descs); 945 ci->ci_cpuid_level = descs[0]; 946 ci->ci_vendor[0] = descs[1]; 947 ci->ci_vendor[2] = descs[2]; 948 ci->ci_vendor[1] = descs[3]; 949 ci->ci_vendor[3] = 0; 950 951 x86_cpuid(0x80000000, brand); 952 if (brand[0] >= 0x80000004) { 953 x86_cpuid(0x80000002, brand); 954 x86_cpuid(0x80000003, brand + 4); 955 x86_cpuid(0x80000004, brand + 8); 956 for (i = 0; i < 48; i++) 957 if (((char *) brand)[i] != ' ') 958 break; 959 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 960 } 961 962 if (ci->ci_cpuid_level < 1) 963 return; 964 965 x86_cpuid(1, descs); 966 ci->ci_signature = descs[0]; 967 miscbytes = descs[1]; 968 ci->ci_feature2_flags = descs[2]; 969 ci->ci_feature_flags = descs[3]; 970 971 /* Brand is low order 8 bits of ebx */ 972 ci->ci_brand_id = miscbytes & 0xff; 973 ci->ci_initapicid = (miscbytes >> 24) & 0xff; 974 if (ci->ci_cpuid_level < 2) 975 return; 976 977 /* 978 * Parse the cache info from `cpuid', if we have it. 979 * XXX This is kinda ugly, but hey, so is the architecture... 980 */ 981 982 x86_cpuid(2, descs); 983 984 iterations = descs[0] & 0xff; 985 while (iterations-- > 0) { 986 for (i = 0; i < 4; i++) { 987 if (descs[i] & 0x80000000) 988 continue; 989 for (j = 0; j < 4; j++) { 990 if (i == 0 && j == 0) 991 continue; 992 desc = (descs[i] >> (j * 8)) & 0xff; 993 if (desc == 0) 994 continue; 995 cai = cache_info_lookup(intel_cpuid_cache_info, 996 desc); 997 if (cai != NULL) 998 ci->ci_cinfo[cai->cai_index] = *cai; 999 } 1000 } 1001 x86_cpuid(2, descs); 1002 } 1003 1004 if (ci->ci_cpuid_level < 3) 1005 return; 1006 1007 /* 1008 * If the processor serial number misfeature is present and supported, 1009 * extract it here. 1010 */ 1011 if ((ci->ci_feature_flags & CPUID_PN) != 0) { 1012 ci->ci_cpu_serial[0] = ci->ci_signature; 1013 x86_cpuid(3, descs); 1014 ci->ci_cpu_serial[2] = descs[2]; 1015 ci->ci_cpu_serial[1] = descs[3]; 1016 } 1017 } 1018 1019 static void 1020 cpu_probe_features(struct cpu_info *ci) 1021 { 1022 const struct cpu_cpuid_nameclass *cpup = NULL; 1023 int i, xmax, family; 1024 1025 cpu_probe_base_features(ci); 1026 1027 if (ci->ci_cpuid_level < 1) 1028 return; 1029 1030 xmax = __arraycount(i386_cpuid_cpus); 1031 for (i = 0; i < xmax; i++) { 1032 if (!strncmp((char *)ci->ci_vendor, 1033 i386_cpuid_cpus[i].cpu_id, 12)) { 1034 cpup = &i386_cpuid_cpus[i]; 1035 break; 1036 } 1037 } 1038 1039 if (cpup == NULL) 1040 return; 1041 1042 family = (ci->ci_signature >> 8) & 0xf; 1043 1044 if (family > CPU_MAXFAMILY) { 1045 family = CPU_MAXFAMILY; 1046 } 1047 i = family - CPU_MINFAMILY; 1048 1049 if (cpup->cpu_family[i].cpu_probe == NULL) 1050 return; 1051 1052 (*cpup->cpu_family[i].cpu_probe)(ci); 1053 } 1054 1055 static void 1056 intel_family_new_probe(struct cpu_info *ci) 1057 { 1058 uint32_t descs[4]; 1059 1060 x86_cpuid(0x80000000, descs); 1061 1062 /* 1063 * Determine extended feature flags. 1064 */ 1065 if (descs[0] >= 0x80000001) { 1066 x86_cpuid(0x80000001, descs); 1067 ci->ci_feature3_flags |= descs[3]; 1068 } 1069 } 1070 1071 static void 1072 amd_family6_probe(struct cpu_info *ci) 1073 { 1074 uint32_t descs[4]; 1075 char *p; 1076 int i; 1077 1078 x86_cpuid(0x80000000, descs); 1079 1080 /* 1081 * Determine the extended feature flags. 1082 */ 1083 if (descs[0] >= 0x80000001) { 1084 x86_cpuid(0x80000001, descs); 1085 ci->ci_feature3_flags |= descs[3]; /* %edx */ 1086 ci->ci_feature4_flags = descs[2]; /* %ecx */ 1087 } 1088 1089 if (*cpu_brand_string == '\0') 1090 return; 1091 1092 for (i = 1; i < __arraycount(amd_brand); i++) 1093 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 1094 ci->ci_brand_id = i; 1095 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 1096 break; 1097 } 1098 } 1099 1100 static void 1101 amd_family5_setup(struct cpu_info *ci) 1102 { 1103 1104 switch (CPUID2MODEL(ci->ci_signature)) { 1105 case 0: /* AMD-K5 Model 0 */ 1106 /* 1107 * According to the AMD Processor Recognition App Note, 1108 * the AMD-K5 Model 0 uses the wrong bit to indicate 1109 * support for global PTEs, instead using bit 9 (APIC) 1110 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 1111 */ 1112 if (ci->ci_feature_flags & CPUID_APIC) 1113 ci->ci_feature_flags = (ci->ci_feature_flags & ~CPUID_APIC) | CPUID_PGE; 1114 /* 1115 * XXX But pmap_pg_g is already initialized -- need to kick 1116 * XXX the pmap somehow. How does the MP branch do this? 1117 */ 1118 break; 1119 } 1120 } 1121 1122 static void 1123 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1124 { 1125 u_int descs[4]; 1126 1127 x86_cpuid(0x80860007, descs); 1128 *frequency = descs[0]; 1129 *voltage = descs[1]; 1130 *percentage = descs[2]; 1131 } 1132 1133 static void 1134 transmeta_cpu_info(struct cpu_info *ci) 1135 { 1136 u_int descs[4], nreg; 1137 u_int frequency, voltage, percentage; 1138 1139 x86_cpuid(0x80860000, descs); 1140 nreg = descs[0]; 1141 if (nreg >= 0x80860001) { 1142 x86_cpuid(0x80860001, descs); 1143 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1144 (descs[1] >> 24) & 0xff, 1145 (descs[1] >> 16) & 0xff, 1146 (descs[1] >> 8) & 0xff, 1147 descs[1] & 0xff); 1148 } 1149 if (nreg >= 0x80860002) { 1150 x86_cpuid(0x80860002, descs); 1151 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1152 (descs[1] >> 24) & 0xff, 1153 (descs[1] >> 16) & 0xff, 1154 (descs[1] >> 8) & 0xff, 1155 descs[1] & 0xff, 1156 descs[2]); 1157 } 1158 if (nreg >= 0x80860006) { 1159 union { 1160 char text[65]; 1161 u_int descs[4][4]; 1162 } info; 1163 int i; 1164 1165 for (i=0; i<4; i++) { 1166 x86_cpuid(0x80860003 + i, info.descs[i]); 1167 } 1168 info.text[64] = '\0'; 1169 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1170 } 1171 1172 if (nreg >= 0x80860007) { 1173 tmx86_get_longrun_status(&frequency, 1174 &voltage, &percentage); 1175 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1176 frequency, voltage, percentage); 1177 } 1178 } 1179 1180 void 1181 identifycpu(const char *cpuname) 1182 { 1183 const char *name, *modifier, *vendorname, *brand = ""; 1184 int class = CPUCLASS_386, i, xmax; 1185 int modif, family, model; 1186 const struct cpu_cpuid_nameclass *cpup = NULL; 1187 const struct cpu_cpuid_family *cpufam; 1188 char *buf; 1189 const char *feature_str[5]; 1190 struct cpu_info *ci, cistore; 1191 extern int cpu; 1192 extern int cpu_info_level; 1193 size_t sz; 1194 1195 ci = &cistore; 1196 memset(ci, 0, sizeof(*ci)); 1197 ci->ci_dev = cpuname; 1198 1199 x86_identify(); 1200 ci->ci_cpuid_level = cpu_info_level; 1201 cpu_probe_features(ci); 1202 1203 buf = malloc(MAXPATHLEN); 1204 if (ci->ci_cpuid_level == -1) { 1205 if (cpu < 0 || cpu >= __arraycount(i386_nocpuid_cpus)) 1206 errx(1, "unknown cpu type %d", cpu); 1207 name = i386_nocpuid_cpus[cpu].cpu_name; 1208 cpu_vendor = i386_nocpuid_cpus[cpu].cpu_vendor; 1209 vendorname = i386_nocpuid_cpus[cpu].cpu_vendorname; 1210 class = i386_nocpuid_cpus[cpu].cpu_class; 1211 ci->ci_info = i386_nocpuid_cpus[cpu].cpu_info; 1212 modifier = ""; 1213 } else { 1214 xmax = __arraycount(i386_cpuid_cpus); 1215 modif = (ci->ci_signature >> 12) & 0x3; 1216 family = CPUID2FAMILY(ci->ci_signature); 1217 if (family < CPU_MINFAMILY) 1218 errx(1, "identifycpu: strange family value"); 1219 model = CPUID2MODEL(ci->ci_signature); 1220 1221 for (i = 0; i < xmax; i++) { 1222 if (!strncmp((char *)ci->ci_vendor, 1223 i386_cpuid_cpus[i].cpu_id, 12)) { 1224 cpup = &i386_cpuid_cpus[i]; 1225 break; 1226 } 1227 } 1228 1229 if (cpup == NULL) { 1230 cpu_vendor = CPUVENDOR_UNKNOWN; 1231 if (ci->ci_vendor[0] != '\0') 1232 vendorname = (char *)&ci->ci_vendor[0]; 1233 else 1234 vendorname = "Unknown"; 1235 if (family >= CPU_MAXFAMILY) 1236 family = CPU_MINFAMILY; 1237 class = family - 3; 1238 modifier = ""; 1239 name = ""; 1240 ci->ci_info = NULL; 1241 } else { 1242 cpu_vendor = cpup->cpu_vendor; 1243 vendorname = cpup->cpu_vendorname; 1244 modifier = modifiers[modif]; 1245 if (family > CPU_MAXFAMILY) { 1246 family = CPU_MAXFAMILY; 1247 model = CPU_DEFMODEL; 1248 } else if (model > CPU_MAXMODEL) 1249 model = CPU_DEFMODEL; 1250 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 1251 name = cpufam->cpu_models[model]; 1252 if (name == NULL) 1253 name = cpufam->cpu_models[CPU_DEFMODEL]; 1254 class = cpufam->cpu_class; 1255 ci->ci_info = cpufam->cpu_info; 1256 1257 if (cpu_vendor == CPUVENDOR_INTEL) { 1258 if (family == 6 && model >= 5) { 1259 const char *tmp; 1260 tmp = intel_family6_name(ci); 1261 if (tmp != NULL) 1262 name = tmp; 1263 } 1264 if (family == CPU_MAXFAMILY && 1265 ci->ci_brand_id < 1266 __arraycount(i386_intel_brand) && 1267 i386_intel_brand[ci->ci_brand_id]) 1268 name = 1269 i386_intel_brand[ci->ci_brand_id]; 1270 } 1271 1272 if (cpu_vendor == CPUVENDOR_AMD) { 1273 if (family == 6 && model >= 6) { 1274 if (ci->ci_brand_id == 1) 1275 /* 1276 * It's Duron. We override the 1277 * name, since it might have 1278 * been misidentified as Athlon. 1279 */ 1280 name = 1281 amd_brand[ci->ci_brand_id]; 1282 else 1283 brand = amd_brand_name; 1284 } 1285 if (CPUID2FAMILY(ci->ci_signature) == 0xf) { 1286 /* 1287 * Identify AMD64 CPU names. 1288 * Note family value is clipped by 1289 * CPU_MAXFAMILY. 1290 */ 1291 const char *tmp; 1292 tmp = amd_amd64_name(ci); 1293 if (tmp != NULL) 1294 name = tmp; 1295 } 1296 } 1297 1298 if (cpu_vendor == CPUVENDOR_IDT && family >= 6) 1299 vendorname = "VIA"; 1300 } 1301 } 1302 1303 ci->ci_cpu_class = class; 1304 1305 sz = sizeof(ci->ci_tsc_freq); 1306 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 1307 1308 snprintf(cpu_model, sizeof(cpu_model), "%s%s%s%s%s%s%s (%s-class)", 1309 vendorname, 1310 *modifier ? " " : "", modifier, 1311 *name ? " " : "", name, 1312 *brand ? " " : "", brand, 1313 classnames[class]); 1314 aprint_normal("%s: %s", cpuname, cpu_model); 1315 1316 if (ci->ci_tsc_freq != 0) 1317 aprint_normal(", %qd.%02qd MHz", 1318 (ci->ci_tsc_freq + 4999) / 1000000, 1319 ((ci->ci_tsc_freq + 4999) / 10000) % 100); 1320 if (ci->ci_signature != 0) 1321 aprint_normal(", id 0x%x", ci->ci_signature); 1322 aprint_normal("\n"); 1323 1324 if (ci->ci_info) 1325 (*ci->ci_info)(ci); 1326 1327 feature_str[0] = CPUID_FLAGS1; 1328 feature_str[1] = CPUID_FLAGS2; 1329 feature_str[2] = CPUID_FLAGS3; 1330 1331 switch (cpu_vendor) { 1332 case CPUVENDOR_AMD: 1333 feature_str[3] = CPUID_EXT_FLAGS; 1334 feature_str[4] = CPUID_AMD_FLAGS4; 1335 break; 1336 case CPUVENDOR_INTEL: 1337 feature_str[3] = CPUID_INTEL_FLAGS4; 1338 break; 1339 default: 1340 feature_str[3] = CPUID_EXT_FLAGS; 1341 break; 1342 } 1343 1344 if (ci->ci_feature_flags) { 1345 if ((ci->ci_feature_flags & CPUID_MASK1) != 0) { 1346 bitmask_snprintf(ci->ci_feature_flags, 1347 feature_str[0], buf, MAXPATHLEN); 1348 aprint_verbose("%s: features %s\n", cpuname, buf); 1349 } 1350 if ((ci->ci_feature_flags & CPUID_MASK2) != 0) { 1351 bitmask_snprintf(ci->ci_feature_flags, 1352 feature_str[1], buf, MAXPATHLEN); 1353 aprint_verbose("%s: features %s\n", cpuname, buf); 1354 } 1355 if ((ci->ci_feature_flags & CPUID_MASK3) != 0) { 1356 bitmask_snprintf(ci->ci_feature_flags, 1357 feature_str[2], buf, MAXPATHLEN); 1358 aprint_verbose("%s: features %s\n", cpuname, buf); 1359 } 1360 } 1361 1362 if (ci->ci_feature2_flags) { 1363 bitmask_snprintf(ci->ci_feature2_flags, 1364 CPUID2_FLAGS, buf, MAXPATHLEN); 1365 aprint_verbose("%s: features2 %s\n", cpuname, buf); 1366 } 1367 1368 if (ci->ci_feature3_flags) { 1369 bitmask_snprintf(ci->ci_feature3_flags, 1370 feature_str[3], buf, MAXPATHLEN); 1371 aprint_verbose("%s: features3 %s\n", cpuname, buf); 1372 } 1373 1374 if (ci->ci_feature4_flags) { 1375 bitmask_snprintf(ci->ci_feature4_flags, 1376 feature_str[4], buf, MAXPATHLEN); 1377 aprint_verbose("%s: features4 %s\n", cpuname, buf); 1378 } 1379 1380 if (ci->ci_padlock_flags) { 1381 bitmask_snprintf(ci->ci_padlock_flags, 1382 CPUID_FLAGS_PADLOCK, buf, MAXPATHLEN); 1383 aprint_verbose("%s: padlock features %s\n", cpuname, buf); 1384 } 1385 1386 free(buf); 1387 1388 if (*cpu_brand_string != '\0') 1389 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 1390 1391 x86_print_cacheinfo(ci); 1392 1393 if (ci->ci_cpuid_level >= 3 && (ci->ci_feature_flags & CPUID_PN)) { 1394 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 1395 cpuname, 1396 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 1397 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 1398 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 1399 } 1400 1401 if (ci->ci_cpu_class == CPUCLASS_386) { 1402 errx(1, "NetBSD requires an 80486 or later processor"); 1403 } 1404 1405 if (cpu == CPU_486DLC) { 1406 #ifndef CYRIX_CACHE_WORKS 1407 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 1408 #else 1409 #ifndef CYRIX_CACHE_REALLY_WORKS 1410 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 1411 #else 1412 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 1413 #endif 1414 #endif 1415 } 1416 1417 /* 1418 * Everything past this point requires a Pentium or later. 1419 */ 1420 if (ci->ci_cpuid_level < 0) 1421 return; 1422 1423 identifycpu_cpuids(ci); 1424 1425 #ifdef INTEL_CORETEMP 1426 if (cpu_vendor == CPUVENDOR_INTEL && ci->ci_cpuid_level >= 0x06) 1427 coretemp_register(ci); 1428 #endif 1429 1430 if (cpu_vendor == CPUVENDOR_AMD) { 1431 powernow_probe(ci); 1432 } 1433 1434 #ifdef INTEL_ONDEMAND_CLOCKMOD 1435 clockmod_init(); 1436 #endif 1437 1438 aprint_normal_dev(ci->ci_dev, "family %02x model %02x " 1439 "extfamily %02x extmodel %02x\n", CPUID2FAMILY(ci->ci_signature), 1440 CPUID2MODEL(ci->ci_signature), CPUID2EXTFAMILY(ci->ci_signature), 1441 CPUID2EXTMODEL(ci->ci_signature)); 1442 } 1443 1444 static const char * 1445 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 1446 const char *sep) 1447 { 1448 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1449 char human_num[HUMAN_BUFSIZE]; 1450 1451 if (cai->cai_totalsize == 0) 1452 return sep; 1453 1454 if (sep == NULL) 1455 aprint_verbose_dev(ci->ci_dev, ""); 1456 else 1457 aprint_verbose("%s", sep); 1458 if (name != NULL) 1459 aprint_verbose("%s ", name); 1460 1461 if (cai->cai_string != NULL) { 1462 aprint_verbose("%s ", cai->cai_string); 1463 } else { 1464 (void)humanize_number(human_num, sizeof(human_num), 1465 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 1466 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 1467 } 1468 switch (cai->cai_associativity) { 1469 case 0: 1470 aprint_verbose("disabled"); 1471 break; 1472 case 1: 1473 aprint_verbose("direct-mapped"); 1474 break; 1475 case 0xff: 1476 aprint_verbose("fully associative"); 1477 break; 1478 default: 1479 aprint_verbose("%d-way", cai->cai_associativity); 1480 break; 1481 } 1482 return ", "; 1483 } 1484 1485 static const char * 1486 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 1487 const char *sep) 1488 { 1489 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1490 char human_num[HUMAN_BUFSIZE]; 1491 1492 if (cai->cai_totalsize == 0) 1493 return sep; 1494 1495 if (sep == NULL) 1496 aprint_verbose_dev(ci->ci_dev, ""); 1497 else 1498 aprint_verbose("%s", sep); 1499 if (name != NULL) 1500 aprint_verbose("%s ", name); 1501 1502 if (cai->cai_string != NULL) { 1503 aprint_verbose("%s", cai->cai_string); 1504 } else { 1505 (void)humanize_number(human_num, sizeof(human_num), 1506 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 1507 aprint_verbose("%d %s entries ", cai->cai_totalsize, 1508 human_num); 1509 switch (cai->cai_associativity) { 1510 case 0: 1511 aprint_verbose("disabled"); 1512 break; 1513 case 1: 1514 aprint_verbose("direct-mapped"); 1515 break; 1516 case 0xff: 1517 aprint_verbose("fully associative"); 1518 break; 1519 default: 1520 aprint_verbose("%d-way", cai->cai_associativity); 1521 break; 1522 } 1523 } 1524 return ", "; 1525 } 1526 1527 static const struct x86_cache_info * 1528 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 1529 { 1530 int i; 1531 1532 for (i = 0; cai[i].cai_desc != 0; i++) { 1533 if (cai[i].cai_desc == desc) 1534 return (&cai[i]); 1535 } 1536 1537 return (NULL); 1538 } 1539 1540 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 1541 AMD_L2CACHE_INFO; 1542 1543 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 1544 AMD_L3CACHE_INFO; 1545 1546 static void 1547 amd_cpu_cacheinfo(struct cpu_info *ci) 1548 { 1549 const struct x86_cache_info *cp; 1550 struct x86_cache_info *cai; 1551 int family, model; 1552 u_int descs[4]; 1553 u_int lfunc; 1554 1555 family = (ci->ci_signature >> 8) & 15; 1556 model = CPUID2MODEL(ci->ci_signature); 1557 1558 /* 1559 * K5 model 0 has none of this info. 1560 */ 1561 if (family == 5 && model == 0) 1562 return; 1563 1564 /* 1565 * Get extended values for K8 and up. 1566 */ 1567 if (family == 0xf) { 1568 family += CPUID2EXTFAMILY(ci->ci_signature); 1569 model += CPUID2EXTMODEL(ci->ci_signature); 1570 } 1571 1572 /* 1573 * Determine the largest extended function value. 1574 */ 1575 x86_cpuid(0x80000000, descs); 1576 lfunc = descs[0]; 1577 1578 /* 1579 * Determine L1 cache/TLB info. 1580 */ 1581 if (lfunc < 0x80000005) { 1582 /* No L1 cache info available. */ 1583 return; 1584 } 1585 1586 x86_cpuid(0x80000005, descs); 1587 1588 /* 1589 * K6-III and higher have large page TLBs. 1590 */ 1591 if ((family == 5 && model >= 9) || family >= 6) { 1592 cai = &ci->ci_cinfo[CAI_ITLB2]; 1593 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1594 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1595 cai->cai_linesize = (4 * 1024 * 1024); 1596 1597 cai = &ci->ci_cinfo[CAI_DTLB2]; 1598 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1599 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1600 cai->cai_linesize = (4 * 1024 * 1024); 1601 } 1602 1603 cai = &ci->ci_cinfo[CAI_ITLB]; 1604 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1605 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1606 cai->cai_linesize = (4 * 1024); 1607 1608 cai = &ci->ci_cinfo[CAI_DTLB]; 1609 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1610 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1611 cai->cai_linesize = (4 * 1024); 1612 1613 cai = &ci->ci_cinfo[CAI_DCACHE]; 1614 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1615 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1616 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[2]); 1617 1618 cai = &ci->ci_cinfo[CAI_ICACHE]; 1619 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1620 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1621 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1622 1623 /* 1624 * Determine L2 cache/TLB info. 1625 */ 1626 if (lfunc < 0x80000006) { 1627 /* No L2 cache info available. */ 1628 return; 1629 } 1630 1631 x86_cpuid(0x80000006, descs); 1632 1633 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1634 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1635 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1636 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1637 1638 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1639 cai->cai_associativity); 1640 if (cp != NULL) 1641 cai->cai_associativity = cp->cai_associativity; 1642 else 1643 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1644 1645 /* 1646 * Determine L3 cache info on AMD Family 10h processors 1647 */ 1648 if (family == 0x10) { 1649 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1650 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1651 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1652 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1653 1654 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1655 cai->cai_associativity); 1656 if (cp != NULL) 1657 cai->cai_associativity = cp->cai_associativity; 1658 else 1659 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1660 } 1661 } 1662 1663 static void 1664 via_cpu_cacheinfo(struct cpu_info *ci) 1665 { 1666 struct x86_cache_info *cai; 1667 int family, model, stepping; 1668 u_int descs[4]; 1669 u_int lfunc; 1670 1671 family = (ci->ci_signature >> 8) & 15; 1672 model = CPUID2MODEL(ci->ci_signature); 1673 stepping = CPUID2STEPPING(ci->ci_signature); 1674 1675 /* 1676 * Determine the largest extended function value. 1677 */ 1678 x86_cpuid(0x80000000, descs); 1679 lfunc = descs[0]; 1680 1681 /* 1682 * Determine L1 cache/TLB info. 1683 */ 1684 if (lfunc < 0x80000005) { 1685 /* No L1 cache info available. */ 1686 return; 1687 } 1688 1689 x86_cpuid(0x80000005, descs); 1690 1691 cai = &ci->ci_cinfo[CAI_ITLB]; 1692 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1693 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1694 cai->cai_linesize = (4 * 1024); 1695 1696 cai = &ci->ci_cinfo[CAI_DTLB]; 1697 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1698 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1699 cai->cai_linesize = (4 * 1024); 1700 1701 cai = &ci->ci_cinfo[CAI_DCACHE]; 1702 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1703 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1704 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1705 if (model == 9 && stepping == 8) { 1706 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1707 cai->cai_associativity = 2; 1708 } 1709 1710 cai = &ci->ci_cinfo[CAI_ICACHE]; 1711 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1712 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1713 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1714 if (model == 9 && stepping == 8) { 1715 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1716 cai->cai_associativity = 2; 1717 } 1718 1719 /* 1720 * Determine L2 cache/TLB info. 1721 */ 1722 if (lfunc < 0x80000006) { 1723 /* No L2 cache info available. */ 1724 return; 1725 } 1726 1727 x86_cpuid(0x80000006, descs); 1728 1729 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1730 if (model >= 9) { 1731 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1732 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1733 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1734 } else { 1735 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1736 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1737 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1738 } 1739 } 1740 1741 static void 1742 x86_print_cacheinfo(struct cpu_info *ci) 1743 { 1744 const char *sep; 1745 1746 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 1747 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 1748 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 1749 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 1750 if (sep != NULL) 1751 aprint_verbose("\n"); 1752 } 1753 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 1754 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 1755 if (sep != NULL) 1756 aprint_verbose("\n"); 1757 } 1758 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 1759 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 1760 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 1761 if (sep != NULL) 1762 aprint_verbose("\n"); 1763 } 1764 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 1765 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 1766 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 1767 if (sep != NULL) 1768 aprint_verbose("\n"); 1769 } 1770 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 1771 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 1772 if (sep != NULL) 1773 aprint_verbose("\n"); 1774 } 1775 } 1776 1777 static void 1778 powernow_probe(struct cpu_info *ci) 1779 { 1780 uint32_t regs[4]; 1781 char line[256]; 1782 1783 x86_cpuid(0x80000000, regs); 1784 1785 /* We need CPUID(0x80000007) */ 1786 if (regs[0] < 0x80000007) 1787 return; 1788 x86_cpuid(0x80000007, regs); 1789 1790 1791 1792 bitmask_snprintf(regs[3], "\20\11TscInv\10HwPState\7Clk100MHz" 1793 "\6STC\5TM\4TTP\3VID\2FID\1TS", line, sizeof(line)); 1794 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 1795 line); 1796 } 1797
Indexes created Fri Sep 26 20:09:58 GMT 2025