i386.c revision 1.122
1 /* $NetBSD: i386.c,v 1.122 2021/10/07 13:04:18 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.122 2021/10/07 13:04:18 msaitoh Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cpu_ucode.h> 85 86 #include "../cpuctl.h" 87 #include "cpuctl_i386.h" 88 89 /* Size of buffer for printing humanized numbers */ 90 #define HUMAN_BUFSIZE sizeof("999KB") 91 92 struct cpu_nocpuid_nameclass { 93 int cpu_vendor; 94 const char *cpu_vendorname; 95 const char *cpu_name; 96 int cpu_class; 97 void (*cpu_setup)(struct cpu_info *); 98 void (*cpu_cacheinfo)(struct cpu_info *); 99 void (*cpu_info)(struct cpu_info *); 100 }; 101 102 struct cpu_cpuid_nameclass { 103 const char *cpu_id; 104 int cpu_vendor; 105 const char *cpu_vendorname; 106 struct cpu_cpuid_family { 107 int cpu_class; 108 const char *cpu_models[256]; 109 const char *cpu_model_default; 110 void (*cpu_setup)(struct cpu_info *); 111 void (*cpu_probe)(struct cpu_info *); 112 void (*cpu_info)(struct cpu_info *); 113 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 114 }; 115 116 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 117 118 /* 119 * Map Brand ID from cpuid instruction to brand name. 120 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 121 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 122 * Architectures Software Developer's Manual, Volume 2A". 123 */ 124 static const char * const i386_intel_brand[] = { 125 "", /* Unsupported */ 126 "Celeron", /* Intel (R) Celeron (TM) processor */ 127 "Pentium III", /* Intel (R) Pentium (R) III processor */ 128 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 129 "Pentium III", /* Intel (R) Pentium (R) III processor */ 130 "", /* 0x05: Reserved */ 131 "Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */ 132 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 133 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 134 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 135 "Celeron", /* Intel (R) Celeron (TM) processor */ 136 "Xeon", /* Intel (R) Xeon (TM) processor */ 137 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 138 "", /* 0x0d: Reserved */ 139 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 140 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 141 "", /* 0x10: Reserved */ 142 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 143 "Celeron M", /* Intel (R) Celeron (R) M processor */ 144 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 145 "Celeron", /* Intel (R) Celeron (R) processor */ 146 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 147 "Pentium M", /* Intel (R) Pentium (R) M processor */ 148 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 149 }; 150 151 /* 152 * AMD processors don't have Brand IDs, so we need these names for probe. 153 */ 154 static const char * const amd_brand[] = { 155 "", 156 "Duron", /* AMD Duron(tm) */ 157 "MP", /* AMD Athlon(tm) MP */ 158 "XP", /* AMD Athlon(tm) XP */ 159 "4" /* AMD Athlon(tm) 4 */ 160 }; 161 162 int cpu_vendor; 163 static char cpu_brand_string[49]; 164 static char amd_brand_name[48]; 165 static int use_pae, largepagesize; 166 167 /* Setup functions */ 168 static void disable_tsc(struct cpu_info *); 169 static void amd_family5_setup(struct cpu_info *); 170 static void cyrix6x86_cpu_setup(struct cpu_info *); 171 static void winchip_cpu_setup(struct cpu_info *); 172 /* Brand/Model name functions */ 173 static const char *intel_family6_name(struct cpu_info *); 174 static const char *amd_amd64_name(struct cpu_info *); 175 /* Probe functions */ 176 static void amd_family6_probe(struct cpu_info *); 177 static void powernow_probe(struct cpu_info *); 178 static void intel_family_new_probe(struct cpu_info *); 179 static void via_cpu_probe(struct cpu_info *); 180 /* (Cache) Info functions */ 181 static void intel_cpu_cacheinfo(struct cpu_info *); 182 static void amd_cpu_cacheinfo(struct cpu_info *); 183 static void via_cpu_cacheinfo(struct cpu_info *); 184 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 185 static void transmeta_cpu_info(struct cpu_info *); 186 /* Common functions */ 187 static void cpu_probe_base_features(struct cpu_info *, const char *); 188 static void cpu_probe_hv_features(struct cpu_info *, const char *); 189 static void cpu_probe_features(struct cpu_info *); 190 static void print_bits(const char *, const char *, const char *, uint32_t); 191 static void identifycpu_cpuids(struct cpu_info *); 192 static const char *print_cache_config(struct cpu_info *, int, const char *, 193 const char *); 194 static const char *print_tlb_config(struct cpu_info *, int, const char *, 195 const char *); 196 static void x86_print_cache_and_tlb_info(struct cpu_info *); 197 198 /* 199 * Note: these are just the ones that may not have a cpuid instruction. 200 * We deal with the rest in a different way. 201 */ 202 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 203 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 204 NULL, NULL, NULL }, /* CPU_386SX */ 205 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 206 NULL, NULL, NULL }, /* CPU_386 */ 207 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 208 NULL, NULL, NULL }, /* CPU_486SX */ 209 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 210 NULL, NULL, NULL }, /* CPU_486 */ 211 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 212 NULL, NULL, NULL }, /* CPU_486DLC */ 213 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 214 NULL, NULL, NULL }, /* CPU_6x86 */ 215 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 216 NULL, NULL, NULL }, /* CPU_NX586 */ 217 }; 218 219 const char *classnames[] = { 220 "386", 221 "486", 222 "586", 223 "686" 224 }; 225 226 const char *modifiers[] = { 227 "", 228 "OverDrive", 229 "Dual", 230 "" 231 }; 232 233 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 234 { 235 /* 236 * For Intel processors, check Chapter 35Model-specific 237 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 238 * Software Developer's Manual, Volume 3C". 239 */ 240 "GenuineIntel", 241 CPUVENDOR_INTEL, 242 "Intel", 243 /* Family 4 */ 244 { { 245 CPUCLASS_486, 246 { 247 "486DX", "486DX", "486SX", "486DX2", "486SL", 248 "486SX2", 0, "486DX2 W/B Enhanced", 249 "486DX4", 0, 0, 0, 0, 0, 0, 0, 250 }, 251 "486", /* Default */ 252 NULL, 253 NULL, 254 intel_cpu_cacheinfo, 255 }, 256 /* Family 5 */ 257 { 258 CPUCLASS_586, 259 { 260 "Pentium (P5 A-step)", "Pentium (P5)", 261 "Pentium (P54C)", "Pentium (P24T)", 262 "Pentium/MMX", "Pentium", 0, 263 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 264 "Quark X1000", 0, 0, 0, 0, 0, 0, 265 }, 266 "Pentium", /* Default */ 267 NULL, 268 NULL, 269 intel_cpu_cacheinfo, 270 }, 271 /* Family 6 */ 272 { 273 CPUCLASS_686, 274 { 275 [0x00] = "Pentium Pro (A-step)", 276 [0x01] = "Pentium Pro", 277 [0x03] = "Pentium II (Klamath)", 278 [0x04] = "Pentium Pro", 279 [0x05] = "Pentium II/Celeron (Deschutes)", 280 [0x06] = "Celeron (Mendocino)", 281 [0x07] = "Pentium III (Katmai)", 282 [0x08] = "Pentium III (Coppermine)", 283 [0x09] = "Pentium M (Banias)", 284 [0x0a] = "Pentium III Xeon (Cascades)", 285 [0x0b] = "Pentium III (Tualatin)", 286 [0x0d] = "Pentium M (Dothan)", 287 [0x0e] = "Pentium Core Duo, Core solo", 288 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 289 "Core 2 Quad 6xxx, " 290 "Core 2 Extreme 6xxx, " 291 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 292 "and Pentium DC", 293 [0x15] = "EP80579 Integrated Processor", 294 [0x16] = "Celeron (45nm)", 295 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 296 "Core 2 Quad 8xxx and 9xxx", 297 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 298 "(Nehalem)", 299 [0x1c] = "45nm Atom Family", 300 [0x1d] = "XeonMP 74xx (Nehalem)", 301 [0x1e] = "Core i7 and i5", 302 [0x1f] = "Core i7 and i5", 303 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 304 [0x26] = "Atom Family", 305 [0x27] = "Atom Family", 306 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 307 "i3 2xxx", 308 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 309 [0x2d] = "Xeon E5 Sandy Bridge family, " 310 "Core i7-39xx Extreme", 311 [0x2e] = "Xeon 75xx & 65xx", 312 [0x2f] = "Xeon E7 family", 313 [0x35] = "Atom Family", 314 [0x36] = "Atom S1000", 315 [0x37] = "Atom E3000, Z3[67]00", 316 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 317 "Ivy Bridge", 318 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 319 "(Haswell)", 320 [0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)", 321 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 322 "Core i7-49xx Extreme", 323 [0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), " 324 "Core i7-59xx Extreme", 325 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 326 "(Haswell)", 327 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 328 "(Haswell)", 329 [0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)", 330 [0x4a] = "Atom Z3400", 331 [0x4c] = "Atom X[57]-Z8000 (Airmont)", 332 [0x4d] = "Atom C2000", 333 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 334 [0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme", 335 [0x55] = "Xeon Scalable (Skylake, Cascade Lake, Copper Lake)", 336 [0x56] = "Xeon D-1500 (Broadwell)", 337 [0x57] = "Xeon Phi [357]200 (Knights Landing)", 338 [0x5a] = "Atom E3500", 339 [0x5c] = "Atom (Goldmont)", 340 [0x5d] = "Atom X3-C3000 (Silvermont)", 341 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 342 [0x5f] = "Atom (Goldmont, Denverton)", 343 [0x66] = "8th gen Core i3 (Cannon Lake)", 344 [0x6a] = "3rd gen Xeon Scalable (Ice Lake)", 345 [0x6c] = "3rd gen Xeon Scalable (Ice Lake)", 346 [0x7a] = "Atom (Goldmont Plus)", 347 [0x7d] = "10th gen Core (Ice Lake)", 348 [0x7e] = "10th gen Core (Ice Lake)", 349 [0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)", 350 [0x86] = "Atom (Tremont)", 351 [0x8c] = "11th gen Core (Tiger Lake)", 352 [0x8d] = "11th gen Core (Tiger Lake)", 353 [0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 354 [0x96] = "Atom x6000E (Elkhart Lake)", 355 [0x9c] = "Pentium Silver N6xxx, Celeron N45xx, Celeron N51xx (Jasper Lake)", 356 [0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 357 [0xa5] = "10th gen Core (Comet Lake)", 358 [0xa6] = "10th gen Core (Comet Lake)", 359 }, 360 "Pentium Pro, II or III", /* Default */ 361 NULL, 362 intel_family_new_probe, 363 intel_cpu_cacheinfo, 364 }, 365 /* Family > 6 */ 366 { 367 CPUCLASS_686, 368 { 369 0, 0, 0, 0, 0, 0, 0, 0, 370 0, 0, 0, 0, 0, 0, 0, 0, 371 }, 372 "Pentium 4", /* Default */ 373 NULL, 374 intel_family_new_probe, 375 intel_cpu_cacheinfo, 376 } } 377 }, 378 { 379 "AuthenticAMD", 380 CPUVENDOR_AMD, 381 "AMD", 382 /* Family 4 */ 383 { { 384 CPUCLASS_486, 385 { 386 0, 0, 0, "Am486DX2 W/T", 387 0, 0, 0, "Am486DX2 W/B", 388 "Am486DX4 W/T or Am5x86 W/T 150", 389 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 390 0, 0, "Am5x86 W/T 133/160", 391 "Am5x86 W/B 133/160", 392 }, 393 "Am486 or Am5x86", /* Default */ 394 NULL, 395 NULL, 396 NULL, 397 }, 398 /* Family 5 */ 399 { 400 CPUCLASS_586, 401 { 402 "K5", "K5", "K5", "K5", 0, 0, "K6", 403 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 404 "K6-2+/III+", 0, 0, 405 }, 406 "K5 or K6", /* Default */ 407 amd_family5_setup, 408 NULL, 409 amd_cpu_cacheinfo, 410 }, 411 /* Family 6 */ 412 { 413 CPUCLASS_686, 414 { 415 0, "Athlon Model 1", "Athlon Model 2", 416 "Duron", "Athlon Model 4 (Thunderbird)", 417 0, "Athlon", "Duron", "Athlon", 0, 418 "Athlon", 0, 0, 0, 0, 0, 419 }, 420 "K7 (Athlon)", /* Default */ 421 NULL, 422 amd_family6_probe, 423 amd_cpu_cacheinfo, 424 }, 425 /* Family > 6 */ 426 { 427 CPUCLASS_686, 428 { 429 0, 0, 0, 0, 0, 0, 0, 0, 430 0, 0, 0, 0, 0, 0, 0, 0, 431 }, 432 "Unknown K8 (Athlon)", /* Default */ 433 NULL, 434 amd_family6_probe, 435 amd_cpu_cacheinfo, 436 } } 437 }, 438 { 439 "CyrixInstead", 440 CPUVENDOR_CYRIX, 441 "Cyrix", 442 /* Family 4 */ 443 { { 444 CPUCLASS_486, 445 { 446 0, 0, 0, 447 "MediaGX", 448 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 449 }, 450 "486", /* Default */ 451 cyrix6x86_cpu_setup, /* XXX ?? */ 452 NULL, 453 NULL, 454 }, 455 /* Family 5 */ 456 { 457 CPUCLASS_586, 458 { 459 0, 0, "6x86", 0, 460 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 461 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 462 }, 463 "6x86", /* Default */ 464 cyrix6x86_cpu_setup, 465 NULL, 466 NULL, 467 }, 468 /* Family 6 */ 469 { 470 CPUCLASS_686, 471 { 472 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 473 0, 0, 0, 0, 0, 0, 0, 0, 474 }, 475 "6x86MX", /* Default */ 476 cyrix6x86_cpu_setup, 477 NULL, 478 NULL, 479 }, 480 /* Family > 6 */ 481 { 482 CPUCLASS_686, 483 { 484 0, 0, 0, 0, 0, 0, 0, 0, 485 0, 0, 0, 0, 0, 0, 0, 0, 486 }, 487 "Unknown 6x86MX", /* Default */ 488 NULL, 489 NULL, 490 NULL, 491 } } 492 }, 493 { /* MediaGX is now owned by National Semiconductor */ 494 "Geode by NSC", 495 CPUVENDOR_CYRIX, /* XXX */ 496 "National Semiconductor", 497 /* Family 4, NSC never had any of these */ 498 { { 499 CPUCLASS_486, 500 { 501 0, 0, 0, 0, 0, 0, 0, 0, 502 0, 0, 0, 0, 0, 0, 0, 0, 503 }, 504 "486 compatible", /* Default */ 505 NULL, 506 NULL, 507 NULL, 508 }, 509 /* Family 5: Geode family, formerly MediaGX */ 510 { 511 CPUCLASS_586, 512 { 513 0, 0, 0, 0, 514 "Geode GX1", 515 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 516 }, 517 "Geode", /* Default */ 518 cyrix6x86_cpu_setup, 519 NULL, 520 amd_cpu_cacheinfo, 521 }, 522 /* Family 6, not yet available from NSC */ 523 { 524 CPUCLASS_686, 525 { 526 0, 0, 0, 0, 0, 0, 0, 0, 527 0, 0, 0, 0, 0, 0, 0, 0, 528 }, 529 "Pentium Pro compatible", /* Default */ 530 NULL, 531 NULL, 532 NULL, 533 }, 534 /* Family > 6, not yet available from NSC */ 535 { 536 CPUCLASS_686, 537 { 538 0, 0, 0, 0, 0, 0, 0, 0, 539 0, 0, 0, 0, 0, 0, 0, 0, 540 }, 541 "Pentium Pro compatible", /* Default */ 542 NULL, 543 NULL, 544 NULL, 545 } } 546 }, 547 { 548 "CentaurHauls", 549 CPUVENDOR_IDT, 550 "IDT", 551 /* Family 4, IDT never had any of these */ 552 { { 553 CPUCLASS_486, 554 { 555 0, 0, 0, 0, 0, 0, 0, 0, 556 0, 0, 0, 0, 0, 0, 0, 0, 557 }, 558 "486 compatible", /* Default */ 559 NULL, 560 NULL, 561 NULL, 562 }, 563 /* Family 5 */ 564 { 565 CPUCLASS_586, 566 { 567 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 568 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 569 }, 570 "WinChip", /* Default */ 571 winchip_cpu_setup, 572 NULL, 573 NULL, 574 }, 575 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 576 { 577 CPUCLASS_686, 578 { 579 0, 0, 0, 0, 0, 0, "C3 Samuel", 580 "C3 Samuel 2/Ezra", "C3 Ezra-T", 581 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 582 0, "VIA Nano", 583 }, 584 "Unknown VIA/IDT", /* Default */ 585 NULL, 586 via_cpu_probe, 587 via_cpu_cacheinfo, 588 }, 589 /* Family > 6, not yet available from VIA */ 590 { 591 CPUCLASS_686, 592 { 593 0, 0, 0, 0, 0, 0, 0, 0, 594 0, 0, 0, 0, 0, 0, 0, 0, 595 }, 596 "Pentium Pro compatible", /* Default */ 597 NULL, 598 NULL, 599 NULL, 600 } } 601 }, 602 { 603 "GenuineTMx86", 604 CPUVENDOR_TRANSMETA, 605 "Transmeta", 606 /* Family 4, Transmeta never had any of these */ 607 { { 608 CPUCLASS_486, 609 { 610 0, 0, 0, 0, 0, 0, 0, 0, 611 0, 0, 0, 0, 0, 0, 0, 0, 612 }, 613 "486 compatible", /* Default */ 614 NULL, 615 NULL, 616 NULL, 617 }, 618 /* Family 5 */ 619 { 620 CPUCLASS_586, 621 { 622 0, 0, 0, 0, 0, 0, 0, 0, 623 0, 0, 0, 0, 0, 0, 0, 0, 624 }, 625 "Crusoe", /* Default */ 626 NULL, 627 NULL, 628 transmeta_cpu_info, 629 }, 630 /* Family 6, not yet available from Transmeta */ 631 { 632 CPUCLASS_686, 633 { 634 0, 0, 0, 0, 0, 0, 0, 0, 635 0, 0, 0, 0, 0, 0, 0, 0, 636 }, 637 "Pentium Pro compatible", /* Default */ 638 NULL, 639 NULL, 640 NULL, 641 }, 642 /* Family > 6, not yet available from Transmeta */ 643 { 644 CPUCLASS_686, 645 { 646 0, 0, 0, 0, 0, 0, 0, 0, 647 0, 0, 0, 0, 0, 0, 0, 0, 648 }, 649 "Pentium Pro compatible", /* Default */ 650 NULL, 651 NULL, 652 NULL, 653 } } 654 } 655 }; 656 657 /* 658 * disable the TSC such that we don't use the TSC in microtime(9) 659 * because some CPUs got the implementation wrong. 660 */ 661 static void 662 disable_tsc(struct cpu_info *ci) 663 { 664 if (ci->ci_feat_val[0] & CPUID_TSC) { 665 ci->ci_feat_val[0] &= ~CPUID_TSC; 666 aprint_error("WARNING: broken TSC disabled\n"); 667 } 668 } 669 670 static void 671 amd_family5_setup(struct cpu_info *ci) 672 { 673 674 switch (ci->ci_model) { 675 case 0: /* AMD-K5 Model 0 */ 676 /* 677 * According to the AMD Processor Recognition App Note, 678 * the AMD-K5 Model 0 uses the wrong bit to indicate 679 * support for global PTEs, instead using bit 9 (APIC) 680 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 681 */ 682 if (ci->ci_feat_val[0] & CPUID_APIC) 683 ci->ci_feat_val[0] = 684 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 685 /* 686 * XXX But pmap_pg_g is already initialized -- need to kick 687 * XXX the pmap somehow. How does the MP branch do this? 688 */ 689 break; 690 } 691 } 692 693 static void 694 cyrix6x86_cpu_setup(struct cpu_info *ci) 695 { 696 697 /* 698 * Do not disable the TSC on the Geode GX, it's reported to 699 * work fine. 700 */ 701 if (ci->ci_signature != 0x552) 702 disable_tsc(ci); 703 } 704 705 static void 706 winchip_cpu_setup(struct cpu_info *ci) 707 { 708 switch (ci->ci_model) { 709 case 4: /* WinChip C6 */ 710 disable_tsc(ci); 711 } 712 } 713 714 715 static const char * 716 intel_family6_name(struct cpu_info *ci) 717 { 718 const char *ret = NULL; 719 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 720 721 if (ci->ci_model == 5) { 722 switch (l2cache) { 723 case 0: 724 case 128 * 1024: 725 ret = "Celeron (Covington)"; 726 break; 727 case 256 * 1024: 728 ret = "Mobile Pentium II (Dixon)"; 729 break; 730 case 512 * 1024: 731 ret = "Pentium II"; 732 break; 733 case 1 * 1024 * 1024: 734 case 2 * 1024 * 1024: 735 ret = "Pentium II Xeon"; 736 break; 737 } 738 } else if (ci->ci_model == 6) { 739 switch (l2cache) { 740 case 256 * 1024: 741 case 512 * 1024: 742 ret = "Mobile Pentium II"; 743 break; 744 } 745 } else if (ci->ci_model == 7) { 746 switch (l2cache) { 747 case 512 * 1024: 748 ret = "Pentium III"; 749 break; 750 case 1 * 1024 * 1024: 751 case 2 * 1024 * 1024: 752 ret = "Pentium III Xeon"; 753 break; 754 } 755 } else if (ci->ci_model >= 8) { 756 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 757 switch (ci->ci_brand_id) { 758 case 0x3: 759 if (ci->ci_signature == 0x6B1) 760 ret = "Celeron"; 761 break; 762 case 0x8: 763 if (ci->ci_signature >= 0xF13) 764 ret = "genuine processor"; 765 break; 766 case 0xB: 767 if (ci->ci_signature >= 0xF13) 768 ret = "Xeon MP"; 769 break; 770 case 0xE: 771 if (ci->ci_signature < 0xF13) 772 ret = "Xeon"; 773 break; 774 } 775 if (ret == NULL) 776 ret = i386_intel_brand[ci->ci_brand_id]; 777 } 778 } 779 780 return ret; 781 } 782 783 /* 784 * Identify AMD64 CPU names from cpuid. 785 * 786 * Based on: 787 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 788 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 789 * "Revision Guide for AMD NPT Family 0Fh Processors" 790 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 791 * and other miscellaneous reports. 792 * 793 * This is all rather pointless, these are cross 'brand' since the raw 794 * silicon is shared. 795 */ 796 static const char * 797 amd_amd64_name(struct cpu_info *ci) 798 { 799 static char family_str[32]; 800 801 /* Only called if family >= 15 */ 802 803 switch (ci->ci_family) { 804 case 15: 805 switch (ci->ci_model) { 806 case 0x21: /* rev JH-E1/E6 */ 807 case 0x41: /* rev JH-F2 */ 808 return "Dual-Core Opteron"; 809 case 0x23: /* rev JH-E6 (Toledo) */ 810 return "Dual-Core Opteron or Athlon 64 X2"; 811 case 0x43: /* rev JH-F2 (Windsor) */ 812 return "Athlon 64 FX or Athlon 64 X2"; 813 case 0x24: /* rev SH-E5 (Lancaster?) */ 814 return "Mobile Athlon 64 or Turion 64"; 815 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 816 return "Opteron or Athlon 64 FX"; 817 case 0x15: /* rev SH-D0 */ 818 case 0x25: /* rev SH-E4 */ 819 return "Opteron"; 820 case 0x27: /* rev DH-E4, SH-E4 */ 821 return "Athlon 64 or Athlon 64 FX or Opteron"; 822 case 0x48: /* rev BH-F2 */ 823 return "Turion 64 X2"; 824 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 825 case 0x07: /* rev SH-CG (ClawHammer) */ 826 case 0x0b: /* rev CH-CG */ 827 case 0x14: /* rev SH-D0 */ 828 case 0x17: /* rev SH-D0 */ 829 case 0x1b: /* rev CH-D0 */ 830 return "Athlon 64"; 831 case 0x2b: /* rev BH-E4 (Manchester) */ 832 case 0x4b: /* rev BH-F2 (Windsor) */ 833 return "Athlon 64 X2"; 834 case 0x6b: /* rev BH-G1 (Brisbane) */ 835 return "Athlon X2 or Athlon 64 X2"; 836 case 0x08: /* rev CH-CG */ 837 case 0x0c: /* rev DH-CG (Newcastle) */ 838 case 0x0e: /* rev DH-CG (Newcastle?) */ 839 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 840 case 0x18: /* rev CH-D0 */ 841 case 0x1c: /* rev DH-D0 (Winchester) */ 842 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 843 case 0x2c: /* rev DH-E3/E6 */ 844 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 845 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 846 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 847 case 0x6f: /* rev DH-G1 */ 848 return "Athlon 64 or Sempron"; 849 default: 850 break; 851 } 852 return "Unknown AMD64 CPU"; 853 854 #if 0 855 case 16: 856 return "Family 10h"; 857 case 17: 858 return "Family 11h"; 859 case 18: 860 return "Family 12h"; 861 case 19: 862 return "Family 14h"; 863 case 20: 864 return "Family 15h"; 865 #endif 866 867 default: 868 break; 869 } 870 871 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 872 return family_str; 873 } 874 875 static void 876 intel_family_new_probe(struct cpu_info *ci) 877 { 878 uint32_t descs[4]; 879 880 x86_cpuid(0x80000000, descs); 881 882 /* 883 * Determine extended feature flags. 884 */ 885 if (descs[0] >= 0x80000001) { 886 x86_cpuid(0x80000001, descs); 887 ci->ci_feat_val[2] |= descs[3]; 888 ci->ci_feat_val[3] |= descs[2]; 889 } 890 } 891 892 static void 893 via_cpu_probe(struct cpu_info *ci) 894 { 895 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 896 u_int descs[4]; 897 u_int lfunc; 898 899 /* 900 * Determine the largest extended function value. 901 */ 902 x86_cpuid(0x80000000, descs); 903 lfunc = descs[0]; 904 905 /* 906 * Determine the extended feature flags. 907 */ 908 if (lfunc >= 0x80000001) { 909 x86_cpuid(0x80000001, descs); 910 ci->ci_feat_val[2] |= descs[3]; 911 } 912 913 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 914 return; 915 916 /* Nehemiah or Esther */ 917 x86_cpuid(0xc0000000, descs); 918 lfunc = descs[0]; 919 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 920 return; 921 922 x86_cpuid(0xc0000001, descs); 923 lfunc = descs[3]; 924 ci->ci_feat_val[4] = lfunc; 925 } 926 927 static void 928 amd_family6_probe(struct cpu_info *ci) 929 { 930 uint32_t descs[4]; 931 char *p; 932 size_t i; 933 934 x86_cpuid(0x80000000, descs); 935 936 /* 937 * Determine the extended feature flags. 938 */ 939 if (descs[0] >= 0x80000001) { 940 x86_cpuid(0x80000001, descs); 941 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 942 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 943 } 944 945 if (*cpu_brand_string == '\0') 946 return; 947 948 for (i = 1; i < __arraycount(amd_brand); i++) 949 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 950 ci->ci_brand_id = i; 951 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 952 break; 953 } 954 } 955 956 static void 957 intel_cpu_cacheinfo(struct cpu_info *ci) 958 { 959 const struct x86_cache_info *cai; 960 u_int descs[4]; 961 int iterations, i, j; 962 int type, level, ways, linesize, sets; 963 int caitype = -1; 964 uint8_t desc; 965 966 /* Return if the cpu is old pre-cpuid instruction cpu */ 967 if (ci->ci_cpu_type >= 0) 968 return; 969 970 if (ci->ci_max_cpuid < 2) 971 return; 972 973 /* 974 * Parse the cache info from `cpuid leaf 2', if we have it. 975 * XXX This is kinda ugly, but hey, so is the architecture... 976 */ 977 x86_cpuid(2, descs); 978 iterations = descs[0] & 0xff; 979 while (iterations-- > 0) { 980 for (i = 0; i < 4; i++) { 981 if (descs[i] & 0x80000000) 982 continue; 983 for (j = 0; j < 4; j++) { 984 /* 985 * The least significant byte in EAX 986 * ((desc[0] >> 0) & 0xff) is always 0x01 and 987 * it should be ignored. 988 */ 989 if (i == 0 && j == 0) 990 continue; 991 desc = (descs[i] >> (j * 8)) & 0xff; 992 if (desc == 0) 993 continue; 994 cai = cpu_cacheinfo_lookup( 995 intel_cpuid_cache_info, desc); 996 if (cai != NULL) 997 ci->ci_cinfo[cai->cai_index] = *cai; 998 else if ((verbose != 0) && (desc != 0xff) 999 && (desc != 0xfe)) 1000 aprint_error_dev(ci->ci_dev, "error:" 1001 " Unknown cacheinfo desc %02x\n", 1002 desc); 1003 } 1004 } 1005 x86_cpuid(2, descs); 1006 } 1007 1008 if (ci->ci_max_cpuid < 4) 1009 return; 1010 1011 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1012 cpu_dcp_cacheinfo(ci, 4); 1013 1014 if (ci->ci_max_cpuid < 0x18) 1015 return; 1016 /* Parse the TLB info from `cpuid leaf 18H', if we have it. */ 1017 x86_cpuid(0x18, descs); 1018 iterations = descs[0]; 1019 for (i = 0; i <= iterations; i++) { 1020 uint32_t pgsize; 1021 bool full; 1022 1023 x86_cpuid2(0x18, i, descs); 1024 type = __SHIFTOUT(descs[3], CPUID_DATP_TCTYPE); 1025 if (type == CPUID_DATP_TCTYPE_N) 1026 continue; 1027 level = __SHIFTOUT(descs[3], CPUID_DATP_TCLEVEL); 1028 pgsize = __SHIFTOUT(descs[1], CPUID_DATP_PGSIZE); 1029 switch (level) { 1030 case 1: 1031 if (type == CPUID_DATP_TCTYPE_I) { 1032 switch (pgsize) { 1033 case CPUID_DATP_PGSIZE_4KB: 1034 caitype = CAI_ITLB; 1035 break; 1036 case CPUID_DATP_PGSIZE_2MB 1037 | CPUID_DATP_PGSIZE_4MB: 1038 caitype = CAI_ITLB2; 1039 break; 1040 case CPUID_DATP_PGSIZE_1GB: 1041 caitype = CAI_L1_1GBITLB; 1042 break; 1043 default: 1044 aprint_error_dev(ci->ci_dev, 1045 "error: unknown ITLB size (%d)\n", 1046 pgsize); 1047 caitype = CAI_ITLB; 1048 break; 1049 } 1050 } else if (type == CPUID_DATP_TCTYPE_D) { 1051 switch (pgsize) { 1052 case CPUID_DATP_PGSIZE_4KB: 1053 caitype = CAI_DTLB; 1054 break; 1055 case CPUID_DATP_PGSIZE_2MB 1056 | CPUID_DATP_PGSIZE_4MB: 1057 caitype = CAI_DTLB2; 1058 break; 1059 case CPUID_DATP_PGSIZE_1GB: 1060 caitype = CAI_L1_1GBDTLB; 1061 break; 1062 default: 1063 aprint_error_dev(ci->ci_dev, 1064 "error: unknown DTLB size (%d)\n", 1065 pgsize); 1066 caitype = CAI_DTLB; 1067 break; 1068 } 1069 } else if (type == CPUID_DATP_TCTYPE_L) 1070 caitype = CAI_L1_LD_TLB; 1071 else if (type == CPUID_DATP_TCTYPE_S) 1072 caitype = CAI_L1_ST_TLB; 1073 else 1074 caitype = -1; 1075 break; 1076 case 2: 1077 if (type == CPUID_DATP_TCTYPE_I) 1078 caitype = CAI_L2_ITLB; 1079 else if (type == CPUID_DATP_TCTYPE_D) 1080 caitype = CAI_L2_DTLB; 1081 else if (type == CPUID_DATP_TCTYPE_U) { 1082 if (pgsize == CPUID_DATP_PGSIZE_4KB) 1083 caitype = CAI_L2_STLB; 1084 else if (pgsize == (CPUID_DATP_PGSIZE_4KB 1085 | CPUID_DATP_PGSIZE_2MB)) 1086 caitype = CAI_L2_STLB2; 1087 else if (pgsize == (CPUID_DATP_PGSIZE_2MB 1088 | CPUID_DATP_PGSIZE_4MB)) 1089 caitype = CAI_L2_STLB3; 1090 else if ((pgsize & CPUID_DATP_PGSIZE_1GB) 1091 != 0) { 1092 /* FIXME: 1GB max TLB */ 1093 caitype = CAI_L2_STLB3; 1094 linesize = 1024 * 1024 * 1024; 1095 } else if ((pgsize & CPUID_DATP_PGSIZE_4MB) 1096 != 0) { 1097 /* FIXME: 4MB max TLB */ 1098 caitype = CAI_L2_STLB3; 1099 linesize = 4 * 1024 * 1024; 1100 } else if ((pgsize & CPUID_DATP_PGSIZE_2MB) 1101 != 0) { 1102 /* FIXME: 2MB max TLB */ 1103 caitype = CAI_L2_STLB2; 1104 linesize = 2 * 1024 * 1024; 1105 } else { 1106 aprint_error_dev(ci->ci_dev, "error: " 1107 "unknown L2 STLB size (%d)\n", 1108 pgsize); 1109 caitype = CAI_L2_STLB; 1110 linesize = 4 * 1024; 1111 } 1112 } else 1113 caitype = -1; 1114 break; 1115 case 3: 1116 /* XXX need work for L3 TLB */ 1117 caitype = CAI_L3CACHE; 1118 break; 1119 default: 1120 caitype = -1; 1121 break; 1122 } 1123 if (caitype == -1) { 1124 aprint_error_dev(ci->ci_dev, 1125 "error: unknown TLB level&type (%d & %d)\n", 1126 level, type); 1127 continue; 1128 } 1129 switch (pgsize) { 1130 case CPUID_DATP_PGSIZE_4KB: 1131 linesize = 4 * 1024; 1132 break; 1133 case CPUID_DATP_PGSIZE_2MB: 1134 linesize = 2 * 1024 * 1024; 1135 break; 1136 case CPUID_DATP_PGSIZE_4MB: 1137 linesize = 4 * 1024 * 1024; 1138 break; 1139 case CPUID_DATP_PGSIZE_1GB: 1140 linesize = 1024 * 1024 * 1024; 1141 break; 1142 default: 1143 if ((pgsize & CPUID_DATP_PGSIZE_1GB) != 0) 1144 linesize = 1024 * 1024 * 1024; /* MAX 1G */ 1145 else if ((pgsize & CPUID_DATP_PGSIZE_4MB) != 0) 1146 linesize = 4 * 1024 * 1024; /* MAX 4M */ 1147 else if ((pgsize & CPUID_DATP_PGSIZE_2MB) != 0) 1148 linesize = 2 * 1024 * 1024; /* MAX 2M */ 1149 else 1150 linesize = 4 * 1024; /* XXX default to 4K */ 1151 aprint_error_dev(ci->ci_dev, "WARNING: Currently " 1152 "this info can't print correctly " 1153 "(level = %d, pgsize = %d)\n", 1154 level, pgsize); 1155 break; 1156 } 1157 ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS); 1158 sets = descs[2]; 1159 full = descs[3] & CPUID_DATP_FULLASSOC; 1160 ci->ci_cinfo[caitype].cai_totalsize 1161 = ways * sets; /* entries */ 1162 ci->ci_cinfo[caitype].cai_associativity 1163 = full ? 0xff : ways; 1164 ci->ci_cinfo[caitype].cai_linesize = linesize; /* pg size */ 1165 } 1166 } 1167 1168 static const struct x86_cache_info amd_cpuid_l2l3cache_assoc_info[] = 1169 AMD_L2L3CACHE_INFO; 1170 1171 static void 1172 amd_cpu_cacheinfo(struct cpu_info *ci) 1173 { 1174 const struct x86_cache_info *cp; 1175 struct x86_cache_info *cai; 1176 u_int descs[4]; 1177 u_int lfunc; 1178 1179 /* K5 model 0 has none of this info. */ 1180 if (ci->ci_family == 5 && ci->ci_model == 0) 1181 return; 1182 1183 /* Determine the largest extended function value. */ 1184 x86_cpuid(0x80000000, descs); 1185 lfunc = descs[0]; 1186 1187 if (lfunc < 0x80000005) 1188 return; 1189 1190 /* Determine L1 cache/TLB info. */ 1191 x86_cpuid(0x80000005, descs); 1192 1193 /* K6-III and higher have large page TLBs. */ 1194 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1195 cai = &ci->ci_cinfo[CAI_ITLB2]; 1196 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1197 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1198 cai->cai_linesize = largepagesize; 1199 1200 cai = &ci->ci_cinfo[CAI_DTLB2]; 1201 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1202 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1203 cai->cai_linesize = largepagesize; 1204 } 1205 1206 cai = &ci->ci_cinfo[CAI_ITLB]; 1207 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1208 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1209 cai->cai_linesize = (4 * 1024); 1210 1211 cai = &ci->ci_cinfo[CAI_DTLB]; 1212 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1213 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1214 cai->cai_linesize = (4 * 1024); 1215 1216 cai = &ci->ci_cinfo[CAI_DCACHE]; 1217 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1218 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1219 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1220 1221 cai = &ci->ci_cinfo[CAI_ICACHE]; 1222 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1223 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1224 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1225 1226 if (lfunc < 0x80000006) 1227 return; 1228 1229 /* Determine L2 cache/TLB info. */ 1230 x86_cpuid(0x80000006, descs); 1231 1232 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1233 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1234 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1235 cai->cai_linesize = (4 * 1024); 1236 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1237 cai->cai_associativity); 1238 if (cp != NULL) 1239 cai->cai_associativity = cp->cai_associativity; 1240 else 1241 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1242 1243 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1244 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1245 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1246 cai->cai_linesize = largepagesize; 1247 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1248 cai->cai_associativity); 1249 if (cp != NULL) 1250 cai->cai_associativity = cp->cai_associativity; 1251 else 1252 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1253 1254 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1255 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1256 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1257 cai->cai_linesize = (4 * 1024); 1258 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1259 cai->cai_associativity); 1260 if (cp != NULL) 1261 cai->cai_associativity = cp->cai_associativity; 1262 else 1263 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1264 1265 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1266 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1267 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1268 cai->cai_linesize = largepagesize; 1269 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1270 cai->cai_associativity); 1271 if (cp != NULL) 1272 cai->cai_associativity = cp->cai_associativity; 1273 else 1274 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1275 1276 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1277 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1278 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1279 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1280 1281 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1282 cai->cai_associativity); 1283 if (cp != NULL) 1284 cai->cai_associativity = cp->cai_associativity; 1285 else 1286 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1287 1288 /* Determine L3 cache info on AMD Family 10h and newer processors */ 1289 if (ci->ci_family >= 0x10) { 1290 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1291 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1292 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1293 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1294 1295 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1296 cai->cai_associativity); 1297 if (cp != NULL) 1298 cai->cai_associativity = cp->cai_associativity; 1299 else 1300 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1301 } 1302 1303 if (lfunc < 0x80000019) 1304 return; 1305 1306 /* Determine 1GB TLB info. */ 1307 x86_cpuid(0x80000019, descs); 1308 1309 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1310 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1311 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1312 cai->cai_linesize = (1024 * 1024 * 1024); 1313 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1314 cai->cai_associativity); 1315 if (cp != NULL) 1316 cai->cai_associativity = cp->cai_associativity; 1317 else 1318 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1319 1320 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1321 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1322 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1323 cai->cai_linesize = (1024 * 1024 * 1024); 1324 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1325 cai->cai_associativity); 1326 if (cp != NULL) 1327 cai->cai_associativity = cp->cai_associativity; 1328 else 1329 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1330 1331 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1332 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1333 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1334 cai->cai_linesize = (1024 * 1024 * 1024); 1335 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1336 cai->cai_associativity); 1337 if (cp != NULL) 1338 cai->cai_associativity = cp->cai_associativity; 1339 else 1340 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1341 1342 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1343 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1344 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1345 cai->cai_linesize = (1024 * 1024 * 1024); 1346 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1347 cai->cai_associativity); 1348 if (cp != NULL) 1349 cai->cai_associativity = cp->cai_associativity; 1350 else 1351 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1352 1353 if (lfunc < 0x8000001d) 1354 return; 1355 1356 if (ci->ci_feat_val[3] & CPUID_TOPOEXT) 1357 cpu_dcp_cacheinfo(ci, 0x8000001d); 1358 } 1359 1360 static void 1361 via_cpu_cacheinfo(struct cpu_info *ci) 1362 { 1363 struct x86_cache_info *cai; 1364 int stepping; 1365 u_int descs[4]; 1366 u_int lfunc; 1367 1368 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1369 1370 /* 1371 * Determine the largest extended function value. 1372 */ 1373 x86_cpuid(0x80000000, descs); 1374 lfunc = descs[0]; 1375 1376 /* 1377 * Determine L1 cache/TLB info. 1378 */ 1379 if (lfunc < 0x80000005) { 1380 /* No L1 cache info available. */ 1381 return; 1382 } 1383 1384 x86_cpuid(0x80000005, descs); 1385 1386 cai = &ci->ci_cinfo[CAI_ITLB]; 1387 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1388 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1389 cai->cai_linesize = (4 * 1024); 1390 1391 cai = &ci->ci_cinfo[CAI_DTLB]; 1392 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1393 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1394 cai->cai_linesize = (4 * 1024); 1395 1396 cai = &ci->ci_cinfo[CAI_DCACHE]; 1397 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1398 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1399 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1400 if (ci->ci_model == 9 && stepping == 8) { 1401 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1402 cai->cai_associativity = 2; 1403 } 1404 1405 cai = &ci->ci_cinfo[CAI_ICACHE]; 1406 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1407 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1408 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1409 if (ci->ci_model == 9 && stepping == 8) { 1410 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1411 cai->cai_associativity = 2; 1412 } 1413 1414 /* 1415 * Determine L2 cache/TLB info. 1416 */ 1417 if (lfunc < 0x80000006) { 1418 /* No L2 cache info available. */ 1419 return; 1420 } 1421 1422 x86_cpuid(0x80000006, descs); 1423 1424 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1425 if (ci->ci_model >= 9) { 1426 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1427 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1428 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1429 } else { 1430 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1431 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1432 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1433 } 1434 } 1435 1436 static void 1437 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1438 { 1439 u_int descs[4]; 1440 1441 x86_cpuid(0x80860007, descs); 1442 *frequency = descs[0]; 1443 *voltage = descs[1]; 1444 *percentage = descs[2]; 1445 } 1446 1447 static void 1448 transmeta_cpu_info(struct cpu_info *ci) 1449 { 1450 u_int descs[4], nreg; 1451 u_int frequency, voltage, percentage; 1452 1453 x86_cpuid(0x80860000, descs); 1454 nreg = descs[0]; 1455 if (nreg >= 0x80860001) { 1456 x86_cpuid(0x80860001, descs); 1457 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1458 (descs[1] >> 24) & 0xff, 1459 (descs[1] >> 16) & 0xff, 1460 (descs[1] >> 8) & 0xff, 1461 descs[1] & 0xff); 1462 } 1463 if (nreg >= 0x80860002) { 1464 x86_cpuid(0x80860002, descs); 1465 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1466 (descs[1] >> 24) & 0xff, 1467 (descs[1] >> 16) & 0xff, 1468 (descs[1] >> 8) & 0xff, 1469 descs[1] & 0xff, 1470 descs[2]); 1471 } 1472 if (nreg >= 0x80860006) { 1473 union { 1474 char text[65]; 1475 u_int descs[4][4]; 1476 } info; 1477 int i; 1478 1479 for (i=0; i<4; i++) { 1480 x86_cpuid(0x80860003 + i, info.descs[i]); 1481 } 1482 info.text[64] = '\0'; 1483 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1484 } 1485 1486 if (nreg >= 0x80860007) { 1487 tmx86_get_longrun_status(&frequency, 1488 &voltage, &percentage); 1489 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1490 frequency, voltage, percentage); 1491 } 1492 } 1493 1494 static void 1495 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1496 { 1497 u_int descs[4]; 1498 int i; 1499 uint32_t brand[12]; 1500 1501 memset(ci, 0, sizeof(*ci)); 1502 ci->ci_dev = cpuname; 1503 1504 ci->ci_cpu_type = x86_identify(); 1505 if (ci->ci_cpu_type >= 0) { 1506 /* Old pre-cpuid instruction cpu */ 1507 ci->ci_max_cpuid = -1; 1508 return; 1509 } 1510 1511 /* 1512 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1513 * function. 1514 */ 1515 1516 /* 1517 * Fn0000_0000: 1518 * - Save cpuid max level. 1519 * - Save vendor string. 1520 */ 1521 x86_cpuid(0, descs); 1522 ci->ci_max_cpuid = descs[0]; 1523 /* Save vendor string */ 1524 ci->ci_vendor[0] = descs[1]; 1525 ci->ci_vendor[2] = descs[2]; 1526 ci->ci_vendor[1] = descs[3]; 1527 ci->ci_vendor[3] = 0; 1528 1529 /* 1530 * Fn8000_0000: 1531 * - Get cpuid extended function's max level. 1532 */ 1533 x86_cpuid(0x80000000, descs); 1534 if (descs[0] >= 0x80000000) 1535 ci->ci_max_ext_cpuid = descs[0]; 1536 else { 1537 /* Set lower value than 0x80000000 */ 1538 ci->ci_max_ext_cpuid = 0; 1539 } 1540 1541 /* 1542 * Fn8000_000[2-4]: 1543 * - Save brand string. 1544 */ 1545 if (ci->ci_max_ext_cpuid >= 0x80000004) { 1546 x86_cpuid(0x80000002, brand); 1547 x86_cpuid(0x80000003, brand + 4); 1548 x86_cpuid(0x80000004, brand + 8); 1549 for (i = 0; i < 48; i++) 1550 if (((char *) brand)[i] != ' ') 1551 break; 1552 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1553 } 1554 1555 if (ci->ci_max_cpuid < 1) 1556 return; 1557 1558 /* 1559 * Fn0000_0001: 1560 * - Get CPU family, model and stepping (from eax). 1561 * - Initial local APIC ID and brand ID (from ebx) 1562 * - CPUID2 (from ecx) 1563 * - CPUID (from edx) 1564 */ 1565 x86_cpuid(1, descs); 1566 ci->ci_signature = descs[0]; 1567 1568 /* Extract full family/model values */ 1569 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1570 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1571 1572 /* Brand is low order 8 bits of ebx */ 1573 ci->ci_brand_id = __SHIFTOUT(descs[1], CPUID_BRAND_INDEX); 1574 /* Initial local APIC ID */ 1575 ci->ci_initapicid = __SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID); 1576 1577 ci->ci_feat_val[1] = descs[2]; 1578 ci->ci_feat_val[0] = descs[3]; 1579 1580 if (ci->ci_max_cpuid < 3) 1581 return; 1582 1583 /* 1584 * If the processor serial number misfeature is present and supported, 1585 * extract it here. 1586 */ 1587 if ((ci->ci_feat_val[0] & CPUID_PSN) != 0) { 1588 ci->ci_cpu_serial[0] = ci->ci_signature; 1589 x86_cpuid(3, descs); 1590 ci->ci_cpu_serial[2] = descs[2]; 1591 ci->ci_cpu_serial[1] = descs[3]; 1592 } 1593 1594 if (ci->ci_max_cpuid < 0x7) 1595 return; 1596 1597 x86_cpuid(7, descs); 1598 ci->ci_feat_val[5] = descs[1]; 1599 ci->ci_feat_val[6] = descs[2]; 1600 ci->ci_feat_val[7] = descs[3]; 1601 1602 if (ci->ci_max_cpuid < 0xd) 1603 return; 1604 1605 /* Get support XCR0 bits */ 1606 x86_cpuid2(0xd, 0, descs); 1607 ci->ci_feat_val[8] = descs[0]; /* Actually 64 bits */ 1608 ci->ci_cur_xsave = descs[1]; 1609 ci->ci_max_xsave = descs[2]; 1610 1611 /* Additional flags (eg xsaveopt support) */ 1612 x86_cpuid2(0xd, 1, descs); 1613 ci->ci_feat_val[9] = descs[0]; /* Actually 64 bits */ 1614 } 1615 1616 static void 1617 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1618 { 1619 uint32_t descs[4]; 1620 char hv_sig[13]; 1621 char *p; 1622 const char *hv_name; 1623 int i; 1624 1625 /* 1626 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1627 * http://lkml.org/lkml/2008/10/1/246 1628 * 1629 * KB1009458: Mechanisms to determine if software is running in 1630 * a VMware virtual machine 1631 * http://kb.vmware.com/kb/1009458 1632 */ 1633 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1634 x86_cpuid(0x40000000, descs); 1635 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1636 memcpy(p, &descs[i], sizeof(descs[i])); 1637 *p = '\0'; 1638 /* 1639 * HV vendor ID string 1640 * ------------+-------------- 1641 * HAXM "HAXMHAXMHAXM" 1642 * KVM "KVMKVMKVM" 1643 * Microsoft "Microsoft Hv" 1644 * QEMU(TCG) "TCGTCGTCGTCG" 1645 * VMware "VMwareVMware" 1646 * Xen "XenVMMXenVMM" 1647 * NetBSD "___ NVMM ___" 1648 */ 1649 if (strncmp(hv_sig, "HAXMHAXMHAXM", 12) == 0) 1650 hv_name = "HAXM"; 1651 else if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1652 hv_name = "KVM"; 1653 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1654 hv_name = "Hyper-V"; 1655 else if (strncmp(hv_sig, "TCGTCGTCGTCG", 12) == 0) 1656 hv_name = "QEMU(TCG)"; 1657 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1658 hv_name = "VMware"; 1659 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1660 hv_name = "Xen"; 1661 else if (strncmp(hv_sig, "___ NVMM ___", 12) == 0) 1662 hv_name = "NVMM"; 1663 else 1664 hv_name = "unknown"; 1665 1666 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1667 } 1668 } 1669 1670 static void 1671 cpu_probe_features(struct cpu_info *ci) 1672 { 1673 const struct cpu_cpuid_nameclass *cpup = NULL; 1674 unsigned int i; 1675 1676 if (ci->ci_max_cpuid < 1) 1677 return; 1678 1679 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1680 if (!strncmp((char *)ci->ci_vendor, 1681 i386_cpuid_cpus[i].cpu_id, 12)) { 1682 cpup = &i386_cpuid_cpus[i]; 1683 break; 1684 } 1685 } 1686 1687 if (cpup == NULL) 1688 return; 1689 1690 i = ci->ci_family - CPU_MINFAMILY; 1691 1692 if (i >= __arraycount(cpup->cpu_family)) 1693 i = __arraycount(cpup->cpu_family) - 1; 1694 1695 if (cpup->cpu_family[i].cpu_probe == NULL) 1696 return; 1697 1698 (*cpup->cpu_family[i].cpu_probe)(ci); 1699 } 1700 1701 static void 1702 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1703 { 1704 char buf[32 * 16]; 1705 char *bp; 1706 1707 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1708 1709 if (val == 0 || fmt == NULL) 1710 return; 1711 1712 snprintb_m(buf, sizeof(buf), fmt, val, 1713 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1714 bp = buf; 1715 while (*bp != '\0') { 1716 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1717 bp += strlen(bp) + 1; 1718 } 1719 } 1720 1721 static void 1722 dump_descs(uint32_t leafstart, uint32_t leafend, const char *cpuname, 1723 const char *blockname) 1724 { 1725 uint32_t descs[4]; 1726 uint32_t leaf; 1727 1728 aprint_verbose("%s: highest %s info %08x\n", cpuname, blockname, 1729 leafend); 1730 1731 if (verbose) { 1732 for (leaf = leafstart; leaf <= leafend; leaf++) { 1733 x86_cpuid(leaf, descs); 1734 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1735 leaf, descs[0], descs[1], descs[2], descs[3]); 1736 } 1737 } 1738 } 1739 1740 static void 1741 identifycpu_cpuids_intel_0x04(struct cpu_info *ci) 1742 { 1743 u_int lp_max = 1; /* logical processors per package */ 1744 u_int smt_max; /* smt per core */ 1745 u_int core_max = 1; /* core per package */ 1746 u_int smt_bits, core_bits; 1747 uint32_t descs[4]; 1748 1749 /* 1750 * 253668.pdf 7.10.2 1751 */ 1752 1753 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1754 x86_cpuid(1, descs); 1755 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1756 } 1757 x86_cpuid2(4, 0, descs); 1758 core_max = __SHIFTOUT(descs[0], CPUID_DCP_CORE_P_PKG) + 1; 1759 1760 assert(lp_max >= core_max); 1761 smt_max = lp_max / core_max; 1762 smt_bits = ilog2(smt_max - 1) + 1; 1763 core_bits = ilog2(core_max - 1) + 1; 1764 1765 if (smt_bits + core_bits) 1766 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1767 1768 if (core_bits) 1769 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1770 __BITS(smt_bits, smt_bits + core_bits - 1)); 1771 1772 if (smt_bits) 1773 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1774 __BITS((int)0, (int)(smt_bits - 1))); 1775 } 1776 1777 static void 1778 identifycpu_cpuids_intel_0x0b(struct cpu_info *ci) 1779 { 1780 const char *cpuname = ci->ci_dev; 1781 u_int smt_bits, core_bits, core_shift = 0, pkg_shift = 0; 1782 uint32_t descs[4]; 1783 int i; 1784 1785 x86_cpuid(0x0b, descs); 1786 if (descs[1] == 0) { 1787 identifycpu_cpuids_intel_0x04(ci); 1788 return; 1789 } 1790 1791 for (i = 0; ; i++) { 1792 unsigned int shiftnum, lvltype; 1793 x86_cpuid2(0x0b, i, descs); 1794 1795 /* On invalid level, (EAX and) EBX return 0 */ 1796 if (descs[1] == 0) 1797 break; 1798 1799 shiftnum = __SHIFTOUT(descs[0], CPUID_TOP_SHIFTNUM); 1800 lvltype = __SHIFTOUT(descs[2], CPUID_TOP_LVLTYPE); 1801 switch (lvltype) { 1802 case CPUID_TOP_LVLTYPE_SMT: 1803 core_shift = shiftnum; 1804 break; 1805 case CPUID_TOP_LVLTYPE_CORE: 1806 pkg_shift = shiftnum; 1807 break; 1808 case CPUID_TOP_LVLTYPE_INVAL: 1809 aprint_verbose("%s: Invalid level type\n", cpuname); 1810 break; 1811 default: 1812 aprint_verbose("%s: Unknown level type(%d) \n", 1813 cpuname, lvltype); 1814 break; 1815 } 1816 } 1817 1818 assert(pkg_shift >= core_shift); 1819 smt_bits = core_shift; 1820 core_bits = pkg_shift - core_shift; 1821 1822 ci->ci_packageid = ci->ci_initapicid >> pkg_shift; 1823 1824 if (core_bits) 1825 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1826 __BITS(core_shift, pkg_shift - 1)); 1827 1828 if (smt_bits) 1829 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1830 __BITS((int)0, core_shift - 1)); 1831 } 1832 1833 static void 1834 identifycpu_cpuids_intel(struct cpu_info *ci) 1835 { 1836 const char *cpuname = ci->ci_dev; 1837 1838 if (ci->ci_max_cpuid >= 0x0b) 1839 identifycpu_cpuids_intel_0x0b(ci); 1840 else if (ci->ci_max_cpuid >= 4) 1841 identifycpu_cpuids_intel_0x04(ci); 1842 1843 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1844 ci->ci_packageid); 1845 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1846 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1847 } 1848 1849 static void 1850 identifycpu_cpuids_amd(struct cpu_info *ci) 1851 { 1852 const char *cpuname = ci->ci_dev; 1853 u_int lp_max, core_max; 1854 int n, cpu_family, apic_id, smt_bits, core_bits = 0; 1855 uint32_t descs[4]; 1856 1857 apic_id = ci->ci_initapicid; 1858 cpu_family = CPUID_TO_FAMILY(ci->ci_signature); 1859 1860 if (cpu_family < 0xf) 1861 return; 1862 1863 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1864 x86_cpuid(1, descs); 1865 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1866 1867 if (cpu_family >= 0x10 && ci->ci_max_ext_cpuid >= 0x8000008) { 1868 x86_cpuid(0x8000008, descs); 1869 core_max = (descs[2] & 0xff) + 1; 1870 n = (descs[2] >> 12) & 0x0f; 1871 if (n != 0) 1872 core_bits = n; 1873 } 1874 } else { 1875 lp_max = 1; 1876 } 1877 core_max = lp_max; 1878 1879 smt_bits = ilog2((lp_max / core_max) - 1) + 1; 1880 if (core_bits == 0) 1881 core_bits = ilog2(core_max - 1) + 1; 1882 1883 #if 0 /* MSRs need kernel mode */ 1884 if (cpu_family < 0x11) { 1885 const uint64_t reg = rdmsr(MSR_NB_CFG); 1886 if ((reg & NB_CFG_INITAPICCPUIDLO) == 0) { 1887 const u_int node_id = apic_id & __BITS(0, 2); 1888 apic_id = (cpu_family == 0xf) ? 1889 (apic_id >> core_bits) | (node_id << core_bits) : 1890 (apic_id >> 5) | (node_id << 2); 1891 } 1892 } 1893 #endif 1894 1895 if (cpu_family == 0x17) { 1896 x86_cpuid(0x8000001e, descs); 1897 const u_int threads = ((descs[1] >> 8) & 0xff) + 1; 1898 smt_bits = ilog2(threads); 1899 core_bits -= smt_bits; 1900 } 1901 1902 if (smt_bits + core_bits) { 1903 if (smt_bits + core_bits < 32) 1904 ci->ci_packageid = 0; 1905 } 1906 if (core_bits) { 1907 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1908 ci->ci_coreid = __SHIFTOUT(apic_id, core_mask); 1909 } 1910 if (smt_bits) { 1911 u_int smt_mask = __BITS(0, smt_bits - 1); 1912 ci->ci_smtid = __SHIFTOUT(apic_id, smt_mask); 1913 } 1914 1915 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1916 ci->ci_packageid); 1917 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1918 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1919 } 1920 1921 static void 1922 identifycpu_cpuids(struct cpu_info *ci) 1923 { 1924 const char *cpuname = ci->ci_dev; 1925 1926 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1927 ci->ci_packageid = ci->ci_initapicid; 1928 ci->ci_coreid = 0; 1929 ci->ci_smtid = 0; 1930 1931 if (cpu_vendor == CPUVENDOR_INTEL) 1932 identifycpu_cpuids_intel(ci); 1933 else if (cpu_vendor == CPUVENDOR_AMD) 1934 identifycpu_cpuids_amd(ci); 1935 } 1936 1937 void 1938 identifycpu(int fd, const char *cpuname) 1939 { 1940 const char *name = "", *modifier, *vendorname, *brand = ""; 1941 int class = CPUCLASS_386; 1942 unsigned int i; 1943 int modif, family; 1944 const struct cpu_cpuid_nameclass *cpup = NULL; 1945 const struct cpu_cpuid_family *cpufam; 1946 struct cpu_info *ci, cistore; 1947 u_int descs[4]; 1948 size_t sz; 1949 struct cpu_ucode_version ucode; 1950 union { 1951 struct cpu_ucode_version_amd amd; 1952 struct cpu_ucode_version_intel1 intel1; 1953 } ucvers; 1954 1955 ci = &cistore; 1956 cpu_probe_base_features(ci, cpuname); 1957 dump_descs(0x00000000, ci->ci_max_cpuid, cpuname, "basic"); 1958 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1959 x86_cpuid(0x40000000, descs); 1960 dump_descs(0x40000000, descs[0], cpuname, "hypervisor"); 1961 } 1962 dump_descs(0x80000000, ci->ci_max_ext_cpuid, cpuname, "extended"); 1963 1964 cpu_probe_hv_features(ci, cpuname); 1965 cpu_probe_features(ci); 1966 1967 if (ci->ci_cpu_type >= 0) { 1968 /* Old pre-cpuid instruction cpu */ 1969 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1970 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1971 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1972 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1973 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1974 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1975 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1976 modifier = ""; 1977 } else { 1978 /* CPU which support cpuid instruction */ 1979 modif = (ci->ci_signature >> 12) & 0x3; 1980 family = ci->ci_family; 1981 if (family < CPU_MINFAMILY) 1982 errx(1, "identifycpu: strange family value"); 1983 if (family > CPU_MAXFAMILY) 1984 family = CPU_MAXFAMILY; 1985 1986 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1987 if (!strncmp((char *)ci->ci_vendor, 1988 i386_cpuid_cpus[i].cpu_id, 12)) { 1989 cpup = &i386_cpuid_cpus[i]; 1990 break; 1991 } 1992 } 1993 1994 if (cpup == NULL) { 1995 cpu_vendor = CPUVENDOR_UNKNOWN; 1996 if (ci->ci_vendor[0] != '\0') 1997 vendorname = (char *)&ci->ci_vendor[0]; 1998 else 1999 vendorname = "Unknown"; 2000 class = family - 3; 2001 modifier = ""; 2002 name = ""; 2003 ci->ci_info = NULL; 2004 } else { 2005 cpu_vendor = cpup->cpu_vendor; 2006 vendorname = cpup->cpu_vendorname; 2007 modifier = modifiers[modif]; 2008 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 2009 name = cpufam->cpu_models[ci->ci_model]; 2010 if (name == NULL || *name == '\0') 2011 name = cpufam->cpu_model_default; 2012 class = cpufam->cpu_class; 2013 ci->ci_info = cpufam->cpu_info; 2014 2015 if (cpu_vendor == CPUVENDOR_INTEL) { 2016 if (ci->ci_family == 6 && ci->ci_model >= 5) { 2017 const char *tmp; 2018 tmp = intel_family6_name(ci); 2019 if (tmp != NULL) 2020 name = tmp; 2021 } 2022 if (ci->ci_family == 15 && 2023 ci->ci_brand_id < 2024 __arraycount(i386_intel_brand) && 2025 i386_intel_brand[ci->ci_brand_id]) 2026 name = 2027 i386_intel_brand[ci->ci_brand_id]; 2028 } 2029 2030 if (cpu_vendor == CPUVENDOR_AMD) { 2031 if (ci->ci_family == 6 && ci->ci_model >= 6) { 2032 if (ci->ci_brand_id == 1) 2033 /* 2034 * It's Duron. We override the 2035 * name, since it might have 2036 * been misidentified as Athlon. 2037 */ 2038 name = 2039 amd_brand[ci->ci_brand_id]; 2040 else 2041 brand = amd_brand_name; 2042 } 2043 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 2044 == 0xf) { 2045 /* Identify AMD64 CPU names. */ 2046 const char *tmp; 2047 tmp = amd_amd64_name(ci); 2048 if (tmp != NULL) 2049 name = tmp; 2050 } 2051 } 2052 2053 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 2054 vendorname = "VIA"; 2055 } 2056 } 2057 2058 ci->ci_cpu_class = class; 2059 2060 sz = sizeof(ci->ci_tsc_freq); 2061 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 2062 sz = sizeof(use_pae); 2063 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 2064 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 2065 2066 /* 2067 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 2068 * we try to determine from the family/model values. 2069 */ 2070 if (*cpu_brand_string != '\0') 2071 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 2072 2073 aprint_normal("%s: %s", cpuname, vendorname); 2074 if (*modifier) 2075 aprint_normal(" %s", modifier); 2076 if (*name) 2077 aprint_normal(" %s", name); 2078 if (*brand) 2079 aprint_normal(" %s", brand); 2080 aprint_normal(" (%s-class)", classnames[class]); 2081 2082 if (ci->ci_tsc_freq != 0) 2083 aprint_normal(", %ju.%02ju MHz", 2084 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 2085 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 2086 aprint_normal("\n"); 2087 2088 (void)cpu_tsc_freq_cpuid(ci); 2089 2090 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 2091 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 2092 if (ci->ci_signature != 0) 2093 aprint_normal(" (id %#x)", ci->ci_signature); 2094 aprint_normal("\n"); 2095 2096 if (ci->ci_info) 2097 (*ci->ci_info)(ci); 2098 2099 /* 2100 * display CPU feature flags 2101 */ 2102 2103 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 2104 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 2105 2106 /* These next two are actually common definitions! */ 2107 print_bits(cpuname, "features2", 2108 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 2109 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 2110 print_bits(cpuname, "features3", 2111 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 2112 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 2113 2114 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 2115 ci->ci_feat_val[4]); 2116 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2117 print_bits(cpuname, "features5", CPUID_SEF_FLAGS, 2118 ci->ci_feat_val[5]); 2119 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2120 print_bits(cpuname, "features6", CPUID_SEF_FLAGS1, 2121 ci->ci_feat_val[6]); 2122 2123 if (cpu_vendor == CPUVENDOR_INTEL) 2124 print_bits(cpuname, "features7", CPUID_SEF_FLAGS2, 2125 ci->ci_feat_val[7]); 2126 2127 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[8]); 2128 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 2129 ci->ci_feat_val[9]); 2130 2131 if (ci->ci_max_xsave != 0) { 2132 aprint_normal("%s: xsave area size: current %d, maximum %d", 2133 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 2134 aprint_normal(", xgetbv %sabled\n", 2135 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 2136 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 2137 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 2138 x86_xgetbv()); 2139 } 2140 2141 x86_print_cache_and_tlb_info(ci); 2142 2143 if (ci->ci_max_cpuid >= 3 && (ci->ci_feat_val[0] & CPUID_PSN)) { 2144 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 2145 cpuname, 2146 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 2147 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 2148 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 2149 } 2150 2151 if (ci->ci_cpu_class == CPUCLASS_386) 2152 errx(1, "NetBSD requires an 80486 or later processor"); 2153 2154 if (ci->ci_cpu_type == CPU_486DLC) { 2155 #ifndef CYRIX_CACHE_WORKS 2156 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 2157 #else 2158 #ifndef CYRIX_CACHE_REALLY_WORKS 2159 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 2160 #else 2161 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 2162 #endif 2163 #endif 2164 } 2165 2166 /* 2167 * Everything past this point requires a Pentium or later. 2168 */ 2169 if (ci->ci_max_cpuid < 0) 2170 return; 2171 2172 identifycpu_cpuids(ci); 2173 2174 if ((ci->ci_max_cpuid >= 5) 2175 && ((cpu_vendor == CPUVENDOR_INTEL) 2176 || (cpu_vendor == CPUVENDOR_AMD))) { 2177 uint16_t lmin, lmax; 2178 x86_cpuid(5, descs); 2179 2180 print_bits(cpuname, "MONITOR/MWAIT extensions", 2181 CPUID_MON_FLAGS, descs[2]); 2182 lmin = __SHIFTOUT(descs[0], CPUID_MON_MINSIZE); 2183 lmax = __SHIFTOUT(descs[1], CPUID_MON_MAXSIZE); 2184 aprint_normal("%s: monitor-line size %hu", cpuname, lmin); 2185 if (lmin != lmax) 2186 aprint_normal("-%hu", lmax); 2187 aprint_normal("\n"); 2188 2189 for (i = 0; i <= 7; i++) { 2190 unsigned int num = CPUID_MON_SUBSTATE(descs[3], i); 2191 2192 if (num != 0) 2193 aprint_normal("%s: C%u substates %u\n", 2194 cpuname, i, num); 2195 } 2196 } 2197 if ((ci->ci_max_cpuid >= 6) 2198 && ((cpu_vendor == CPUVENDOR_INTEL) 2199 || (cpu_vendor == CPUVENDOR_AMD))) { 2200 x86_cpuid(6, descs); 2201 print_bits(cpuname, "DSPM-eax", CPUID_DSPM_FLAGS, descs[0]); 2202 print_bits(cpuname, "DSPM-ecx", CPUID_DSPM_FLAGS1, descs[2]); 2203 } 2204 if ((ci->ci_max_cpuid >= 7) 2205 && ((cpu_vendor == CPUVENDOR_INTEL) 2206 || (cpu_vendor == CPUVENDOR_AMD))) { 2207 x86_cpuid(7, descs); 2208 aprint_verbose("%s: SEF highest subleaf %08x\n", 2209 cpuname, descs[0]); 2210 if (descs[0] >= 1) { 2211 x86_cpuid2(7, 1, descs); 2212 print_bits(cpuname, "SEF-subleaf1-eax", 2213 CPUID_SEF1_FLAGS_A, descs[0]); 2214 } 2215 } 2216 2217 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) { 2218 if (ci->ci_max_ext_cpuid >= 0x80000007) 2219 powernow_probe(ci); 2220 2221 if (ci->ci_max_ext_cpuid >= 0x80000008) { 2222 x86_cpuid(0x80000008, descs); 2223 print_bits(cpuname, "AMD Extended features", 2224 CPUID_CAPEX_FLAGS, descs[1]); 2225 } 2226 } 2227 2228 if (cpu_vendor == CPUVENDOR_AMD) { 2229 if ((ci->ci_max_ext_cpuid >= 0x8000000a) 2230 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 2231 x86_cpuid(0x8000000a, descs); 2232 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 2233 descs[0] & 0xf); 2234 aprint_verbose("%s: SVM NASID %d\n", cpuname, 2235 descs[1]); 2236 print_bits(cpuname, "SVM features", 2237 CPUID_AMD_SVM_FLAGS, descs[3]); 2238 } 2239 if (ci->ci_max_ext_cpuid >= 0x8000001f) { 2240 x86_cpuid(0x8000001f, descs); 2241 print_bits(cpuname, "Encrypted Memory features", 2242 CPUID_AMD_ENCMEM_FLAGS, descs[0]); 2243 } 2244 } else if (cpu_vendor == CPUVENDOR_INTEL) { 2245 int32_t bi_index; 2246 2247 for (bi_index = 1; bi_index <= ci->ci_max_cpuid; bi_index++) { 2248 x86_cpuid(bi_index, descs); 2249 switch (bi_index) { 2250 case 0x0a: 2251 print_bits(cpuname, "Perfmon-eax", 2252 CPUID_PERF_FLAGS0, descs[0]); 2253 print_bits(cpuname, "Perfmon-ebx", 2254 CPUID_PERF_FLAGS1, descs[1]); 2255 print_bits(cpuname, "Perfmon-edx", 2256 CPUID_PERF_FLAGS3, descs[3]); 2257 break; 2258 default: 2259 #if 0 2260 aprint_verbose("%s: basic %08x-eax %08x\n", 2261 cpuname, bi_index, descs[0]); 2262 aprint_verbose("%s: basic %08x-ebx %08x\n", 2263 cpuname, bi_index, descs[1]); 2264 aprint_verbose("%s: basic %08x-ecx %08x\n", 2265 cpuname, bi_index, descs[2]); 2266 aprint_verbose("%s: basic %08x-edx %08x\n", 2267 cpuname, bi_index, descs[3]); 2268 #endif 2269 break; 2270 } 2271 } 2272 } 2273 2274 #ifdef INTEL_ONDEMAND_CLOCKMOD 2275 clockmod_init(); 2276 #endif 2277 2278 if (cpu_vendor == CPUVENDOR_AMD) 2279 ucode.loader_version = CPU_UCODE_LOADER_AMD; 2280 else if (cpu_vendor == CPUVENDOR_INTEL) 2281 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 2282 else 2283 return; 2284 2285 ucode.data = &ucvers; 2286 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 2287 #ifdef __i386__ 2288 struct cpu_ucode_version_64 ucode_64; 2289 if (errno != ENOTTY) 2290 return; 2291 /* Try the 64 bit ioctl */ 2292 memset(&ucode_64, 0, sizeof ucode_64); 2293 ucode_64.data = &ucvers; 2294 ucode_64.loader_version = ucode.loader_version; 2295 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 2296 return; 2297 #else 2298 return; 2299 #endif 2300 } 2301 2302 if (cpu_vendor == CPUVENDOR_AMD) 2303 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2304 else if (cpu_vendor == CPUVENDOR_INTEL) 2305 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2306 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2307 } 2308 2309 static const char * 2310 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2311 const char *sep) 2312 { 2313 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2314 char human_num[HUMAN_BUFSIZE]; 2315 2316 if (cai->cai_totalsize == 0) 2317 return sep; 2318 2319 if (sep == NULL) 2320 aprint_verbose_dev(ci->ci_dev, ""); 2321 else 2322 aprint_verbose("%s", sep); 2323 if (name != NULL) 2324 aprint_verbose("%s ", name); 2325 2326 if (cai->cai_string != NULL) { 2327 aprint_verbose("%s ", cai->cai_string); 2328 } else { 2329 (void)humanize_number(human_num, sizeof(human_num), 2330 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2331 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2332 } 2333 switch (cai->cai_associativity) { 2334 case 0: 2335 aprint_verbose("disabled"); 2336 break; 2337 case 1: 2338 aprint_verbose("direct-mapped"); 2339 break; 2340 case 0xff: 2341 aprint_verbose("fully associative"); 2342 break; 2343 default: 2344 aprint_verbose("%d-way", cai->cai_associativity); 2345 break; 2346 } 2347 return ", "; 2348 } 2349 2350 static const char * 2351 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2352 const char *sep) 2353 { 2354 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2355 char human_num[HUMAN_BUFSIZE]; 2356 2357 if (cai->cai_totalsize == 0) 2358 return sep; 2359 2360 if (sep == NULL) 2361 aprint_verbose_dev(ci->ci_dev, ""); 2362 else 2363 aprint_verbose("%s", sep); 2364 if ((name != NULL) && (sep == NULL)) 2365 aprint_verbose("%s ", name); 2366 2367 if (cai->cai_string != NULL) { 2368 aprint_verbose("%s", cai->cai_string); 2369 } else { 2370 (void)humanize_number(human_num, sizeof(human_num), 2371 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2372 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2373 human_num); 2374 switch (cai->cai_associativity) { 2375 case 0: 2376 aprint_verbose("disabled"); 2377 break; 2378 case 1: 2379 aprint_verbose("direct-mapped"); 2380 break; 2381 case 0xff: 2382 aprint_verbose("fully associative"); 2383 break; 2384 default: 2385 aprint_verbose("%d-way", cai->cai_associativity); 2386 break; 2387 } 2388 } 2389 return ", "; 2390 } 2391 2392 static void 2393 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2394 { 2395 const char *sep = NULL; 2396 2397 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2398 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2399 sep = print_cache_config(ci, CAI_ICACHE, "I-cache:", NULL); 2400 sep = print_cache_config(ci, CAI_DCACHE, "D-cache:", sep); 2401 if (sep != NULL) 2402 aprint_verbose("\n"); 2403 } 2404 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2405 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache:", NULL); 2406 if (sep != NULL) 2407 aprint_verbose("\n"); 2408 } 2409 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2410 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache:", NULL); 2411 if (sep != NULL) 2412 aprint_verbose("\n"); 2413 } 2414 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2415 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2416 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2417 if (sep != NULL) 2418 aprint_verbose("\n"); 2419 } 2420 2421 sep = print_tlb_config(ci, CAI_ITLB, "ITLB:", NULL); 2422 sep = print_tlb_config(ci, CAI_ITLB2, "ITLB:", sep); 2423 if (sep != NULL) 2424 aprint_verbose("\n"); 2425 2426 sep = print_tlb_config(ci, CAI_DTLB, "DTLB:", NULL); 2427 sep = print_tlb_config(ci, CAI_DTLB2, "DTLB:", sep); 2428 if (sep != NULL) 2429 aprint_verbose("\n"); 2430 2431 sep = print_tlb_config(ci, CAI_L1_LD_TLB, "Load only TLB:", NULL); 2432 if (sep != NULL) 2433 aprint_verbose("\n"); 2434 2435 sep = print_tlb_config(ci, CAI_L1_ST_TLB, "Store only TLB:", NULL); 2436 if (sep != NULL) 2437 aprint_verbose("\n"); 2438 2439 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB:", NULL); 2440 sep = print_tlb_config(ci, CAI_L2_ITLB2, "L2 ITLB:", sep); 2441 if (sep != NULL) 2442 aprint_verbose("\n"); 2443 2444 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB:", NULL); 2445 sep = print_tlb_config(ci, CAI_L2_DTLB2, "L2 DTLB:", sep); 2446 if (sep != NULL) 2447 aprint_verbose("\n"); 2448 2449 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB:", NULL); 2450 sep = print_tlb_config(ci, CAI_L2_STLB2, "L2 STLB:", sep); 2451 sep = print_tlb_config(ci, CAI_L2_STLB3, "L2 STLB:", sep); 2452 if (sep != NULL) 2453 aprint_verbose("\n"); 2454 2455 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB:", NULL); 2456 if (sep != NULL) 2457 aprint_verbose("\n"); 2458 2459 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB:", NULL); 2460 if (sep != NULL) 2461 aprint_verbose("\n"); 2462 2463 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB:", NULL); 2464 if (sep != NULL) 2465 aprint_verbose("\n"); 2466 2467 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB:", NULL); 2468 if (sep != NULL) 2469 aprint_verbose("\n"); 2470 } 2471 2472 static void 2473 powernow_probe(struct cpu_info *ci) 2474 { 2475 uint32_t regs[4]; 2476 char buf[256]; 2477 2478 x86_cpuid(0x80000007, regs); 2479 2480 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2481 aprint_normal_dev(ci->ci_dev, "Power Management features: %s\n", buf); 2482 } 2483 2484 bool 2485 identifycpu_bind(void) 2486 { 2487 2488 return true; 2489 } 2490 2491 int 2492 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2493 { 2494 struct cpu_info ci; 2495 int loader_version, res; 2496 struct cpu_ucode_version versreq; 2497 2498 cpu_probe_base_features(&ci, "unknown"); 2499 2500 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2501 loader_version = CPU_UCODE_LOADER_AMD; 2502 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2503 loader_version = CPU_UCODE_LOADER_INTEL1; 2504 else 2505 return -1; 2506 2507 /* check whether the kernel understands this loader version */ 2508 versreq.loader_version = loader_version; 2509 versreq.data = 0; 2510 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2511 if (res) 2512 return -1; 2513 2514 switch (loader_version) { 2515 case CPU_UCODE_LOADER_AMD: 2516 if (uc->cpu_nr != -1) { 2517 /* printf? */ 2518 return -1; 2519 } 2520 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2521 break; 2522 case CPU_UCODE_LOADER_INTEL1: 2523 if (uc->cpu_nr == -1) 2524 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2525 else 2526 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2527 break; 2528 default: /* can't happen */ 2529 return -1; 2530 } 2531 uc->loader_version = loader_version; 2532 return 0; 2533 } 2534
Indexes created Fri Sep 26 20:09:58 GMT 2025