i386.c revision 1.13.2.5
1 /* $NetBSD: i386.c,v 1.13.2.5 2012/03/17 18:41:15 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.13.2.5 2012/03/17 18:41:15 bouyer Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 68 #include <string.h> 69 #include <stdio.h> 70 #include <stdlib.h> 71 #include <err.h> 72 #include <assert.h> 73 #include <math.h> 74 #include <util.h> 75 76 #include <machine/specialreg.h> 77 #include <machine/cpu.h> 78 79 #include <x86/cpuvar.h> 80 #include <x86/cputypes.h> 81 #include <x86/cacheinfo.h> 82 83 #include "../cpuctl.h" 84 85 /* Size of buffer for printing humanized numbers */ 86 #define HUMAN_BUFSIZE sizeof("999KB") 87 88 #define x86_cpuid(a,b) x86_cpuid2((a),0,(b)) 89 90 void x86_cpuid2(uint32_t, uint32_t, uint32_t *); 91 void x86_identify(void); 92 93 struct cpu_info { 94 const char *ci_dev; 95 int32_t ci_cpuid_level; 96 uint32_t ci_signature; /* X86 cpuid type */ 97 uint32_t ci_feature_flags;/* X86 %edx CPUID feature bits */ 98 uint32_t ci_feature2_flags;/* X86 %ecx CPUID feature bits */ 99 uint32_t ci_feature3_flags;/* X86 extended %edx feature bits */ 100 uint32_t ci_feature4_flags;/* X86 extended %ecx feature bits */ 101 uint32_t ci_padlock_flags;/* VIA PadLock feature bits */ 102 uint32_t ci_cpu_class; /* CPU class */ 103 uint32_t ci_brand_id; /* Intel brand id */ 104 uint32_t ci_vendor[4]; /* vendor string */ 105 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 106 uint64_t ci_tsc_freq; /* cpu cycles/second */ 107 uint8_t ci_packageid; 108 uint8_t ci_coreid; 109 uint8_t ci_smtid; 110 uint32_t ci_initapicid; 111 struct x86_cache_info ci_cinfo[CAI_COUNT]; 112 void (*ci_info)(struct cpu_info *); 113 }; 114 115 struct cpu_nocpuid_nameclass { 116 int cpu_vendor; 117 const char *cpu_vendorname; 118 const char *cpu_name; 119 int cpu_class; 120 void (*cpu_setup)(struct cpu_info *); 121 void (*cpu_cacheinfo)(struct cpu_info *); 122 void (*cpu_info)(struct cpu_info *); 123 }; 124 125 struct cpu_extend_nameclass { 126 int ext_model; 127 const char *cpu_models[CPU_MAXMODEL+1]; 128 }; 129 130 struct cpu_cpuid_nameclass { 131 const char *cpu_id; 132 int cpu_vendor; 133 const char *cpu_vendorname; 134 struct cpu_cpuid_family { 135 int cpu_class; 136 const char *cpu_models[CPU_MAXMODEL+2]; 137 void (*cpu_setup)(struct cpu_info *); 138 void (*cpu_probe)(struct cpu_info *); 139 void (*cpu_info)(struct cpu_info *); 140 struct cpu_extend_nameclass *cpu_extended_names; 141 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 142 }; 143 144 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 145 146 /* 147 * Map Brand ID from cpuid instruction to brand name. 148 * Source: Intel Processor Identification and the CPUID Instruction, AP-485 149 */ 150 static const char * const i386_intel_brand[] = { 151 "", /* Unsupported */ 152 "Celeron", /* Intel (R) Celeron (TM) processor */ 153 "Pentium III", /* Intel (R) Pentium (R) III processor */ 154 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 155 "Pentium III", /* Intel (R) Pentium (R) III processor */ 156 "", /* Reserved */ 157 "Mobile Pentium III", /* Mobile Intel (R) Pentium (R) III processor-M */ 158 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 159 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 160 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 161 "Celeron", /* Intel (R) Celeron (TM) processor */ 162 "Xeon", /* Intel (R) Xeon (TM) processor */ 163 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 164 "", /* Reserved */ 165 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 166 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 167 }; 168 169 /* 170 * AMD processors don't have Brand IDs, so we need these names for probe. 171 */ 172 static const char * const amd_brand[] = { 173 "", 174 "Duron", /* AMD Duron(tm) */ 175 "MP", /* AMD Athlon(tm) MP */ 176 "XP", /* AMD Athlon(tm) XP */ 177 "4" /* AMD Athlon(tm) 4 */ 178 }; 179 180 static int cpu_vendor; 181 static char cpu_brand_string[49]; 182 static char amd_brand_name[48]; 183 184 static void via_cpu_probe(struct cpu_info *); 185 static void amd_family6_probe(struct cpu_info *); 186 static void intel_family_new_probe(struct cpu_info *); 187 static const char *intel_family6_name(struct cpu_info *); 188 static const char *amd_amd64_name(struct cpu_info *); 189 static void amd_family5_setup(struct cpu_info *); 190 static void transmeta_cpu_info(struct cpu_info *); 191 static const char *print_cache_config(struct cpu_info *, int, const char *, 192 const char *); 193 static const char *print_tlb_config(struct cpu_info *, int, const char *, 194 const char *); 195 static void amd_cpu_cacheinfo(struct cpu_info *); 196 static void via_cpu_cacheinfo(struct cpu_info *); 197 static void x86_print_cacheinfo(struct cpu_info *); 198 static const struct x86_cache_info *cache_info_lookup( 199 const struct x86_cache_info *, uint8_t); 200 static void cyrix6x86_cpu_setup(struct cpu_info *); 201 static void winchip_cpu_setup(struct cpu_info *); 202 static void amd_family5_setup(struct cpu_info *); 203 static void powernow_probe(struct cpu_info *); 204 205 /* 206 * Info for CTL_HW 207 */ 208 static char cpu_model[120]; 209 210 /* 211 * Note: these are just the ones that may not have a cpuid instruction. 212 * We deal with the rest in a different way. 213 */ 214 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 215 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 216 NULL, NULL, NULL }, /* CPU_386SX */ 217 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 218 NULL, NULL, NULL }, /* CPU_386 */ 219 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 220 NULL, NULL, NULL }, /* CPU_486SX */ 221 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 222 NULL, NULL, NULL }, /* CPU_486 */ 223 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 224 NULL, NULL, NULL }, /* CPU_486DLC */ 225 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 226 NULL, NULL, NULL }, /* CPU_6x86 */ 227 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 228 NULL, NULL, NULL }, /* CPU_NX586 */ 229 }; 230 231 const char *classnames[] = { 232 "386", 233 "486", 234 "586", 235 "686" 236 }; 237 238 const char *modifiers[] = { 239 "", 240 "OverDrive", 241 "Dual", 242 "" 243 }; 244 245 struct cpu_extend_nameclass intel_family6_ext_models[] = { 246 { /* Extended models 1x */ 247 0x01, { NULL, NULL, 248 NULL, NULL, 249 NULL, "EP80579 Integrated Processor", 250 "Celeron (45nm)", "Core 2 Extreme", 251 NULL, NULL, 252 "Core i7 (Nehalem)", NULL, 253 "Atom", "XeonMP (Nehalem)", 254 NULL, NULL} }, 255 { /* End of list */ 256 0x00, { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 257 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL} } 258 }; 259 260 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 261 { 262 "GenuineIntel", 263 CPUVENDOR_INTEL, 264 "Intel", 265 /* Family 4 */ 266 { { 267 CPUCLASS_486, 268 { 269 "486DX", "486DX", "486SX", "486DX2", "486SL", 270 "486SX2", 0, "486DX2 W/B Enhanced", 271 "486DX4", 0, 0, 0, 0, 0, 0, 0, 272 "486" /* Default */ 273 }, 274 NULL, 275 NULL, 276 NULL, 277 NULL, 278 }, 279 /* Family 5 */ 280 { 281 CPUCLASS_586, 282 { 283 "Pentium (P5 A-step)", "Pentium (P5)", 284 "Pentium (P54C)", "Pentium (P24T)", 285 "Pentium/MMX", "Pentium", 0, 286 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 287 0, 0, 0, 0, 0, 0, 0, 288 "Pentium" /* Default */ 289 }, 290 NULL, 291 NULL, 292 NULL, 293 NULL, 294 }, 295 /* Family 6 */ 296 { 297 CPUCLASS_686, 298 { 299 "Pentium Pro (A-step)", "Pentium Pro", 0, 300 "Pentium II (Klamath)", "Pentium Pro", 301 "Pentium II/Celeron (Deschutes)", 302 "Celeron (Mendocino)", 303 "Pentium III (Katmai)", 304 "Pentium III (Coppermine)", 305 "Pentium M (Banias)", 306 "Pentium III Xeon (Cascades)", 307 "Pentium III (Tualatin)", 0, 308 "Pentium M (Dothan)", 309 "Pentium M (Yonah)", 310 "Core 2 (Merom)", 311 "Pentium Pro, II or III" /* Default */ 312 }, 313 NULL, 314 intel_family_new_probe, 315 NULL, 316 &intel_family6_ext_models[0], 317 }, 318 /* Family > 6 */ 319 { 320 CPUCLASS_686, 321 { 322 0, 0, 0, 0, 0, 0, 0, 0, 323 0, 0, 0, 0, 0, 0, 0, 0, 324 "Pentium 4" /* Default */ 325 }, 326 NULL, 327 intel_family_new_probe, 328 NULL, 329 NULL, 330 } } 331 }, 332 { 333 "AuthenticAMD", 334 CPUVENDOR_AMD, 335 "AMD", 336 /* Family 4 */ 337 { { 338 CPUCLASS_486, 339 { 340 0, 0, 0, "Am486DX2 W/T", 341 0, 0, 0, "Am486DX2 W/B", 342 "Am486DX4 W/T or Am5x86 W/T 150", 343 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 344 0, 0, "Am5x86 W/T 133/160", 345 "Am5x86 W/B 133/160", 346 "Am486 or Am5x86" /* Default */ 347 }, 348 NULL, 349 NULL, 350 NULL, 351 NULL, 352 }, 353 /* Family 5 */ 354 { 355 CPUCLASS_586, 356 { 357 "K5", "K5", "K5", "K5", 0, 0, "K6", 358 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 359 "K6-2+/III+", 0, 0, 360 "K5 or K6" /* Default */ 361 }, 362 amd_family5_setup, 363 NULL, 364 amd_cpu_cacheinfo, 365 NULL, 366 }, 367 /* Family 6 */ 368 { 369 CPUCLASS_686, 370 { 371 0, "Athlon Model 1", "Athlon Model 2", 372 "Duron", "Athlon Model 4 (Thunderbird)", 373 0, "Athlon", "Duron", "Athlon", 0, 374 "Athlon", 0, 0, 0, 0, 0, 375 "K7 (Athlon)" /* Default */ 376 }, 377 NULL, 378 amd_family6_probe, 379 amd_cpu_cacheinfo, 380 NULL, 381 }, 382 /* Family > 6 */ 383 { 384 CPUCLASS_686, 385 { 386 0, 0, 0, 0, 0, 0, 0, 0, 387 0, 0, 0, 0, 0, 0, 0, 0, 388 "Unknown K8 (Athlon)" /* Default */ 389 }, 390 NULL, 391 amd_family6_probe, 392 amd_cpu_cacheinfo, 393 NULL, 394 } } 395 }, 396 { 397 "CyrixInstead", 398 CPUVENDOR_CYRIX, 399 "Cyrix", 400 /* Family 4 */ 401 { { 402 CPUCLASS_486, 403 { 404 0, 0, 0, 405 "MediaGX", 406 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 407 "486" /* Default */ 408 }, 409 cyrix6x86_cpu_setup, /* XXX ?? */ 410 NULL, 411 NULL, 412 NULL, 413 }, 414 /* Family 5 */ 415 { 416 CPUCLASS_586, 417 { 418 0, 0, "6x86", 0, 419 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 420 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 421 "6x86" /* Default */ 422 }, 423 cyrix6x86_cpu_setup, 424 NULL, 425 NULL, 426 NULL, 427 }, 428 /* Family 6 */ 429 { 430 CPUCLASS_686, 431 { 432 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 433 0, 0, 0, 0, 0, 0, 0, 0, 434 "6x86MX" /* Default */ 435 }, 436 cyrix6x86_cpu_setup, 437 NULL, 438 NULL, 439 NULL, 440 }, 441 /* Family > 6 */ 442 { 443 CPUCLASS_686, 444 { 445 0, 0, 0, 0, 0, 0, 0, 0, 446 0, 0, 0, 0, 0, 0, 0, 0, 447 "Unknown 6x86MX" /* Default */ 448 }, 449 NULL, 450 NULL, 451 NULL, 452 NULL, 453 } } 454 }, 455 { /* MediaGX is now owned by National Semiconductor */ 456 "Geode by NSC", 457 CPUVENDOR_CYRIX, /* XXX */ 458 "National Semiconductor", 459 /* Family 4, NSC never had any of these */ 460 { { 461 CPUCLASS_486, 462 { 463 0, 0, 0, 0, 0, 0, 0, 0, 464 0, 0, 0, 0, 0, 0, 0, 0, 465 "486 compatible" /* Default */ 466 }, 467 NULL, 468 NULL, 469 NULL, 470 NULL, 471 }, 472 /* Family 5: Geode family, formerly MediaGX */ 473 { 474 CPUCLASS_586, 475 { 476 0, 0, 0, 0, 477 "Geode GX1", 478 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 479 "Geode" /* Default */ 480 }, 481 cyrix6x86_cpu_setup, 482 NULL, 483 amd_cpu_cacheinfo, 484 NULL, 485 }, 486 /* Family 6, not yet available from NSC */ 487 { 488 CPUCLASS_686, 489 { 490 0, 0, 0, 0, 0, 0, 0, 0, 491 0, 0, 0, 0, 0, 0, 0, 0, 492 "Pentium Pro compatible" /* Default */ 493 }, 494 NULL, 495 NULL, 496 NULL, 497 NULL, 498 }, 499 /* Family > 6, not yet available from NSC */ 500 { 501 CPUCLASS_686, 502 { 503 0, 0, 0, 0, 0, 0, 0, 0, 504 0, 0, 0, 0, 0, 0, 0, 0, 505 "Pentium Pro compatible" /* Default */ 506 }, 507 NULL, 508 NULL, 509 NULL, 510 NULL, 511 } } 512 }, 513 { 514 "CentaurHauls", 515 CPUVENDOR_IDT, 516 "IDT", 517 /* Family 4, IDT never had any of these */ 518 { { 519 CPUCLASS_486, 520 { 521 0, 0, 0, 0, 0, 0, 0, 0, 522 0, 0, 0, 0, 0, 0, 0, 0, 523 "486 compatible" /* Default */ 524 }, 525 NULL, 526 NULL, 527 NULL, 528 NULL, 529 }, 530 /* Family 5 */ 531 { 532 CPUCLASS_586, 533 { 534 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 535 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 536 "WinChip" /* Default */ 537 }, 538 winchip_cpu_setup, 539 NULL, 540 NULL, 541 NULL, 542 }, 543 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 544 { 545 CPUCLASS_686, 546 { 547 0, 0, 0, 0, 0, 0, "C3 Samuel", 548 "C3 Samuel 2/Ezra", "C3 Ezra-T", 549 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 550 0, "VIA Nano", 551 "Unknown VIA/IDT" /* Default */ 552 }, 553 NULL, 554 via_cpu_probe, 555 via_cpu_cacheinfo, 556 NULL, 557 }, 558 /* Family > 6, not yet available from VIA */ 559 { 560 CPUCLASS_686, 561 { 562 0, 0, 0, 0, 0, 0, 0, 0, 563 0, 0, 0, 0, 0, 0, 0, 0, 564 "Pentium Pro compatible" /* Default */ 565 }, 566 NULL, 567 NULL, 568 NULL, 569 NULL, 570 } } 571 }, 572 { 573 "GenuineTMx86", 574 CPUVENDOR_TRANSMETA, 575 "Transmeta", 576 /* Family 4, Transmeta never had any of these */ 577 { { 578 CPUCLASS_486, 579 { 580 0, 0, 0, 0, 0, 0, 0, 0, 581 0, 0, 0, 0, 0, 0, 0, 0, 582 "486 compatible" /* Default */ 583 }, 584 NULL, 585 NULL, 586 NULL, 587 NULL, 588 }, 589 /* Family 5 */ 590 { 591 CPUCLASS_586, 592 { 593 0, 0, 0, 0, 0, 0, 0, 0, 594 0, 0, 0, 0, 0, 0, 0, 0, 595 "Crusoe" /* Default */ 596 }, 597 NULL, 598 NULL, 599 transmeta_cpu_info, 600 NULL, 601 }, 602 /* Family 6, not yet available from Transmeta */ 603 { 604 CPUCLASS_686, 605 { 606 0, 0, 0, 0, 0, 0, 0, 0, 607 0, 0, 0, 0, 0, 0, 0, 0, 608 "Pentium Pro compatible" /* Default */ 609 }, 610 NULL, 611 NULL, 612 NULL, 613 NULL, 614 }, 615 /* Family > 6, not yet available from Transmeta */ 616 { 617 CPUCLASS_686, 618 { 619 0, 0, 0, 0, 0, 0, 0, 0, 620 0, 0, 0, 0, 0, 0, 0, 0, 621 "Pentium Pro compatible" /* Default */ 622 }, 623 NULL, 624 NULL, 625 NULL, 626 NULL, 627 } } 628 } 629 }; 630 631 /* 632 * disable the TSC such that we don't use the TSC in microtime(9) 633 * because some CPUs got the implementation wrong. 634 */ 635 static void 636 disable_tsc(struct cpu_info *ci) 637 { 638 if (ci->ci_feature_flags & CPUID_TSC) { 639 ci->ci_feature_flags &= ~CPUID_TSC; 640 aprint_error("WARNING: broken TSC disabled\n"); 641 } 642 } 643 644 static void 645 cyrix6x86_cpu_setup(struct cpu_info *ci) 646 { 647 648 /* 649 * Do not disable the TSC on the Geode GX, it's reported to 650 * work fine. 651 */ 652 if (ci->ci_signature != 0x552) 653 disable_tsc(ci); 654 } 655 656 void 657 winchip_cpu_setup(struct cpu_info *ci) 658 { 659 switch (CPUID2MODEL(ci->ci_signature)) { /* model */ 660 case 4: /* WinChip C6 */ 661 disable_tsc(ci); 662 } 663 } 664 665 666 static void 667 identifycpu_cpuids(struct cpu_info *ci) 668 { 669 const char *cpuname = ci->ci_dev; 670 u_int lp_max = 1; /* logical processors per package */ 671 u_int smt_max; /* smt per core */ 672 u_int core_max = 1; /* core per package */ 673 int smt_bits, core_bits; 674 uint32_t descs[4]; 675 676 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 677 ci->ci_packageid = ci->ci_initapicid; 678 ci->ci_coreid = 0; 679 ci->ci_smtid = 0; 680 if (cpu_vendor != CPUVENDOR_INTEL) { 681 return; 682 } 683 684 /* 685 * 253668.pdf 7.10.2 686 */ 687 688 if ((ci->ci_feature_flags & CPUID_HTT) != 0) { 689 x86_cpuid(1, descs); 690 lp_max = (descs[1] >> 16) & 0xff; 691 } 692 x86_cpuid(0, descs); 693 if (descs[0] >= 4) { 694 x86_cpuid2(4, 0, descs); 695 core_max = (descs[0] >> 26) + 1; 696 } 697 assert(lp_max >= core_max); 698 smt_max = lp_max / core_max; 699 smt_bits = ilog2(smt_max - 1) + 1; 700 core_bits = ilog2(core_max - 1) + 1; 701 if (smt_bits + core_bits) { 702 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 703 } 704 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 705 ci->ci_packageid); 706 if (core_bits) { 707 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 708 709 ci->ci_coreid = 710 __SHIFTOUT(ci->ci_initapicid, core_mask); 711 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 712 } 713 if (smt_bits) { 714 u_int smt_mask = __BITS(0, smt_bits - 1); 715 716 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, smt_mask); 717 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 718 } 719 } 720 721 static void 722 via_cpu_probe(struct cpu_info *ci) 723 { 724 u_int model = CPUID2MODEL(ci->ci_signature); 725 u_int stepping = CPUID2STEPPING(ci->ci_signature); 726 u_int descs[4]; 727 u_int lfunc; 728 729 /* 730 * Determine the largest extended function value. 731 */ 732 x86_cpuid(0x80000000, descs); 733 lfunc = descs[0]; 734 735 /* 736 * Determine the extended feature flags. 737 */ 738 if (lfunc >= 0x80000001) { 739 x86_cpuid(0x80000001, descs); 740 ci->ci_feature3_flags |= descs[3]; 741 } 742 743 if (model < 0x9) 744 return; 745 746 /* Nehemiah or Esther */ 747 x86_cpuid(0xc0000000, descs); 748 lfunc = descs[0]; 749 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 750 return; 751 752 x86_cpuid(0xc0000001, descs); 753 lfunc = descs[3]; 754 if (model > 0x9 || stepping >= 8) { /* ACE */ 755 if (lfunc & CPUID_VIA_HAS_ACE) { 756 ci->ci_padlock_flags = lfunc; 757 } 758 } 759 } 760 761 static const char * 762 intel_family6_name(struct cpu_info *ci) 763 { 764 int model = CPUID2MODEL(ci->ci_signature); 765 const char *ret = NULL; 766 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 767 768 if (model == 5) { 769 switch (l2cache) { 770 case 0: 771 case 128 * 1024: 772 ret = "Celeron (Covington)"; 773 break; 774 case 256 * 1024: 775 ret = "Mobile Pentium II (Dixon)"; 776 break; 777 case 512 * 1024: 778 ret = "Pentium II"; 779 break; 780 case 1 * 1024 * 1024: 781 case 2 * 1024 * 1024: 782 ret = "Pentium II Xeon"; 783 break; 784 } 785 } else if (model == 6) { 786 switch (l2cache) { 787 case 256 * 1024: 788 case 512 * 1024: 789 ret = "Mobile Pentium II"; 790 break; 791 } 792 } else if (model == 7) { 793 switch (l2cache) { 794 case 512 * 1024: 795 ret = "Pentium III"; 796 break; 797 case 1 * 1024 * 1024: 798 case 2 * 1024 * 1024: 799 ret = "Pentium III Xeon"; 800 break; 801 } 802 } else if (model >= 8) { 803 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 804 switch (ci->ci_brand_id) { 805 case 0x3: 806 if (ci->ci_signature == 0x6B1) 807 ret = "Celeron"; 808 break; 809 case 0x8: 810 if (ci->ci_signature >= 0xF13) 811 ret = "genuine processor"; 812 break; 813 case 0xB: 814 if (ci->ci_signature >= 0xF13) 815 ret = "Xeon MP"; 816 break; 817 case 0xE: 818 if (ci->ci_signature < 0xF13) 819 ret = "Xeon"; 820 break; 821 } 822 if (ret == NULL) 823 ret = i386_intel_brand[ci->ci_brand_id]; 824 } 825 } 826 827 return ret; 828 } 829 830 /* 831 * Identify AMD64 CPU names from cpuid. 832 * 833 * Based on: 834 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 835 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 836 * "Revision Guide for AMD NPT Family 0Fh Processors" 837 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 838 * and other miscellaneous reports. 839 */ 840 static const char * 841 amd_amd64_name(struct cpu_info *ci) 842 { 843 int extfamily, extmodel, model; 844 const char *ret = NULL; 845 846 model = CPUID2MODEL(ci->ci_signature); 847 extfamily = CPUID2EXTFAMILY(ci->ci_signature); 848 extmodel = CPUID2EXTMODEL(ci->ci_signature); 849 850 switch (extfamily) { 851 case 0x00: 852 switch (model) { 853 case 0x1: 854 switch (extmodel) { 855 case 0x2: /* rev JH-E1/E6 */ 856 case 0x4: /* rev JH-F2 */ 857 ret = "Dual-Core Opteron"; 858 break; 859 } 860 break; 861 case 0x3: 862 switch (extmodel) { 863 case 0x2: /* rev JH-E6 (Toledo) */ 864 ret = "Dual-Core Opteron or Athlon 64 X2"; 865 break; 866 case 0x4: /* rev JH-F2 (Windsor) */ 867 ret = "Athlon 64 FX or Athlon 64 X2"; 868 break; 869 } 870 break; 871 case 0x4: 872 switch (extmodel) { 873 case 0x0: /* rev SH-B0/C0/CG (ClawHammer) */ 874 case 0x1: /* rev SH-D0 */ 875 ret = "Athlon 64"; 876 break; 877 case 0x2: /* rev SH-E5 (Lancaster?) */ 878 ret = "Mobile Athlon 64 or Turion 64"; 879 break; 880 } 881 break; 882 case 0x5: 883 switch (extmodel) { 884 case 0x0: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 885 ret = "Opteron or Athlon 64 FX"; 886 break; 887 case 0x1: /* rev SH-D0 */ 888 case 0x2: /* rev SH-E4 */ 889 ret = "Opteron"; 890 break; 891 } 892 break; 893 case 0x7: 894 switch (extmodel) { 895 case 0x0: /* rev SH-CG (ClawHammer) */ 896 case 0x1: /* rev SH-D0 */ 897 ret = "Athlon 64"; 898 break; 899 case 0x2: /* rev DH-E4, SH-E4 */ 900 ret = "Athlon 64 or Athlon 64 FX or Opteron"; 901 break; 902 } 903 break; 904 case 0x8: 905 switch (extmodel) { 906 case 0x0: /* rev CH-CG */ 907 case 0x1: /* rev CH-D0 */ 908 ret = "Athlon 64 or Sempron"; 909 break; 910 case 0x4: /* rev BH-F2 */ 911 ret = "Turion 64 X2"; 912 break; 913 } 914 break; 915 case 0xb: 916 switch (extmodel) { 917 case 0x0: /* rev CH-CG */ 918 case 0x1: /* rev CH-D0 */ 919 ret = "Athlon 64"; 920 break; 921 case 0x2: /* rev BH-E4 (Manchester) */ 922 case 0x4: /* rev BH-F2 (Windsor) */ 923 ret = "Athlon 64 X2"; 924 break; 925 case 0x6: /* rev BH-G1 (Brisbane) */ 926 ret = "Athlon X2 or Athlon 64 X2"; 927 break; 928 } 929 break; 930 case 0xc: 931 switch (extmodel) { 932 case 0x0: /* rev DH-CG (Newcastle) */ 933 case 0x1: /* rev DH-D0 (Winchester) */ 934 case 0x2: /* rev DH-E3/E6 */ 935 ret = "Athlon 64 or Sempron"; 936 break; 937 } 938 break; 939 case 0xe: 940 switch (extmodel) { 941 case 0x0: /* rev DH-CG (Newcastle?) */ 942 ret = "Athlon 64 or Sempron"; 943 break; 944 } 945 break; 946 case 0xf: 947 switch (extmodel) { 948 case 0x0: /* rev DH-CG (Newcastle/Paris) */ 949 case 0x1: /* rev DH-D0 (Winchester/Victoria) */ 950 case 0x2: /* rev DH-E3/E6 (Venice/Palermo) */ 951 case 0x4: /* rev DH-F2 (Orleans/Manila) */ 952 case 0x5: /* rev DH-F2 (Orleans/Manila) */ 953 case 0x6: /* rev DH-G1 */ 954 ret = "Athlon 64 or Sempron"; 955 break; 956 } 957 break; 958 default: 959 ret = "Unknown AMD64 CPU"; 960 } 961 break; 962 case 0x01: 963 switch (model) { 964 case 0x02: 965 ret = "Family 10h"; 966 break; 967 default: 968 ret = "Unknown AMD64 CPU"; 969 break; 970 } 971 break; 972 } 973 974 return ret; 975 } 976 977 static void 978 cpu_probe_base_features(struct cpu_info *ci) 979 { 980 const struct x86_cache_info *cai; 981 u_int descs[4]; 982 int iterations, i, j; 983 uint8_t desc; 984 uint32_t miscbytes; 985 uint32_t brand[12]; 986 987 if (ci->ci_cpuid_level < 0) 988 return; 989 990 x86_cpuid(0, descs); 991 ci->ci_cpuid_level = descs[0]; 992 ci->ci_vendor[0] = descs[1]; 993 ci->ci_vendor[2] = descs[2]; 994 ci->ci_vendor[1] = descs[3]; 995 ci->ci_vendor[3] = 0; 996 997 x86_cpuid(0x80000000, brand); 998 if (brand[0] >= 0x80000004) { 999 x86_cpuid(0x80000002, brand); 1000 x86_cpuid(0x80000003, brand + 4); 1001 x86_cpuid(0x80000004, brand + 8); 1002 for (i = 0; i < 48; i++) 1003 if (((char *) brand)[i] != ' ') 1004 break; 1005 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1006 } 1007 1008 if (ci->ci_cpuid_level < 1) 1009 return; 1010 1011 x86_cpuid(1, descs); 1012 ci->ci_signature = descs[0]; 1013 miscbytes = descs[1]; 1014 ci->ci_feature2_flags = descs[2]; 1015 ci->ci_feature_flags = descs[3]; 1016 1017 /* Brand is low order 8 bits of ebx */ 1018 ci->ci_brand_id = miscbytes & 0xff; 1019 ci->ci_initapicid = (miscbytes >> 24) & 0xff; 1020 if (ci->ci_cpuid_level < 2) 1021 return; 1022 1023 /* 1024 * Parse the cache info from `cpuid', if we have it. 1025 * XXX This is kinda ugly, but hey, so is the architecture... 1026 */ 1027 1028 x86_cpuid(2, descs); 1029 1030 iterations = descs[0] & 0xff; 1031 while (iterations-- > 0) { 1032 for (i = 0; i < 4; i++) { 1033 if (descs[i] & 0x80000000) 1034 continue; 1035 for (j = 0; j < 4; j++) { 1036 if (i == 0 && j == 0) 1037 continue; 1038 desc = (descs[i] >> (j * 8)) & 0xff; 1039 if (desc == 0) 1040 continue; 1041 cai = cache_info_lookup(intel_cpuid_cache_info, 1042 desc); 1043 if (cai != NULL) 1044 ci->ci_cinfo[cai->cai_index] = *cai; 1045 } 1046 } 1047 x86_cpuid(2, descs); 1048 } 1049 1050 if (ci->ci_cpuid_level < 3) 1051 return; 1052 1053 /* 1054 * If the processor serial number misfeature is present and supported, 1055 * extract it here. 1056 */ 1057 if ((ci->ci_feature_flags & CPUID_PN) != 0) { 1058 ci->ci_cpu_serial[0] = ci->ci_signature; 1059 x86_cpuid(3, descs); 1060 ci->ci_cpu_serial[2] = descs[2]; 1061 ci->ci_cpu_serial[1] = descs[3]; 1062 } 1063 } 1064 1065 static void 1066 cpu_probe_features(struct cpu_info *ci) 1067 { 1068 const struct cpu_cpuid_nameclass *cpup = NULL; 1069 int i, xmax, family; 1070 1071 cpu_probe_base_features(ci); 1072 1073 if (ci->ci_cpuid_level < 1) 1074 return; 1075 1076 xmax = __arraycount(i386_cpuid_cpus); 1077 for (i = 0; i < xmax; i++) { 1078 if (!strncmp((char *)ci->ci_vendor, 1079 i386_cpuid_cpus[i].cpu_id, 12)) { 1080 cpup = &i386_cpuid_cpus[i]; 1081 break; 1082 } 1083 } 1084 1085 if (cpup == NULL) 1086 return; 1087 1088 family = (ci->ci_signature >> 8) & 0xf; 1089 1090 if (family > CPU_MAXFAMILY) { 1091 family = CPU_MAXFAMILY; 1092 } 1093 i = family - CPU_MINFAMILY; 1094 1095 if (cpup->cpu_family[i].cpu_probe == NULL) 1096 return; 1097 1098 (*cpup->cpu_family[i].cpu_probe)(ci); 1099 } 1100 1101 static void 1102 intel_family_new_probe(struct cpu_info *ci) 1103 { 1104 uint32_t descs[4]; 1105 1106 x86_cpuid(0x80000000, descs); 1107 1108 /* 1109 * Determine extended feature flags. 1110 */ 1111 if (descs[0] >= 0x80000001) { 1112 x86_cpuid(0x80000001, descs); 1113 ci->ci_feature3_flags |= descs[3]; 1114 } 1115 } 1116 1117 static void 1118 amd_family6_probe(struct cpu_info *ci) 1119 { 1120 uint32_t descs[4]; 1121 char *p; 1122 int i; 1123 1124 x86_cpuid(0x80000000, descs); 1125 1126 /* 1127 * Determine the extended feature flags. 1128 */ 1129 if (descs[0] >= 0x80000001) { 1130 x86_cpuid(0x80000001, descs); 1131 ci->ci_feature3_flags |= descs[3]; /* %edx */ 1132 ci->ci_feature4_flags = descs[2]; /* %ecx */ 1133 } 1134 1135 if (*cpu_brand_string == '\0') 1136 return; 1137 1138 for (i = 1; i < __arraycount(amd_brand); i++) 1139 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 1140 ci->ci_brand_id = i; 1141 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 1142 break; 1143 } 1144 } 1145 1146 static void 1147 amd_family5_setup(struct cpu_info *ci) 1148 { 1149 1150 switch (CPUID2MODEL(ci->ci_signature)) { 1151 case 0: /* AMD-K5 Model 0 */ 1152 /* 1153 * According to the AMD Processor Recognition App Note, 1154 * the AMD-K5 Model 0 uses the wrong bit to indicate 1155 * support for global PTEs, instead using bit 9 (APIC) 1156 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 1157 */ 1158 if (ci->ci_feature_flags & CPUID_APIC) 1159 ci->ci_feature_flags = (ci->ci_feature_flags & ~CPUID_APIC) | CPUID_PGE; 1160 /* 1161 * XXX But pmap_pg_g is already initialized -- need to kick 1162 * XXX the pmap somehow. How does the MP branch do this? 1163 */ 1164 break; 1165 } 1166 } 1167 1168 static void 1169 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1170 { 1171 u_int descs[4]; 1172 1173 x86_cpuid(0x80860007, descs); 1174 *frequency = descs[0]; 1175 *voltage = descs[1]; 1176 *percentage = descs[2]; 1177 } 1178 1179 static void 1180 transmeta_cpu_info(struct cpu_info *ci) 1181 { 1182 u_int descs[4], nreg; 1183 u_int frequency, voltage, percentage; 1184 1185 x86_cpuid(0x80860000, descs); 1186 nreg = descs[0]; 1187 if (nreg >= 0x80860001) { 1188 x86_cpuid(0x80860001, descs); 1189 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1190 (descs[1] >> 24) & 0xff, 1191 (descs[1] >> 16) & 0xff, 1192 (descs[1] >> 8) & 0xff, 1193 descs[1] & 0xff); 1194 } 1195 if (nreg >= 0x80860002) { 1196 x86_cpuid(0x80860002, descs); 1197 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1198 (descs[1] >> 24) & 0xff, 1199 (descs[1] >> 16) & 0xff, 1200 (descs[1] >> 8) & 0xff, 1201 descs[1] & 0xff, 1202 descs[2]); 1203 } 1204 if (nreg >= 0x80860006) { 1205 union { 1206 char text[65]; 1207 u_int descs[4][4]; 1208 } info; 1209 int i; 1210 1211 for (i=0; i<4; i++) { 1212 x86_cpuid(0x80860003 + i, info.descs[i]); 1213 } 1214 info.text[64] = '\0'; 1215 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1216 } 1217 1218 if (nreg >= 0x80860007) { 1219 tmx86_get_longrun_status(&frequency, 1220 &voltage, &percentage); 1221 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1222 frequency, voltage, percentage); 1223 } 1224 } 1225 1226 void 1227 identifycpu(const char *cpuname) 1228 { 1229 const char *name = "", *modifier, *vendorname, *brand = ""; 1230 int class = CPUCLASS_386, i, xmax; 1231 int modif, family, model, ext_model; 1232 const struct cpu_extend_nameclass *modlist; 1233 const struct cpu_cpuid_nameclass *cpup = NULL; 1234 const struct cpu_cpuid_family *cpufam; 1235 const char *feature_str[5]; 1236 struct cpu_info *ci, cistore; 1237 extern int cpu; 1238 extern int cpu_info_level; 1239 size_t sz; 1240 char buf[256]; 1241 1242 ci = &cistore; 1243 memset(ci, 0, sizeof(*ci)); 1244 ci->ci_dev = cpuname; 1245 1246 x86_identify(); 1247 ci->ci_cpuid_level = cpu_info_level; 1248 cpu_probe_features(ci); 1249 1250 if (ci->ci_cpuid_level == -1) { 1251 if (cpu < 0 || cpu >= __arraycount(i386_nocpuid_cpus)) 1252 errx(1, "unknown cpu type %d", cpu); 1253 name = i386_nocpuid_cpus[cpu].cpu_name; 1254 cpu_vendor = i386_nocpuid_cpus[cpu].cpu_vendor; 1255 vendorname = i386_nocpuid_cpus[cpu].cpu_vendorname; 1256 class = i386_nocpuid_cpus[cpu].cpu_class; 1257 ci->ci_info = i386_nocpuid_cpus[cpu].cpu_info; 1258 modifier = ""; 1259 } else { 1260 xmax = __arraycount(i386_cpuid_cpus); 1261 modif = (ci->ci_signature >> 12) & 0x3; 1262 family = CPUID2FAMILY(ci->ci_signature); 1263 if (family < CPU_MINFAMILY) 1264 errx(1, "identifycpu: strange family value"); 1265 model = CPUID2MODEL(ci->ci_signature); 1266 ext_model = CPUID2EXTMODEL(ci->ci_signature); 1267 1268 for (i = 0; i < xmax; i++) { 1269 if (!strncmp((char *)ci->ci_vendor, 1270 i386_cpuid_cpus[i].cpu_id, 12)) { 1271 cpup = &i386_cpuid_cpus[i]; 1272 break; 1273 } 1274 } 1275 1276 if (cpup == NULL) { 1277 cpu_vendor = CPUVENDOR_UNKNOWN; 1278 if (ci->ci_vendor[0] != '\0') 1279 vendorname = (char *)&ci->ci_vendor[0]; 1280 else 1281 vendorname = "Unknown"; 1282 if (family >= CPU_MAXFAMILY) 1283 family = CPU_MINFAMILY; 1284 class = family - 3; 1285 modifier = ""; 1286 name = ""; 1287 ci->ci_info = NULL; 1288 } else { 1289 cpu_vendor = cpup->cpu_vendor; 1290 vendorname = cpup->cpu_vendorname; 1291 modifier = modifiers[modif]; 1292 if (family > CPU_MAXFAMILY) { 1293 family = CPU_MAXFAMILY; 1294 model = CPU_DEFMODEL; 1295 } else if (model > CPU_MAXMODEL) { 1296 model = CPU_DEFMODEL; 1297 ext_model = 0; 1298 } 1299 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 1300 if (cpufam->cpu_extended_names == NULL || 1301 ext_model == 0) 1302 name = cpufam->cpu_models[model]; 1303 else { 1304 /* 1305 * Scan list(s) of extended model names 1306 */ 1307 modlist = cpufam->cpu_extended_names; 1308 while (modlist->ext_model != 0) { 1309 if (modlist->ext_model == ext_model) { 1310 name = 1311 modlist->cpu_models[model]; 1312 break; 1313 } 1314 modlist++; 1315 } 1316 } 1317 if (name == NULL || *name == '\0') 1318 name = cpufam->cpu_models[CPU_DEFMODEL]; 1319 class = cpufam->cpu_class; 1320 ci->ci_info = cpufam->cpu_info; 1321 1322 if (cpu_vendor == CPUVENDOR_INTEL) { 1323 if (family == 6 && model >= 5) { 1324 const char *tmp; 1325 tmp = intel_family6_name(ci); 1326 if (tmp != NULL) 1327 name = tmp; 1328 } 1329 if (family == CPU_MAXFAMILY && 1330 ci->ci_brand_id < 1331 __arraycount(i386_intel_brand) && 1332 i386_intel_brand[ci->ci_brand_id]) 1333 name = 1334 i386_intel_brand[ci->ci_brand_id]; 1335 } 1336 1337 if (cpu_vendor == CPUVENDOR_AMD) { 1338 if (family == 6 && model >= 6) { 1339 if (ci->ci_brand_id == 1) 1340 /* 1341 * It's Duron. We override the 1342 * name, since it might have 1343 * been misidentified as Athlon. 1344 */ 1345 name = 1346 amd_brand[ci->ci_brand_id]; 1347 else 1348 brand = amd_brand_name; 1349 } 1350 if (CPUID2FAMILY(ci->ci_signature) == 0xf) { 1351 /* 1352 * Identify AMD64 CPU names. 1353 * Note family value is clipped by 1354 * CPU_MAXFAMILY. 1355 */ 1356 const char *tmp; 1357 tmp = amd_amd64_name(ci); 1358 if (tmp != NULL) 1359 name = tmp; 1360 } 1361 } 1362 1363 if (cpu_vendor == CPUVENDOR_IDT && family >= 6) 1364 vendorname = "VIA"; 1365 } 1366 } 1367 1368 ci->ci_cpu_class = class; 1369 1370 sz = sizeof(ci->ci_tsc_freq); 1371 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 1372 1373 snprintf(cpu_model, sizeof(cpu_model), "%s%s%s%s%s%s%s (%s-class)", 1374 vendorname, 1375 *modifier ? " " : "", modifier, 1376 *name ? " " : "", name, 1377 *brand ? " " : "", brand, 1378 classnames[class]); 1379 aprint_normal("%s: %s", cpuname, cpu_model); 1380 1381 if (ci->ci_tsc_freq != 0) 1382 aprint_normal(", %qd.%02qd MHz", 1383 (ci->ci_tsc_freq + 4999) / 1000000, 1384 ((ci->ci_tsc_freq + 4999) / 10000) % 100); 1385 if (ci->ci_signature != 0) 1386 aprint_normal(", id 0x%x", ci->ci_signature); 1387 aprint_normal("\n"); 1388 1389 if (ci->ci_info) 1390 (*ci->ci_info)(ci); 1391 1392 feature_str[0] = CPUID_FLAGS1; 1393 feature_str[1] = CPUID_FLAGS2; 1394 feature_str[2] = CPUID_FLAGS3; 1395 1396 switch (cpu_vendor) { 1397 case CPUVENDOR_AMD: 1398 feature_str[3] = CPUID_EXT_FLAGS; 1399 feature_str[4] = CPUID_AMD_FLAGS4; 1400 break; 1401 case CPUVENDOR_INTEL: 1402 feature_str[3] = CPUID_INTEL_FLAGS4; 1403 break; 1404 default: 1405 feature_str[3] = CPUID_EXT_FLAGS; 1406 break; 1407 } 1408 1409 if (ci->ci_feature_flags) { 1410 if ((ci->ci_feature_flags & CPUID_MASK1) != 0) { 1411 snprintb(buf, sizeof(buf), feature_str[0], 1412 ci->ci_feature_flags); 1413 aprint_verbose("%s: features %s\n", cpuname, buf); 1414 } 1415 if ((ci->ci_feature_flags & CPUID_MASK2) != 0) { 1416 snprintb(buf, sizeof(buf), feature_str[1], 1417 ci->ci_feature_flags); 1418 aprint_verbose("%s: features %s\n", cpuname, buf); 1419 } 1420 if ((ci->ci_feature_flags & CPUID_MASK3) != 0) { 1421 snprintb(buf, sizeof(buf), feature_str[2], 1422 ci->ci_feature_flags); 1423 aprint_verbose("%s: features %s\n", cpuname, buf); 1424 } 1425 } 1426 1427 if (ci->ci_feature2_flags) { 1428 snprintb(buf, sizeof(buf), CPUID2_FLAGS, ci->ci_feature2_flags); 1429 aprint_verbose("%s: features2 %s\n", cpuname, buf); 1430 } 1431 1432 if (ci->ci_feature3_flags) { 1433 snprintb(buf, sizeof(buf), feature_str[3], 1434 ci->ci_feature3_flags); 1435 aprint_verbose("%s: features3 %s\n", cpuname, buf); 1436 } 1437 1438 if (ci->ci_feature4_flags) { 1439 snprintb(buf, sizeof(buf), feature_str[4], 1440 ci->ci_feature4_flags); 1441 aprint_verbose("%s: features4 %s\n", cpuname, buf); 1442 } 1443 1444 if (ci->ci_padlock_flags) { 1445 snprintb(buf, sizeof(buf), CPUID_FLAGS_PADLOCK, 1446 ci->ci_padlock_flags); 1447 aprint_verbose("%s: padlock features %s\n", cpuname, buf); 1448 } 1449 1450 if (*cpu_brand_string != '\0') 1451 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 1452 1453 x86_print_cacheinfo(ci); 1454 1455 if (ci->ci_cpuid_level >= 3 && (ci->ci_feature_flags & CPUID_PN)) { 1456 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 1457 cpuname, 1458 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 1459 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 1460 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 1461 } 1462 1463 if (ci->ci_cpu_class == CPUCLASS_386) { 1464 errx(1, "NetBSD requires an 80486 or later processor"); 1465 } 1466 1467 if (cpu == CPU_486DLC) { 1468 #ifndef CYRIX_CACHE_WORKS 1469 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 1470 #else 1471 #ifndef CYRIX_CACHE_REALLY_WORKS 1472 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 1473 #else 1474 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 1475 #endif 1476 #endif 1477 } 1478 1479 /* 1480 * Everything past this point requires a Pentium or later. 1481 */ 1482 if (ci->ci_cpuid_level < 0) 1483 return; 1484 1485 identifycpu_cpuids(ci); 1486 1487 #ifdef INTEL_CORETEMP 1488 if (cpu_vendor == CPUVENDOR_INTEL && ci->ci_cpuid_level >= 0x06) 1489 coretemp_register(ci); 1490 #endif 1491 1492 if (cpu_vendor == CPUVENDOR_AMD) { 1493 powernow_probe(ci); 1494 } 1495 1496 #ifdef INTEL_ONDEMAND_CLOCKMOD 1497 clockmod_init(); 1498 #endif 1499 1500 aprint_normal_dev(ci->ci_dev, "family %02x model %02x " 1501 "extfamily %02x extmodel %02x stepping %02x\n", 1502 CPUID2FAMILY(ci->ci_signature), CPUID2MODEL(ci->ci_signature), 1503 CPUID2EXTFAMILY(ci->ci_signature), CPUID2EXTMODEL(ci->ci_signature), 1504 CPUID2STEPPING(ci->ci_signature)); 1505 } 1506 1507 static const char * 1508 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 1509 const char *sep) 1510 { 1511 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1512 char human_num[HUMAN_BUFSIZE]; 1513 1514 if (cai->cai_totalsize == 0) 1515 return sep; 1516 1517 if (sep == NULL) 1518 aprint_verbose_dev(ci->ci_dev, ""); 1519 else 1520 aprint_verbose("%s", sep); 1521 if (name != NULL) 1522 aprint_verbose("%s ", name); 1523 1524 if (cai->cai_string != NULL) { 1525 aprint_verbose("%s ", cai->cai_string); 1526 } else { 1527 (void)humanize_number(human_num, sizeof(human_num), 1528 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 1529 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 1530 } 1531 switch (cai->cai_associativity) { 1532 case 0: 1533 aprint_verbose("disabled"); 1534 break; 1535 case 1: 1536 aprint_verbose("direct-mapped"); 1537 break; 1538 case 0xff: 1539 aprint_verbose("fully associative"); 1540 break; 1541 default: 1542 aprint_verbose("%d-way", cai->cai_associativity); 1543 break; 1544 } 1545 return ", "; 1546 } 1547 1548 static const char * 1549 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 1550 const char *sep) 1551 { 1552 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1553 char human_num[HUMAN_BUFSIZE]; 1554 1555 if (cai->cai_totalsize == 0) 1556 return sep; 1557 1558 if (sep == NULL) 1559 aprint_verbose_dev(ci->ci_dev, ""); 1560 else 1561 aprint_verbose("%s", sep); 1562 if (name != NULL) 1563 aprint_verbose("%s ", name); 1564 1565 if (cai->cai_string != NULL) { 1566 aprint_verbose("%s", cai->cai_string); 1567 } else { 1568 (void)humanize_number(human_num, sizeof(human_num), 1569 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 1570 aprint_verbose("%d %s entries ", cai->cai_totalsize, 1571 human_num); 1572 switch (cai->cai_associativity) { 1573 case 0: 1574 aprint_verbose("disabled"); 1575 break; 1576 case 1: 1577 aprint_verbose("direct-mapped"); 1578 break; 1579 case 0xff: 1580 aprint_verbose("fully associative"); 1581 break; 1582 default: 1583 aprint_verbose("%d-way", cai->cai_associativity); 1584 break; 1585 } 1586 } 1587 return ", "; 1588 } 1589 1590 static const struct x86_cache_info * 1591 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 1592 { 1593 int i; 1594 1595 for (i = 0; cai[i].cai_desc != 0; i++) { 1596 if (cai[i].cai_desc == desc) 1597 return (&cai[i]); 1598 } 1599 1600 return (NULL); 1601 } 1602 1603 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 1604 AMD_L2CACHE_INFO; 1605 1606 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 1607 AMD_L3CACHE_INFO; 1608 1609 static void 1610 amd_cpu_cacheinfo(struct cpu_info *ci) 1611 { 1612 const struct x86_cache_info *cp; 1613 struct x86_cache_info *cai; 1614 int family, model; 1615 u_int descs[4]; 1616 u_int lfunc; 1617 1618 family = (ci->ci_signature >> 8) & 15; 1619 model = CPUID2MODEL(ci->ci_signature); 1620 1621 /* 1622 * K5 model 0 has none of this info. 1623 */ 1624 if (family == 5 && model == 0) 1625 return; 1626 1627 /* 1628 * Get extended values for K8 and up. 1629 */ 1630 if (family == 0xf) { 1631 family += CPUID2EXTFAMILY(ci->ci_signature); 1632 model += CPUID2EXTMODEL(ci->ci_signature); 1633 } 1634 1635 /* 1636 * Determine the largest extended function value. 1637 */ 1638 x86_cpuid(0x80000000, descs); 1639 lfunc = descs[0]; 1640 1641 /* 1642 * Determine L1 cache/TLB info. 1643 */ 1644 if (lfunc < 0x80000005) { 1645 /* No L1 cache info available. */ 1646 return; 1647 } 1648 1649 x86_cpuid(0x80000005, descs); 1650 1651 /* 1652 * K6-III and higher have large page TLBs. 1653 */ 1654 if ((family == 5 && model >= 9) || family >= 6) { 1655 cai = &ci->ci_cinfo[CAI_ITLB2]; 1656 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1657 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1658 cai->cai_linesize = (4 * 1024 * 1024); 1659 1660 cai = &ci->ci_cinfo[CAI_DTLB2]; 1661 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1662 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1663 cai->cai_linesize = (4 * 1024 * 1024); 1664 } 1665 1666 cai = &ci->ci_cinfo[CAI_ITLB]; 1667 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1668 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1669 cai->cai_linesize = (4 * 1024); 1670 1671 cai = &ci->ci_cinfo[CAI_DTLB]; 1672 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1673 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1674 cai->cai_linesize = (4 * 1024); 1675 1676 cai = &ci->ci_cinfo[CAI_DCACHE]; 1677 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1678 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1679 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[2]); 1680 1681 cai = &ci->ci_cinfo[CAI_ICACHE]; 1682 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1683 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1684 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1685 1686 /* 1687 * Determine L2 cache/TLB info. 1688 */ 1689 if (lfunc < 0x80000006) { 1690 /* No L2 cache info available. */ 1691 return; 1692 } 1693 1694 x86_cpuid(0x80000006, descs); 1695 1696 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1697 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1698 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1699 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1700 1701 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1702 cai->cai_associativity); 1703 if (cp != NULL) 1704 cai->cai_associativity = cp->cai_associativity; 1705 else 1706 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1707 1708 /* 1709 * Determine L3 cache info on AMD Family 10h processors 1710 */ 1711 if (family == 0x10) { 1712 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1713 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1714 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1715 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1716 1717 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1718 cai->cai_associativity); 1719 if (cp != NULL) 1720 cai->cai_associativity = cp->cai_associativity; 1721 else 1722 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1723 } 1724 } 1725 1726 static void 1727 via_cpu_cacheinfo(struct cpu_info *ci) 1728 { 1729 struct x86_cache_info *cai; 1730 int family, model, stepping; 1731 u_int descs[4]; 1732 u_int lfunc; 1733 1734 family = (ci->ci_signature >> 8) & 15; 1735 model = CPUID2MODEL(ci->ci_signature); 1736 stepping = CPUID2STEPPING(ci->ci_signature); 1737 1738 /* 1739 * Determine the largest extended function value. 1740 */ 1741 x86_cpuid(0x80000000, descs); 1742 lfunc = descs[0]; 1743 1744 /* 1745 * Determine L1 cache/TLB info. 1746 */ 1747 if (lfunc < 0x80000005) { 1748 /* No L1 cache info available. */ 1749 return; 1750 } 1751 1752 x86_cpuid(0x80000005, descs); 1753 1754 cai = &ci->ci_cinfo[CAI_ITLB]; 1755 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1756 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1757 cai->cai_linesize = (4 * 1024); 1758 1759 cai = &ci->ci_cinfo[CAI_DTLB]; 1760 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1761 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1762 cai->cai_linesize = (4 * 1024); 1763 1764 cai = &ci->ci_cinfo[CAI_DCACHE]; 1765 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1766 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1767 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1768 if (model == 9 && stepping == 8) { 1769 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1770 cai->cai_associativity = 2; 1771 } 1772 1773 cai = &ci->ci_cinfo[CAI_ICACHE]; 1774 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1775 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1776 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1777 if (model == 9 && stepping == 8) { 1778 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1779 cai->cai_associativity = 2; 1780 } 1781 1782 /* 1783 * Determine L2 cache/TLB info. 1784 */ 1785 if (lfunc < 0x80000006) { 1786 /* No L2 cache info available. */ 1787 return; 1788 } 1789 1790 x86_cpuid(0x80000006, descs); 1791 1792 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1793 if (model >= 9) { 1794 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1795 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1796 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1797 } else { 1798 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1799 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1800 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1801 } 1802 } 1803 1804 static void 1805 x86_print_cacheinfo(struct cpu_info *ci) 1806 { 1807 const char *sep; 1808 1809 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 1810 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 1811 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 1812 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 1813 if (sep != NULL) 1814 aprint_verbose("\n"); 1815 } 1816 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 1817 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 1818 if (sep != NULL) 1819 aprint_verbose("\n"); 1820 } 1821 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 1822 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 1823 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 1824 if (sep != NULL) 1825 aprint_verbose("\n"); 1826 } 1827 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 1828 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 1829 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 1830 if (sep != NULL) 1831 aprint_verbose("\n"); 1832 } 1833 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 1834 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 1835 if (sep != NULL) 1836 aprint_verbose("\n"); 1837 } 1838 } 1839 1840 static void 1841 powernow_probe(struct cpu_info *ci) 1842 { 1843 uint32_t regs[4]; 1844 char buf[256]; 1845 1846 x86_cpuid(0x80000000, regs); 1847 1848 /* We need CPUID(0x80000007) */ 1849 if (regs[0] < 0x80000007) 1850 return; 1851 x86_cpuid(0x80000007, regs); 1852 1853 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 1854 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 1855 buf); 1856 } 1857
Indexes created Sun Oct 26 13:09:57 GMT 2025