i386.c revision 1.133.2.4
1 /* $NetBSD: i386.c,v 1.133.2.4 2024/10/03 12:00:57 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.133.2.4 2024/10/03 12:00:57 martin Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cpu_ucode.h> 85 86 #include "../cpuctl.h" 87 #include "cpuctl_i386.h" 88 89 /* Size of buffer for printing humanized numbers */ 90 #define HUMAN_BUFSIZE sizeof("999KB") 91 92 struct cpu_nocpuid_nameclass { 93 int cpu_vendor; 94 const char *cpu_vendorname; 95 const char *cpu_name; 96 int cpu_class; 97 void (*cpu_setup)(struct cpu_info *); 98 void (*cpu_cacheinfo)(struct cpu_info *); 99 void (*cpu_info)(struct cpu_info *); 100 }; 101 102 struct cpu_cpuid_nameclass { 103 const char *cpu_id; 104 int cpu_vendor; 105 const char *cpu_vendorname; 106 struct cpu_cpuid_family { 107 int cpu_class; 108 const char *cpu_models[256]; 109 const char *cpu_model_default; 110 void (*cpu_setup)(struct cpu_info *); 111 void (*cpu_probe)(struct cpu_info *); 112 void (*cpu_info)(struct cpu_info *); 113 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 114 }; 115 116 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 117 118 /* 119 * Map Brand ID from cpuid instruction to brand name. 120 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 121 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 122 * Architectures Software Developer's Manual, Volume 2A". 123 */ 124 static const char * const i386_intel_brand[] = { 125 "", /* Unsupported */ 126 "Celeron", /* Intel (R) Celeron (TM) processor */ 127 "Pentium III", /* Intel (R) Pentium (R) III processor */ 128 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 129 "Pentium III", /* Intel (R) Pentium (R) III processor */ 130 "", /* 0x05: Reserved */ 131 "Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */ 132 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 133 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 134 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 135 "Celeron", /* Intel (R) Celeron (TM) processor */ 136 "Xeon", /* Intel (R) Xeon (TM) processor */ 137 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 138 "", /* 0x0d: Reserved */ 139 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 140 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 141 "", /* 0x10: Reserved */ 142 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 143 "Celeron M", /* Intel (R) Celeron (R) M processor */ 144 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 145 "Celeron", /* Intel (R) Celeron (R) processor */ 146 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 147 "Pentium M", /* Intel (R) Pentium (R) M processor */ 148 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 149 }; 150 151 /* 152 * AMD processors don't have Brand IDs, so we need these names for probe. 153 */ 154 static const char * const amd_brand[] = { 155 "", 156 "Duron", /* AMD Duron(tm) */ 157 "MP", /* AMD Athlon(tm) MP */ 158 "XP", /* AMD Athlon(tm) XP */ 159 "4" /* AMD Athlon(tm) 4 */ 160 }; 161 162 int cpu_vendor; 163 static char cpu_brand_string[49]; 164 static char amd_brand_name[48]; 165 static int use_pae, largepagesize; 166 167 /* Setup functions */ 168 static void disable_tsc(struct cpu_info *); 169 static void amd_family5_setup(struct cpu_info *); 170 static void cyrix6x86_cpu_setup(struct cpu_info *); 171 static void winchip_cpu_setup(struct cpu_info *); 172 /* Brand/Model name functions */ 173 static const char *intel_family6_name(struct cpu_info *); 174 static const char *amd_amd64_name(struct cpu_info *); 175 /* Probe functions */ 176 static void amd_family6_probe(struct cpu_info *); 177 static void powernow_probe(struct cpu_info *); 178 static void intel_family_new_probe(struct cpu_info *); 179 static void via_cpu_probe(struct cpu_info *); 180 /* (Cache) Info functions */ 181 static void intel_cpu_cacheinfo(struct cpu_info *); 182 static void amd_cpu_cacheinfo(struct cpu_info *); 183 static void via_cpu_cacheinfo(struct cpu_info *); 184 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 185 static void transmeta_cpu_info(struct cpu_info *); 186 /* Common functions */ 187 static void cpu_probe_base_features(struct cpu_info *, const char *); 188 static void cpu_probe_hv_features(struct cpu_info *, const char *); 189 static void cpu_probe_features(struct cpu_info *); 190 static void print_bits(const char *, const char *, const char *, uint32_t); 191 static void identifycpu_cpuids(struct cpu_info *); 192 static const char *print_cache_config(struct cpu_info *, int, const char *, 193 const char *); 194 static const char *print_tlb_config(struct cpu_info *, int, const char *, 195 const char *); 196 static void x86_print_cache_and_tlb_info(struct cpu_info *); 197 198 /* 199 * Note: these are just the ones that may not have a cpuid instruction. 200 * We deal with the rest in a different way. 201 */ 202 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 203 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 204 NULL, NULL, NULL }, /* CPU_386SX */ 205 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 206 NULL, NULL, NULL }, /* CPU_386 */ 207 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 208 NULL, NULL, NULL }, /* CPU_486SX */ 209 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 210 NULL, NULL, NULL }, /* CPU_486 */ 211 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 212 NULL, NULL, NULL }, /* CPU_486DLC */ 213 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 214 NULL, NULL, NULL }, /* CPU_6x86 */ 215 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 216 NULL, NULL, NULL }, /* CPU_NX586 */ 217 }; 218 219 const char *classnames[] = { 220 "386", 221 "486", 222 "586", 223 "686" 224 }; 225 226 const char *modifiers[] = { 227 "", 228 "OverDrive", 229 "Dual", 230 "" 231 }; 232 233 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 234 { 235 /* 236 * For Intel processors, check Chapter 35Model-specific 237 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 238 * Software Developer's Manual, Volume 3C". 239 */ 240 "GenuineIntel", 241 CPUVENDOR_INTEL, 242 "Intel", 243 /* Family 4 */ 244 { { 245 CPUCLASS_486, 246 { 247 "486DX", "486DX", "486SX", "486DX2", "486SL", 248 "486SX2", 0, "486DX2 W/B Enhanced", 249 "486DX4", 0, 0, 0, 0, 0, 0, 0, 250 }, 251 "486", /* Default */ 252 NULL, 253 NULL, 254 intel_cpu_cacheinfo, 255 }, 256 /* Family 5 */ 257 { 258 CPUCLASS_586, 259 { 260 "Pentium (P5 A-step)", "Pentium (P5)", 261 "Pentium (P54C)", "Pentium (P24T)", 262 "Pentium/MMX", "Pentium", 0, 263 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 264 "Quark X1000", 0, 0, 0, 0, 0, 0, 265 }, 266 "Pentium", /* Default */ 267 NULL, 268 NULL, 269 intel_cpu_cacheinfo, 270 }, 271 /* Family 6 */ 272 { 273 CPUCLASS_686, 274 { 275 [0x00] = "Pentium Pro (A-step)", 276 [0x01] = "Pentium Pro", 277 [0x03] = "Pentium II (Klamath)", 278 [0x04] = "Pentium Pro", 279 [0x05] = "Pentium II/Celeron (Deschutes)", 280 [0x06] = "Celeron (Mendocino)", 281 [0x07] = "Pentium III (Katmai)", 282 [0x08] = "Pentium III (Coppermine)", 283 [0x09] = "Pentium M (Banias)", 284 [0x0a] = "Pentium III Xeon (Cascades)", 285 [0x0b] = "Pentium III (Tualatin)", 286 [0x0d] = "Pentium M (Dothan)", 287 [0x0e] = "Pentium Core Duo, Core solo", 288 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 289 "Core 2 Quad 6xxx, " 290 "Core 2 Extreme 6xxx, " 291 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 292 "and Pentium DC", 293 [0x15] = "EP80579 Integrated Processor", 294 [0x16] = "Celeron (45nm)", 295 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 296 "Core 2 Quad 8xxx and 9xxx", 297 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 298 "(Nehalem)", 299 [0x1c] = "45nm Atom Family", 300 [0x1d] = "XeonMP 74xx (Nehalem)", 301 [0x1e] = "Core i7 and i5", 302 [0x1f] = "Core i7 and i5", 303 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 304 [0x26] = "Atom Family", 305 [0x27] = "Atom Family", 306 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 307 "i3 2xxx", 308 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 309 [0x2d] = "Xeon E5 Sandy Bridge family, " 310 "Core i7-39xx Extreme", 311 [0x2e] = "Xeon 75xx & 65xx", 312 [0x2f] = "Xeon E7 family", 313 [0x35] = "Atom Family", 314 [0x36] = "Atom S1000", 315 [0x37] = "Atom E3000, Z3[67]00", 316 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 317 "Ivy Bridge", 318 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 319 "(Haswell)", 320 [0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)", 321 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 322 "Core i7-49xx Extreme", 323 [0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), " 324 "Core i7-59xx Extreme", 325 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 326 "(Haswell)", 327 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 328 "(Haswell)", 329 [0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)", 330 [0x4a] = "Atom Z3400", 331 [0x4c] = "Atom X[57]-Z8000 (Airmont)", 332 [0x4d] = "Atom C2000", 333 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 334 [0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme", 335 [0x55] = "Xeon Scalable (Skylake, Cascade Lake, Copper Lake)", 336 [0x56] = "Xeon D-1500 (Broadwell)", 337 [0x57] = "Xeon Phi [357]200 (Knights Landing)", 338 [0x5a] = "Atom Z3500", 339 [0x5c] = "Atom (Goldmont)", 340 [0x5d] = "Atom X3-C3000 (Silvermont)", 341 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 342 [0x5f] = "Atom (Goldmont, Denverton)", 343 [0x66] = "8th gen Core i3 (Cannon Lake)", 344 [0x6a] = "3rd gen Xeon Scalable (Ice Lake)", 345 [0x6c] = "3rd gen Xeon Scalable (Ice Lake)", 346 [0x7a] = "Atom (Goldmont Plus)", 347 [0x7d] = "10th gen Core (Ice Lake)", 348 [0x7e] = "10th gen Core (Ice Lake)", 349 [0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)", 350 [0x86] = "Atom (Tremont)", 351 [0x8c] = "11th gen Core (Tiger Lake)", 352 [0x8d] = "11th gen Core (Tiger Lake)", 353 [0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 354 [0x8f] = "4th gen Xeon Scalable (Sapphire Rapids)", 355 [0x96] = "Atom x6000E (Elkhart Lake)", 356 [0x97] = "12th gen Core (Alder Lake)", 357 [0x9a] = "12th gen Core (Alder Lake)", 358 [0x9c] = "Pentium Silver N6xxx, Celeron N45xx, Celeron N51xx (Jasper Lake)", 359 [0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 360 [0xa5] = "10th gen Core (Comet Lake)", 361 [0xa6] = "10th gen Core (Comet Lake)", 362 [0xa7] = "11th gen Core (Rocket Lake)", 363 [0xa8] = "11th gen Core (Rocket Lake)", 364 [0xb7] = "13th gen Core (Raptor Lake)", 365 [0xba] = "13th gen Core (Raptor Lake)", 366 [0xbe] = "Core i3-N3xx N[12]xx Nxx Atom x7xxxE (Alder Lake-N)", 367 [0xbf] = "13th gen Core (Raptor Lake)", 368 }, 369 "Pentium Pro, II or III", /* Default */ 370 NULL, 371 intel_family_new_probe, 372 intel_cpu_cacheinfo, 373 }, 374 /* Family > 6 */ 375 { 376 CPUCLASS_686, 377 { 378 0, 0, 0, 0, 0, 0, 0, 0, 379 0, 0, 0, 0, 0, 0, 0, 0, 380 }, 381 "Pentium 4", /* Default */ 382 NULL, 383 intel_family_new_probe, 384 intel_cpu_cacheinfo, 385 } } 386 }, 387 { 388 "AuthenticAMD", 389 CPUVENDOR_AMD, 390 "AMD", 391 /* Family 4 */ 392 { { 393 CPUCLASS_486, 394 { 395 0, 0, 0, "Am486DX2 W/T", 396 0, 0, 0, "Am486DX2 W/B", 397 "Am486DX4 W/T or Am5x86 W/T 150", 398 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 399 0, 0, "Am5x86 W/T 133/160", 400 "Am5x86 W/B 133/160", 401 }, 402 "Am486 or Am5x86", /* Default */ 403 NULL, 404 NULL, 405 NULL, 406 }, 407 /* Family 5 */ 408 { 409 CPUCLASS_586, 410 { 411 "K5", "K5", "K5", "K5", 0, 0, "K6", 412 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 413 "K6-2+/III+", 0, 0, 414 }, 415 "K5 or K6", /* Default */ 416 amd_family5_setup, 417 NULL, 418 amd_cpu_cacheinfo, 419 }, 420 /* Family 6 */ 421 { 422 CPUCLASS_686, 423 { 424 0, "Athlon Model 1", "Athlon Model 2", 425 "Duron", "Athlon Model 4 (Thunderbird)", 426 0, "Athlon", "Duron", "Athlon", 0, 427 "Athlon", 0, 0, 0, 0, 0, 428 }, 429 "K7 (Athlon)", /* Default */ 430 NULL, 431 amd_family6_probe, 432 amd_cpu_cacheinfo, 433 }, 434 /* Family > 6 */ 435 { 436 CPUCLASS_686, 437 { 438 0, 0, 0, 0, 0, 0, 0, 0, 439 0, 0, 0, 0, 0, 0, 0, 0, 440 }, 441 "Unknown K8 (Athlon)", /* Default */ 442 NULL, 443 amd_family6_probe, 444 amd_cpu_cacheinfo, 445 } } 446 }, 447 { 448 "CyrixInstead", 449 CPUVENDOR_CYRIX, 450 "Cyrix", 451 /* Family 4 */ 452 { { 453 CPUCLASS_486, 454 { 455 0, 0, 0, 456 "MediaGX", 457 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 458 }, 459 "486", /* Default */ 460 cyrix6x86_cpu_setup, /* XXX ?? */ 461 NULL, 462 NULL, 463 }, 464 /* Family 5 */ 465 { 466 CPUCLASS_586, 467 { 468 0, 0, "6x86", 0, 469 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 470 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 471 }, 472 "6x86", /* Default */ 473 cyrix6x86_cpu_setup, 474 NULL, 475 NULL, 476 }, 477 /* Family 6 */ 478 { 479 CPUCLASS_686, 480 { 481 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 482 0, 0, 0, 0, 0, 0, 0, 0, 483 }, 484 "6x86MX", /* Default */ 485 cyrix6x86_cpu_setup, 486 NULL, 487 NULL, 488 }, 489 /* Family > 6 */ 490 { 491 CPUCLASS_686, 492 { 493 0, 0, 0, 0, 0, 0, 0, 0, 494 0, 0, 0, 0, 0, 0, 0, 0, 495 }, 496 "Unknown 6x86MX", /* Default */ 497 NULL, 498 NULL, 499 NULL, 500 } } 501 }, 502 { /* MediaGX is now owned by National Semiconductor */ 503 "Geode by NSC", 504 CPUVENDOR_CYRIX, /* XXX */ 505 "National Semiconductor", 506 /* Family 4, NSC never had any of these */ 507 { { 508 CPUCLASS_486, 509 { 510 0, 0, 0, 0, 0, 0, 0, 0, 511 0, 0, 0, 0, 0, 0, 0, 0, 512 }, 513 "486 compatible", /* Default */ 514 NULL, 515 NULL, 516 NULL, 517 }, 518 /* Family 5: Geode family, formerly MediaGX */ 519 { 520 CPUCLASS_586, 521 { 522 0, 0, 0, 0, 523 "Geode GX1", 524 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 525 }, 526 "Geode", /* Default */ 527 cyrix6x86_cpu_setup, 528 NULL, 529 amd_cpu_cacheinfo, 530 }, 531 /* Family 6, not yet available from NSC */ 532 { 533 CPUCLASS_686, 534 { 535 0, 0, 0, 0, 0, 0, 0, 0, 536 0, 0, 0, 0, 0, 0, 0, 0, 537 }, 538 "Pentium Pro compatible", /* Default */ 539 NULL, 540 NULL, 541 NULL, 542 }, 543 /* Family > 6, not yet available from NSC */ 544 { 545 CPUCLASS_686, 546 { 547 0, 0, 0, 0, 0, 0, 0, 0, 548 0, 0, 0, 0, 0, 0, 0, 0, 549 }, 550 "Pentium Pro compatible", /* Default */ 551 NULL, 552 NULL, 553 NULL, 554 } } 555 }, 556 { 557 "CentaurHauls", 558 CPUVENDOR_IDT, 559 "IDT", 560 /* Family 4, IDT never had any of these */ 561 { { 562 CPUCLASS_486, 563 { 564 0, 0, 0, 0, 0, 0, 0, 0, 565 0, 0, 0, 0, 0, 0, 0, 0, 566 }, 567 "486 compatible", /* Default */ 568 NULL, 569 NULL, 570 NULL, 571 }, 572 /* Family 5 */ 573 { 574 CPUCLASS_586, 575 { 576 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 577 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 578 }, 579 "WinChip", /* Default */ 580 winchip_cpu_setup, 581 NULL, 582 NULL, 583 }, 584 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 585 { 586 CPUCLASS_686, 587 { 588 0, 0, 0, 0, 0, 0, "C3 Samuel", 589 "C3 Samuel 2/Ezra", "C3 Ezra-T", 590 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 591 0, "VIA Nano", 592 }, 593 "Unknown VIA/IDT", /* Default */ 594 NULL, 595 via_cpu_probe, 596 via_cpu_cacheinfo, 597 }, 598 /* Family > 6, not yet available from VIA */ 599 { 600 CPUCLASS_686, 601 { 602 0, 0, 0, 0, 0, 0, 0, 0, 603 0, 0, 0, 0, 0, 0, 0, 0, 604 }, 605 "Pentium Pro compatible", /* Default */ 606 NULL, 607 NULL, 608 NULL, 609 } } 610 }, 611 { 612 "GenuineTMx86", 613 CPUVENDOR_TRANSMETA, 614 "Transmeta", 615 /* Family 4, Transmeta never had any of these */ 616 { { 617 CPUCLASS_486, 618 { 619 0, 0, 0, 0, 0, 0, 0, 0, 620 0, 0, 0, 0, 0, 0, 0, 0, 621 }, 622 "486 compatible", /* Default */ 623 NULL, 624 NULL, 625 NULL, 626 }, 627 /* Family 5 */ 628 { 629 CPUCLASS_586, 630 { 631 0, 0, 0, 0, 0, 0, 0, 0, 632 0, 0, 0, 0, 0, 0, 0, 0, 633 }, 634 "Crusoe", /* Default */ 635 NULL, 636 NULL, 637 transmeta_cpu_info, 638 }, 639 /* Family 6, not yet available from Transmeta */ 640 { 641 CPUCLASS_686, 642 { 643 0, 0, 0, 0, 0, 0, 0, 0, 644 0, 0, 0, 0, 0, 0, 0, 0, 645 }, 646 "Pentium Pro compatible", /* Default */ 647 NULL, 648 NULL, 649 NULL, 650 }, 651 /* Family > 6, not yet available from Transmeta */ 652 { 653 CPUCLASS_686, 654 { 655 0, 0, 0, 0, 0, 0, 0, 0, 656 0, 0, 0, 0, 0, 0, 0, 0, 657 }, 658 "Pentium Pro compatible", /* Default */ 659 NULL, 660 NULL, 661 NULL, 662 } } 663 } 664 }; 665 666 /* 667 * disable the TSC such that we don't use the TSC in microtime(9) 668 * because some CPUs got the implementation wrong. 669 */ 670 static void 671 disable_tsc(struct cpu_info *ci) 672 { 673 if (ci->ci_feat_val[0] & CPUID_TSC) { 674 ci->ci_feat_val[0] &= ~CPUID_TSC; 675 aprint_error("WARNING: broken TSC disabled\n"); 676 } 677 } 678 679 static void 680 amd_family5_setup(struct cpu_info *ci) 681 { 682 683 switch (ci->ci_model) { 684 case 0: /* AMD-K5 Model 0 */ 685 /* 686 * According to the AMD Processor Recognition App Note, 687 * the AMD-K5 Model 0 uses the wrong bit to indicate 688 * support for global PTEs, instead using bit 9 (APIC) 689 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 690 */ 691 if (ci->ci_feat_val[0] & CPUID_APIC) 692 ci->ci_feat_val[0] = 693 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 694 /* 695 * XXX But pmap_pg_g is already initialized -- need to kick 696 * XXX the pmap somehow. How does the MP branch do this? 697 */ 698 break; 699 } 700 } 701 702 static void 703 cyrix6x86_cpu_setup(struct cpu_info *ci) 704 { 705 706 /* 707 * Do not disable the TSC on the Geode GX, it's reported to 708 * work fine. 709 */ 710 if (ci->ci_signature != 0x552) 711 disable_tsc(ci); 712 } 713 714 static void 715 winchip_cpu_setup(struct cpu_info *ci) 716 { 717 switch (ci->ci_model) { 718 case 4: /* WinChip C6 */ 719 disable_tsc(ci); 720 } 721 } 722 723 724 static const char * 725 intel_family6_name(struct cpu_info *ci) 726 { 727 const char *ret = NULL; 728 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 729 730 if (ci->ci_model == 5) { 731 switch (l2cache) { 732 case 0: 733 case 128 * 1024: 734 ret = "Celeron (Covington)"; 735 break; 736 case 256 * 1024: 737 ret = "Mobile Pentium II (Dixon)"; 738 break; 739 case 512 * 1024: 740 ret = "Pentium II"; 741 break; 742 case 1 * 1024 * 1024: 743 case 2 * 1024 * 1024: 744 ret = "Pentium II Xeon"; 745 break; 746 } 747 } else if (ci->ci_model == 6) { 748 switch (l2cache) { 749 case 256 * 1024: 750 case 512 * 1024: 751 ret = "Mobile Pentium II"; 752 break; 753 } 754 } else if (ci->ci_model == 7) { 755 switch (l2cache) { 756 case 512 * 1024: 757 ret = "Pentium III"; 758 break; 759 case 1 * 1024 * 1024: 760 case 2 * 1024 * 1024: 761 ret = "Pentium III Xeon"; 762 break; 763 } 764 } else if (ci->ci_model >= 8) { 765 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 766 switch (ci->ci_brand_id) { 767 case 0x3: 768 if (ci->ci_signature == 0x6B1) 769 ret = "Celeron"; 770 break; 771 case 0x8: 772 if (ci->ci_signature >= 0xF13) 773 ret = "genuine processor"; 774 break; 775 case 0xB: 776 if (ci->ci_signature >= 0xF13) 777 ret = "Xeon MP"; 778 break; 779 case 0xE: 780 if (ci->ci_signature < 0xF13) 781 ret = "Xeon"; 782 break; 783 } 784 if (ret == NULL) 785 ret = i386_intel_brand[ci->ci_brand_id]; 786 } 787 } 788 789 return ret; 790 } 791 792 /* 793 * Identify AMD64 CPU names from cpuid. 794 * 795 * Based on: 796 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 797 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 798 * "Revision Guide for AMD NPT Family 0Fh Processors" 799 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 800 * and other miscellaneous reports. 801 * 802 * This is all rather pointless, these are cross 'brand' since the raw 803 * silicon is shared. 804 */ 805 static const char * 806 amd_amd64_name(struct cpu_info *ci) 807 { 808 static char family_str[32]; 809 810 /* Only called if family >= 15 */ 811 812 switch (ci->ci_family) { 813 case 15: 814 switch (ci->ci_model) { 815 case 0x21: /* rev JH-E1/E6 */ 816 case 0x41: /* rev JH-F2 */ 817 return "Dual-Core Opteron"; 818 case 0x23: /* rev JH-E6 (Toledo) */ 819 return "Dual-Core Opteron or Athlon 64 X2"; 820 case 0x43: /* rev JH-F2 (Windsor) */ 821 return "Athlon 64 FX or Athlon 64 X2"; 822 case 0x24: /* rev SH-E5 (Lancaster?) */ 823 return "Mobile Athlon 64 or Turion 64"; 824 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 825 return "Opteron or Athlon 64 FX"; 826 case 0x15: /* rev SH-D0 */ 827 case 0x25: /* rev SH-E4 */ 828 return "Opteron"; 829 case 0x27: /* rev DH-E4, SH-E4 */ 830 return "Athlon 64 or Athlon 64 FX or Opteron"; 831 case 0x48: /* rev BH-F2 */ 832 return "Turion 64 X2"; 833 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 834 case 0x07: /* rev SH-CG (ClawHammer) */ 835 case 0x0b: /* rev CH-CG */ 836 case 0x14: /* rev SH-D0 */ 837 case 0x17: /* rev SH-D0 */ 838 case 0x1b: /* rev CH-D0 */ 839 return "Athlon 64"; 840 case 0x2b: /* rev BH-E4 (Manchester) */ 841 case 0x4b: /* rev BH-F2 (Windsor) */ 842 return "Athlon 64 X2"; 843 case 0x6b: /* rev BH-G1 (Brisbane) */ 844 return "Athlon X2 or Athlon 64 X2"; 845 case 0x08: /* rev CH-CG */ 846 case 0x0c: /* rev DH-CG (Newcastle) */ 847 case 0x0e: /* rev DH-CG (Newcastle?) */ 848 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 849 case 0x18: /* rev CH-D0 */ 850 case 0x1c: /* rev DH-D0 (Winchester) */ 851 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 852 case 0x2c: /* rev DH-E3/E6 */ 853 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 854 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 855 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 856 case 0x6f: /* rev DH-G1 */ 857 return "Athlon 64 or Sempron"; 858 default: 859 break; 860 } 861 return "Unknown AMD64 CPU"; 862 863 #if 0 864 case 16: 865 return "Family 10h"; 866 case 17: 867 return "Family 11h"; 868 case 18: 869 return "Family 12h"; 870 case 19: 871 return "Family 14h"; 872 case 20: 873 return "Family 15h"; 874 #endif 875 876 default: 877 break; 878 } 879 880 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 881 return family_str; 882 } 883 884 static void 885 intel_family_new_probe(struct cpu_info *ci) 886 { 887 uint32_t descs[4]; 888 889 x86_cpuid(0x80000000, descs); 890 891 /* 892 * Determine extended feature flags. 893 */ 894 if (descs[0] >= 0x80000001) { 895 x86_cpuid(0x80000001, descs); 896 ci->ci_feat_val[2] |= descs[3]; 897 ci->ci_feat_val[3] |= descs[2]; 898 } 899 } 900 901 static void 902 via_cpu_probe(struct cpu_info *ci) 903 { 904 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 905 u_int descs[4]; 906 u_int lfunc; 907 908 /* 909 * Determine the largest extended function value. 910 */ 911 x86_cpuid(0x80000000, descs); 912 lfunc = descs[0]; 913 914 /* 915 * Determine the extended feature flags. 916 */ 917 if (lfunc >= 0x80000001) { 918 x86_cpuid(0x80000001, descs); 919 ci->ci_feat_val[2] |= descs[3]; 920 } 921 922 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 923 return; 924 925 /* Nehemiah or Esther */ 926 x86_cpuid(0xc0000000, descs); 927 lfunc = descs[0]; 928 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 929 return; 930 931 x86_cpuid(0xc0000001, descs); 932 lfunc = descs[3]; 933 ci->ci_feat_val[4] = lfunc; 934 } 935 936 static void 937 amd_family6_probe(struct cpu_info *ci) 938 { 939 uint32_t descs[4]; 940 char *p; 941 size_t i; 942 943 x86_cpuid(0x80000000, descs); 944 945 /* 946 * Determine the extended feature flags. 947 */ 948 if (descs[0] >= 0x80000001) { 949 x86_cpuid(0x80000001, descs); 950 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 951 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 952 } 953 954 if (*cpu_brand_string == '\0') 955 return; 956 957 for (i = 1; i < __arraycount(amd_brand); i++) 958 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 959 ci->ci_brand_id = i; 960 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 961 break; 962 } 963 } 964 965 static void 966 intel_cpu_cacheinfo(struct cpu_info *ci) 967 { 968 const struct x86_cache_info *cai; 969 u_int descs[4]; 970 int iterations, i, j; 971 int type, level, ways, linesize, sets; 972 int caitype = -1; 973 uint8_t desc; 974 975 /* Return if the cpu is old pre-cpuid instruction cpu */ 976 if (ci->ci_cpu_type >= 0) 977 return; 978 979 if (ci->ci_max_cpuid < 2) 980 return; 981 982 /* 983 * Parse the cache info from `cpuid leaf 2', if we have it. 984 * XXX This is kinda ugly, but hey, so is the architecture... 985 */ 986 x86_cpuid(2, descs); 987 iterations = descs[0] & 0xff; 988 while (iterations-- > 0) { 989 for (i = 0; i < 4; i++) { 990 if (descs[i] & 0x80000000) 991 continue; 992 for (j = 0; j < 4; j++) { 993 /* 994 * The least significant byte in EAX 995 * ((desc[0] >> 0) & 0xff) is always 0x01 and 996 * it should be ignored. 997 */ 998 if (i == 0 && j == 0) 999 continue; 1000 desc = (descs[i] >> (j * 8)) & 0xff; 1001 if (desc == 0) 1002 continue; 1003 cai = cpu_cacheinfo_lookup( 1004 intel_cpuid_cache_info, desc); 1005 if (cai != NULL) 1006 ci->ci_cinfo[cai->cai_index] = *cai; 1007 else if ((verbose != 0) && (desc != 0xff) 1008 && (desc != 0xfe)) 1009 aprint_error_dev(ci->ci_dev, "error:" 1010 " Unknown cacheinfo desc %02x\n", 1011 desc); 1012 } 1013 } 1014 x86_cpuid(2, descs); 1015 } 1016 1017 if (ci->ci_max_cpuid < 4) 1018 return; 1019 1020 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1021 cpu_dcp_cacheinfo(ci, 4); 1022 1023 if (ci->ci_max_cpuid < 0x18) 1024 return; 1025 /* Parse the TLB info from `cpuid leaf 18H', if we have it. */ 1026 x86_cpuid(0x18, descs); 1027 iterations = descs[0]; 1028 for (i = 0; i <= iterations; i++) { 1029 uint32_t pgsize; 1030 bool full; 1031 1032 x86_cpuid2(0x18, i, descs); 1033 type = __SHIFTOUT(descs[3], CPUID_DATP_TCTYPE); 1034 if (type == CPUID_DATP_TCTYPE_N) 1035 continue; 1036 level = __SHIFTOUT(descs[3], CPUID_DATP_TCLEVEL); 1037 pgsize = __SHIFTOUT(descs[1], CPUID_DATP_PGSIZE); 1038 switch (level) { 1039 case 1: 1040 if (type == CPUID_DATP_TCTYPE_I) { 1041 switch (pgsize) { 1042 case CPUID_DATP_PGSIZE_4KB: 1043 caitype = CAI_ITLB; 1044 break; 1045 case CPUID_DATP_PGSIZE_2MB 1046 | CPUID_DATP_PGSIZE_4MB: 1047 caitype = CAI_ITLB2; 1048 break; 1049 case CPUID_DATP_PGSIZE_1GB: 1050 caitype = CAI_L1_1GBITLB; 1051 break; 1052 default: 1053 aprint_error_dev(ci->ci_dev, 1054 "error: unknown ITLB size (%d)\n", 1055 pgsize); 1056 caitype = CAI_ITLB; 1057 break; 1058 } 1059 } else if (type == CPUID_DATP_TCTYPE_D) { 1060 switch (pgsize) { 1061 case CPUID_DATP_PGSIZE_4KB: 1062 caitype = CAI_DTLB; 1063 break; 1064 case CPUID_DATP_PGSIZE_2MB 1065 | CPUID_DATP_PGSIZE_4MB: 1066 caitype = CAI_DTLB2; 1067 break; 1068 case CPUID_DATP_PGSIZE_1GB: 1069 caitype = CAI_L1_1GBDTLB; 1070 break; 1071 default: 1072 aprint_error_dev(ci->ci_dev, 1073 "error: unknown DTLB size (%d)\n", 1074 pgsize); 1075 caitype = CAI_DTLB; 1076 break; 1077 } 1078 } else if (type == CPUID_DATP_TCTYPE_L) 1079 caitype = CAI_L1_LD_TLB; 1080 else if (type == CPUID_DATP_TCTYPE_S) 1081 caitype = CAI_L1_ST_TLB; 1082 else 1083 caitype = -1; 1084 break; 1085 case 2: 1086 if (type == CPUID_DATP_TCTYPE_I) 1087 caitype = CAI_L2_ITLB; 1088 else if (type == CPUID_DATP_TCTYPE_D) 1089 caitype = CAI_L2_DTLB; 1090 else if (type == CPUID_DATP_TCTYPE_U) { 1091 if (pgsize == CPUID_DATP_PGSIZE_4KB) 1092 caitype = CAI_L2_STLB; 1093 else if (pgsize == (CPUID_DATP_PGSIZE_4KB 1094 | CPUID_DATP_PGSIZE_2MB)) 1095 caitype = CAI_L2_STLB2; 1096 else if (pgsize == (CPUID_DATP_PGSIZE_2MB 1097 | CPUID_DATP_PGSIZE_4MB)) 1098 caitype = CAI_L2_STLB3; 1099 else if ((pgsize & CPUID_DATP_PGSIZE_1GB) 1100 != 0) { 1101 /* FIXME: 1GB max TLB */ 1102 caitype = CAI_L2_STLB3; 1103 linesize = 1024 * 1024 * 1024; 1104 } else if ((pgsize & CPUID_DATP_PGSIZE_4MB) 1105 != 0) { 1106 /* FIXME: 4MB max TLB */ 1107 caitype = CAI_L2_STLB3; 1108 linesize = 4 * 1024 * 1024; 1109 } else if ((pgsize & CPUID_DATP_PGSIZE_2MB) 1110 != 0) { 1111 /* FIXME: 2MB max TLB */ 1112 caitype = CAI_L2_STLB2; 1113 linesize = 2 * 1024 * 1024; 1114 } else { 1115 aprint_error_dev(ci->ci_dev, "error: " 1116 "unknown L2 STLB size (%d)\n", 1117 pgsize); 1118 caitype = CAI_L2_STLB; 1119 linesize = 4 * 1024; 1120 } 1121 } else 1122 caitype = -1; 1123 break; 1124 case 3: 1125 /* XXX need work for L3 TLB */ 1126 caitype = CAI_L3CACHE; 1127 break; 1128 default: 1129 caitype = -1; 1130 break; 1131 } 1132 if (caitype == -1) { 1133 aprint_error_dev(ci->ci_dev, 1134 "error: unknown TLB level&type (%d & %d)\n", 1135 level, type); 1136 continue; 1137 } 1138 switch (pgsize) { 1139 case CPUID_DATP_PGSIZE_4KB: 1140 linesize = 4 * 1024; 1141 break; 1142 case CPUID_DATP_PGSIZE_2MB: 1143 linesize = 2 * 1024 * 1024; 1144 break; 1145 case CPUID_DATP_PGSIZE_4MB: 1146 linesize = 4 * 1024 * 1024; 1147 break; 1148 case CPUID_DATP_PGSIZE_1GB: 1149 linesize = 1024 * 1024 * 1024; 1150 break; 1151 default: 1152 if ((pgsize & CPUID_DATP_PGSIZE_1GB) != 0) 1153 linesize = 1024 * 1024 * 1024; /* MAX 1G */ 1154 else if ((pgsize & CPUID_DATP_PGSIZE_4MB) != 0) 1155 linesize = 4 * 1024 * 1024; /* MAX 4M */ 1156 else if ((pgsize & CPUID_DATP_PGSIZE_2MB) != 0) 1157 linesize = 2 * 1024 * 1024; /* MAX 2M */ 1158 else 1159 linesize = 4 * 1024; /* XXX default to 4K */ 1160 aprint_error_dev(ci->ci_dev, "WARNING: Currently " 1161 "this info can't print correctly " 1162 "(level = %d, pgsize = %d)\n", 1163 level, pgsize); 1164 break; 1165 } 1166 ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS); 1167 sets = descs[2]; 1168 full = descs[3] & CPUID_DATP_FULLASSOC; 1169 ci->ci_cinfo[caitype].cai_totalsize 1170 = ways * sets; /* entries */ 1171 ci->ci_cinfo[caitype].cai_associativity 1172 = full ? 0xff : ways; 1173 ci->ci_cinfo[caitype].cai_linesize = linesize; /* pg size */ 1174 } 1175 } 1176 1177 static const struct x86_cache_info amd_cpuid_l2l3cache_assoc_info[] = 1178 AMD_L2L3CACHE_INFO; 1179 1180 static void 1181 amd_cpu_cacheinfo(struct cpu_info *ci) 1182 { 1183 const struct x86_cache_info *cp; 1184 struct x86_cache_info *cai; 1185 u_int descs[4]; 1186 u_int lfunc; 1187 1188 /* K5 model 0 has none of this info. */ 1189 if (ci->ci_family == 5 && ci->ci_model == 0) 1190 return; 1191 1192 /* Determine the largest extended function value. */ 1193 x86_cpuid(0x80000000, descs); 1194 lfunc = descs[0]; 1195 1196 if (lfunc < 0x80000005) 1197 return; 1198 1199 /* Determine L1 cache/TLB info. */ 1200 x86_cpuid(0x80000005, descs); 1201 1202 /* K6-III and higher have large page TLBs. */ 1203 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1204 cai = &ci->ci_cinfo[CAI_ITLB2]; 1205 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1206 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1207 cai->cai_linesize = largepagesize; 1208 1209 cai = &ci->ci_cinfo[CAI_DTLB2]; 1210 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1211 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1212 cai->cai_linesize = largepagesize; 1213 } 1214 1215 cai = &ci->ci_cinfo[CAI_ITLB]; 1216 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1217 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1218 cai->cai_linesize = (4 * 1024); 1219 1220 cai = &ci->ci_cinfo[CAI_DTLB]; 1221 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1222 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1223 cai->cai_linesize = (4 * 1024); 1224 1225 cai = &ci->ci_cinfo[CAI_DCACHE]; 1226 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1227 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1228 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1229 1230 cai = &ci->ci_cinfo[CAI_ICACHE]; 1231 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1232 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1233 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1234 1235 if (lfunc < 0x80000006) 1236 return; 1237 1238 /* Determine L2 cache/TLB info. */ 1239 x86_cpuid(0x80000006, descs); 1240 1241 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1242 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1243 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1244 cai->cai_linesize = (4 * 1024); 1245 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1246 cai->cai_associativity); 1247 if (cp != NULL) 1248 cai->cai_associativity = cp->cai_associativity; 1249 else 1250 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1251 1252 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1253 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1254 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1255 cai->cai_linesize = largepagesize; 1256 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1257 cai->cai_associativity); 1258 if (cp != NULL) 1259 cai->cai_associativity = cp->cai_associativity; 1260 else 1261 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1262 1263 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1264 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1265 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1266 cai->cai_linesize = (4 * 1024); 1267 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1268 cai->cai_associativity); 1269 if (cp != NULL) 1270 cai->cai_associativity = cp->cai_associativity; 1271 else 1272 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1273 1274 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1275 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1276 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1277 cai->cai_linesize = largepagesize; 1278 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1279 cai->cai_associativity); 1280 if (cp != NULL) 1281 cai->cai_associativity = cp->cai_associativity; 1282 else 1283 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1284 1285 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1286 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1287 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1288 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1289 1290 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1291 cai->cai_associativity); 1292 if (cp != NULL) 1293 cai->cai_associativity = cp->cai_associativity; 1294 else 1295 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1296 1297 /* Determine L3 cache info on AMD Family 10h and newer processors */ 1298 if (ci->ci_family >= 0x10) { 1299 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1300 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1301 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1302 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1303 1304 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1305 cai->cai_associativity); 1306 if (cp != NULL) 1307 cai->cai_associativity = cp->cai_associativity; 1308 else 1309 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1310 } 1311 1312 if (lfunc < 0x80000019) 1313 return; 1314 1315 /* Determine 1GB TLB info. */ 1316 x86_cpuid(0x80000019, descs); 1317 1318 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1319 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1320 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1321 cai->cai_linesize = (1024 * 1024 * 1024); 1322 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1323 cai->cai_associativity); 1324 if (cp != NULL) 1325 cai->cai_associativity = cp->cai_associativity; 1326 else 1327 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1328 1329 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1330 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1331 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1332 cai->cai_linesize = (1024 * 1024 * 1024); 1333 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1334 cai->cai_associativity); 1335 if (cp != NULL) 1336 cai->cai_associativity = cp->cai_associativity; 1337 else 1338 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1339 1340 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1341 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1342 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1343 cai->cai_linesize = (1024 * 1024 * 1024); 1344 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1345 cai->cai_associativity); 1346 if (cp != NULL) 1347 cai->cai_associativity = cp->cai_associativity; 1348 else 1349 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1350 1351 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1352 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1353 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1354 cai->cai_linesize = (1024 * 1024 * 1024); 1355 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1356 cai->cai_associativity); 1357 if (cp != NULL) 1358 cai->cai_associativity = cp->cai_associativity; 1359 else 1360 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1361 1362 if (lfunc < 0x8000001d) 1363 return; 1364 1365 if (ci->ci_feat_val[3] & CPUID_TOPOEXT) 1366 cpu_dcp_cacheinfo(ci, 0x8000001d); 1367 } 1368 1369 static void 1370 via_cpu_cacheinfo(struct cpu_info *ci) 1371 { 1372 struct x86_cache_info *cai; 1373 int stepping; 1374 u_int descs[4]; 1375 u_int lfunc; 1376 1377 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1378 1379 /* 1380 * Determine the largest extended function value. 1381 */ 1382 x86_cpuid(0x80000000, descs); 1383 lfunc = descs[0]; 1384 1385 /* 1386 * Determine L1 cache/TLB info. 1387 */ 1388 if (lfunc < 0x80000005) { 1389 /* No L1 cache info available. */ 1390 return; 1391 } 1392 1393 x86_cpuid(0x80000005, descs); 1394 1395 cai = &ci->ci_cinfo[CAI_ITLB]; 1396 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1397 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1398 cai->cai_linesize = (4 * 1024); 1399 1400 cai = &ci->ci_cinfo[CAI_DTLB]; 1401 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1402 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1403 cai->cai_linesize = (4 * 1024); 1404 1405 cai = &ci->ci_cinfo[CAI_DCACHE]; 1406 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1407 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1408 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1409 if (ci->ci_model == 9 && stepping == 8) { 1410 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1411 cai->cai_associativity = 2; 1412 } 1413 1414 cai = &ci->ci_cinfo[CAI_ICACHE]; 1415 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1416 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1417 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1418 if (ci->ci_model == 9 && stepping == 8) { 1419 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1420 cai->cai_associativity = 2; 1421 } 1422 1423 /* 1424 * Determine L2 cache/TLB info. 1425 */ 1426 if (lfunc < 0x80000006) { 1427 /* No L2 cache info available. */ 1428 return; 1429 } 1430 1431 x86_cpuid(0x80000006, descs); 1432 1433 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1434 if (ci->ci_model >= 9) { 1435 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1436 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1437 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1438 } else { 1439 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1440 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1441 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1442 } 1443 } 1444 1445 static void 1446 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1447 { 1448 u_int descs[4]; 1449 1450 x86_cpuid(0x80860007, descs); 1451 *frequency = descs[0]; 1452 *voltage = descs[1]; 1453 *percentage = descs[2]; 1454 } 1455 1456 static void 1457 transmeta_cpu_info(struct cpu_info *ci) 1458 { 1459 u_int descs[4], nreg; 1460 u_int frequency, voltage, percentage; 1461 1462 x86_cpuid(0x80860000, descs); 1463 nreg = descs[0]; 1464 if (nreg >= 0x80860001) { 1465 x86_cpuid(0x80860001, descs); 1466 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1467 (descs[1] >> 24) & 0xff, 1468 (descs[1] >> 16) & 0xff, 1469 (descs[1] >> 8) & 0xff, 1470 descs[1] & 0xff); 1471 } 1472 if (nreg >= 0x80860002) { 1473 x86_cpuid(0x80860002, descs); 1474 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1475 (descs[1] >> 24) & 0xff, 1476 (descs[1] >> 16) & 0xff, 1477 (descs[1] >> 8) & 0xff, 1478 descs[1] & 0xff, 1479 descs[2]); 1480 } 1481 if (nreg >= 0x80860006) { 1482 union { 1483 char text[65]; 1484 u_int descs[4][4]; 1485 } info; 1486 int i; 1487 1488 for (i=0; i<4; i++) { 1489 x86_cpuid(0x80860003 + i, info.descs[i]); 1490 } 1491 info.text[64] = '\0'; 1492 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1493 } 1494 1495 if (nreg >= 0x80860007) { 1496 tmx86_get_longrun_status(&frequency, 1497 &voltage, &percentage); 1498 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1499 frequency, voltage, percentage); 1500 } 1501 } 1502 1503 static void 1504 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1505 { 1506 u_int descs[4]; 1507 int i; 1508 uint32_t brand[12]; 1509 1510 memset(ci, 0, sizeof(*ci)); 1511 ci->ci_dev = cpuname; 1512 1513 ci->ci_cpu_type = x86_identify(); 1514 if (ci->ci_cpu_type >= 0) { 1515 /* Old pre-cpuid instruction cpu */ 1516 ci->ci_max_cpuid = -1; 1517 return; 1518 } 1519 1520 /* 1521 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1522 * function. 1523 */ 1524 1525 /* 1526 * Fn0000_0000: 1527 * - Save cpuid max level. 1528 * - Save vendor string. 1529 */ 1530 x86_cpuid(0, descs); 1531 ci->ci_max_cpuid = descs[0]; 1532 /* Save vendor string */ 1533 ci->ci_vendor[0] = descs[1]; 1534 ci->ci_vendor[2] = descs[2]; 1535 ci->ci_vendor[1] = descs[3]; 1536 ci->ci_vendor[3] = 0; 1537 1538 /* 1539 * Fn8000_0000: 1540 * - Get cpuid extended function's max level. 1541 */ 1542 x86_cpuid(0x80000000, descs); 1543 if (descs[0] >= 0x80000000) 1544 ci->ci_max_ext_cpuid = descs[0]; 1545 else { 1546 /* Set lower value than 0x80000000 */ 1547 ci->ci_max_ext_cpuid = 0; 1548 } 1549 1550 /* 1551 * Fn8000_000[2-4]: 1552 * - Save brand string. 1553 */ 1554 if (ci->ci_max_ext_cpuid >= 0x80000004) { 1555 x86_cpuid(0x80000002, brand); 1556 x86_cpuid(0x80000003, brand + 4); 1557 x86_cpuid(0x80000004, brand + 8); 1558 for (i = 0; i < 48; i++) 1559 if (((char *) brand)[i] != ' ') 1560 break; 1561 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1562 } 1563 1564 if (ci->ci_max_cpuid < 1) 1565 return; 1566 1567 /* 1568 * Fn0000_0001: 1569 * - Get CPU family, model and stepping (from eax). 1570 * - Initial local APIC ID and brand ID (from ebx) 1571 * - CPUID2 (from ecx) 1572 * - CPUID (from edx) 1573 */ 1574 x86_cpuid(1, descs); 1575 ci->ci_signature = descs[0]; 1576 1577 /* Extract full family/model values */ 1578 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1579 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1580 1581 /* Brand is low order 8 bits of ebx */ 1582 ci->ci_brand_id = __SHIFTOUT(descs[1], CPUID_BRAND_INDEX); 1583 /* Initial local APIC ID */ 1584 ci->ci_initapicid = __SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID); 1585 1586 ci->ci_feat_val[1] = descs[2]; 1587 ci->ci_feat_val[0] = descs[3]; 1588 1589 if (ci->ci_max_cpuid < 3) 1590 return; 1591 1592 /* 1593 * If the processor serial number misfeature is present and supported, 1594 * extract it here. 1595 */ 1596 if ((ci->ci_feat_val[0] & CPUID_PSN) != 0) { 1597 ci->ci_cpu_serial[0] = ci->ci_signature; 1598 x86_cpuid(3, descs); 1599 ci->ci_cpu_serial[2] = descs[2]; 1600 ci->ci_cpu_serial[1] = descs[3]; 1601 } 1602 1603 if (ci->ci_max_cpuid < 0x7) 1604 return; 1605 1606 x86_cpuid(7, descs); 1607 ci->ci_feat_val[5] = descs[1]; 1608 ci->ci_feat_val[6] = descs[2]; 1609 ci->ci_feat_val[7] = descs[3]; 1610 1611 if (ci->ci_max_cpuid < 0xd) 1612 return; 1613 1614 /* Get support XCR0 bits */ 1615 x86_cpuid2(0xd, 0, descs); 1616 ci->ci_feat_val[8] = descs[0]; /* Actually 64 bits */ 1617 ci->ci_cur_xsave = descs[1]; 1618 ci->ci_max_xsave = descs[2]; 1619 1620 /* Additional flags (eg xsaveopt support) */ 1621 x86_cpuid2(0xd, 1, descs); 1622 ci->ci_feat_val[9] = descs[0]; /* Actually 64 bits */ 1623 } 1624 1625 static void 1626 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1627 { 1628 uint32_t descs[4]; 1629 char hv_sig[13]; 1630 char *p; 1631 const char *hv_name; 1632 int i; 1633 1634 /* 1635 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1636 * http://lkml.org/lkml/2008/10/1/246 1637 * 1638 * KB1009458: Mechanisms to determine if software is running in 1639 * a VMware virtual machine 1640 * http://kb.vmware.com/kb/1009458 1641 */ 1642 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1643 x86_cpuid(0x40000000, descs); 1644 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1645 memcpy(p, &descs[i], sizeof(descs[i])); 1646 *p = '\0'; 1647 /* 1648 * HV vendor ID string 1649 * ------------+-------------- 1650 * HAXM "HAXMHAXMHAXM" 1651 * KVM "KVMKVMKVM" 1652 * Microsoft "Microsoft Hv" 1653 * QEMU(TCG) "TCGTCGTCGTCG" 1654 * VMware "VMwareVMware" 1655 * Xen "XenVMMXenVMM" 1656 * NetBSD "___ NVMM ___" 1657 */ 1658 if (strncmp(hv_sig, "HAXMHAXMHAXM", 12) == 0) 1659 hv_name = "HAXM"; 1660 else if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1661 hv_name = "KVM"; 1662 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1663 hv_name = "Hyper-V"; 1664 else if (strncmp(hv_sig, "TCGTCGTCGTCG", 12) == 0) 1665 hv_name = "QEMU(TCG)"; 1666 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1667 hv_name = "VMware"; 1668 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1669 hv_name = "Xen"; 1670 else if (strncmp(hv_sig, "___ NVMM ___", 12) == 0) 1671 hv_name = "NVMM"; 1672 else 1673 hv_name = "unknown"; 1674 1675 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1676 } 1677 } 1678 1679 static void 1680 cpu_probe_features(struct cpu_info *ci) 1681 { 1682 const struct cpu_cpuid_nameclass *cpup = NULL; 1683 unsigned int i; 1684 1685 if (ci->ci_max_cpuid < 1) 1686 return; 1687 1688 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1689 if (!strncmp((char *)ci->ci_vendor, 1690 i386_cpuid_cpus[i].cpu_id, 12)) { 1691 cpup = &i386_cpuid_cpus[i]; 1692 break; 1693 } 1694 } 1695 1696 if (cpup == NULL) 1697 return; 1698 1699 i = ci->ci_family - CPU_MINFAMILY; 1700 1701 if (i >= __arraycount(cpup->cpu_family)) 1702 i = __arraycount(cpup->cpu_family) - 1; 1703 1704 if (cpup->cpu_family[i].cpu_probe == NULL) 1705 return; 1706 1707 (*cpup->cpu_family[i].cpu_probe)(ci); 1708 } 1709 1710 static void 1711 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1712 { 1713 char buf[32 * 16]; 1714 char *bp; 1715 1716 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1717 1718 if (val == 0 || fmt == NULL) 1719 return; 1720 1721 snprintb_m(buf, sizeof(buf), fmt, val, 1722 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1723 bp = buf; 1724 while (*bp != '\0') { 1725 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1726 bp += strlen(bp) + 1; 1727 } 1728 } 1729 #ifdef lint 1730 #define print_bits(cpuname, hdr, fmt, val) \ 1731 do { \ 1732 print_bits(cpuname, hdr, fmt, val); \ 1733 snprintb(NULL, 0, fmt, val); \ 1734 } while (0) 1735 #endif 1736 1737 static void 1738 dump_descs(uint32_t leafstart, uint32_t leafend, const char *cpuname, 1739 const char *blockname) 1740 { 1741 uint32_t descs[4]; 1742 uint32_t leaf; 1743 1744 aprint_verbose("%s: highest %s info %08x\n", cpuname, blockname, 1745 leafend); 1746 1747 if (verbose) { 1748 for (leaf = leafstart; leaf <= leafend; leaf++) { 1749 x86_cpuid(leaf, descs); 1750 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1751 leaf, descs[0], descs[1], descs[2], descs[3]); 1752 } 1753 } 1754 } 1755 1756 static void 1757 identifycpu_cpuids_intel_0x04(struct cpu_info *ci) 1758 { 1759 u_int lp_max = 1; /* logical processors per package */ 1760 u_int smt_max; /* smt per core */ 1761 u_int core_max = 1; /* core per package */ 1762 u_int smt_bits, core_bits; 1763 uint32_t descs[4]; 1764 1765 /* 1766 * 253668.pdf 7.10.2 1767 */ 1768 1769 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1770 x86_cpuid(1, descs); 1771 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1772 } 1773 x86_cpuid2(4, 0, descs); 1774 core_max = __SHIFTOUT(descs[0], CPUID_DCP_CORE_P_PKG) + 1; 1775 1776 assert(lp_max >= core_max); 1777 smt_max = lp_max / core_max; 1778 smt_bits = ilog2(smt_max - 1) + 1; 1779 core_bits = ilog2(core_max - 1) + 1; 1780 1781 if (smt_bits + core_bits) 1782 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1783 1784 if (core_bits) 1785 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1786 __BITS(smt_bits, smt_bits + core_bits - 1)); 1787 1788 if (smt_bits) 1789 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1790 __BITS((int)0, (int)(smt_bits - 1))); 1791 } 1792 1793 static void 1794 identifycpu_cpuids_intel_0x0b(struct cpu_info *ci) 1795 { 1796 const char *cpuname = ci->ci_dev; 1797 u_int smt_bits, core_bits, core_shift = 0, pkg_shift = 0; 1798 uint32_t descs[4]; 1799 int i; 1800 1801 x86_cpuid(0x0b, descs); 1802 if (descs[1] == 0) { 1803 identifycpu_cpuids_intel_0x04(ci); 1804 return; 1805 } 1806 1807 for (i = 0; ; i++) { 1808 unsigned int shiftnum, lvltype; 1809 x86_cpuid2(0x0b, i, descs); 1810 1811 /* On invalid level, (EAX and) EBX return 0 */ 1812 if (descs[1] == 0) 1813 break; 1814 1815 shiftnum = __SHIFTOUT(descs[0], CPUID_TOP_SHIFTNUM); 1816 lvltype = __SHIFTOUT(descs[2], CPUID_TOP_LVLTYPE); 1817 switch (lvltype) { 1818 case CPUID_TOP_LVLTYPE_SMT: 1819 core_shift = shiftnum; 1820 break; 1821 case CPUID_TOP_LVLTYPE_CORE: 1822 pkg_shift = shiftnum; 1823 break; 1824 case CPUID_TOP_LVLTYPE_INVAL: 1825 aprint_verbose("%s: Invalid level type\n", cpuname); 1826 break; 1827 default: 1828 aprint_verbose("%s: Unknown level type(%d) \n", 1829 cpuname, lvltype); 1830 break; 1831 } 1832 } 1833 1834 assert(pkg_shift >= core_shift); 1835 smt_bits = core_shift; 1836 core_bits = pkg_shift - core_shift; 1837 1838 ci->ci_packageid = ci->ci_initapicid >> pkg_shift; 1839 1840 if (core_bits) 1841 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1842 __BITS(core_shift, pkg_shift - 1)); 1843 1844 if (smt_bits) 1845 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1846 __BITS((int)0, core_shift - 1)); 1847 } 1848 1849 static void 1850 identifycpu_cpuids_intel(struct cpu_info *ci) 1851 { 1852 const char *cpuname = ci->ci_dev; 1853 1854 if (ci->ci_max_cpuid >= 0x0b) 1855 identifycpu_cpuids_intel_0x0b(ci); 1856 else if (ci->ci_max_cpuid >= 4) 1857 identifycpu_cpuids_intel_0x04(ci); 1858 1859 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1860 ci->ci_packageid); 1861 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1862 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1863 } 1864 1865 static void 1866 identifycpu_cpuids_amd(struct cpu_info *ci) 1867 { 1868 const char *cpuname = ci->ci_dev; 1869 u_int lp_max, core_max; 1870 int n, cpu_family, apic_id, smt_bits, core_bits = 0; 1871 uint32_t descs[4]; 1872 1873 apic_id = ci->ci_initapicid; 1874 cpu_family = CPUID_TO_FAMILY(ci->ci_signature); 1875 1876 if (cpu_family < 0xf) 1877 return; 1878 1879 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1880 x86_cpuid(1, descs); 1881 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1882 1883 if (cpu_family >= 0x10 && ci->ci_max_ext_cpuid >= 0x8000008) { 1884 x86_cpuid(0x8000008, descs); 1885 core_max = (descs[2] & 0xff) + 1; 1886 n = (descs[2] >> 12) & 0x0f; 1887 if (n != 0) 1888 core_bits = n; 1889 } 1890 } else { 1891 lp_max = 1; 1892 } 1893 core_max = lp_max; 1894 1895 smt_bits = ilog2((lp_max / core_max) - 1) + 1; 1896 if (core_bits == 0) 1897 core_bits = ilog2(core_max - 1) + 1; 1898 1899 #if 0 /* MSRs need kernel mode */ 1900 if (cpu_family < 0x11) { 1901 const uint64_t reg = rdmsr(MSR_NB_CFG); 1902 if ((reg & NB_CFG_INITAPICCPUIDLO) == 0) { 1903 const u_int node_id = apic_id & __BITS(0, 2); 1904 apic_id = (cpu_family == 0xf) ? 1905 (apic_id >> core_bits) | (node_id << core_bits) : 1906 (apic_id >> 5) | (node_id << 2); 1907 } 1908 } 1909 #endif 1910 1911 if (cpu_family >= 0x17) { 1912 x86_cpuid(0x8000001e, descs); 1913 const u_int threads = ((descs[1] >> 8) & 0xff) + 1; 1914 smt_bits = ilog2(threads); 1915 core_bits -= smt_bits; 1916 } 1917 1918 if (smt_bits + core_bits) { 1919 if (smt_bits + core_bits < 32) 1920 ci->ci_packageid = 0; 1921 } 1922 if (core_bits) { 1923 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1924 ci->ci_coreid = __SHIFTOUT(apic_id, core_mask); 1925 } 1926 if (smt_bits) { 1927 u_int smt_mask = __BITS(0, smt_bits - 1); 1928 ci->ci_smtid = __SHIFTOUT(apic_id, smt_mask); 1929 } 1930 1931 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1932 ci->ci_packageid); 1933 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1934 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1935 } 1936 1937 static void 1938 identifycpu_cpuids(struct cpu_info *ci) 1939 { 1940 const char *cpuname = ci->ci_dev; 1941 1942 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1943 ci->ci_packageid = ci->ci_initapicid; 1944 ci->ci_coreid = 0; 1945 ci->ci_smtid = 0; 1946 1947 if (cpu_vendor == CPUVENDOR_INTEL) 1948 identifycpu_cpuids_intel(ci); 1949 else if (cpu_vendor == CPUVENDOR_AMD) 1950 identifycpu_cpuids_amd(ci); 1951 } 1952 1953 void 1954 identifycpu(int fd, const char *cpuname) 1955 { 1956 const char *name = "", *modifier, *vendorname, *brand = ""; 1957 int class = CPUCLASS_386; 1958 unsigned int i; 1959 int modif, family; 1960 const struct cpu_cpuid_nameclass *cpup = NULL; 1961 const struct cpu_cpuid_family *cpufam; 1962 struct cpu_info *ci, cistore; 1963 u_int descs[4]; 1964 size_t sz; 1965 struct cpu_ucode_version ucode; 1966 union { 1967 struct cpu_ucode_version_amd amd; 1968 struct cpu_ucode_version_intel1 intel1; 1969 } ucvers; 1970 1971 ci = &cistore; 1972 cpu_probe_base_features(ci, cpuname); 1973 dump_descs(0x00000000, ci->ci_max_cpuid, cpuname, "basic"); 1974 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1975 x86_cpuid(0x40000000, descs); 1976 dump_descs(0x40000000, descs[0], cpuname, "hypervisor"); 1977 } 1978 dump_descs(0x80000000, ci->ci_max_ext_cpuid, cpuname, "extended"); 1979 1980 cpu_probe_hv_features(ci, cpuname); 1981 cpu_probe_features(ci); 1982 1983 if (ci->ci_cpu_type >= 0) { 1984 /* Old pre-cpuid instruction cpu */ 1985 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1986 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1987 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1988 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1989 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1990 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1991 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1992 modifier = ""; 1993 } else { 1994 /* CPU which support cpuid instruction */ 1995 modif = (ci->ci_signature >> 12) & 0x3; 1996 family = ci->ci_family; 1997 if (family < CPU_MINFAMILY) 1998 errx(1, "identifycpu: strange family value"); 1999 if (family > CPU_MAXFAMILY) 2000 family = CPU_MAXFAMILY; 2001 2002 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 2003 if (!strncmp((char *)ci->ci_vendor, 2004 i386_cpuid_cpus[i].cpu_id, 12)) { 2005 cpup = &i386_cpuid_cpus[i]; 2006 break; 2007 } 2008 } 2009 2010 if (cpup == NULL) { 2011 cpu_vendor = CPUVENDOR_UNKNOWN; 2012 if (ci->ci_vendor[0] != '\0') 2013 vendorname = (char *)&ci->ci_vendor[0]; 2014 else 2015 vendorname = "Unknown"; 2016 class = family - 3; 2017 modifier = ""; 2018 name = ""; 2019 ci->ci_info = NULL; 2020 } else { 2021 cpu_vendor = cpup->cpu_vendor; 2022 vendorname = cpup->cpu_vendorname; 2023 modifier = modifiers[modif]; 2024 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 2025 name = cpufam->cpu_models[ci->ci_model]; 2026 if (name == NULL || *name == '\0') 2027 name = cpufam->cpu_model_default; 2028 class = cpufam->cpu_class; 2029 ci->ci_info = cpufam->cpu_info; 2030 2031 if (cpu_vendor == CPUVENDOR_INTEL) { 2032 if (ci->ci_family == 6 && ci->ci_model >= 5) { 2033 const char *tmp; 2034 tmp = intel_family6_name(ci); 2035 if (tmp != NULL) 2036 name = tmp; 2037 } 2038 if (ci->ci_family == 15 && 2039 ci->ci_brand_id < 2040 __arraycount(i386_intel_brand) && 2041 i386_intel_brand[ci->ci_brand_id]) 2042 name = 2043 i386_intel_brand[ci->ci_brand_id]; 2044 } 2045 2046 if (cpu_vendor == CPUVENDOR_AMD) { 2047 if (ci->ci_family == 6 && ci->ci_model >= 6) { 2048 if (ci->ci_brand_id == 1) 2049 /* 2050 * It's Duron. We override the 2051 * name, since it might have 2052 * been misidentified as Athlon. 2053 */ 2054 name = 2055 amd_brand[ci->ci_brand_id]; 2056 else 2057 brand = amd_brand_name; 2058 } 2059 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 2060 == 0xf) { 2061 /* Identify AMD64 CPU names. */ 2062 const char *tmp; 2063 tmp = amd_amd64_name(ci); 2064 if (tmp != NULL) 2065 name = tmp; 2066 } 2067 } 2068 2069 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 2070 vendorname = "VIA"; 2071 } 2072 } 2073 2074 ci->ci_cpu_class = class; 2075 2076 sz = sizeof(ci->ci_tsc_freq); 2077 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 2078 sz = sizeof(use_pae); 2079 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 2080 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 2081 2082 /* 2083 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 2084 * we try to determine from the family/model values. 2085 */ 2086 if (*cpu_brand_string != '\0') 2087 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 2088 2089 aprint_normal("%s: %s", cpuname, vendorname); 2090 if (*modifier) 2091 aprint_normal(" %s", modifier); 2092 if (*name) 2093 aprint_normal(" %s", name); 2094 if (*brand) 2095 aprint_normal(" %s", brand); 2096 aprint_normal(" (%s-class)", classnames[class]); 2097 2098 if (ci->ci_tsc_freq != 0) 2099 aprint_normal(", %ju.%02ju MHz", 2100 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 2101 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 2102 aprint_normal("\n"); 2103 2104 (void)cpu_tsc_freq_cpuid(ci); 2105 2106 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 2107 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 2108 if (ci->ci_signature != 0) 2109 aprint_normal(" (id %#x)", ci->ci_signature); 2110 aprint_normal("\n"); 2111 2112 if (ci->ci_info) 2113 (*ci->ci_info)(ci); 2114 2115 /* 2116 * display CPU feature flags 2117 */ 2118 2119 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 2120 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 2121 2122 /* These next two are actually common definitions! */ 2123 print_bits(cpuname, "features2", 2124 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 2125 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 2126 print_bits(cpuname, "features3", 2127 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 2128 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 2129 2130 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 2131 ci->ci_feat_val[4]); 2132 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2133 print_bits(cpuname, "features5", CPUID_SEF_FLAGS, 2134 ci->ci_feat_val[5]); 2135 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2136 print_bits(cpuname, "features6", CPUID_SEF_FLAGS1, 2137 ci->ci_feat_val[6]); 2138 2139 if (cpu_vendor == CPUVENDOR_INTEL) 2140 print_bits(cpuname, "features7", CPUID_SEF_FLAGS2, 2141 ci->ci_feat_val[7]); 2142 2143 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[8]); 2144 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 2145 ci->ci_feat_val[9]); 2146 2147 if (ci->ci_max_xsave != 0) { 2148 aprint_normal("%s: xsave area size: current %d, maximum %d", 2149 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 2150 aprint_normal(", xgetbv %sabled\n", 2151 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 2152 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 2153 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 2154 x86_xgetbv()); 2155 } 2156 2157 x86_print_cache_and_tlb_info(ci); 2158 2159 if (ci->ci_max_cpuid >= 3 && (ci->ci_feat_val[0] & CPUID_PSN)) { 2160 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 2161 cpuname, 2162 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 2163 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 2164 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 2165 } 2166 2167 if (ci->ci_cpu_class == CPUCLASS_386) 2168 errx(1, "NetBSD requires an 80486 or later processor"); 2169 2170 if (ci->ci_cpu_type == CPU_486DLC) { 2171 #ifndef CYRIX_CACHE_WORKS 2172 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 2173 #else 2174 #ifndef CYRIX_CACHE_REALLY_WORKS 2175 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 2176 #else 2177 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 2178 #endif 2179 #endif 2180 } 2181 2182 /* 2183 * Everything past this point requires a Pentium or later. 2184 */ 2185 if (ci->ci_max_cpuid < 0) 2186 return; 2187 2188 identifycpu_cpuids(ci); 2189 2190 if ((ci->ci_max_cpuid >= 5) 2191 && ((cpu_vendor == CPUVENDOR_INTEL) 2192 || (cpu_vendor == CPUVENDOR_AMD))) { 2193 uint16_t lmin, lmax; 2194 x86_cpuid(5, descs); 2195 2196 print_bits(cpuname, "MONITOR/MWAIT extensions", 2197 CPUID_MON_FLAGS, descs[2]); 2198 lmin = __SHIFTOUT(descs[0], CPUID_MON_MINSIZE); 2199 lmax = __SHIFTOUT(descs[1], CPUID_MON_MAXSIZE); 2200 aprint_normal("%s: monitor-line size %hu", cpuname, lmin); 2201 if (lmin != lmax) 2202 aprint_normal("-%hu", lmax); 2203 aprint_normal("\n"); 2204 2205 for (i = 0; i <= 7; i++) { 2206 unsigned int num = CPUID_MON_SUBSTATE(descs[3], i); 2207 2208 if (num != 0) 2209 aprint_normal("%s: C%u substates %u\n", 2210 cpuname, i, num); 2211 } 2212 } 2213 if ((ci->ci_max_cpuid >= 6) 2214 && ((cpu_vendor == CPUVENDOR_INTEL) 2215 || (cpu_vendor == CPUVENDOR_AMD))) { 2216 x86_cpuid(6, descs); 2217 print_bits(cpuname, "DSPM-eax", CPUID_DSPM_FLAGS, descs[0]); 2218 print_bits(cpuname, "DSPM-ecx", CPUID_DSPM_FLAGS1, descs[2]); 2219 } 2220 if ((ci->ci_max_cpuid >= 7) 2221 && ((cpu_vendor == CPUVENDOR_INTEL) 2222 || (cpu_vendor == CPUVENDOR_AMD))) { 2223 unsigned int maxsubleaf; 2224 2225 x86_cpuid(7, descs); 2226 maxsubleaf = descs[0]; 2227 aprint_verbose("%s: SEF highest subleaf %08x\n", 2228 cpuname, maxsubleaf); 2229 if (maxsubleaf >= 1) { 2230 x86_cpuid2(7, 1, descs); 2231 print_bits(cpuname, "SEF-subleaf1-eax", 2232 CPUID_SEF1_FLAGS_A, descs[0]); 2233 print_bits(cpuname, "SEF-subleaf1-ebx", 2234 CPUID_SEF1_FLAGS_B, descs[1]); 2235 print_bits(cpuname, "SEF-subleaf1-edx", 2236 CPUID_SEF1_FLAGS_D, descs[3]); 2237 } 2238 if (maxsubleaf >= 2) { 2239 x86_cpuid2(7, 2, descs); 2240 print_bits(cpuname, "SEF-subleaf2-edx", 2241 CPUID_SEF2_FLAGS_D, descs[3]); 2242 } 2243 } 2244 2245 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) { 2246 if (ci->ci_max_ext_cpuid >= 0x80000007) 2247 powernow_probe(ci); 2248 2249 if (ci->ci_max_ext_cpuid >= 0x80000008) { 2250 x86_cpuid(0x80000008, descs); 2251 print_bits(cpuname, "AMD Extended features", 2252 CPUID_CAPEX_FLAGS, descs[1]); 2253 } 2254 } 2255 2256 if (cpu_vendor == CPUVENDOR_AMD) { 2257 if (ci->ci_max_ext_cpuid >= 0x80000021) { 2258 x86_cpuid(0x80000021, descs); 2259 print_bits(cpuname, "AMD Extended features2", 2260 CPUID_AMDEXT2_FLAGS, descs[0]); 2261 } 2262 2263 if (ci->ci_max_ext_cpuid >= 0x80000007) { 2264 x86_cpuid(0x80000007, descs); 2265 print_bits(cpuname, "RAS features", 2266 CPUID_RAS_FLAGS, descs[1]); 2267 } 2268 if ((ci->ci_max_ext_cpuid >= 0x8000000a) 2269 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 2270 x86_cpuid(0x8000000a, descs); 2271 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 2272 descs[0] & 0xf); 2273 aprint_verbose("%s: SVM NASID %d\n", cpuname, 2274 descs[1]); 2275 print_bits(cpuname, "SVM features", 2276 CPUID_AMD_SVM_FLAGS, descs[3]); 2277 } 2278 if (ci->ci_max_ext_cpuid >= 0x8000001b) { 2279 x86_cpuid(0x8000001b, descs); 2280 print_bits(cpuname, "IBS features", 2281 CPUID_IBS_FLAGS, descs[0]); 2282 } 2283 if (ci->ci_max_ext_cpuid >= 0x8000001f) { 2284 x86_cpuid(0x8000001f, descs); 2285 print_bits(cpuname, "Encrypted Memory features", 2286 CPUID_AMD_ENCMEM_FLAGS, descs[0]); 2287 } 2288 if (ci->ci_max_ext_cpuid >= 0x80000022) { 2289 uint8_t ncore, nnb, numc, nlbrs; 2290 2291 x86_cpuid(0x80000022, descs); 2292 print_bits(cpuname, "Perfmon:", 2293 CPUID_AXPERF_FLAGS, descs[0]); 2294 2295 ncore = __SHIFTOUT(descs[1], CPUID_AXPERF_NCPC); 2296 nnb = __SHIFTOUT(descs[1], CPUID_AXPERF_NNBPC); 2297 numc = __SHIFTOUT(descs[1], CPUID_AXPERF_NUMCPC); 2298 nlbrs = __SHIFTOUT(descs[1], CPUID_AXPERF_NLBRSTACK); 2299 aprint_verbose("%s: Perfmon: counters: " 2300 "Core %hhu, Northbridge %hhu, UMC %hhu\n", cpuname, 2301 ncore, nnb, numc); 2302 aprint_verbose("%s: Perfmon: LBR Stack %hhu entries\n", 2303 cpuname, nlbrs); 2304 } 2305 } else if (cpu_vendor == CPUVENDOR_INTEL) { 2306 if (ci->ci_max_cpuid >= 0x0a) { 2307 unsigned int pmcver, ncounter, veclen; 2308 2309 x86_cpuid(0x0a, descs); 2310 pmcver = __SHIFTOUT(descs[0], CPUID_PERF_VERSION); 2311 ncounter = __SHIFTOUT(descs[0], CPUID_PERF_NGPPC); 2312 veclen = __SHIFTOUT(descs[0], CPUID_PERF_BVECLEN); 2313 aprint_verbose("%s: Perfmon: Ver. %u", 2314 cpuname, pmcver); 2315 if (((pmcver >= 3) && (pmcver <= 4)) || 2316 ((pmcver >= 5) && 2317 (descs[3] & CPUID_PERF_ANYTHREADDEPR) == 0)) 2318 aprint_verbose(" <ANYTHREAD>\n"); 2319 else 2320 aprint_verbose("\n"); 2321 2322 aprint_verbose("%s: Perfmon: General: " 2323 "bitwidth %u, %u counters\n", cpuname, 2324 (uint32_t)__SHIFTOUT(descs[0], CPUID_PERF_NBWGPPC), 2325 ncounter); 2326 /* Invert logic for the output */ 2327 descs[1] ^= __BITS(veclen - 1, 0); 2328 /* 2329 * Mask unrelated bits. An hypervisor reduces the 2330 * vector and set bit(s) out of the vector. 2331 */ 2332 descs[1] &= __BITS(veclen - 1, 0); 2333 print_bits(cpuname, "Perfmon: General: avail", 2334 CPUID_PERF_FLAGS1, descs[1]); 2335 2336 if (pmcver >= 2) { 2337 ncounter = __SHIFTOUT(descs[3], 2338 CPUID_PERF_NFFPC); 2339 aprint_verbose("%s: Perfmon: Fixed: " 2340 "bitwidth %u, %u counters\n", cpuname, 2341 (uint32_t)__SHIFTOUT(descs[3], 2342 CPUID_PERF_NBWFFPC), 2343 ncounter); 2344 if (pmcver <= 4) 2345 descs[2] = __BITS(ncounter - 1, 0); 2346 print_bits(cpuname, "Perfmon: Fixed: avail", 2347 CPUID_PERF_FLAGS2, descs[2]); 2348 } 2349 } 2350 if (ci->ci_max_cpuid >= 0x1a) { 2351 x86_cpuid(0x1a, descs); 2352 if (descs[0] != 0) { 2353 aprint_verbose("%s: Hybrid: Core type %02x, " 2354 "Native Model ID %07x\n", 2355 cpuname, 2356 (uint8_t)__SHIFTOUT(descs[0], 2357 CPUID_HYBRID_CORETYPE), 2358 (uint32_t)__SHIFTOUT(descs[0], 2359 CPUID_HYBRID_NATIVEID)); 2360 } 2361 } 2362 } 2363 2364 #ifdef INTEL_ONDEMAND_CLOCKMOD 2365 clockmod_init(); 2366 #endif 2367 2368 if (cpu_vendor == CPUVENDOR_AMD) 2369 ucode.loader_version = CPU_UCODE_LOADER_AMD; 2370 else if (cpu_vendor == CPUVENDOR_INTEL) 2371 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 2372 else 2373 return; 2374 2375 ucode.data = &ucvers; 2376 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 2377 #ifdef __i386__ 2378 struct cpu_ucode_version_64 ucode_64; 2379 if (errno != ENOTTY) 2380 return; 2381 /* Try the 64 bit ioctl */ 2382 memset(&ucode_64, 0, sizeof ucode_64); 2383 ucode_64.data = &ucvers; 2384 ucode_64.loader_version = ucode.loader_version; 2385 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 2386 return; 2387 #else 2388 return; 2389 #endif 2390 } 2391 2392 if (cpu_vendor == CPUVENDOR_AMD) 2393 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2394 else if (cpu_vendor == CPUVENDOR_INTEL) 2395 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2396 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2397 } 2398 2399 static const char * 2400 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2401 const char *sep) 2402 { 2403 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2404 char human_num[HUMAN_BUFSIZE]; 2405 2406 if (cai->cai_totalsize == 0) 2407 return sep; 2408 2409 if (sep == NULL) 2410 aprint_verbose_dev(ci->ci_dev, ""); 2411 else 2412 aprint_verbose("%s", sep); 2413 if (name != NULL) 2414 aprint_verbose("%s ", name); 2415 2416 if (cai->cai_string != NULL) { 2417 aprint_verbose("%s ", cai->cai_string); 2418 } else { 2419 (void)humanize_number(human_num, sizeof(human_num), 2420 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2421 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2422 } 2423 switch (cai->cai_associativity) { 2424 case 0: 2425 aprint_verbose("disabled"); 2426 break; 2427 case 1: 2428 aprint_verbose("direct-mapped"); 2429 break; 2430 case 0xff: 2431 aprint_verbose("fully associative"); 2432 break; 2433 default: 2434 aprint_verbose("%d-way", cai->cai_associativity); 2435 break; 2436 } 2437 return ", "; 2438 } 2439 2440 static const char * 2441 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2442 const char *sep) 2443 { 2444 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2445 char human_num[HUMAN_BUFSIZE]; 2446 2447 if (cai->cai_totalsize == 0) 2448 return sep; 2449 2450 if (sep == NULL) 2451 aprint_verbose_dev(ci->ci_dev, ""); 2452 else 2453 aprint_verbose("%s", sep); 2454 if ((name != NULL) && (sep == NULL)) 2455 aprint_verbose("%s ", name); 2456 2457 if (cai->cai_string != NULL) { 2458 aprint_verbose("%s", cai->cai_string); 2459 } else { 2460 (void)humanize_number(human_num, sizeof(human_num), 2461 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2462 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2463 human_num); 2464 switch (cai->cai_associativity) { 2465 case 0: 2466 aprint_verbose("disabled"); 2467 break; 2468 case 1: 2469 aprint_verbose("direct-mapped"); 2470 break; 2471 case 0xff: 2472 aprint_verbose("fully associative"); 2473 break; 2474 default: 2475 aprint_verbose("%d-way", cai->cai_associativity); 2476 break; 2477 } 2478 } 2479 return ", "; 2480 } 2481 2482 static void 2483 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2484 { 2485 const char *sep = NULL; 2486 2487 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2488 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2489 sep = print_cache_config(ci, CAI_ICACHE, "I-cache:", NULL); 2490 sep = print_cache_config(ci, CAI_DCACHE, "D-cache:", sep); 2491 if (sep != NULL) 2492 aprint_verbose("\n"); 2493 } 2494 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2495 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache:", NULL); 2496 if (sep != NULL) 2497 aprint_verbose("\n"); 2498 } 2499 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2500 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache:", NULL); 2501 if (sep != NULL) 2502 aprint_verbose("\n"); 2503 } 2504 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2505 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2506 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2507 if (sep != NULL) 2508 aprint_verbose("\n"); 2509 } 2510 2511 sep = print_tlb_config(ci, CAI_ITLB, "ITLB:", NULL); 2512 sep = print_tlb_config(ci, CAI_ITLB2, "ITLB:", sep); 2513 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "ITLB:", sep); 2514 if (sep != NULL) 2515 aprint_verbose("\n"); 2516 2517 sep = print_tlb_config(ci, CAI_DTLB, "DTLB:", NULL); 2518 sep = print_tlb_config(ci, CAI_DTLB2, "DTLB:", sep); 2519 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "DTLB:", sep); 2520 if (sep != NULL) 2521 aprint_verbose("\n"); 2522 2523 sep = print_tlb_config(ci, CAI_L1_LD_TLB, "Load only TLB:", NULL); 2524 if (sep != NULL) 2525 aprint_verbose("\n"); 2526 2527 sep = print_tlb_config(ci, CAI_L1_ST_TLB, "Store only TLB:", NULL); 2528 if (sep != NULL) 2529 aprint_verbose("\n"); 2530 2531 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB:", NULL); 2532 sep = print_tlb_config(ci, CAI_L2_ITLB2, "L2 ITLB:", sep); 2533 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 ITLB:", sep); 2534 if (sep != NULL) 2535 aprint_verbose("\n"); 2536 2537 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB:", NULL); 2538 sep = print_tlb_config(ci, CAI_L2_DTLB2, "L2 DTLB:", sep); 2539 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 DTLB:", sep); 2540 if (sep != NULL) 2541 aprint_verbose("\n"); 2542 2543 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB:", NULL); 2544 sep = print_tlb_config(ci, CAI_L2_STLB2, "L2 STLB:", sep); 2545 sep = print_tlb_config(ci, CAI_L2_STLB3, "L2 STLB:", sep); 2546 if (sep != NULL) 2547 aprint_verbose("\n"); 2548 } 2549 2550 static void 2551 powernow_probe(struct cpu_info *ci) 2552 { 2553 uint32_t regs[4]; 2554 char buf[256]; 2555 2556 x86_cpuid(0x80000007, regs); 2557 2558 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2559 aprint_normal_dev(ci->ci_dev, "Power Management features: %s\n", buf); 2560 } 2561 2562 bool 2563 identifycpu_bind(void) 2564 { 2565 2566 return true; 2567 } 2568 2569 int 2570 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2571 { 2572 struct cpu_info ci; 2573 int loader_version, res; 2574 struct cpu_ucode_version versreq; 2575 2576 cpu_probe_base_features(&ci, "unknown"); 2577 2578 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2579 loader_version = CPU_UCODE_LOADER_AMD; 2580 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2581 loader_version = CPU_UCODE_LOADER_INTEL1; 2582 else 2583 return -1; 2584 2585 /* check whether the kernel understands this loader version */ 2586 versreq.loader_version = loader_version; 2587 versreq.data = 0; 2588 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2589 if (res) 2590 return -1; 2591 2592 switch (loader_version) { 2593 case CPU_UCODE_LOADER_AMD: 2594 if (uc->cpu_nr != -1) { 2595 /* printf? */ 2596 return -1; 2597 } 2598 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2599 break; 2600 case CPU_UCODE_LOADER_INTEL1: 2601 if (uc->cpu_nr == -1) 2602 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2603 else 2604 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2605 break; 2606 default: /* can't happen */ 2607 return -1; 2608 } 2609 uc->loader_version = loader_version; 2610 return 0; 2611 } 2612
Indexes created Sun Oct 26 21:10:03 GMT 2025