i386.c revision 1.136
1 /* $NetBSD: i386.c,v 1.136 2023/02/14 15:46:06 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.136 2023/02/14 15:46:06 msaitoh Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cpu_ucode.h> 85 86 #include "../cpuctl.h" 87 #include "cpuctl_i386.h" 88 89 /* Size of buffer for printing humanized numbers */ 90 #define HUMAN_BUFSIZE sizeof("999KB") 91 92 struct cpu_nocpuid_nameclass { 93 int cpu_vendor; 94 const char *cpu_vendorname; 95 const char *cpu_name; 96 int cpu_class; 97 void (*cpu_setup)(struct cpu_info *); 98 void (*cpu_cacheinfo)(struct cpu_info *); 99 void (*cpu_info)(struct cpu_info *); 100 }; 101 102 struct cpu_cpuid_nameclass { 103 const char *cpu_id; 104 int cpu_vendor; 105 const char *cpu_vendorname; 106 struct cpu_cpuid_family { 107 int cpu_class; 108 const char *cpu_models[256]; 109 const char *cpu_model_default; 110 void (*cpu_setup)(struct cpu_info *); 111 void (*cpu_probe)(struct cpu_info *); 112 void (*cpu_info)(struct cpu_info *); 113 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 114 }; 115 116 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 117 118 /* 119 * Map Brand ID from cpuid instruction to brand name. 120 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 121 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 122 * Architectures Software Developer's Manual, Volume 2A". 123 */ 124 static const char * const i386_intel_brand[] = { 125 "", /* Unsupported */ 126 "Celeron", /* Intel (R) Celeron (TM) processor */ 127 "Pentium III", /* Intel (R) Pentium (R) III processor */ 128 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 129 "Pentium III", /* Intel (R) Pentium (R) III processor */ 130 "", /* 0x05: Reserved */ 131 "Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */ 132 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 133 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 134 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 135 "Celeron", /* Intel (R) Celeron (TM) processor */ 136 "Xeon", /* Intel (R) Xeon (TM) processor */ 137 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 138 "", /* 0x0d: Reserved */ 139 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 140 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 141 "", /* 0x10: Reserved */ 142 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 143 "Celeron M", /* Intel (R) Celeron (R) M processor */ 144 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 145 "Celeron", /* Intel (R) Celeron (R) processor */ 146 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 147 "Pentium M", /* Intel (R) Pentium (R) M processor */ 148 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 149 }; 150 151 /* 152 * AMD processors don't have Brand IDs, so we need these names for probe. 153 */ 154 static const char * const amd_brand[] = { 155 "", 156 "Duron", /* AMD Duron(tm) */ 157 "MP", /* AMD Athlon(tm) MP */ 158 "XP", /* AMD Athlon(tm) XP */ 159 "4" /* AMD Athlon(tm) 4 */ 160 }; 161 162 int cpu_vendor; 163 static char cpu_brand_string[49]; 164 static char amd_brand_name[48]; 165 static int use_pae, largepagesize; 166 167 /* Setup functions */ 168 static void disable_tsc(struct cpu_info *); 169 static void amd_family5_setup(struct cpu_info *); 170 static void cyrix6x86_cpu_setup(struct cpu_info *); 171 static void winchip_cpu_setup(struct cpu_info *); 172 /* Brand/Model name functions */ 173 static const char *intel_family6_name(struct cpu_info *); 174 static const char *amd_amd64_name(struct cpu_info *); 175 /* Probe functions */ 176 static void amd_family6_probe(struct cpu_info *); 177 static void powernow_probe(struct cpu_info *); 178 static void intel_family_new_probe(struct cpu_info *); 179 static void via_cpu_probe(struct cpu_info *); 180 /* (Cache) Info functions */ 181 static void intel_cpu_cacheinfo(struct cpu_info *); 182 static void amd_cpu_cacheinfo(struct cpu_info *); 183 static void via_cpu_cacheinfo(struct cpu_info *); 184 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 185 static void transmeta_cpu_info(struct cpu_info *); 186 /* Common functions */ 187 static void cpu_probe_base_features(struct cpu_info *, const char *); 188 static void cpu_probe_hv_features(struct cpu_info *, const char *); 189 static void cpu_probe_features(struct cpu_info *); 190 static void print_bits(const char *, const char *, const char *, uint32_t); 191 static void identifycpu_cpuids(struct cpu_info *); 192 static const char *print_cache_config(struct cpu_info *, int, const char *, 193 const char *); 194 static const char *print_tlb_config(struct cpu_info *, int, const char *, 195 const char *); 196 static void x86_print_cache_and_tlb_info(struct cpu_info *); 197 198 /* 199 * Note: these are just the ones that may not have a cpuid instruction. 200 * We deal with the rest in a different way. 201 */ 202 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 203 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 204 NULL, NULL, NULL }, /* CPU_386SX */ 205 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 206 NULL, NULL, NULL }, /* CPU_386 */ 207 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 208 NULL, NULL, NULL }, /* CPU_486SX */ 209 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 210 NULL, NULL, NULL }, /* CPU_486 */ 211 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 212 NULL, NULL, NULL }, /* CPU_486DLC */ 213 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 214 NULL, NULL, NULL }, /* CPU_6x86 */ 215 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 216 NULL, NULL, NULL }, /* CPU_NX586 */ 217 }; 218 219 const char *classnames[] = { 220 "386", 221 "486", 222 "586", 223 "686" 224 }; 225 226 const char *modifiers[] = { 227 "", 228 "OverDrive", 229 "Dual", 230 "" 231 }; 232 233 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 234 { 235 /* 236 * For Intel processors, check Chapter 35Model-specific 237 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 238 * Software Developer's Manual, Volume 3C". 239 */ 240 "GenuineIntel", 241 CPUVENDOR_INTEL, 242 "Intel", 243 /* Family 4 */ 244 { { 245 CPUCLASS_486, 246 { 247 "486DX", "486DX", "486SX", "486DX2", "486SL", 248 "486SX2", 0, "486DX2 W/B Enhanced", 249 "486DX4", 0, 0, 0, 0, 0, 0, 0, 250 }, 251 "486", /* Default */ 252 NULL, 253 NULL, 254 intel_cpu_cacheinfo, 255 }, 256 /* Family 5 */ 257 { 258 CPUCLASS_586, 259 { 260 "Pentium (P5 A-step)", "Pentium (P5)", 261 "Pentium (P54C)", "Pentium (P24T)", 262 "Pentium/MMX", "Pentium", 0, 263 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 264 "Quark X1000", 0, 0, 0, 0, 0, 0, 265 }, 266 "Pentium", /* Default */ 267 NULL, 268 NULL, 269 intel_cpu_cacheinfo, 270 }, 271 /* Family 6 */ 272 { 273 CPUCLASS_686, 274 { 275 [0x00] = "Pentium Pro (A-step)", 276 [0x01] = "Pentium Pro", 277 [0x03] = "Pentium II (Klamath)", 278 [0x04] = "Pentium Pro", 279 [0x05] = "Pentium II/Celeron (Deschutes)", 280 [0x06] = "Celeron (Mendocino)", 281 [0x07] = "Pentium III (Katmai)", 282 [0x08] = "Pentium III (Coppermine)", 283 [0x09] = "Pentium M (Banias)", 284 [0x0a] = "Pentium III Xeon (Cascades)", 285 [0x0b] = "Pentium III (Tualatin)", 286 [0x0d] = "Pentium M (Dothan)", 287 [0x0e] = "Pentium Core Duo, Core solo", 288 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 289 "Core 2 Quad 6xxx, " 290 "Core 2 Extreme 6xxx, " 291 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 292 "and Pentium DC", 293 [0x15] = "EP80579 Integrated Processor", 294 [0x16] = "Celeron (45nm)", 295 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 296 "Core 2 Quad 8xxx and 9xxx", 297 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 298 "(Nehalem)", 299 [0x1c] = "45nm Atom Family", 300 [0x1d] = "XeonMP 74xx (Nehalem)", 301 [0x1e] = "Core i7 and i5", 302 [0x1f] = "Core i7 and i5", 303 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 304 [0x26] = "Atom Family", 305 [0x27] = "Atom Family", 306 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 307 "i3 2xxx", 308 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 309 [0x2d] = "Xeon E5 Sandy Bridge family, " 310 "Core i7-39xx Extreme", 311 [0x2e] = "Xeon 75xx & 65xx", 312 [0x2f] = "Xeon E7 family", 313 [0x35] = "Atom Family", 314 [0x36] = "Atom S1000", 315 [0x37] = "Atom E3000, Z3[67]00", 316 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 317 "Ivy Bridge", 318 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 319 "(Haswell)", 320 [0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)", 321 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 322 "Core i7-49xx Extreme", 323 [0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), " 324 "Core i7-59xx Extreme", 325 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 326 "(Haswell)", 327 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 328 "(Haswell)", 329 [0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)", 330 [0x4a] = "Atom Z3400", 331 [0x4c] = "Atom X[57]-Z8000 (Airmont)", 332 [0x4d] = "Atom C2000", 333 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 334 [0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme", 335 [0x55] = "Xeon Scalable (Skylake, Cascade Lake, Copper Lake)", 336 [0x56] = "Xeon D-1500 (Broadwell)", 337 [0x57] = "Xeon Phi [357]200 (Knights Landing)", 338 [0x5a] = "Atom E3500", 339 [0x5c] = "Atom (Goldmont)", 340 [0x5d] = "Atom X3-C3000 (Silvermont)", 341 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 342 [0x5f] = "Atom (Goldmont, Denverton)", 343 [0x66] = "8th gen Core i3 (Cannon Lake)", 344 [0x6a] = "3rd gen Xeon Scalable (Ice Lake)", 345 [0x6c] = "3rd gen Xeon Scalable (Ice Lake)", 346 [0x7a] = "Atom (Goldmont Plus)", 347 [0x7d] = "10th gen Core (Ice Lake)", 348 [0x7e] = "10th gen Core (Ice Lake)", 349 [0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)", 350 [0x86] = "Atom (Tremont)", 351 [0x8c] = "11th gen Core (Tiger Lake)", 352 [0x8d] = "11th gen Core (Tiger Lake)", 353 [0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 354 [0x8f] = "4th gen Xeon Scalable (Sapphire Rapids)", 355 [0x96] = "Atom x6000E (Elkhart Lake)", 356 [0x97] = "12th gen Core (Alder Lake)", 357 [0x9a] = "12th gen Core (Alder Lake)", 358 [0x9c] = "Pentium Silver N6xxx, Celeron N45xx, Celeron N51xx (Jasper Lake)", 359 [0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 360 [0xa5] = "10th gen Core (Comet Lake)", 361 [0xa6] = "10th gen Core (Comet Lake)", 362 [0xa7] = "11th gen Core (Rocket Lake)", 363 [0xa8] = "11th gen Core (Rocket Lake)", 364 [0xba] = "13th gen Core (Raptor Lake)", 365 [0xb7] = "13th gen Core (Raptor Lake)", 366 [0xbf] = "13th gen Core (Raptor Lake)", 367 }, 368 "Pentium Pro, II or III", /* Default */ 369 NULL, 370 intel_family_new_probe, 371 intel_cpu_cacheinfo, 372 }, 373 /* Family > 6 */ 374 { 375 CPUCLASS_686, 376 { 377 0, 0, 0, 0, 0, 0, 0, 0, 378 0, 0, 0, 0, 0, 0, 0, 0, 379 }, 380 "Pentium 4", /* Default */ 381 NULL, 382 intel_family_new_probe, 383 intel_cpu_cacheinfo, 384 } } 385 }, 386 { 387 "AuthenticAMD", 388 CPUVENDOR_AMD, 389 "AMD", 390 /* Family 4 */ 391 { { 392 CPUCLASS_486, 393 { 394 0, 0, 0, "Am486DX2 W/T", 395 0, 0, 0, "Am486DX2 W/B", 396 "Am486DX4 W/T or Am5x86 W/T 150", 397 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 398 0, 0, "Am5x86 W/T 133/160", 399 "Am5x86 W/B 133/160", 400 }, 401 "Am486 or Am5x86", /* Default */ 402 NULL, 403 NULL, 404 NULL, 405 }, 406 /* Family 5 */ 407 { 408 CPUCLASS_586, 409 { 410 "K5", "K5", "K5", "K5", 0, 0, "K6", 411 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 412 "K6-2+/III+", 0, 0, 413 }, 414 "K5 or K6", /* Default */ 415 amd_family5_setup, 416 NULL, 417 amd_cpu_cacheinfo, 418 }, 419 /* Family 6 */ 420 { 421 CPUCLASS_686, 422 { 423 0, "Athlon Model 1", "Athlon Model 2", 424 "Duron", "Athlon Model 4 (Thunderbird)", 425 0, "Athlon", "Duron", "Athlon", 0, 426 "Athlon", 0, 0, 0, 0, 0, 427 }, 428 "K7 (Athlon)", /* Default */ 429 NULL, 430 amd_family6_probe, 431 amd_cpu_cacheinfo, 432 }, 433 /* Family > 6 */ 434 { 435 CPUCLASS_686, 436 { 437 0, 0, 0, 0, 0, 0, 0, 0, 438 0, 0, 0, 0, 0, 0, 0, 0, 439 }, 440 "Unknown K8 (Athlon)", /* Default */ 441 NULL, 442 amd_family6_probe, 443 amd_cpu_cacheinfo, 444 } } 445 }, 446 { 447 "CyrixInstead", 448 CPUVENDOR_CYRIX, 449 "Cyrix", 450 /* Family 4 */ 451 { { 452 CPUCLASS_486, 453 { 454 0, 0, 0, 455 "MediaGX", 456 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 457 }, 458 "486", /* Default */ 459 cyrix6x86_cpu_setup, /* XXX ?? */ 460 NULL, 461 NULL, 462 }, 463 /* Family 5 */ 464 { 465 CPUCLASS_586, 466 { 467 0, 0, "6x86", 0, 468 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 469 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 470 }, 471 "6x86", /* Default */ 472 cyrix6x86_cpu_setup, 473 NULL, 474 NULL, 475 }, 476 /* Family 6 */ 477 { 478 CPUCLASS_686, 479 { 480 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 481 0, 0, 0, 0, 0, 0, 0, 0, 482 }, 483 "6x86MX", /* Default */ 484 cyrix6x86_cpu_setup, 485 NULL, 486 NULL, 487 }, 488 /* Family > 6 */ 489 { 490 CPUCLASS_686, 491 { 492 0, 0, 0, 0, 0, 0, 0, 0, 493 0, 0, 0, 0, 0, 0, 0, 0, 494 }, 495 "Unknown 6x86MX", /* Default */ 496 NULL, 497 NULL, 498 NULL, 499 } } 500 }, 501 { /* MediaGX is now owned by National Semiconductor */ 502 "Geode by NSC", 503 CPUVENDOR_CYRIX, /* XXX */ 504 "National Semiconductor", 505 /* Family 4, NSC never had any of these */ 506 { { 507 CPUCLASS_486, 508 { 509 0, 0, 0, 0, 0, 0, 0, 0, 510 0, 0, 0, 0, 0, 0, 0, 0, 511 }, 512 "486 compatible", /* Default */ 513 NULL, 514 NULL, 515 NULL, 516 }, 517 /* Family 5: Geode family, formerly MediaGX */ 518 { 519 CPUCLASS_586, 520 { 521 0, 0, 0, 0, 522 "Geode GX1", 523 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 524 }, 525 "Geode", /* Default */ 526 cyrix6x86_cpu_setup, 527 NULL, 528 amd_cpu_cacheinfo, 529 }, 530 /* Family 6, not yet available from NSC */ 531 { 532 CPUCLASS_686, 533 { 534 0, 0, 0, 0, 0, 0, 0, 0, 535 0, 0, 0, 0, 0, 0, 0, 0, 536 }, 537 "Pentium Pro compatible", /* Default */ 538 NULL, 539 NULL, 540 NULL, 541 }, 542 /* Family > 6, not yet available from NSC */ 543 { 544 CPUCLASS_686, 545 { 546 0, 0, 0, 0, 0, 0, 0, 0, 547 0, 0, 0, 0, 0, 0, 0, 0, 548 }, 549 "Pentium Pro compatible", /* Default */ 550 NULL, 551 NULL, 552 NULL, 553 } } 554 }, 555 { 556 "CentaurHauls", 557 CPUVENDOR_IDT, 558 "IDT", 559 /* Family 4, IDT never had any of these */ 560 { { 561 CPUCLASS_486, 562 { 563 0, 0, 0, 0, 0, 0, 0, 0, 564 0, 0, 0, 0, 0, 0, 0, 0, 565 }, 566 "486 compatible", /* Default */ 567 NULL, 568 NULL, 569 NULL, 570 }, 571 /* Family 5 */ 572 { 573 CPUCLASS_586, 574 { 575 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 576 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 577 }, 578 "WinChip", /* Default */ 579 winchip_cpu_setup, 580 NULL, 581 NULL, 582 }, 583 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 584 { 585 CPUCLASS_686, 586 { 587 0, 0, 0, 0, 0, 0, "C3 Samuel", 588 "C3 Samuel 2/Ezra", "C3 Ezra-T", 589 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 590 0, "VIA Nano", 591 }, 592 "Unknown VIA/IDT", /* Default */ 593 NULL, 594 via_cpu_probe, 595 via_cpu_cacheinfo, 596 }, 597 /* Family > 6, not yet available from VIA */ 598 { 599 CPUCLASS_686, 600 { 601 0, 0, 0, 0, 0, 0, 0, 0, 602 0, 0, 0, 0, 0, 0, 0, 0, 603 }, 604 "Pentium Pro compatible", /* Default */ 605 NULL, 606 NULL, 607 NULL, 608 } } 609 }, 610 { 611 "GenuineTMx86", 612 CPUVENDOR_TRANSMETA, 613 "Transmeta", 614 /* Family 4, Transmeta never had any of these */ 615 { { 616 CPUCLASS_486, 617 { 618 0, 0, 0, 0, 0, 0, 0, 0, 619 0, 0, 0, 0, 0, 0, 0, 0, 620 }, 621 "486 compatible", /* Default */ 622 NULL, 623 NULL, 624 NULL, 625 }, 626 /* Family 5 */ 627 { 628 CPUCLASS_586, 629 { 630 0, 0, 0, 0, 0, 0, 0, 0, 631 0, 0, 0, 0, 0, 0, 0, 0, 632 }, 633 "Crusoe", /* Default */ 634 NULL, 635 NULL, 636 transmeta_cpu_info, 637 }, 638 /* Family 6, not yet available from Transmeta */ 639 { 640 CPUCLASS_686, 641 { 642 0, 0, 0, 0, 0, 0, 0, 0, 643 0, 0, 0, 0, 0, 0, 0, 0, 644 }, 645 "Pentium Pro compatible", /* Default */ 646 NULL, 647 NULL, 648 NULL, 649 }, 650 /* Family > 6, not yet available from Transmeta */ 651 { 652 CPUCLASS_686, 653 { 654 0, 0, 0, 0, 0, 0, 0, 0, 655 0, 0, 0, 0, 0, 0, 0, 0, 656 }, 657 "Pentium Pro compatible", /* Default */ 658 NULL, 659 NULL, 660 NULL, 661 } } 662 } 663 }; 664 665 /* 666 * disable the TSC such that we don't use the TSC in microtime(9) 667 * because some CPUs got the implementation wrong. 668 */ 669 static void 670 disable_tsc(struct cpu_info *ci) 671 { 672 if (ci->ci_feat_val[0] & CPUID_TSC) { 673 ci->ci_feat_val[0] &= ~CPUID_TSC; 674 aprint_error("WARNING: broken TSC disabled\n"); 675 } 676 } 677 678 static void 679 amd_family5_setup(struct cpu_info *ci) 680 { 681 682 switch (ci->ci_model) { 683 case 0: /* AMD-K5 Model 0 */ 684 /* 685 * According to the AMD Processor Recognition App Note, 686 * the AMD-K5 Model 0 uses the wrong bit to indicate 687 * support for global PTEs, instead using bit 9 (APIC) 688 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 689 */ 690 if (ci->ci_feat_val[0] & CPUID_APIC) 691 ci->ci_feat_val[0] = 692 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 693 /* 694 * XXX But pmap_pg_g is already initialized -- need to kick 695 * XXX the pmap somehow. How does the MP branch do this? 696 */ 697 break; 698 } 699 } 700 701 static void 702 cyrix6x86_cpu_setup(struct cpu_info *ci) 703 { 704 705 /* 706 * Do not disable the TSC on the Geode GX, it's reported to 707 * work fine. 708 */ 709 if (ci->ci_signature != 0x552) 710 disable_tsc(ci); 711 } 712 713 static void 714 winchip_cpu_setup(struct cpu_info *ci) 715 { 716 switch (ci->ci_model) { 717 case 4: /* WinChip C6 */ 718 disable_tsc(ci); 719 } 720 } 721 722 723 static const char * 724 intel_family6_name(struct cpu_info *ci) 725 { 726 const char *ret = NULL; 727 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 728 729 if (ci->ci_model == 5) { 730 switch (l2cache) { 731 case 0: 732 case 128 * 1024: 733 ret = "Celeron (Covington)"; 734 break; 735 case 256 * 1024: 736 ret = "Mobile Pentium II (Dixon)"; 737 break; 738 case 512 * 1024: 739 ret = "Pentium II"; 740 break; 741 case 1 * 1024 * 1024: 742 case 2 * 1024 * 1024: 743 ret = "Pentium II Xeon"; 744 break; 745 } 746 } else if (ci->ci_model == 6) { 747 switch (l2cache) { 748 case 256 * 1024: 749 case 512 * 1024: 750 ret = "Mobile Pentium II"; 751 break; 752 } 753 } else if (ci->ci_model == 7) { 754 switch (l2cache) { 755 case 512 * 1024: 756 ret = "Pentium III"; 757 break; 758 case 1 * 1024 * 1024: 759 case 2 * 1024 * 1024: 760 ret = "Pentium III Xeon"; 761 break; 762 } 763 } else if (ci->ci_model >= 8) { 764 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 765 switch (ci->ci_brand_id) { 766 case 0x3: 767 if (ci->ci_signature == 0x6B1) 768 ret = "Celeron"; 769 break; 770 case 0x8: 771 if (ci->ci_signature >= 0xF13) 772 ret = "genuine processor"; 773 break; 774 case 0xB: 775 if (ci->ci_signature >= 0xF13) 776 ret = "Xeon MP"; 777 break; 778 case 0xE: 779 if (ci->ci_signature < 0xF13) 780 ret = "Xeon"; 781 break; 782 } 783 if (ret == NULL) 784 ret = i386_intel_brand[ci->ci_brand_id]; 785 } 786 } 787 788 return ret; 789 } 790 791 /* 792 * Identify AMD64 CPU names from cpuid. 793 * 794 * Based on: 795 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 796 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 797 * "Revision Guide for AMD NPT Family 0Fh Processors" 798 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 799 * and other miscellaneous reports. 800 * 801 * This is all rather pointless, these are cross 'brand' since the raw 802 * silicon is shared. 803 */ 804 static const char * 805 amd_amd64_name(struct cpu_info *ci) 806 { 807 static char family_str[32]; 808 809 /* Only called if family >= 15 */ 810 811 switch (ci->ci_family) { 812 case 15: 813 switch (ci->ci_model) { 814 case 0x21: /* rev JH-E1/E6 */ 815 case 0x41: /* rev JH-F2 */ 816 return "Dual-Core Opteron"; 817 case 0x23: /* rev JH-E6 (Toledo) */ 818 return "Dual-Core Opteron or Athlon 64 X2"; 819 case 0x43: /* rev JH-F2 (Windsor) */ 820 return "Athlon 64 FX or Athlon 64 X2"; 821 case 0x24: /* rev SH-E5 (Lancaster?) */ 822 return "Mobile Athlon 64 or Turion 64"; 823 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 824 return "Opteron or Athlon 64 FX"; 825 case 0x15: /* rev SH-D0 */ 826 case 0x25: /* rev SH-E4 */ 827 return "Opteron"; 828 case 0x27: /* rev DH-E4, SH-E4 */ 829 return "Athlon 64 or Athlon 64 FX or Opteron"; 830 case 0x48: /* rev BH-F2 */ 831 return "Turion 64 X2"; 832 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 833 case 0x07: /* rev SH-CG (ClawHammer) */ 834 case 0x0b: /* rev CH-CG */ 835 case 0x14: /* rev SH-D0 */ 836 case 0x17: /* rev SH-D0 */ 837 case 0x1b: /* rev CH-D0 */ 838 return "Athlon 64"; 839 case 0x2b: /* rev BH-E4 (Manchester) */ 840 case 0x4b: /* rev BH-F2 (Windsor) */ 841 return "Athlon 64 X2"; 842 case 0x6b: /* rev BH-G1 (Brisbane) */ 843 return "Athlon X2 or Athlon 64 X2"; 844 case 0x08: /* rev CH-CG */ 845 case 0x0c: /* rev DH-CG (Newcastle) */ 846 case 0x0e: /* rev DH-CG (Newcastle?) */ 847 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 848 case 0x18: /* rev CH-D0 */ 849 case 0x1c: /* rev DH-D0 (Winchester) */ 850 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 851 case 0x2c: /* rev DH-E3/E6 */ 852 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 853 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 854 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 855 case 0x6f: /* rev DH-G1 */ 856 return "Athlon 64 or Sempron"; 857 default: 858 break; 859 } 860 return "Unknown AMD64 CPU"; 861 862 #if 0 863 case 16: 864 return "Family 10h"; 865 case 17: 866 return "Family 11h"; 867 case 18: 868 return "Family 12h"; 869 case 19: 870 return "Family 14h"; 871 case 20: 872 return "Family 15h"; 873 #endif 874 875 default: 876 break; 877 } 878 879 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 880 return family_str; 881 } 882 883 static void 884 intel_family_new_probe(struct cpu_info *ci) 885 { 886 uint32_t descs[4]; 887 888 x86_cpuid(0x80000000, descs); 889 890 /* 891 * Determine extended feature flags. 892 */ 893 if (descs[0] >= 0x80000001) { 894 x86_cpuid(0x80000001, descs); 895 ci->ci_feat_val[2] |= descs[3]; 896 ci->ci_feat_val[3] |= descs[2]; 897 } 898 } 899 900 static void 901 via_cpu_probe(struct cpu_info *ci) 902 { 903 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 904 u_int descs[4]; 905 u_int lfunc; 906 907 /* 908 * Determine the largest extended function value. 909 */ 910 x86_cpuid(0x80000000, descs); 911 lfunc = descs[0]; 912 913 /* 914 * Determine the extended feature flags. 915 */ 916 if (lfunc >= 0x80000001) { 917 x86_cpuid(0x80000001, descs); 918 ci->ci_feat_val[2] |= descs[3]; 919 } 920 921 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 922 return; 923 924 /* Nehemiah or Esther */ 925 x86_cpuid(0xc0000000, descs); 926 lfunc = descs[0]; 927 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 928 return; 929 930 x86_cpuid(0xc0000001, descs); 931 lfunc = descs[3]; 932 ci->ci_feat_val[4] = lfunc; 933 } 934 935 static void 936 amd_family6_probe(struct cpu_info *ci) 937 { 938 uint32_t descs[4]; 939 char *p; 940 size_t i; 941 942 x86_cpuid(0x80000000, descs); 943 944 /* 945 * Determine the extended feature flags. 946 */ 947 if (descs[0] >= 0x80000001) { 948 x86_cpuid(0x80000001, descs); 949 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 950 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 951 } 952 953 if (*cpu_brand_string == '\0') 954 return; 955 956 for (i = 1; i < __arraycount(amd_brand); i++) 957 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 958 ci->ci_brand_id = i; 959 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 960 break; 961 } 962 } 963 964 static void 965 intel_cpu_cacheinfo(struct cpu_info *ci) 966 { 967 const struct x86_cache_info *cai; 968 u_int descs[4]; 969 int iterations, i, j; 970 int type, level, ways, linesize, sets; 971 int caitype = -1; 972 uint8_t desc; 973 974 /* Return if the cpu is old pre-cpuid instruction cpu */ 975 if (ci->ci_cpu_type >= 0) 976 return; 977 978 if (ci->ci_max_cpuid < 2) 979 return; 980 981 /* 982 * Parse the cache info from `cpuid leaf 2', if we have it. 983 * XXX This is kinda ugly, but hey, so is the architecture... 984 */ 985 x86_cpuid(2, descs); 986 iterations = descs[0] & 0xff; 987 while (iterations-- > 0) { 988 for (i = 0; i < 4; i++) { 989 if (descs[i] & 0x80000000) 990 continue; 991 for (j = 0; j < 4; j++) { 992 /* 993 * The least significant byte in EAX 994 * ((desc[0] >> 0) & 0xff) is always 0x01 and 995 * it should be ignored. 996 */ 997 if (i == 0 && j == 0) 998 continue; 999 desc = (descs[i] >> (j * 8)) & 0xff; 1000 if (desc == 0) 1001 continue; 1002 cai = cpu_cacheinfo_lookup( 1003 intel_cpuid_cache_info, desc); 1004 if (cai != NULL) 1005 ci->ci_cinfo[cai->cai_index] = *cai; 1006 else if ((verbose != 0) && (desc != 0xff) 1007 && (desc != 0xfe)) 1008 aprint_error_dev(ci->ci_dev, "error:" 1009 " Unknown cacheinfo desc %02x\n", 1010 desc); 1011 } 1012 } 1013 x86_cpuid(2, descs); 1014 } 1015 1016 if (ci->ci_max_cpuid < 4) 1017 return; 1018 1019 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1020 cpu_dcp_cacheinfo(ci, 4); 1021 1022 if (ci->ci_max_cpuid < 0x18) 1023 return; 1024 /* Parse the TLB info from `cpuid leaf 18H', if we have it. */ 1025 x86_cpuid(0x18, descs); 1026 iterations = descs[0]; 1027 for (i = 0; i <= iterations; i++) { 1028 uint32_t pgsize; 1029 bool full; 1030 1031 x86_cpuid2(0x18, i, descs); 1032 type = __SHIFTOUT(descs[3], CPUID_DATP_TCTYPE); 1033 if (type == CPUID_DATP_TCTYPE_N) 1034 continue; 1035 level = __SHIFTOUT(descs[3], CPUID_DATP_TCLEVEL); 1036 pgsize = __SHIFTOUT(descs[1], CPUID_DATP_PGSIZE); 1037 switch (level) { 1038 case 1: 1039 if (type == CPUID_DATP_TCTYPE_I) { 1040 switch (pgsize) { 1041 case CPUID_DATP_PGSIZE_4KB: 1042 caitype = CAI_ITLB; 1043 break; 1044 case CPUID_DATP_PGSIZE_2MB 1045 | CPUID_DATP_PGSIZE_4MB: 1046 caitype = CAI_ITLB2; 1047 break; 1048 case CPUID_DATP_PGSIZE_1GB: 1049 caitype = CAI_L1_1GBITLB; 1050 break; 1051 default: 1052 aprint_error_dev(ci->ci_dev, 1053 "error: unknown ITLB size (%d)\n", 1054 pgsize); 1055 caitype = CAI_ITLB; 1056 break; 1057 } 1058 } else if (type == CPUID_DATP_TCTYPE_D) { 1059 switch (pgsize) { 1060 case CPUID_DATP_PGSIZE_4KB: 1061 caitype = CAI_DTLB; 1062 break; 1063 case CPUID_DATP_PGSIZE_2MB 1064 | CPUID_DATP_PGSIZE_4MB: 1065 caitype = CAI_DTLB2; 1066 break; 1067 case CPUID_DATP_PGSIZE_1GB: 1068 caitype = CAI_L1_1GBDTLB; 1069 break; 1070 default: 1071 aprint_error_dev(ci->ci_dev, 1072 "error: unknown DTLB size (%d)\n", 1073 pgsize); 1074 caitype = CAI_DTLB; 1075 break; 1076 } 1077 } else if (type == CPUID_DATP_TCTYPE_L) 1078 caitype = CAI_L1_LD_TLB; 1079 else if (type == CPUID_DATP_TCTYPE_S) 1080 caitype = CAI_L1_ST_TLB; 1081 else 1082 caitype = -1; 1083 break; 1084 case 2: 1085 if (type == CPUID_DATP_TCTYPE_I) 1086 caitype = CAI_L2_ITLB; 1087 else if (type == CPUID_DATP_TCTYPE_D) 1088 caitype = CAI_L2_DTLB; 1089 else if (type == CPUID_DATP_TCTYPE_U) { 1090 if (pgsize == CPUID_DATP_PGSIZE_4KB) 1091 caitype = CAI_L2_STLB; 1092 else if (pgsize == (CPUID_DATP_PGSIZE_4KB 1093 | CPUID_DATP_PGSIZE_2MB)) 1094 caitype = CAI_L2_STLB2; 1095 else if (pgsize == (CPUID_DATP_PGSIZE_2MB 1096 | CPUID_DATP_PGSIZE_4MB)) 1097 caitype = CAI_L2_STLB3; 1098 else if ((pgsize & CPUID_DATP_PGSIZE_1GB) 1099 != 0) { 1100 /* FIXME: 1GB max TLB */ 1101 caitype = CAI_L2_STLB3; 1102 linesize = 1024 * 1024 * 1024; 1103 } else if ((pgsize & CPUID_DATP_PGSIZE_4MB) 1104 != 0) { 1105 /* FIXME: 4MB max TLB */ 1106 caitype = CAI_L2_STLB3; 1107 linesize = 4 * 1024 * 1024; 1108 } else if ((pgsize & CPUID_DATP_PGSIZE_2MB) 1109 != 0) { 1110 /* FIXME: 2MB max TLB */ 1111 caitype = CAI_L2_STLB2; 1112 linesize = 2 * 1024 * 1024; 1113 } else { 1114 aprint_error_dev(ci->ci_dev, "error: " 1115 "unknown L2 STLB size (%d)\n", 1116 pgsize); 1117 caitype = CAI_L2_STLB; 1118 linesize = 4 * 1024; 1119 } 1120 } else 1121 caitype = -1; 1122 break; 1123 case 3: 1124 /* XXX need work for L3 TLB */ 1125 caitype = CAI_L3CACHE; 1126 break; 1127 default: 1128 caitype = -1; 1129 break; 1130 } 1131 if (caitype == -1) { 1132 aprint_error_dev(ci->ci_dev, 1133 "error: unknown TLB level&type (%d & %d)\n", 1134 level, type); 1135 continue; 1136 } 1137 switch (pgsize) { 1138 case CPUID_DATP_PGSIZE_4KB: 1139 linesize = 4 * 1024; 1140 break; 1141 case CPUID_DATP_PGSIZE_2MB: 1142 linesize = 2 * 1024 * 1024; 1143 break; 1144 case CPUID_DATP_PGSIZE_4MB: 1145 linesize = 4 * 1024 * 1024; 1146 break; 1147 case CPUID_DATP_PGSIZE_1GB: 1148 linesize = 1024 * 1024 * 1024; 1149 break; 1150 default: 1151 if ((pgsize & CPUID_DATP_PGSIZE_1GB) != 0) 1152 linesize = 1024 * 1024 * 1024; /* MAX 1G */ 1153 else if ((pgsize & CPUID_DATP_PGSIZE_4MB) != 0) 1154 linesize = 4 * 1024 * 1024; /* MAX 4M */ 1155 else if ((pgsize & CPUID_DATP_PGSIZE_2MB) != 0) 1156 linesize = 2 * 1024 * 1024; /* MAX 2M */ 1157 else 1158 linesize = 4 * 1024; /* XXX default to 4K */ 1159 aprint_error_dev(ci->ci_dev, "WARNING: Currently " 1160 "this info can't print correctly " 1161 "(level = %d, pgsize = %d)\n", 1162 level, pgsize); 1163 break; 1164 } 1165 ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS); 1166 sets = descs[2]; 1167 full = descs[3] & CPUID_DATP_FULLASSOC; 1168 ci->ci_cinfo[caitype].cai_totalsize 1169 = ways * sets; /* entries */ 1170 ci->ci_cinfo[caitype].cai_associativity 1171 = full ? 0xff : ways; 1172 ci->ci_cinfo[caitype].cai_linesize = linesize; /* pg size */ 1173 } 1174 } 1175 1176 static const struct x86_cache_info amd_cpuid_l2l3cache_assoc_info[] = 1177 AMD_L2L3CACHE_INFO; 1178 1179 static void 1180 amd_cpu_cacheinfo(struct cpu_info *ci) 1181 { 1182 const struct x86_cache_info *cp; 1183 struct x86_cache_info *cai; 1184 u_int descs[4]; 1185 u_int lfunc; 1186 1187 /* K5 model 0 has none of this info. */ 1188 if (ci->ci_family == 5 && ci->ci_model == 0) 1189 return; 1190 1191 /* Determine the largest extended function value. */ 1192 x86_cpuid(0x80000000, descs); 1193 lfunc = descs[0]; 1194 1195 if (lfunc < 0x80000005) 1196 return; 1197 1198 /* Determine L1 cache/TLB info. */ 1199 x86_cpuid(0x80000005, descs); 1200 1201 /* K6-III and higher have large page TLBs. */ 1202 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1203 cai = &ci->ci_cinfo[CAI_ITLB2]; 1204 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1205 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1206 cai->cai_linesize = largepagesize; 1207 1208 cai = &ci->ci_cinfo[CAI_DTLB2]; 1209 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1210 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1211 cai->cai_linesize = largepagesize; 1212 } 1213 1214 cai = &ci->ci_cinfo[CAI_ITLB]; 1215 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1216 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1217 cai->cai_linesize = (4 * 1024); 1218 1219 cai = &ci->ci_cinfo[CAI_DTLB]; 1220 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1221 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1222 cai->cai_linesize = (4 * 1024); 1223 1224 cai = &ci->ci_cinfo[CAI_DCACHE]; 1225 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1226 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1227 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1228 1229 cai = &ci->ci_cinfo[CAI_ICACHE]; 1230 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1231 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1232 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1233 1234 if (lfunc < 0x80000006) 1235 return; 1236 1237 /* Determine L2 cache/TLB info. */ 1238 x86_cpuid(0x80000006, descs); 1239 1240 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1241 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1242 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1243 cai->cai_linesize = (4 * 1024); 1244 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1245 cai->cai_associativity); 1246 if (cp != NULL) 1247 cai->cai_associativity = cp->cai_associativity; 1248 else 1249 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1250 1251 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1252 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1253 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1254 cai->cai_linesize = largepagesize; 1255 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1256 cai->cai_associativity); 1257 if (cp != NULL) 1258 cai->cai_associativity = cp->cai_associativity; 1259 else 1260 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1261 1262 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1263 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1264 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1265 cai->cai_linesize = (4 * 1024); 1266 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1267 cai->cai_associativity); 1268 if (cp != NULL) 1269 cai->cai_associativity = cp->cai_associativity; 1270 else 1271 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1272 1273 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1274 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1275 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1276 cai->cai_linesize = largepagesize; 1277 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1278 cai->cai_associativity); 1279 if (cp != NULL) 1280 cai->cai_associativity = cp->cai_associativity; 1281 else 1282 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1283 1284 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1285 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1286 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1287 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1288 1289 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1290 cai->cai_associativity); 1291 if (cp != NULL) 1292 cai->cai_associativity = cp->cai_associativity; 1293 else 1294 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1295 1296 /* Determine L3 cache info on AMD Family 10h and newer processors */ 1297 if (ci->ci_family >= 0x10) { 1298 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1299 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1300 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1301 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1302 1303 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1304 cai->cai_associativity); 1305 if (cp != NULL) 1306 cai->cai_associativity = cp->cai_associativity; 1307 else 1308 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1309 } 1310 1311 if (lfunc < 0x80000019) 1312 return; 1313 1314 /* Determine 1GB TLB info. */ 1315 x86_cpuid(0x80000019, descs); 1316 1317 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1318 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1319 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1320 cai->cai_linesize = (1024 * 1024 * 1024); 1321 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1322 cai->cai_associativity); 1323 if (cp != NULL) 1324 cai->cai_associativity = cp->cai_associativity; 1325 else 1326 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1327 1328 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1329 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1330 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1331 cai->cai_linesize = (1024 * 1024 * 1024); 1332 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1333 cai->cai_associativity); 1334 if (cp != NULL) 1335 cai->cai_associativity = cp->cai_associativity; 1336 else 1337 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1338 1339 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1340 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1341 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1342 cai->cai_linesize = (1024 * 1024 * 1024); 1343 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1344 cai->cai_associativity); 1345 if (cp != NULL) 1346 cai->cai_associativity = cp->cai_associativity; 1347 else 1348 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1349 1350 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1351 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1352 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1353 cai->cai_linesize = (1024 * 1024 * 1024); 1354 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1355 cai->cai_associativity); 1356 if (cp != NULL) 1357 cai->cai_associativity = cp->cai_associativity; 1358 else 1359 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1360 1361 if (lfunc < 0x8000001d) 1362 return; 1363 1364 if (ci->ci_feat_val[3] & CPUID_TOPOEXT) 1365 cpu_dcp_cacheinfo(ci, 0x8000001d); 1366 } 1367 1368 static void 1369 via_cpu_cacheinfo(struct cpu_info *ci) 1370 { 1371 struct x86_cache_info *cai; 1372 int stepping; 1373 u_int descs[4]; 1374 u_int lfunc; 1375 1376 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1377 1378 /* 1379 * Determine the largest extended function value. 1380 */ 1381 x86_cpuid(0x80000000, descs); 1382 lfunc = descs[0]; 1383 1384 /* 1385 * Determine L1 cache/TLB info. 1386 */ 1387 if (lfunc < 0x80000005) { 1388 /* No L1 cache info available. */ 1389 return; 1390 } 1391 1392 x86_cpuid(0x80000005, descs); 1393 1394 cai = &ci->ci_cinfo[CAI_ITLB]; 1395 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1396 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1397 cai->cai_linesize = (4 * 1024); 1398 1399 cai = &ci->ci_cinfo[CAI_DTLB]; 1400 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1401 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1402 cai->cai_linesize = (4 * 1024); 1403 1404 cai = &ci->ci_cinfo[CAI_DCACHE]; 1405 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1406 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1407 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1408 if (ci->ci_model == 9 && stepping == 8) { 1409 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1410 cai->cai_associativity = 2; 1411 } 1412 1413 cai = &ci->ci_cinfo[CAI_ICACHE]; 1414 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1415 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1416 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1417 if (ci->ci_model == 9 && stepping == 8) { 1418 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1419 cai->cai_associativity = 2; 1420 } 1421 1422 /* 1423 * Determine L2 cache/TLB info. 1424 */ 1425 if (lfunc < 0x80000006) { 1426 /* No L2 cache info available. */ 1427 return; 1428 } 1429 1430 x86_cpuid(0x80000006, descs); 1431 1432 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1433 if (ci->ci_model >= 9) { 1434 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1435 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1436 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1437 } else { 1438 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1439 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1440 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1441 } 1442 } 1443 1444 static void 1445 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1446 { 1447 u_int descs[4]; 1448 1449 x86_cpuid(0x80860007, descs); 1450 *frequency = descs[0]; 1451 *voltage = descs[1]; 1452 *percentage = descs[2]; 1453 } 1454 1455 static void 1456 transmeta_cpu_info(struct cpu_info *ci) 1457 { 1458 u_int descs[4], nreg; 1459 u_int frequency, voltage, percentage; 1460 1461 x86_cpuid(0x80860000, descs); 1462 nreg = descs[0]; 1463 if (nreg >= 0x80860001) { 1464 x86_cpuid(0x80860001, descs); 1465 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1466 (descs[1] >> 24) & 0xff, 1467 (descs[1] >> 16) & 0xff, 1468 (descs[1] >> 8) & 0xff, 1469 descs[1] & 0xff); 1470 } 1471 if (nreg >= 0x80860002) { 1472 x86_cpuid(0x80860002, descs); 1473 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1474 (descs[1] >> 24) & 0xff, 1475 (descs[1] >> 16) & 0xff, 1476 (descs[1] >> 8) & 0xff, 1477 descs[1] & 0xff, 1478 descs[2]); 1479 } 1480 if (nreg >= 0x80860006) { 1481 union { 1482 char text[65]; 1483 u_int descs[4][4]; 1484 } info; 1485 int i; 1486 1487 for (i=0; i<4; i++) { 1488 x86_cpuid(0x80860003 + i, info.descs[i]); 1489 } 1490 info.text[64] = '\0'; 1491 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1492 } 1493 1494 if (nreg >= 0x80860007) { 1495 tmx86_get_longrun_status(&frequency, 1496 &voltage, &percentage); 1497 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1498 frequency, voltage, percentage); 1499 } 1500 } 1501 1502 static void 1503 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1504 { 1505 u_int descs[4]; 1506 int i; 1507 uint32_t brand[12]; 1508 1509 memset(ci, 0, sizeof(*ci)); 1510 ci->ci_dev = cpuname; 1511 1512 ci->ci_cpu_type = x86_identify(); 1513 if (ci->ci_cpu_type >= 0) { 1514 /* Old pre-cpuid instruction cpu */ 1515 ci->ci_max_cpuid = -1; 1516 return; 1517 } 1518 1519 /* 1520 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1521 * function. 1522 */ 1523 1524 /* 1525 * Fn0000_0000: 1526 * - Save cpuid max level. 1527 * - Save vendor string. 1528 */ 1529 x86_cpuid(0, descs); 1530 ci->ci_max_cpuid = descs[0]; 1531 /* Save vendor string */ 1532 ci->ci_vendor[0] = descs[1]; 1533 ci->ci_vendor[2] = descs[2]; 1534 ci->ci_vendor[1] = descs[3]; 1535 ci->ci_vendor[3] = 0; 1536 1537 /* 1538 * Fn8000_0000: 1539 * - Get cpuid extended function's max level. 1540 */ 1541 x86_cpuid(0x80000000, descs); 1542 if (descs[0] >= 0x80000000) 1543 ci->ci_max_ext_cpuid = descs[0]; 1544 else { 1545 /* Set lower value than 0x80000000 */ 1546 ci->ci_max_ext_cpuid = 0; 1547 } 1548 1549 /* 1550 * Fn8000_000[2-4]: 1551 * - Save brand string. 1552 */ 1553 if (ci->ci_max_ext_cpuid >= 0x80000004) { 1554 x86_cpuid(0x80000002, brand); 1555 x86_cpuid(0x80000003, brand + 4); 1556 x86_cpuid(0x80000004, brand + 8); 1557 for (i = 0; i < 48; i++) 1558 if (((char *) brand)[i] != ' ') 1559 break; 1560 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1561 } 1562 1563 if (ci->ci_max_cpuid < 1) 1564 return; 1565 1566 /* 1567 * Fn0000_0001: 1568 * - Get CPU family, model and stepping (from eax). 1569 * - Initial local APIC ID and brand ID (from ebx) 1570 * - CPUID2 (from ecx) 1571 * - CPUID (from edx) 1572 */ 1573 x86_cpuid(1, descs); 1574 ci->ci_signature = descs[0]; 1575 1576 /* Extract full family/model values */ 1577 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1578 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1579 1580 /* Brand is low order 8 bits of ebx */ 1581 ci->ci_brand_id = __SHIFTOUT(descs[1], CPUID_BRAND_INDEX); 1582 /* Initial local APIC ID */ 1583 ci->ci_initapicid = __SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID); 1584 1585 ci->ci_feat_val[1] = descs[2]; 1586 ci->ci_feat_val[0] = descs[3]; 1587 1588 if (ci->ci_max_cpuid < 3) 1589 return; 1590 1591 /* 1592 * If the processor serial number misfeature is present and supported, 1593 * extract it here. 1594 */ 1595 if ((ci->ci_feat_val[0] & CPUID_PSN) != 0) { 1596 ci->ci_cpu_serial[0] = ci->ci_signature; 1597 x86_cpuid(3, descs); 1598 ci->ci_cpu_serial[2] = descs[2]; 1599 ci->ci_cpu_serial[1] = descs[3]; 1600 } 1601 1602 if (ci->ci_max_cpuid < 0x7) 1603 return; 1604 1605 x86_cpuid(7, descs); 1606 ci->ci_feat_val[5] = descs[1]; 1607 ci->ci_feat_val[6] = descs[2]; 1608 ci->ci_feat_val[7] = descs[3]; 1609 1610 if (ci->ci_max_cpuid < 0xd) 1611 return; 1612 1613 /* Get support XCR0 bits */ 1614 x86_cpuid2(0xd, 0, descs); 1615 ci->ci_feat_val[8] = descs[0]; /* Actually 64 bits */ 1616 ci->ci_cur_xsave = descs[1]; 1617 ci->ci_max_xsave = descs[2]; 1618 1619 /* Additional flags (eg xsaveopt support) */ 1620 x86_cpuid2(0xd, 1, descs); 1621 ci->ci_feat_val[9] = descs[0]; /* Actually 64 bits */ 1622 } 1623 1624 static void 1625 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1626 { 1627 uint32_t descs[4]; 1628 char hv_sig[13]; 1629 char *p; 1630 const char *hv_name; 1631 int i; 1632 1633 /* 1634 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1635 * http://lkml.org/lkml/2008/10/1/246 1636 * 1637 * KB1009458: Mechanisms to determine if software is running in 1638 * a VMware virtual machine 1639 * http://kb.vmware.com/kb/1009458 1640 */ 1641 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1642 x86_cpuid(0x40000000, descs); 1643 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1644 memcpy(p, &descs[i], sizeof(descs[i])); 1645 *p = '\0'; 1646 /* 1647 * HV vendor ID string 1648 * ------------+-------------- 1649 * HAXM "HAXMHAXMHAXM" 1650 * KVM "KVMKVMKVM" 1651 * Microsoft "Microsoft Hv" 1652 * QEMU(TCG) "TCGTCGTCGTCG" 1653 * VMware "VMwareVMware" 1654 * Xen "XenVMMXenVMM" 1655 * NetBSD "___ NVMM ___" 1656 */ 1657 if (strncmp(hv_sig, "HAXMHAXMHAXM", 12) == 0) 1658 hv_name = "HAXM"; 1659 else if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1660 hv_name = "KVM"; 1661 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1662 hv_name = "Hyper-V"; 1663 else if (strncmp(hv_sig, "TCGTCGTCGTCG", 12) == 0) 1664 hv_name = "QEMU(TCG)"; 1665 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1666 hv_name = "VMware"; 1667 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1668 hv_name = "Xen"; 1669 else if (strncmp(hv_sig, "___ NVMM ___", 12) == 0) 1670 hv_name = "NVMM"; 1671 else 1672 hv_name = "unknown"; 1673 1674 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1675 } 1676 } 1677 1678 static void 1679 cpu_probe_features(struct cpu_info *ci) 1680 { 1681 const struct cpu_cpuid_nameclass *cpup = NULL; 1682 unsigned int i; 1683 1684 if (ci->ci_max_cpuid < 1) 1685 return; 1686 1687 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1688 if (!strncmp((char *)ci->ci_vendor, 1689 i386_cpuid_cpus[i].cpu_id, 12)) { 1690 cpup = &i386_cpuid_cpus[i]; 1691 break; 1692 } 1693 } 1694 1695 if (cpup == NULL) 1696 return; 1697 1698 i = ci->ci_family - CPU_MINFAMILY; 1699 1700 if (i >= __arraycount(cpup->cpu_family)) 1701 i = __arraycount(cpup->cpu_family) - 1; 1702 1703 if (cpup->cpu_family[i].cpu_probe == NULL) 1704 return; 1705 1706 (*cpup->cpu_family[i].cpu_probe)(ci); 1707 } 1708 1709 static void 1710 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1711 { 1712 char buf[32 * 16]; 1713 char *bp; 1714 1715 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1716 1717 if (val == 0 || fmt == NULL) 1718 return; 1719 1720 snprintb_m(buf, sizeof(buf), fmt, val, 1721 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1722 bp = buf; 1723 while (*bp != '\0') { 1724 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1725 bp += strlen(bp) + 1; 1726 } 1727 } 1728 1729 static void 1730 dump_descs(uint32_t leafstart, uint32_t leafend, const char *cpuname, 1731 const char *blockname) 1732 { 1733 uint32_t descs[4]; 1734 uint32_t leaf; 1735 1736 aprint_verbose("%s: highest %s info %08x\n", cpuname, blockname, 1737 leafend); 1738 1739 if (verbose) { 1740 for (leaf = leafstart; leaf <= leafend; leaf++) { 1741 x86_cpuid(leaf, descs); 1742 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1743 leaf, descs[0], descs[1], descs[2], descs[3]); 1744 } 1745 } 1746 } 1747 1748 static void 1749 identifycpu_cpuids_intel_0x04(struct cpu_info *ci) 1750 { 1751 u_int lp_max = 1; /* logical processors per package */ 1752 u_int smt_max; /* smt per core */ 1753 u_int core_max = 1; /* core per package */ 1754 u_int smt_bits, core_bits; 1755 uint32_t descs[4]; 1756 1757 /* 1758 * 253668.pdf 7.10.2 1759 */ 1760 1761 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1762 x86_cpuid(1, descs); 1763 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1764 } 1765 x86_cpuid2(4, 0, descs); 1766 core_max = __SHIFTOUT(descs[0], CPUID_DCP_CORE_P_PKG) + 1; 1767 1768 assert(lp_max >= core_max); 1769 smt_max = lp_max / core_max; 1770 smt_bits = ilog2(smt_max - 1) + 1; 1771 core_bits = ilog2(core_max - 1) + 1; 1772 1773 if (smt_bits + core_bits) 1774 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1775 1776 if (core_bits) 1777 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1778 __BITS(smt_bits, smt_bits + core_bits - 1)); 1779 1780 if (smt_bits) 1781 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1782 __BITS((int)0, (int)(smt_bits - 1))); 1783 } 1784 1785 static void 1786 identifycpu_cpuids_intel_0x0b(struct cpu_info *ci) 1787 { 1788 const char *cpuname = ci->ci_dev; 1789 u_int smt_bits, core_bits, core_shift = 0, pkg_shift = 0; 1790 uint32_t descs[4]; 1791 int i; 1792 1793 x86_cpuid(0x0b, descs); 1794 if (descs[1] == 0) { 1795 identifycpu_cpuids_intel_0x04(ci); 1796 return; 1797 } 1798 1799 for (i = 0; ; i++) { 1800 unsigned int shiftnum, lvltype; 1801 x86_cpuid2(0x0b, i, descs); 1802 1803 /* On invalid level, (EAX and) EBX return 0 */ 1804 if (descs[1] == 0) 1805 break; 1806 1807 shiftnum = __SHIFTOUT(descs[0], CPUID_TOP_SHIFTNUM); 1808 lvltype = __SHIFTOUT(descs[2], CPUID_TOP_LVLTYPE); 1809 switch (lvltype) { 1810 case CPUID_TOP_LVLTYPE_SMT: 1811 core_shift = shiftnum; 1812 break; 1813 case CPUID_TOP_LVLTYPE_CORE: 1814 pkg_shift = shiftnum; 1815 break; 1816 case CPUID_TOP_LVLTYPE_INVAL: 1817 aprint_verbose("%s: Invalid level type\n", cpuname); 1818 break; 1819 default: 1820 aprint_verbose("%s: Unknown level type(%d) \n", 1821 cpuname, lvltype); 1822 break; 1823 } 1824 } 1825 1826 assert(pkg_shift >= core_shift); 1827 smt_bits = core_shift; 1828 core_bits = pkg_shift - core_shift; 1829 1830 ci->ci_packageid = ci->ci_initapicid >> pkg_shift; 1831 1832 if (core_bits) 1833 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1834 __BITS(core_shift, pkg_shift - 1)); 1835 1836 if (smt_bits) 1837 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1838 __BITS((int)0, core_shift - 1)); 1839 } 1840 1841 static void 1842 identifycpu_cpuids_intel(struct cpu_info *ci) 1843 { 1844 const char *cpuname = ci->ci_dev; 1845 1846 if (ci->ci_max_cpuid >= 0x0b) 1847 identifycpu_cpuids_intel_0x0b(ci); 1848 else if (ci->ci_max_cpuid >= 4) 1849 identifycpu_cpuids_intel_0x04(ci); 1850 1851 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1852 ci->ci_packageid); 1853 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1854 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1855 } 1856 1857 static void 1858 identifycpu_cpuids_amd(struct cpu_info *ci) 1859 { 1860 const char *cpuname = ci->ci_dev; 1861 u_int lp_max, core_max; 1862 int n, cpu_family, apic_id, smt_bits, core_bits = 0; 1863 uint32_t descs[4]; 1864 1865 apic_id = ci->ci_initapicid; 1866 cpu_family = CPUID_TO_FAMILY(ci->ci_signature); 1867 1868 if (cpu_family < 0xf) 1869 return; 1870 1871 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1872 x86_cpuid(1, descs); 1873 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1874 1875 if (cpu_family >= 0x10 && ci->ci_max_ext_cpuid >= 0x8000008) { 1876 x86_cpuid(0x8000008, descs); 1877 core_max = (descs[2] & 0xff) + 1; 1878 n = (descs[2] >> 12) & 0x0f; 1879 if (n != 0) 1880 core_bits = n; 1881 } 1882 } else { 1883 lp_max = 1; 1884 } 1885 core_max = lp_max; 1886 1887 smt_bits = ilog2((lp_max / core_max) - 1) + 1; 1888 if (core_bits == 0) 1889 core_bits = ilog2(core_max - 1) + 1; 1890 1891 #if 0 /* MSRs need kernel mode */ 1892 if (cpu_family < 0x11) { 1893 const uint64_t reg = rdmsr(MSR_NB_CFG); 1894 if ((reg & NB_CFG_INITAPICCPUIDLO) == 0) { 1895 const u_int node_id = apic_id & __BITS(0, 2); 1896 apic_id = (cpu_family == 0xf) ? 1897 (apic_id >> core_bits) | (node_id << core_bits) : 1898 (apic_id >> 5) | (node_id << 2); 1899 } 1900 } 1901 #endif 1902 1903 if (cpu_family >= 0x17) { 1904 x86_cpuid(0x8000001e, descs); 1905 const u_int threads = ((descs[1] >> 8) & 0xff) + 1; 1906 smt_bits = ilog2(threads); 1907 core_bits -= smt_bits; 1908 } 1909 1910 if (smt_bits + core_bits) { 1911 if (smt_bits + core_bits < 32) 1912 ci->ci_packageid = 0; 1913 } 1914 if (core_bits) { 1915 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1916 ci->ci_coreid = __SHIFTOUT(apic_id, core_mask); 1917 } 1918 if (smt_bits) { 1919 u_int smt_mask = __BITS(0, smt_bits - 1); 1920 ci->ci_smtid = __SHIFTOUT(apic_id, smt_mask); 1921 } 1922 1923 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1924 ci->ci_packageid); 1925 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1926 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1927 } 1928 1929 static void 1930 identifycpu_cpuids(struct cpu_info *ci) 1931 { 1932 const char *cpuname = ci->ci_dev; 1933 1934 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1935 ci->ci_packageid = ci->ci_initapicid; 1936 ci->ci_coreid = 0; 1937 ci->ci_smtid = 0; 1938 1939 if (cpu_vendor == CPUVENDOR_INTEL) 1940 identifycpu_cpuids_intel(ci); 1941 else if (cpu_vendor == CPUVENDOR_AMD) 1942 identifycpu_cpuids_amd(ci); 1943 } 1944 1945 void 1946 identifycpu(int fd, const char *cpuname) 1947 { 1948 const char *name = "", *modifier, *vendorname, *brand = ""; 1949 int class = CPUCLASS_386; 1950 unsigned int i; 1951 int modif, family; 1952 const struct cpu_cpuid_nameclass *cpup = NULL; 1953 const struct cpu_cpuid_family *cpufam; 1954 struct cpu_info *ci, cistore; 1955 u_int descs[4]; 1956 size_t sz; 1957 struct cpu_ucode_version ucode; 1958 union { 1959 struct cpu_ucode_version_amd amd; 1960 struct cpu_ucode_version_intel1 intel1; 1961 } ucvers; 1962 1963 ci = &cistore; 1964 cpu_probe_base_features(ci, cpuname); 1965 dump_descs(0x00000000, ci->ci_max_cpuid, cpuname, "basic"); 1966 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1967 x86_cpuid(0x40000000, descs); 1968 dump_descs(0x40000000, descs[0], cpuname, "hypervisor"); 1969 } 1970 dump_descs(0x80000000, ci->ci_max_ext_cpuid, cpuname, "extended"); 1971 1972 cpu_probe_hv_features(ci, cpuname); 1973 cpu_probe_features(ci); 1974 1975 if (ci->ci_cpu_type >= 0) { 1976 /* Old pre-cpuid instruction cpu */ 1977 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1978 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1979 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1980 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1981 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1982 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1983 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1984 modifier = ""; 1985 } else { 1986 /* CPU which support cpuid instruction */ 1987 modif = (ci->ci_signature >> 12) & 0x3; 1988 family = ci->ci_family; 1989 if (family < CPU_MINFAMILY) 1990 errx(1, "identifycpu: strange family value"); 1991 if (family > CPU_MAXFAMILY) 1992 family = CPU_MAXFAMILY; 1993 1994 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1995 if (!strncmp((char *)ci->ci_vendor, 1996 i386_cpuid_cpus[i].cpu_id, 12)) { 1997 cpup = &i386_cpuid_cpus[i]; 1998 break; 1999 } 2000 } 2001 2002 if (cpup == NULL) { 2003 cpu_vendor = CPUVENDOR_UNKNOWN; 2004 if (ci->ci_vendor[0] != '\0') 2005 vendorname = (char *)&ci->ci_vendor[0]; 2006 else 2007 vendorname = "Unknown"; 2008 class = family - 3; 2009 modifier = ""; 2010 name = ""; 2011 ci->ci_info = NULL; 2012 } else { 2013 cpu_vendor = cpup->cpu_vendor; 2014 vendorname = cpup->cpu_vendorname; 2015 modifier = modifiers[modif]; 2016 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 2017 name = cpufam->cpu_models[ci->ci_model]; 2018 if (name == NULL || *name == '\0') 2019 name = cpufam->cpu_model_default; 2020 class = cpufam->cpu_class; 2021 ci->ci_info = cpufam->cpu_info; 2022 2023 if (cpu_vendor == CPUVENDOR_INTEL) { 2024 if (ci->ci_family == 6 && ci->ci_model >= 5) { 2025 const char *tmp; 2026 tmp = intel_family6_name(ci); 2027 if (tmp != NULL) 2028 name = tmp; 2029 } 2030 if (ci->ci_family == 15 && 2031 ci->ci_brand_id < 2032 __arraycount(i386_intel_brand) && 2033 i386_intel_brand[ci->ci_brand_id]) 2034 name = 2035 i386_intel_brand[ci->ci_brand_id]; 2036 } 2037 2038 if (cpu_vendor == CPUVENDOR_AMD) { 2039 if (ci->ci_family == 6 && ci->ci_model >= 6) { 2040 if (ci->ci_brand_id == 1) 2041 /* 2042 * It's Duron. We override the 2043 * name, since it might have 2044 * been misidentified as Athlon. 2045 */ 2046 name = 2047 amd_brand[ci->ci_brand_id]; 2048 else 2049 brand = amd_brand_name; 2050 } 2051 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 2052 == 0xf) { 2053 /* Identify AMD64 CPU names. */ 2054 const char *tmp; 2055 tmp = amd_amd64_name(ci); 2056 if (tmp != NULL) 2057 name = tmp; 2058 } 2059 } 2060 2061 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 2062 vendorname = "VIA"; 2063 } 2064 } 2065 2066 ci->ci_cpu_class = class; 2067 2068 sz = sizeof(ci->ci_tsc_freq); 2069 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 2070 sz = sizeof(use_pae); 2071 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 2072 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 2073 2074 /* 2075 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 2076 * we try to determine from the family/model values. 2077 */ 2078 if (*cpu_brand_string != '\0') 2079 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 2080 2081 aprint_normal("%s: %s", cpuname, vendorname); 2082 if (*modifier) 2083 aprint_normal(" %s", modifier); 2084 if (*name) 2085 aprint_normal(" %s", name); 2086 if (*brand) 2087 aprint_normal(" %s", brand); 2088 aprint_normal(" (%s-class)", classnames[class]); 2089 2090 if (ci->ci_tsc_freq != 0) 2091 aprint_normal(", %ju.%02ju MHz", 2092 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 2093 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 2094 aprint_normal("\n"); 2095 2096 (void)cpu_tsc_freq_cpuid(ci); 2097 2098 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 2099 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 2100 if (ci->ci_signature != 0) 2101 aprint_normal(" (id %#x)", ci->ci_signature); 2102 aprint_normal("\n"); 2103 2104 if (ci->ci_info) 2105 (*ci->ci_info)(ci); 2106 2107 /* 2108 * display CPU feature flags 2109 */ 2110 2111 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 2112 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 2113 2114 /* These next two are actually common definitions! */ 2115 print_bits(cpuname, "features2", 2116 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 2117 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 2118 print_bits(cpuname, "features3", 2119 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 2120 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 2121 2122 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 2123 ci->ci_feat_val[4]); 2124 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2125 print_bits(cpuname, "features5", CPUID_SEF_FLAGS, 2126 ci->ci_feat_val[5]); 2127 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2128 print_bits(cpuname, "features6", CPUID_SEF_FLAGS1, 2129 ci->ci_feat_val[6]); 2130 2131 if (cpu_vendor == CPUVENDOR_INTEL) 2132 print_bits(cpuname, "features7", CPUID_SEF_FLAGS2, 2133 ci->ci_feat_val[7]); 2134 2135 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[8]); 2136 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 2137 ci->ci_feat_val[9]); 2138 2139 if (ci->ci_max_xsave != 0) { 2140 aprint_normal("%s: xsave area size: current %d, maximum %d", 2141 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 2142 aprint_normal(", xgetbv %sabled\n", 2143 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 2144 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 2145 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 2146 x86_xgetbv()); 2147 } 2148 2149 x86_print_cache_and_tlb_info(ci); 2150 2151 if (ci->ci_max_cpuid >= 3 && (ci->ci_feat_val[0] & CPUID_PSN)) { 2152 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 2153 cpuname, 2154 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 2155 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 2156 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 2157 } 2158 2159 if (ci->ci_cpu_class == CPUCLASS_386) 2160 errx(1, "NetBSD requires an 80486 or later processor"); 2161 2162 if (ci->ci_cpu_type == CPU_486DLC) { 2163 #ifndef CYRIX_CACHE_WORKS 2164 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 2165 #else 2166 #ifndef CYRIX_CACHE_REALLY_WORKS 2167 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 2168 #else 2169 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 2170 #endif 2171 #endif 2172 } 2173 2174 /* 2175 * Everything past this point requires a Pentium or later. 2176 */ 2177 if (ci->ci_max_cpuid < 0) 2178 return; 2179 2180 identifycpu_cpuids(ci); 2181 2182 if ((ci->ci_max_cpuid >= 5) 2183 && ((cpu_vendor == CPUVENDOR_INTEL) 2184 || (cpu_vendor == CPUVENDOR_AMD))) { 2185 uint16_t lmin, lmax; 2186 x86_cpuid(5, descs); 2187 2188 print_bits(cpuname, "MONITOR/MWAIT extensions", 2189 CPUID_MON_FLAGS, descs[2]); 2190 lmin = __SHIFTOUT(descs[0], CPUID_MON_MINSIZE); 2191 lmax = __SHIFTOUT(descs[1], CPUID_MON_MAXSIZE); 2192 aprint_normal("%s: monitor-line size %hu", cpuname, lmin); 2193 if (lmin != lmax) 2194 aprint_normal("-%hu", lmax); 2195 aprint_normal("\n"); 2196 2197 for (i = 0; i <= 7; i++) { 2198 unsigned int num = CPUID_MON_SUBSTATE(descs[3], i); 2199 2200 if (num != 0) 2201 aprint_normal("%s: C%u substates %u\n", 2202 cpuname, i, num); 2203 } 2204 } 2205 if ((ci->ci_max_cpuid >= 6) 2206 && ((cpu_vendor == CPUVENDOR_INTEL) 2207 || (cpu_vendor == CPUVENDOR_AMD))) { 2208 x86_cpuid(6, descs); 2209 print_bits(cpuname, "DSPM-eax", CPUID_DSPM_FLAGS, descs[0]); 2210 print_bits(cpuname, "DSPM-ecx", CPUID_DSPM_FLAGS1, descs[2]); 2211 } 2212 if ((ci->ci_max_cpuid >= 7) 2213 && ((cpu_vendor == CPUVENDOR_INTEL) 2214 || (cpu_vendor == CPUVENDOR_AMD))) { 2215 unsigned int maxsubleaf; 2216 2217 x86_cpuid(7, descs); 2218 maxsubleaf = descs[0]; 2219 aprint_verbose("%s: SEF highest subleaf %08x\n", 2220 cpuname, maxsubleaf); 2221 if (maxsubleaf >= 1) { 2222 x86_cpuid2(7, 1, descs); 2223 print_bits(cpuname, "SEF-subleaf1-eax", 2224 CPUID_SEF1_FLAGS_A, descs[0]); 2225 print_bits(cpuname, "SEF-subleaf1-ebx", 2226 CPUID_SEF1_FLAGS_B, descs[1]); 2227 print_bits(cpuname, "SEF-subleaf1-edx", 2228 CPUID_SEF1_FLAGS_D, descs[3]); 2229 } 2230 if (maxsubleaf >= 2) { 2231 x86_cpuid2(7, 2, descs); 2232 print_bits(cpuname, "SEF-subleaf2-edx", 2233 CPUID_SEF2_FLAGS_D, descs[3]); 2234 } 2235 } 2236 2237 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) { 2238 if (ci->ci_max_ext_cpuid >= 0x80000007) 2239 powernow_probe(ci); 2240 2241 if (ci->ci_max_ext_cpuid >= 0x80000008) { 2242 x86_cpuid(0x80000008, descs); 2243 print_bits(cpuname, "AMD Extended features", 2244 CPUID_CAPEX_FLAGS, descs[1]); 2245 } 2246 } 2247 2248 if (cpu_vendor == CPUVENDOR_AMD) { 2249 if (ci->ci_max_ext_cpuid >= 0x80000021) { 2250 x86_cpuid(0x80000021, descs); 2251 print_bits(cpuname, "AMD Extended features2", 2252 CPUID_AMDEXT2_FLAGS, descs[0]); 2253 } 2254 2255 if (ci->ci_max_ext_cpuid >= 0x80000007) { 2256 x86_cpuid(0x80000007, descs); 2257 print_bits(cpuname, "RAS features", 2258 CPUID_RAS_FLAGS, descs[1]); 2259 } 2260 if ((ci->ci_max_ext_cpuid >= 0x8000000a) 2261 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 2262 x86_cpuid(0x8000000a, descs); 2263 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 2264 descs[0] & 0xf); 2265 aprint_verbose("%s: SVM NASID %d\n", cpuname, 2266 descs[1]); 2267 print_bits(cpuname, "SVM features", 2268 CPUID_AMD_SVM_FLAGS, descs[3]); 2269 } 2270 if (ci->ci_max_ext_cpuid >= 0x8000001b) { 2271 x86_cpuid(0x8000001b, descs); 2272 print_bits(cpuname, "IBS features", 2273 CPUID_IBS_FLAGS, descs[0]); 2274 } 2275 if (ci->ci_max_ext_cpuid >= 0x8000001f) { 2276 x86_cpuid(0x8000001f, descs); 2277 print_bits(cpuname, "Encrypted Memory features", 2278 CPUID_AMD_ENCMEM_FLAGS, descs[0]); 2279 } 2280 if (ci->ci_max_ext_cpuid >= 0x80000022) { 2281 uint8_t ncore, nnb, numc, nlbrs; 2282 2283 x86_cpuid(0x80000022, descs); 2284 print_bits(cpuname, "Perfmon:", 2285 CPUID_AXPERF_FLAGS, descs[0]); 2286 2287 ncore = __SHIFTOUT(descs[1], CPUID_AXPERF_NCPC); 2288 nnb = __SHIFTOUT(descs[1], CPUID_AXPERF_NNBPC); 2289 numc = __SHIFTOUT(descs[1], CPUID_AXPERF_NUMCPC); 2290 nlbrs = __SHIFTOUT(descs[1], CPUID_AXPERF_NLBRSTACK); 2291 aprint_verbose("%s: Perfmon: counters: " 2292 "Core %hhu, Northbridge %hhu, UMC %hhu\n", cpuname, 2293 ncore, nnb, numc); 2294 aprint_verbose("%s: Perfmon: LBR Stack %hhu entries\n", 2295 cpuname, nlbrs); 2296 } 2297 } else if (cpu_vendor == CPUVENDOR_INTEL) { 2298 if (ci->ci_max_cpuid >= 0x0a) { 2299 unsigned int pmcver, ncounter, veclen; 2300 2301 x86_cpuid(0x0a, descs); 2302 pmcver = __SHIFTOUT(descs[0], CPUID_PERF_VERSION); 2303 ncounter = __SHIFTOUT(descs[0], CPUID_PERF_NGPPC); 2304 veclen = __SHIFTOUT(descs[0], CPUID_PERF_BVECLEN); 2305 aprint_verbose("%s: Perfmon: Ver. %u", 2306 cpuname, pmcver); 2307 if (((pmcver >= 3) && (pmcver <= 4)) || 2308 ((pmcver >= 5) && 2309 (descs[3] & CPUID_PERF_ANYTHREADDEPR) == 0)) 2310 aprint_verbose(" <ANYTHREAD>\n"); 2311 else 2312 aprint_verbose("\n"); 2313 2314 aprint_verbose("%s: Perfmon: General: " 2315 "bitwidth %u, %u counters\n", cpuname, 2316 (uint32_t)__SHIFTOUT(descs[0], CPUID_PERF_NBWGPPC), 2317 ncounter); 2318 /* Invert logic for the output */ 2319 descs[1] ^= __BITS(veclen - 1, 0); 2320 /* 2321 * Mask unrelated bits. An hypervisor reduces the 2322 * vector and set bit(s) out of the vector. 2323 */ 2324 descs[1] &= __BITS(veclen - 1, 0); 2325 print_bits(cpuname, "Perfmon: General: avail", 2326 CPUID_PERF_FLAGS1, descs[1]); 2327 2328 if (pmcver >= 2) { 2329 ncounter = __SHIFTOUT(descs[3], 2330 CPUID_PERF_NFFPC); 2331 aprint_verbose("%s: Perfmon: Fixed: " 2332 "bitwidth %u, %u counters\n", cpuname, 2333 (uint32_t)__SHIFTOUT(descs[3], 2334 CPUID_PERF_NBWFFPC), 2335 ncounter); 2336 if (pmcver <= 4) 2337 descs[2] = __BITS(ncounter - 1, 0); 2338 print_bits(cpuname, "Perfmon: Fixed: avail", 2339 CPUID_PERF_FLAGS2, descs[2]); 2340 } 2341 } 2342 if (ci->ci_max_cpuid >= 0x1a) { 2343 x86_cpuid(0x1a, descs); 2344 if (descs[0] != 0) { 2345 aprint_verbose("%s: Hybrid: Core type %02x, " 2346 "Native Model ID %07x\n", 2347 cpuname, 2348 (uint8_t)__SHIFTOUT(descs[0], 2349 CPUID_HYBRID_CORETYPE), 2350 (uint32_t)__SHIFTOUT(descs[0], 2351 CPUID_HYBRID_NATIVEID)); 2352 } 2353 } 2354 } 2355 2356 #ifdef INTEL_ONDEMAND_CLOCKMOD 2357 clockmod_init(); 2358 #endif 2359 2360 if (cpu_vendor == CPUVENDOR_AMD) 2361 ucode.loader_version = CPU_UCODE_LOADER_AMD; 2362 else if (cpu_vendor == CPUVENDOR_INTEL) 2363 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 2364 else 2365 return; 2366 2367 ucode.data = &ucvers; 2368 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 2369 #ifdef __i386__ 2370 struct cpu_ucode_version_64 ucode_64; 2371 if (errno != ENOTTY) 2372 return; 2373 /* Try the 64 bit ioctl */ 2374 memset(&ucode_64, 0, sizeof ucode_64); 2375 ucode_64.data = &ucvers; 2376 ucode_64.loader_version = ucode.loader_version; 2377 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 2378 return; 2379 #else 2380 return; 2381 #endif 2382 } 2383 2384 if (cpu_vendor == CPUVENDOR_AMD) 2385 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2386 else if (cpu_vendor == CPUVENDOR_INTEL) 2387 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2388 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2389 } 2390 2391 static const char * 2392 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2393 const char *sep) 2394 { 2395 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2396 char human_num[HUMAN_BUFSIZE]; 2397 2398 if (cai->cai_totalsize == 0) 2399 return sep; 2400 2401 if (sep == NULL) 2402 aprint_verbose_dev(ci->ci_dev, ""); 2403 else 2404 aprint_verbose("%s", sep); 2405 if (name != NULL) 2406 aprint_verbose("%s ", name); 2407 2408 if (cai->cai_string != NULL) { 2409 aprint_verbose("%s ", cai->cai_string); 2410 } else { 2411 (void)humanize_number(human_num, sizeof(human_num), 2412 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2413 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2414 } 2415 switch (cai->cai_associativity) { 2416 case 0: 2417 aprint_verbose("disabled"); 2418 break; 2419 case 1: 2420 aprint_verbose("direct-mapped"); 2421 break; 2422 case 0xff: 2423 aprint_verbose("fully associative"); 2424 break; 2425 default: 2426 aprint_verbose("%d-way", cai->cai_associativity); 2427 break; 2428 } 2429 return ", "; 2430 } 2431 2432 static const char * 2433 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2434 const char *sep) 2435 { 2436 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2437 char human_num[HUMAN_BUFSIZE]; 2438 2439 if (cai->cai_totalsize == 0) 2440 return sep; 2441 2442 if (sep == NULL) 2443 aprint_verbose_dev(ci->ci_dev, ""); 2444 else 2445 aprint_verbose("%s", sep); 2446 if ((name != NULL) && (sep == NULL)) 2447 aprint_verbose("%s ", name); 2448 2449 if (cai->cai_string != NULL) { 2450 aprint_verbose("%s", cai->cai_string); 2451 } else { 2452 (void)humanize_number(human_num, sizeof(human_num), 2453 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2454 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2455 human_num); 2456 switch (cai->cai_associativity) { 2457 case 0: 2458 aprint_verbose("disabled"); 2459 break; 2460 case 1: 2461 aprint_verbose("direct-mapped"); 2462 break; 2463 case 0xff: 2464 aprint_verbose("fully associative"); 2465 break; 2466 default: 2467 aprint_verbose("%d-way", cai->cai_associativity); 2468 break; 2469 } 2470 } 2471 return ", "; 2472 } 2473 2474 static void 2475 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2476 { 2477 const char *sep = NULL; 2478 2479 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2480 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2481 sep = print_cache_config(ci, CAI_ICACHE, "I-cache:", NULL); 2482 sep = print_cache_config(ci, CAI_DCACHE, "D-cache:", sep); 2483 if (sep != NULL) 2484 aprint_verbose("\n"); 2485 } 2486 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2487 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache:", NULL); 2488 if (sep != NULL) 2489 aprint_verbose("\n"); 2490 } 2491 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2492 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache:", NULL); 2493 if (sep != NULL) 2494 aprint_verbose("\n"); 2495 } 2496 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2497 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2498 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2499 if (sep != NULL) 2500 aprint_verbose("\n"); 2501 } 2502 2503 sep = print_tlb_config(ci, CAI_ITLB, "ITLB:", NULL); 2504 sep = print_tlb_config(ci, CAI_ITLB2, "ITLB:", sep); 2505 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "ITLB:", sep); 2506 if (sep != NULL) 2507 aprint_verbose("\n"); 2508 2509 sep = print_tlb_config(ci, CAI_DTLB, "DTLB:", NULL); 2510 sep = print_tlb_config(ci, CAI_DTLB2, "DTLB:", sep); 2511 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "DTLB:", sep); 2512 if (sep != NULL) 2513 aprint_verbose("\n"); 2514 2515 sep = print_tlb_config(ci, CAI_L1_LD_TLB, "Load only TLB:", NULL); 2516 if (sep != NULL) 2517 aprint_verbose("\n"); 2518 2519 sep = print_tlb_config(ci, CAI_L1_ST_TLB, "Store only TLB:", NULL); 2520 if (sep != NULL) 2521 aprint_verbose("\n"); 2522 2523 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB:", NULL); 2524 sep = print_tlb_config(ci, CAI_L2_ITLB2, "L2 ITLB:", sep); 2525 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 ITLB:", sep); 2526 if (sep != NULL) 2527 aprint_verbose("\n"); 2528 2529 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB:", NULL); 2530 sep = print_tlb_config(ci, CAI_L2_DTLB2, "L2 DTLB:", sep); 2531 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 DTLB:", sep); 2532 if (sep != NULL) 2533 aprint_verbose("\n"); 2534 2535 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB:", NULL); 2536 sep = print_tlb_config(ci, CAI_L2_STLB2, "L2 STLB:", sep); 2537 sep = print_tlb_config(ci, CAI_L2_STLB3, "L2 STLB:", sep); 2538 if (sep != NULL) 2539 aprint_verbose("\n"); 2540 } 2541 2542 static void 2543 powernow_probe(struct cpu_info *ci) 2544 { 2545 uint32_t regs[4]; 2546 char buf[256]; 2547 2548 x86_cpuid(0x80000007, regs); 2549 2550 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2551 aprint_normal_dev(ci->ci_dev, "Power Management features: %s\n", buf); 2552 } 2553 2554 bool 2555 identifycpu_bind(void) 2556 { 2557 2558 return true; 2559 } 2560 2561 int 2562 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2563 { 2564 struct cpu_info ci; 2565 int loader_version, res; 2566 struct cpu_ucode_version versreq; 2567 2568 cpu_probe_base_features(&ci, "unknown"); 2569 2570 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2571 loader_version = CPU_UCODE_LOADER_AMD; 2572 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2573 loader_version = CPU_UCODE_LOADER_INTEL1; 2574 else 2575 return -1; 2576 2577 /* check whether the kernel understands this loader version */ 2578 versreq.loader_version = loader_version; 2579 versreq.data = 0; 2580 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2581 if (res) 2582 return -1; 2583 2584 switch (loader_version) { 2585 case CPU_UCODE_LOADER_AMD: 2586 if (uc->cpu_nr != -1) { 2587 /* printf? */ 2588 return -1; 2589 } 2590 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2591 break; 2592 case CPU_UCODE_LOADER_INTEL1: 2593 if (uc->cpu_nr == -1) 2594 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2595 else 2596 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2597 break; 2598 default: /* can't happen */ 2599 return -1; 2600 } 2601 uc->loader_version = loader_version; 2602 return 0; 2603 } 2604
Indexes created Fri Sep 26 20:09:58 GMT 2025