i386.c revision 1.146
1 /* $NetBSD: i386.c,v 1.146 2024/10/19 16:32:43 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.146 2024/10/19 16:32:43 msaitoh Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cpu_ucode.h> 85 86 #include "../cpuctl.h" 87 #include "cpuctl_i386.h" 88 89 /* Size of buffer for printing humanized numbers */ 90 #define HUMAN_BUFSIZE sizeof("999KB") 91 92 struct cpu_nocpuid_nameclass { 93 int cpu_vendor; 94 const char *cpu_vendorname; 95 const char *cpu_name; 96 int cpu_class; 97 void (*cpu_setup)(struct cpu_info *); 98 void (*cpu_cacheinfo)(struct cpu_info *); 99 void (*cpu_info)(struct cpu_info *); 100 }; 101 102 struct cpu_cpuid_nameclass { 103 const char *cpu_id; 104 int cpu_vendor; 105 const char *cpu_vendorname; 106 struct cpu_cpuid_family { 107 int cpu_class; 108 const char *cpu_models[256]; 109 const char *cpu_model_default; 110 void (*cpu_setup)(struct cpu_info *); 111 void (*cpu_probe)(struct cpu_info *); 112 void (*cpu_info)(struct cpu_info *); 113 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 114 }; 115 116 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 117 118 /* 119 * Map Brand ID from cpuid instruction to brand name. 120 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 121 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 122 * Architectures Software Developer's Manual, Volume 2A". 123 */ 124 static const char * const i386_intel_brand[] = { 125 "", /* Unsupported */ 126 "Celeron", /* Intel (R) Celeron (TM) processor */ 127 "Pentium III", /* Intel (R) Pentium (R) III processor */ 128 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 129 "Pentium III", /* Intel (R) Pentium (R) III processor */ 130 "", /* 0x05: Reserved */ 131 "Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */ 132 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 133 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 134 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 135 "Celeron", /* Intel (R) Celeron (TM) processor */ 136 "Xeon", /* Intel (R) Xeon (TM) processor */ 137 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 138 "", /* 0x0d: Reserved */ 139 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 140 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 141 "", /* 0x10: Reserved */ 142 "Mobile Genuine", /* Mobile Genuine Intel (R) processor */ 143 "Celeron M", /* Intel (R) Celeron (R) M processor */ 144 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 145 "Celeron", /* Intel (R) Celeron (R) processor */ 146 "Mobile Genuine", /* Mobile Genuine Intel (R) processor */ 147 "Pentium M", /* Intel (R) Pentium (R) M processor */ 148 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 149 }; 150 151 /* 152 * AMD processors don't have Brand IDs, so we need these names for probe. 153 */ 154 static const char * const amd_brand[] = { 155 "", 156 "Duron", /* AMD Duron(tm) */ 157 "MP", /* AMD Athlon(tm) MP */ 158 "XP", /* AMD Athlon(tm) XP */ 159 "4" /* AMD Athlon(tm) 4 */ 160 }; 161 162 int cpu_vendor; 163 static char cpu_brand_string[49]; 164 static char amd_brand_name[48]; 165 static int use_pae, largepagesize; 166 167 /* Setup functions */ 168 static void disable_tsc(struct cpu_info *); 169 static void amd_family5_setup(struct cpu_info *); 170 static void cyrix6x86_cpu_setup(struct cpu_info *); 171 static void winchip_cpu_setup(struct cpu_info *); 172 /* Brand/Model name functions */ 173 static const char *intel_family6_name(struct cpu_info *); 174 static const char *amd_amd64_name(struct cpu_info *); 175 /* Probe functions */ 176 static void amd_family6_probe(struct cpu_info *); 177 static void powernow_probe(struct cpu_info *); 178 static void intel_family_new_probe(struct cpu_info *); 179 static void via_cpu_probe(struct cpu_info *); 180 /* (Cache) Info functions */ 181 static void intel_cpu_cacheinfo(struct cpu_info *); 182 static void amd_cpu_cacheinfo(struct cpu_info *); 183 static void via_cpu_cacheinfo(struct cpu_info *); 184 static void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 185 static void transmeta_cpu_info(struct cpu_info *); 186 /* Common functions */ 187 static void cpu_probe_base_features(struct cpu_info *, const char *); 188 static void cpu_probe_hv_features(struct cpu_info *, const char *); 189 static void cpu_probe_features(struct cpu_info *); 190 static void print_bits(const char *, const char *, const char *, uint32_t); 191 static void identifycpu_cpuids(struct cpu_info *); 192 static const char *print_cache_config(struct cpu_info *, int, const char *, 193 const char *); 194 static const char *print_tlb_config(struct cpu_info *, int, const char *, 195 const char *); 196 static void x86_print_cache_and_tlb_info(struct cpu_info *); 197 198 /* 199 * Note: these are just the ones that may not have a cpuid instruction. 200 * We deal with the rest in a different way. 201 */ 202 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 203 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 204 NULL, NULL, NULL }, /* CPU_386SX */ 205 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 206 NULL, NULL, NULL }, /* CPU_386 */ 207 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 208 NULL, NULL, NULL }, /* CPU_486SX */ 209 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 210 NULL, NULL, NULL }, /* CPU_486 */ 211 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 212 NULL, NULL, NULL }, /* CPU_486DLC */ 213 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 214 NULL, NULL, NULL }, /* CPU_6x86 */ 215 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 216 NULL, NULL, NULL }, /* CPU_NX586 */ 217 }; 218 219 const char *classnames[] = { 220 "386", 221 "486", 222 "586", 223 "686" 224 }; 225 226 const char *modifiers[] = { 227 "", 228 "OverDrive", 229 "Dual", 230 "" 231 }; 232 233 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 234 { 235 /* 236 * For Intel processors, check Chapter 35Model-specific 237 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 238 * Software Developer's Manual, Volume 3C". 239 */ 240 "GenuineIntel", 241 CPUVENDOR_INTEL, 242 "Intel", 243 /* Family 4 */ 244 { { 245 CPUCLASS_486, 246 { 247 "486DX", "486DX", "486SX", "486DX2", "486SL", 248 "486SX2", 0, "486DX2 W/B Enhanced", 249 "486DX4", 0, 0, 0, 0, 0, 0, 0, 250 }, 251 "486", /* Default */ 252 NULL, 253 NULL, 254 intel_cpu_cacheinfo, 255 }, 256 /* Family 5 */ 257 { 258 CPUCLASS_586, 259 { 260 "Pentium (P5 A-step)", "Pentium (P5)", 261 "Pentium (P54C)", "Pentium (P24T)", 262 "Pentium/MMX", "Pentium", 0, 263 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 264 "Quark X1000", 0, 0, 0, 0, 0, 0, 265 }, 266 "Pentium", /* Default */ 267 NULL, 268 NULL, 269 intel_cpu_cacheinfo, 270 }, 271 /* Family 6 */ 272 { 273 CPUCLASS_686, 274 { 275 [0x00] = "Pentium Pro (A-step)", 276 [0x01] = "Pentium Pro", 277 [0x03] = "Pentium II (Klamath)", 278 [0x04] = "Pentium Pro", 279 [0x05] = "Pentium II/Celeron (Deschutes)", 280 [0x06] = "Celeron (Mendocino)", 281 [0x07] = "Pentium III (Katmai)", 282 [0x08] = "Pentium III (Coppermine)", 283 [0x09] = "Pentium M (Banias)", 284 [0x0a] = "Pentium III Xeon (Cascades)", 285 [0x0b] = "Pentium III (Tualatin)", 286 [0x0d] = "Pentium M (Dothan)", 287 [0x0e] = "Pentium Core Duo, Core solo", 288 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 289 "Core 2 Quad 6xxx, " 290 "Core 2 Extreme 6xxx, " 291 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 292 "and Pentium DC", 293 [0x15] = "EP80579 Integrated Processor", 294 [0x16] = "Celeron (45nm)", 295 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 296 "Core 2 Quad 8xxx and 9xxx", 297 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 298 "(Nehalem)", 299 [0x1c] = "45nm Atom Family", 300 [0x1d] = "XeonMP 74xx (Nehalem)", 301 [0x1e] = "Core i7 and i5", 302 [0x1f] = "Core i7 and i5", 303 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 304 [0x26] = "Atom Family", 305 [0x27] = "Atom Family", 306 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 307 "i3 2xxx", 308 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 309 [0x2d] = "Xeon E5 Sandy Bridge family, " 310 "Core i7-39xx Extreme", 311 [0x2e] = "Xeon 75xx & 65xx", 312 [0x2f] = "Xeon E7 family", 313 [0x35] = "Atom Family", 314 [0x36] = "Atom S1000", 315 [0x37] = "Atom E3000, Z3[67]00", 316 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 317 "Ivy Bridge", 318 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 319 "(Haswell)", 320 [0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)", 321 [0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), " 322 "Core i7-49xx Extreme", 323 [0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), " 324 "Core i7-59xx Extreme", 325 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 326 "(Haswell)", 327 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 328 "(Haswell)", 329 [0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)", 330 [0x4a] = "Atom Z3400", 331 [0x4c] = "Atom X[57]-Z8000 (Airmont)", 332 [0x4d] = "Atom C2000", 333 [0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 334 [0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme", 335 [0x55] = "Xeon Scalable (Skylake, Cascade Lake, Copper Lake)", 336 [0x56] = "Xeon D-1500 (Broadwell)", 337 [0x57] = "Xeon Phi [357]200 (Knights Landing)", 338 [0x5a] = "Atom Z3500", 339 [0x5c] = "Atom (Goldmont)", 340 [0x5d] = "Atom X3-C3000 (Silvermont)", 341 [0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)", 342 [0x5f] = "Atom (Goldmont, Denverton)", 343 [0x66] = "8th gen Core i3 (Cannon Lake)", 344 [0x6a] = "3rd gen Xeon Scalable (Ice Lake)", 345 [0x6c] = "3rd gen Xeon Scalable (Ice Lake)", 346 [0x7a] = "Atom (Goldmont Plus)", 347 [0x7d] = "10th gen Core (Ice Lake)", 348 [0x7e] = "10th gen Core (Ice Lake)", 349 [0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)", 350 [0x86] = "Atom (Tremont)", 351 [0x8c] = "11th gen Core (Tiger Lake)", 352 [0x8d] = "11th gen Core (Tiger Lake)", 353 [0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 354 [0x8f] = "4th gen Xeon Scalable (Sapphire Rapids)", 355 [0x96] = "Atom x6000E (Elkhart Lake)", 356 [0x97] = "12th gen Core (Alder Lake)", 357 [0x9a] = "12th gen Core (Alder Lake)", 358 [0x9c] = "Pentium Silver N6xxx, Celeron N45xx, Celeron N51xx (Jasper Lake)", 359 [0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)", 360 [0xa5] = "10th gen Core (Comet Lake)", 361 [0xa6] = "10th gen Core (Comet Lake)", 362 [0xa7] = "11th gen Core (Rocket Lake)", 363 [0xa8] = "11th gen Core (Rocket Lake)", 364 [0xaa] = "Core Ultra 7 (Meteor Lake)", 365 [0xb7] = "13th gen Core (Raptor Lake)", 366 [0xba] = "13th gen Core (Raptor Lake)", 367 [0xbe] = "Core i3-N3xx N[12]xx Nxx Atom x7xxxE (Alder Lake-N)", 368 [0xbf] = "13th gen Core (Raptor Lake)", 369 [0xcf] = "5th gen Xeon Scalable (Emerald Rapids)", 370 }, 371 "Pentium Pro, II or III", /* Default */ 372 NULL, 373 intel_family_new_probe, 374 intel_cpu_cacheinfo, 375 }, 376 /* Family > 6 */ 377 { 378 CPUCLASS_686, 379 { 380 0, 0, 0, 0, 0, 0, 0, 0, 381 0, 0, 0, 0, 0, 0, 0, 0, 382 }, 383 "Pentium 4", /* Default */ 384 NULL, 385 intel_family_new_probe, 386 intel_cpu_cacheinfo, 387 } } 388 }, 389 { 390 "AuthenticAMD", 391 CPUVENDOR_AMD, 392 "AMD", 393 /* Family 4 */ 394 { { 395 CPUCLASS_486, 396 { 397 0, 0, 0, "Am486DX2 W/T", 398 0, 0, 0, "Am486DX2 W/B", 399 "Am486DX4 W/T or Am5x86 W/T 150", 400 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 401 0, 0, "Am5x86 W/T 133/160", 402 "Am5x86 W/B 133/160", 403 }, 404 "Am486 or Am5x86", /* Default */ 405 NULL, 406 NULL, 407 NULL, 408 }, 409 /* Family 5 */ 410 { 411 CPUCLASS_586, 412 { 413 "K5", "K5", "K5", "K5", 0, 0, "K6", 414 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 415 "K6-2+/III+", 0, 0, 416 }, 417 "K5 or K6", /* Default */ 418 amd_family5_setup, 419 NULL, 420 amd_cpu_cacheinfo, 421 }, 422 /* Family 6 */ 423 { 424 CPUCLASS_686, 425 { 426 0, "Athlon Model 1", "Athlon Model 2", 427 "Duron", "Athlon Model 4 (Thunderbird)", 428 0, "Athlon", "Duron", "Athlon", 0, 429 "Athlon", 0, 0, 0, 0, 0, 430 }, 431 "K7 (Athlon)", /* Default */ 432 NULL, 433 amd_family6_probe, 434 amd_cpu_cacheinfo, 435 }, 436 /* Family > 6 */ 437 { 438 CPUCLASS_686, 439 { 440 0, 0, 0, 0, 0, 0, 0, 0, 441 0, 0, 0, 0, 0, 0, 0, 0, 442 }, 443 "Unknown K8 (Athlon)", /* Default */ 444 NULL, 445 amd_family6_probe, 446 amd_cpu_cacheinfo, 447 } } 448 }, 449 { 450 "CyrixInstead", 451 CPUVENDOR_CYRIX, 452 "Cyrix", 453 /* Family 4 */ 454 { { 455 CPUCLASS_486, 456 { 457 0, 0, 0, 458 "MediaGX", 459 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 460 }, 461 "486", /* Default */ 462 cyrix6x86_cpu_setup, /* XXX ?? */ 463 NULL, 464 NULL, 465 }, 466 /* Family 5 */ 467 { 468 CPUCLASS_586, 469 { 470 0, 0, "6x86", 0, 471 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 472 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 473 }, 474 "6x86", /* Default */ 475 cyrix6x86_cpu_setup, 476 NULL, 477 NULL, 478 }, 479 /* Family 6 */ 480 { 481 CPUCLASS_686, 482 { 483 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 484 0, 0, 0, 0, 0, 0, 0, 0, 485 }, 486 "6x86MX", /* Default */ 487 cyrix6x86_cpu_setup, 488 NULL, 489 NULL, 490 }, 491 /* Family > 6 */ 492 { 493 CPUCLASS_686, 494 { 495 0, 0, 0, 0, 0, 0, 0, 0, 496 0, 0, 0, 0, 0, 0, 0, 0, 497 }, 498 "Unknown 6x86MX", /* Default */ 499 NULL, 500 NULL, 501 NULL, 502 } } 503 }, 504 { /* MediaGX is now owned by National Semiconductor */ 505 "Geode by NSC", 506 CPUVENDOR_CYRIX, /* XXX */ 507 "National Semiconductor", 508 /* Family 4, NSC never had any of these */ 509 { { 510 CPUCLASS_486, 511 { 512 0, 0, 0, 0, 0, 0, 0, 0, 513 0, 0, 0, 0, 0, 0, 0, 0, 514 }, 515 "486 compatible", /* Default */ 516 NULL, 517 NULL, 518 NULL, 519 }, 520 /* Family 5: Geode family, formerly MediaGX */ 521 { 522 CPUCLASS_586, 523 { 524 0, 0, 0, 0, 525 "Geode GX1", 526 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 527 }, 528 "Geode", /* Default */ 529 cyrix6x86_cpu_setup, 530 NULL, 531 amd_cpu_cacheinfo, 532 }, 533 /* Family 6, not yet available from NSC */ 534 { 535 CPUCLASS_686, 536 { 537 0, 0, 0, 0, 0, 0, 0, 0, 538 0, 0, 0, 0, 0, 0, 0, 0, 539 }, 540 "Pentium Pro compatible", /* Default */ 541 NULL, 542 NULL, 543 NULL, 544 }, 545 /* Family > 6, not yet available from NSC */ 546 { 547 CPUCLASS_686, 548 { 549 0, 0, 0, 0, 0, 0, 0, 0, 550 0, 0, 0, 0, 0, 0, 0, 0, 551 }, 552 "Pentium Pro compatible", /* Default */ 553 NULL, 554 NULL, 555 NULL, 556 } } 557 }, 558 { 559 "CentaurHauls", 560 CPUVENDOR_IDT, 561 "IDT", 562 /* Family 4, IDT never had any of these */ 563 { { 564 CPUCLASS_486, 565 { 566 0, 0, 0, 0, 0, 0, 0, 0, 567 0, 0, 0, 0, 0, 0, 0, 0, 568 }, 569 "486 compatible", /* Default */ 570 NULL, 571 NULL, 572 NULL, 573 }, 574 /* Family 5 */ 575 { 576 CPUCLASS_586, 577 { 578 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 579 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 580 }, 581 "WinChip", /* Default */ 582 winchip_cpu_setup, 583 NULL, 584 NULL, 585 }, 586 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 587 { 588 CPUCLASS_686, 589 { 590 0, 0, 0, 0, 0, 0, "C3 Samuel", 591 "C3 Samuel 2/Ezra", "C3 Ezra-T", 592 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 593 0, "VIA Nano", 594 }, 595 "Unknown VIA/IDT", /* Default */ 596 NULL, 597 via_cpu_probe, 598 via_cpu_cacheinfo, 599 }, 600 /* Family > 6, not yet available from VIA */ 601 { 602 CPUCLASS_686, 603 { 604 0, 0, 0, 0, 0, 0, 0, 0, 605 0, 0, 0, 0, 0, 0, 0, 0, 606 }, 607 "Pentium Pro compatible", /* Default */ 608 NULL, 609 NULL, 610 NULL, 611 } } 612 }, 613 { 614 "GenuineTMx86", 615 CPUVENDOR_TRANSMETA, 616 "Transmeta", 617 /* Family 4, Transmeta never had any of these */ 618 { { 619 CPUCLASS_486, 620 { 621 0, 0, 0, 0, 0, 0, 0, 0, 622 0, 0, 0, 0, 0, 0, 0, 0, 623 }, 624 "486 compatible", /* Default */ 625 NULL, 626 NULL, 627 NULL, 628 }, 629 /* Family 5 */ 630 { 631 CPUCLASS_586, 632 { 633 0, 0, 0, 0, 0, 0, 0, 0, 634 0, 0, 0, 0, 0, 0, 0, 0, 635 }, 636 "Crusoe", /* Default */ 637 NULL, 638 NULL, 639 transmeta_cpu_info, 640 }, 641 /* Family 6, not yet available from Transmeta */ 642 { 643 CPUCLASS_686, 644 { 645 0, 0, 0, 0, 0, 0, 0, 0, 646 0, 0, 0, 0, 0, 0, 0, 0, 647 }, 648 "Pentium Pro compatible", /* Default */ 649 NULL, 650 NULL, 651 NULL, 652 }, 653 /* Family > 6, not yet available from Transmeta */ 654 { 655 CPUCLASS_686, 656 { 657 0, 0, 0, 0, 0, 0, 0, 0, 658 0, 0, 0, 0, 0, 0, 0, 0, 659 }, 660 "Pentium Pro compatible", /* Default */ 661 NULL, 662 NULL, 663 NULL, 664 } } 665 } 666 }; 667 668 /* 669 * disable the TSC such that we don't use the TSC in microtime(9) 670 * because some CPUs got the implementation wrong. 671 */ 672 static void 673 disable_tsc(struct cpu_info *ci) 674 { 675 if (ci->ci_feat_val[0] & CPUID_TSC) { 676 ci->ci_feat_val[0] &= ~CPUID_TSC; 677 aprint_error("WARNING: broken TSC disabled\n"); 678 } 679 } 680 681 static void 682 amd_family5_setup(struct cpu_info *ci) 683 { 684 685 switch (ci->ci_model) { 686 case 0: /* AMD-K5 Model 0 */ 687 /* 688 * According to the AMD Processor Recognition App Note, 689 * the AMD-K5 Model 0 uses the wrong bit to indicate 690 * support for global PTEs, instead using bit 9 (APIC) 691 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 692 */ 693 if (ci->ci_feat_val[0] & CPUID_APIC) 694 ci->ci_feat_val[0] = 695 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 696 /* 697 * XXX But pmap_pg_g is already initialized -- need to kick 698 * XXX the pmap somehow. How does the MP branch do this? 699 */ 700 break; 701 } 702 } 703 704 static void 705 cyrix6x86_cpu_setup(struct cpu_info *ci) 706 { 707 708 /* 709 * Do not disable the TSC on the Geode GX, it's reported to 710 * work fine. 711 */ 712 if (ci->ci_signature != 0x552) 713 disable_tsc(ci); 714 } 715 716 static void 717 winchip_cpu_setup(struct cpu_info *ci) 718 { 719 switch (ci->ci_model) { 720 case 4: /* WinChip C6 */ 721 disable_tsc(ci); 722 } 723 } 724 725 726 static const char * 727 intel_family6_name(struct cpu_info *ci) 728 { 729 const char *ret = NULL; 730 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 731 732 if (ci->ci_model == 5) { 733 switch (l2cache) { 734 case 0: 735 case 128 * 1024: 736 ret = "Celeron (Covington)"; 737 break; 738 case 256 * 1024: 739 ret = "Mobile Pentium II (Dixon)"; 740 break; 741 case 512 * 1024: 742 ret = "Pentium II"; 743 break; 744 case 1 * 1024 * 1024: 745 case 2 * 1024 * 1024: 746 ret = "Pentium II Xeon"; 747 break; 748 } 749 } else if (ci->ci_model == 6) { 750 switch (l2cache) { 751 case 256 * 1024: 752 case 512 * 1024: 753 ret = "Mobile Pentium II"; 754 break; 755 } 756 } else if (ci->ci_model == 7) { 757 switch (l2cache) { 758 case 512 * 1024: 759 ret = "Pentium III"; 760 break; 761 case 1 * 1024 * 1024: 762 case 2 * 1024 * 1024: 763 ret = "Pentium III Xeon"; 764 break; 765 } 766 } else if (ci->ci_model >= 8) { 767 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 768 switch (ci->ci_brand_id) { 769 case 0x3: 770 if (ci->ci_signature == 0x6B1) 771 ret = "Celeron"; 772 break; 773 case 0x8: 774 if (ci->ci_signature >= 0xF13) 775 ret = "genuine processor"; 776 break; 777 case 0xB: 778 if (ci->ci_signature >= 0xF13) 779 ret = "Xeon MP"; 780 break; 781 case 0xE: 782 if (ci->ci_signature < 0xF13) 783 ret = "Xeon"; 784 break; 785 } 786 if (ret == NULL) 787 ret = i386_intel_brand[ci->ci_brand_id]; 788 } 789 } 790 791 return ret; 792 } 793 794 /* 795 * Identify AMD64 CPU names from cpuid. 796 * 797 * Based on: 798 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 799 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 800 * "Revision Guide for AMD NPT Family 0Fh Processors" 801 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 802 * and other miscellaneous reports. 803 * 804 * This is all rather pointless, these are cross 'brand' since the raw 805 * silicon is shared. 806 */ 807 static const char * 808 amd_amd64_name(struct cpu_info *ci) 809 { 810 static char family_str[32]; 811 812 /* Only called if family >= 15 */ 813 814 switch (ci->ci_family) { 815 case 15: 816 switch (ci->ci_model) { 817 case 0x21: /* rev JH-E1/E6 */ 818 case 0x41: /* rev JH-F2 */ 819 return "Dual-Core Opteron"; 820 case 0x23: /* rev JH-E6 (Toledo) */ 821 return "Dual-Core Opteron or Athlon 64 X2"; 822 case 0x43: /* rev JH-F2 (Windsor) */ 823 return "Athlon 64 FX or Athlon 64 X2"; 824 case 0x24: /* rev SH-E5 (Lancaster?) */ 825 return "Mobile Athlon 64 or Turion 64"; 826 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 827 return "Opteron or Athlon 64 FX"; 828 case 0x15: /* rev SH-D0 */ 829 case 0x25: /* rev SH-E4 */ 830 return "Opteron"; 831 case 0x27: /* rev DH-E4, SH-E4 */ 832 return "Athlon 64 or Athlon 64 FX or Opteron"; 833 case 0x48: /* rev BH-F2 */ 834 return "Turion 64 X2"; 835 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 836 case 0x07: /* rev SH-CG (ClawHammer) */ 837 case 0x0b: /* rev CH-CG */ 838 case 0x14: /* rev SH-D0 */ 839 case 0x17: /* rev SH-D0 */ 840 case 0x1b: /* rev CH-D0 */ 841 return "Athlon 64"; 842 case 0x2b: /* rev BH-E4 (Manchester) */ 843 case 0x4b: /* rev BH-F2 (Windsor) */ 844 return "Athlon 64 X2"; 845 case 0x6b: /* rev BH-G1 (Brisbane) */ 846 return "Athlon X2 or Athlon 64 X2"; 847 case 0x08: /* rev CH-CG */ 848 case 0x0c: /* rev DH-CG (Newcastle) */ 849 case 0x0e: /* rev DH-CG (Newcastle?) */ 850 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 851 case 0x18: /* rev CH-D0 */ 852 case 0x1c: /* rev DH-D0 (Winchester) */ 853 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 854 case 0x2c: /* rev DH-E3/E6 */ 855 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 856 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 857 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 858 case 0x6f: /* rev DH-G1 */ 859 return "Athlon 64 or Sempron"; 860 default: 861 break; 862 } 863 return "Unknown AMD64 CPU"; 864 865 #if 0 866 case 16: 867 return "Family 10h"; 868 case 17: 869 return "Family 11h"; 870 case 18: 871 return "Family 12h"; 872 case 19: 873 return "Family 14h"; 874 case 20: 875 return "Family 15h"; 876 #endif 877 878 default: 879 break; 880 } 881 882 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 883 return family_str; 884 } 885 886 static void 887 intel_family_new_probe(struct cpu_info *ci) 888 { 889 uint32_t descs[4]; 890 891 x86_cpuid(0x80000000, descs); 892 893 /* 894 * Determine extended feature flags. 895 */ 896 if (descs[0] >= 0x80000001) { 897 x86_cpuid(0x80000001, descs); 898 ci->ci_feat_val[2] |= descs[3]; 899 ci->ci_feat_val[3] |= descs[2]; 900 } 901 } 902 903 static void 904 via_cpu_probe(struct cpu_info *ci) 905 { 906 u_int stepping = CPUID_TO_STEPPING(ci->ci_signature); 907 u_int descs[4]; 908 u_int lfunc; 909 910 /* 911 * Determine the largest extended function value. 912 */ 913 x86_cpuid(0x80000000, descs); 914 lfunc = descs[0]; 915 916 /* 917 * Determine the extended feature flags. 918 */ 919 if (lfunc >= 0x80000001) { 920 x86_cpuid(0x80000001, descs); 921 ci->ci_feat_val[2] |= descs[3]; 922 } 923 924 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 925 return; 926 927 /* Nehemiah or Esther */ 928 x86_cpuid(0xc0000000, descs); 929 lfunc = descs[0]; 930 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 931 return; 932 933 x86_cpuid(0xc0000001, descs); 934 lfunc = descs[3]; 935 ci->ci_feat_val[4] = lfunc; 936 } 937 938 static void 939 amd_family6_probe(struct cpu_info *ci) 940 { 941 uint32_t descs[4]; 942 char *p; 943 size_t i; 944 945 x86_cpuid(0x80000000, descs); 946 947 /* 948 * Determine the extended feature flags. 949 */ 950 if (descs[0] >= 0x80000001) { 951 x86_cpuid(0x80000001, descs); 952 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 953 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 954 } 955 956 if (*cpu_brand_string == '\0') 957 return; 958 959 for (i = 1; i < __arraycount(amd_brand); i++) 960 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 961 ci->ci_brand_id = i; 962 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 963 break; 964 } 965 } 966 967 static void 968 intel_cpu_cacheinfo(struct cpu_info *ci) 969 { 970 const struct x86_cache_info *cai; 971 u_int descs[4]; 972 int iterations, i, j; 973 int type, level, ways, linesize, sets; 974 int caitype = -1; 975 uint8_t desc; 976 977 /* Return if the cpu is old pre-cpuid instruction cpu */ 978 if (ci->ci_cpu_type >= 0) 979 return; 980 981 if (ci->ci_max_cpuid < 2) 982 return; 983 984 /* 985 * Parse the cache info from `cpuid leaf 2', if we have it. 986 * XXX This is kinda ugly, but hey, so is the architecture... 987 */ 988 x86_cpuid(2, descs); 989 iterations = descs[0] & 0xff; 990 while (iterations-- > 0) { 991 for (i = 0; i < 4; i++) { 992 if (descs[i] & 0x80000000) 993 continue; 994 for (j = 0; j < 4; j++) { 995 /* 996 * The least significant byte in EAX 997 * ((desc[0] >> 0) & 0xff) is always 0x01 and 998 * it should be ignored. 999 */ 1000 if (i == 0 && j == 0) 1001 continue; 1002 desc = (descs[i] >> (j * 8)) & 0xff; 1003 if (desc == 0) 1004 continue; 1005 cai = cpu_cacheinfo_lookup( 1006 intel_cpuid_cache_info, desc); 1007 if (cai != NULL) 1008 ci->ci_cinfo[cai->cai_index] = *cai; 1009 else if ((verbose != 0) && (desc != 0xff) 1010 && (desc != 0xfe)) 1011 aprint_error_dev(ci->ci_dev, "error:" 1012 " Unknown cacheinfo desc %02x\n", 1013 desc); 1014 } 1015 } 1016 x86_cpuid(2, descs); 1017 } 1018 1019 if (ci->ci_max_cpuid < 4) 1020 return; 1021 1022 /* Parse the cache info from `cpuid leaf 4', if we have it. */ 1023 cpu_dcp_cacheinfo(ci, 4); 1024 1025 if (ci->ci_max_cpuid < 0x18) 1026 return; 1027 /* Parse the TLB info from `cpuid leaf 18H', if we have it. */ 1028 x86_cpuid(0x18, descs); 1029 iterations = descs[0]; 1030 for (i = 0; i <= iterations; i++) { 1031 uint32_t pgsize; 1032 bool full; 1033 1034 x86_cpuid2(0x18, i, descs); 1035 type = __SHIFTOUT(descs[3], CPUID_DATP_TCTYPE); 1036 if (type == CPUID_DATP_TCTYPE_N) 1037 continue; 1038 level = __SHIFTOUT(descs[3], CPUID_DATP_TCLEVEL); 1039 pgsize = __SHIFTOUT(descs[1], CPUID_DATP_PGSIZE); 1040 switch (level) { 1041 case 1: 1042 if (type == CPUID_DATP_TCTYPE_I) { 1043 switch (pgsize) { 1044 case CPUID_DATP_PGSIZE_4KB: 1045 caitype = CAI_ITLB; 1046 break; 1047 case CPUID_DATP_PGSIZE_2MB 1048 | CPUID_DATP_PGSIZE_4MB: 1049 caitype = CAI_ITLB2; 1050 break; 1051 case CPUID_DATP_PGSIZE_1GB: 1052 caitype = CAI_L1_1GBITLB; 1053 break; 1054 default: 1055 aprint_error_dev(ci->ci_dev, 1056 "error: unknown ITLB size (%d)\n", 1057 pgsize); 1058 caitype = CAI_ITLB; 1059 break; 1060 } 1061 } else if (type == CPUID_DATP_TCTYPE_D) { 1062 switch (pgsize) { 1063 case CPUID_DATP_PGSIZE_4KB: 1064 caitype = CAI_DTLB; 1065 break; 1066 case CPUID_DATP_PGSIZE_2MB 1067 | CPUID_DATP_PGSIZE_4MB: 1068 caitype = CAI_DTLB2; 1069 break; 1070 case CPUID_DATP_PGSIZE_1GB: 1071 caitype = CAI_L1_1GBDTLB; 1072 break; 1073 default: 1074 aprint_error_dev(ci->ci_dev, 1075 "error: unknown DTLB size (%d)\n", 1076 pgsize); 1077 caitype = CAI_DTLB; 1078 break; 1079 } 1080 } else if (type == CPUID_DATP_TCTYPE_L) 1081 caitype = CAI_L1_LD_TLB; 1082 else if (type == CPUID_DATP_TCTYPE_S) 1083 caitype = CAI_L1_ST_TLB; 1084 else 1085 caitype = -1; 1086 break; 1087 case 2: 1088 if (type == CPUID_DATP_TCTYPE_I) 1089 caitype = CAI_L2_ITLB; 1090 else if (type == CPUID_DATP_TCTYPE_D) 1091 caitype = CAI_L2_DTLB; 1092 else if (type == CPUID_DATP_TCTYPE_U) { 1093 if (pgsize == CPUID_DATP_PGSIZE_4KB) 1094 caitype = CAI_L2_STLB; 1095 else if (pgsize == (CPUID_DATP_PGSIZE_4KB 1096 | CPUID_DATP_PGSIZE_2MB)) 1097 caitype = CAI_L2_STLB2; 1098 else if (pgsize == (CPUID_DATP_PGSIZE_2MB 1099 | CPUID_DATP_PGSIZE_4MB)) 1100 caitype = CAI_L2_STLB3; 1101 else if ((pgsize & CPUID_DATP_PGSIZE_1GB) 1102 != 0) { 1103 /* FIXME: 1GB max TLB */ 1104 caitype = CAI_L2_STLB3; 1105 linesize = 1024 * 1024 * 1024; 1106 } else if ((pgsize & CPUID_DATP_PGSIZE_4MB) 1107 != 0) { 1108 /* FIXME: 4MB max TLB */ 1109 caitype = CAI_L2_STLB3; 1110 linesize = 4 * 1024 * 1024; 1111 } else if ((pgsize & CPUID_DATP_PGSIZE_2MB) 1112 != 0) { 1113 /* FIXME: 2MB max TLB */ 1114 caitype = CAI_L2_STLB2; 1115 linesize = 2 * 1024 * 1024; 1116 } else { 1117 aprint_error_dev(ci->ci_dev, "error: " 1118 "unknown L2 STLB size (%d)\n", 1119 pgsize); 1120 caitype = CAI_L2_STLB; 1121 linesize = 4 * 1024; 1122 } 1123 } else 1124 caitype = -1; 1125 break; 1126 case 3: 1127 /* XXX need work for L3 TLB */ 1128 caitype = CAI_L3CACHE; 1129 break; 1130 default: 1131 caitype = -1; 1132 break; 1133 } 1134 if (caitype == -1) { 1135 aprint_error_dev(ci->ci_dev, 1136 "error: unknown TLB level&type (%d & %d)\n", 1137 level, type); 1138 continue; 1139 } 1140 switch (pgsize) { 1141 case CPUID_DATP_PGSIZE_4KB: 1142 linesize = 4 * 1024; 1143 break; 1144 case CPUID_DATP_PGSIZE_2MB: 1145 linesize = 2 * 1024 * 1024; 1146 break; 1147 case CPUID_DATP_PGSIZE_4MB: 1148 linesize = 4 * 1024 * 1024; 1149 break; 1150 case CPUID_DATP_PGSIZE_1GB: 1151 linesize = 1024 * 1024 * 1024; 1152 break; 1153 default: 1154 if ((pgsize & CPUID_DATP_PGSIZE_1GB) != 0) 1155 linesize = 1024 * 1024 * 1024; /* MAX 1G */ 1156 else if ((pgsize & CPUID_DATP_PGSIZE_4MB) != 0) 1157 linesize = 4 * 1024 * 1024; /* MAX 4M */ 1158 else if ((pgsize & CPUID_DATP_PGSIZE_2MB) != 0) 1159 linesize = 2 * 1024 * 1024; /* MAX 2M */ 1160 else 1161 linesize = 4 * 1024; /* XXX default to 4K */ 1162 aprint_error_dev(ci->ci_dev, "WARNING: Currently " 1163 "this info can't print correctly " 1164 "(level = %d, pgsize = %d)\n", 1165 level, pgsize); 1166 break; 1167 } 1168 ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS); 1169 sets = descs[2]; 1170 full = descs[3] & CPUID_DATP_FULLASSOC; 1171 ci->ci_cinfo[caitype].cai_totalsize 1172 = ways * sets; /* entries */ 1173 ci->ci_cinfo[caitype].cai_associativity 1174 = full ? 0xff : ways; 1175 ci->ci_cinfo[caitype].cai_linesize = linesize; /* pg size */ 1176 } 1177 } 1178 1179 static const struct x86_cache_info amd_cpuid_l2l3cache_assoc_info[] = 1180 AMD_L2L3CACHE_INFO; 1181 1182 static void 1183 amd_cpu_cacheinfo(struct cpu_info *ci) 1184 { 1185 const struct x86_cache_info *cp; 1186 struct x86_cache_info *cai; 1187 u_int descs[4]; 1188 u_int lfunc; 1189 bool l2tlbx32 = false; 1190 1191 /* K5 model 0 has none of this info. */ 1192 if (ci->ci_family == 5 && ci->ci_model == 0) 1193 return; 1194 1195 /* Determine the largest extended function value. */ 1196 x86_cpuid(0x80000000, descs); 1197 lfunc = descs[0]; 1198 1199 if (lfunc < 0x80000005) 1200 return; 1201 1202 /* Determine L1 cache/TLB info. */ 1203 x86_cpuid(0x80000005, descs); 1204 1205 /* K6-III and higher have large page TLBs. */ 1206 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1207 cai = &ci->ci_cinfo[CAI_ITLB2]; 1208 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1209 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1210 cai->cai_linesize = largepagesize; 1211 1212 cai = &ci->ci_cinfo[CAI_DTLB2]; 1213 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1214 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1215 cai->cai_linesize = largepagesize; 1216 } 1217 1218 cai = &ci->ci_cinfo[CAI_ITLB]; 1219 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1220 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1221 cai->cai_linesize = (4 * 1024); 1222 1223 cai = &ci->ci_cinfo[CAI_DTLB]; 1224 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1225 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1226 cai->cai_linesize = (4 * 1024); 1227 1228 cai = &ci->ci_cinfo[CAI_DCACHE]; 1229 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1230 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1231 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1232 1233 cai = &ci->ci_cinfo[CAI_ICACHE]; 1234 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1235 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1236 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1237 1238 if (lfunc < 0x80000006) 1239 return; 1240 1241 /* Determine L2 cache/TLB info. */ 1242 if (lfunc >= 0x80000021) { 1243 x86_cpuid(0x80000021, descs); 1244 l2tlbx32 = descs[0] & CPUID_AMDEXT2_L2TLBSIZEX32; 1245 } 1246 x86_cpuid(0x80000006, descs); 1247 1248 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1249 cai->cai_totalsize = 1250 AMD_L2_EBX_IUTLB_ENTRIES(descs[1]) * (l2tlbx32 ? 32 : 1); 1251 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1252 cai->cai_linesize = (4 * 1024); 1253 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1254 cai->cai_associativity); 1255 if (cp != NULL) 1256 cai->cai_associativity = cp->cai_associativity; 1257 else 1258 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1259 1260 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1261 cai->cai_totalsize = 1262 AMD_L2_EAX_IUTLB_ENTRIES(descs[0]) * (l2tlbx32 ? 32 : 1); 1263 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1264 cai->cai_linesize = largepagesize; 1265 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1266 cai->cai_associativity); 1267 if (cp != NULL) 1268 cai->cai_associativity = cp->cai_associativity; 1269 else 1270 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1271 1272 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1273 cai->cai_totalsize = 1274 AMD_L2_EBX_DTLB_ENTRIES(descs[1]) * (l2tlbx32 ? 32 : 1); 1275 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1276 cai->cai_linesize = (4 * 1024); 1277 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1278 cai->cai_associativity); 1279 if (cp != NULL) 1280 cai->cai_associativity = cp->cai_associativity; 1281 else 1282 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1283 1284 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1285 cai->cai_totalsize = 1286 AMD_L2_EAX_DTLB_ENTRIES(descs[0]) * (l2tlbx32 ? 32 : 1); 1287 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1288 cai->cai_linesize = largepagesize; 1289 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1290 cai->cai_associativity); 1291 if (cp != NULL) 1292 cai->cai_associativity = cp->cai_associativity; 1293 else 1294 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1295 1296 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1297 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1298 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1299 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1300 1301 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1302 cai->cai_associativity); 1303 if (cp != NULL) 1304 cai->cai_associativity = cp->cai_associativity; 1305 else 1306 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1307 1308 /* Determine L3 cache info on AMD Family 10h and newer processors */ 1309 if (ci->ci_family >= 0x10) { 1310 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1311 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1312 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1313 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1314 1315 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1316 cai->cai_associativity); 1317 if (cp != NULL) 1318 cai->cai_associativity = cp->cai_associativity; 1319 else 1320 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1321 } 1322 1323 if (lfunc < 0x80000019) 1324 return; 1325 1326 /* Determine 1GB TLB info. */ 1327 x86_cpuid(0x80000019, descs); 1328 1329 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1330 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1331 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1332 cai->cai_linesize = (1024 * 1024 * 1024); 1333 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1334 cai->cai_associativity); 1335 if (cp != NULL) 1336 cai->cai_associativity = cp->cai_associativity; 1337 else 1338 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1339 1340 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1341 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1342 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1343 cai->cai_linesize = (1024 * 1024 * 1024); 1344 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1345 cai->cai_associativity); 1346 if (cp != NULL) 1347 cai->cai_associativity = cp->cai_associativity; 1348 else 1349 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1350 1351 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1352 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1353 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1354 cai->cai_linesize = (1024 * 1024 * 1024); 1355 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1356 cai->cai_associativity); 1357 if (cp != NULL) 1358 cai->cai_associativity = cp->cai_associativity; 1359 else 1360 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1361 1362 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1363 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1364 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1365 cai->cai_linesize = (1024 * 1024 * 1024); 1366 cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info, 1367 cai->cai_associativity); 1368 if (cp != NULL) 1369 cai->cai_associativity = cp->cai_associativity; 1370 else 1371 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1372 1373 if (lfunc < 0x8000001d) 1374 return; 1375 1376 if (ci->ci_feat_val[3] & CPUID_TOPOEXT) 1377 cpu_dcp_cacheinfo(ci, 0x8000001d); 1378 } 1379 1380 static void 1381 via_cpu_cacheinfo(struct cpu_info *ci) 1382 { 1383 struct x86_cache_info *cai; 1384 int stepping; 1385 u_int descs[4]; 1386 u_int lfunc; 1387 1388 stepping = CPUID_TO_STEPPING(ci->ci_signature); 1389 1390 /* 1391 * Determine the largest extended function value. 1392 */ 1393 x86_cpuid(0x80000000, descs); 1394 lfunc = descs[0]; 1395 1396 /* 1397 * Determine L1 cache/TLB info. 1398 */ 1399 if (lfunc < 0x80000005) { 1400 /* No L1 cache info available. */ 1401 return; 1402 } 1403 1404 x86_cpuid(0x80000005, descs); 1405 1406 cai = &ci->ci_cinfo[CAI_ITLB]; 1407 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1408 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1409 cai->cai_linesize = (4 * 1024); 1410 1411 cai = &ci->ci_cinfo[CAI_DTLB]; 1412 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1413 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1414 cai->cai_linesize = (4 * 1024); 1415 1416 cai = &ci->ci_cinfo[CAI_DCACHE]; 1417 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1418 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1419 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1420 if (ci->ci_model == 9 && stepping == 8) { 1421 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1422 cai->cai_associativity = 2; 1423 } 1424 1425 cai = &ci->ci_cinfo[CAI_ICACHE]; 1426 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1427 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1428 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1429 if (ci->ci_model == 9 && stepping == 8) { 1430 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1431 cai->cai_associativity = 2; 1432 } 1433 1434 /* 1435 * Determine L2 cache/TLB info. 1436 */ 1437 if (lfunc < 0x80000006) { 1438 /* No L2 cache info available. */ 1439 return; 1440 } 1441 1442 x86_cpuid(0x80000006, descs); 1443 1444 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1445 if (ci->ci_model >= 9) { 1446 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1447 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1448 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1449 } else { 1450 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1451 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1452 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1453 } 1454 } 1455 1456 static void 1457 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1458 { 1459 u_int descs[4]; 1460 1461 x86_cpuid(0x80860007, descs); 1462 *frequency = descs[0]; 1463 *voltage = descs[1]; 1464 *percentage = descs[2]; 1465 } 1466 1467 static void 1468 transmeta_cpu_info(struct cpu_info *ci) 1469 { 1470 u_int descs[4], nreg; 1471 u_int frequency, voltage, percentage; 1472 1473 x86_cpuid(0x80860000, descs); 1474 nreg = descs[0]; 1475 if (nreg >= 0x80860001) { 1476 x86_cpuid(0x80860001, descs); 1477 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1478 (descs[1] >> 24) & 0xff, 1479 (descs[1] >> 16) & 0xff, 1480 (descs[1] >> 8) & 0xff, 1481 descs[1] & 0xff); 1482 } 1483 if (nreg >= 0x80860002) { 1484 x86_cpuid(0x80860002, descs); 1485 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1486 (descs[1] >> 24) & 0xff, 1487 (descs[1] >> 16) & 0xff, 1488 (descs[1] >> 8) & 0xff, 1489 descs[1] & 0xff, 1490 descs[2]); 1491 } 1492 if (nreg >= 0x80860006) { 1493 union { 1494 char text[65]; 1495 u_int descs[4][4]; 1496 } info; 1497 int i; 1498 1499 for (i=0; i<4; i++) { 1500 x86_cpuid(0x80860003 + i, info.descs[i]); 1501 } 1502 info.text[64] = '\0'; 1503 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1504 } 1505 1506 if (nreg >= 0x80860007) { 1507 tmx86_get_longrun_status(&frequency, 1508 &voltage, &percentage); 1509 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1510 frequency, voltage, percentage); 1511 } 1512 } 1513 1514 static void 1515 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 1516 { 1517 u_int descs[4]; 1518 int i; 1519 uint32_t brand[12]; 1520 1521 memset(ci, 0, sizeof(*ci)); 1522 ci->ci_dev = cpuname; 1523 1524 ci->ci_cpu_type = x86_identify(); 1525 if (ci->ci_cpu_type >= 0) { 1526 /* Old pre-cpuid instruction cpu */ 1527 ci->ci_max_cpuid = -1; 1528 return; 1529 } 1530 1531 /* 1532 * This CPU supports cpuid instruction, so we can call x86_cpuid() 1533 * function. 1534 */ 1535 1536 /* 1537 * Fn0000_0000: 1538 * - Save cpuid max level. 1539 * - Save vendor string. 1540 */ 1541 x86_cpuid(0, descs); 1542 ci->ci_max_cpuid = descs[0]; 1543 /* Save vendor string */ 1544 ci->ci_vendor[0] = descs[1]; 1545 ci->ci_vendor[2] = descs[2]; 1546 ci->ci_vendor[1] = descs[3]; 1547 ci->ci_vendor[3] = 0; 1548 1549 /* 1550 * Fn8000_0000: 1551 * - Get cpuid extended function's max level. 1552 */ 1553 x86_cpuid(0x80000000, descs); 1554 if (descs[0] >= 0x80000000) 1555 ci->ci_max_ext_cpuid = descs[0]; 1556 else { 1557 /* Set lower value than 0x80000000 */ 1558 ci->ci_max_ext_cpuid = 0; 1559 } 1560 1561 /* 1562 * Fn8000_000[2-4]: 1563 * - Save brand string. 1564 */ 1565 if (ci->ci_max_ext_cpuid >= 0x80000004) { 1566 x86_cpuid(0x80000002, brand); 1567 x86_cpuid(0x80000003, brand + 4); 1568 x86_cpuid(0x80000004, brand + 8); 1569 for (i = 0; i < 48; i++) 1570 if (((char *) brand)[i] != ' ') 1571 break; 1572 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1573 } 1574 1575 if (ci->ci_max_cpuid < 1) 1576 return; 1577 1578 /* 1579 * Fn0000_0001: 1580 * - Get CPU family, model and stepping (from eax). 1581 * - Initial local APIC ID and brand ID (from ebx) 1582 * - CPUID2 (from ecx) 1583 * - CPUID (from edx) 1584 */ 1585 x86_cpuid(1, descs); 1586 ci->ci_signature = descs[0]; 1587 1588 /* Extract full family/model values */ 1589 ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature); 1590 ci->ci_model = CPUID_TO_MODEL(ci->ci_signature); 1591 1592 /* Brand is low order 8 bits of ebx */ 1593 ci->ci_brand_id = __SHIFTOUT(descs[1], CPUID_BRAND_INDEX); 1594 /* Initial local APIC ID */ 1595 ci->ci_initapicid = __SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID); 1596 1597 ci->ci_feat_val[1] = descs[2]; 1598 ci->ci_feat_val[0] = descs[3]; 1599 1600 if (ci->ci_max_cpuid < 3) 1601 return; 1602 1603 /* 1604 * If the processor serial number misfeature is present and supported, 1605 * extract it here. 1606 */ 1607 if ((ci->ci_feat_val[0] & CPUID_PSN) != 0) { 1608 ci->ci_cpu_serial[0] = ci->ci_signature; 1609 x86_cpuid(3, descs); 1610 ci->ci_cpu_serial[2] = descs[2]; 1611 ci->ci_cpu_serial[1] = descs[3]; 1612 } 1613 1614 if (ci->ci_max_cpuid < 0x7) 1615 return; 1616 1617 x86_cpuid(7, descs); 1618 ci->ci_feat_val[5] = descs[1]; 1619 ci->ci_feat_val[6] = descs[2]; 1620 ci->ci_feat_val[7] = descs[3]; 1621 1622 if (ci->ci_max_cpuid < 0xd) 1623 return; 1624 1625 /* Get support XCR0 bits */ 1626 x86_cpuid2(0xd, 0, descs); 1627 ci->ci_feat_val[8] = descs[0]; /* Actually 64 bits */ 1628 ci->ci_cur_xsave = descs[1]; 1629 ci->ci_max_xsave = descs[2]; 1630 1631 /* Additional flags (eg xsaveopt support) */ 1632 x86_cpuid2(0xd, 1, descs); 1633 ci->ci_feat_val[9] = descs[0]; /* Actually 64 bits */ 1634 } 1635 1636 static void 1637 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname) 1638 { 1639 uint32_t descs[4]; 1640 char hv_sig[13]; 1641 char *p; 1642 const char *hv_name; 1643 int i; 1644 1645 /* 1646 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1647 * http://lkml.org/lkml/2008/10/1/246 1648 * 1649 * KB1009458: Mechanisms to determine if software is running in 1650 * a VMware virtual machine 1651 * http://kb.vmware.com/kb/1009458 1652 */ 1653 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1654 x86_cpuid(0x40000000, descs); 1655 for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4) 1656 memcpy(p, &descs[i], sizeof(descs[i])); 1657 *p = '\0'; 1658 /* 1659 * HV vendor ID string 1660 * ------------+-------------- 1661 * HAXM "HAXMHAXMHAXM" 1662 * KVM "KVMKVMKVM" 1663 * Microsoft "Microsoft Hv" 1664 * QEMU(TCG) "TCGTCGTCGTCG" 1665 * VMware "VMwareVMware" 1666 * Xen "XenVMMXenVMM" 1667 * NetBSD "___ NVMM ___" 1668 */ 1669 if (strncmp(hv_sig, "HAXMHAXMHAXM", 12) == 0) 1670 hv_name = "HAXM"; 1671 else if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0) 1672 hv_name = "KVM"; 1673 else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0) 1674 hv_name = "Hyper-V"; 1675 else if (strncmp(hv_sig, "TCGTCGTCGTCG", 12) == 0) 1676 hv_name = "QEMU(TCG)"; 1677 else if (strncmp(hv_sig, "VMwareVMware", 12) == 0) 1678 hv_name = "VMware"; 1679 else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0) 1680 hv_name = "Xen"; 1681 else if (strncmp(hv_sig, "___ NVMM ___", 12) == 0) 1682 hv_name = "NVMM"; 1683 else 1684 hv_name = "unknown"; 1685 1686 printf("%s: Running on hypervisor: %s\n", cpuname, hv_name); 1687 } 1688 } 1689 1690 static void 1691 cpu_probe_features(struct cpu_info *ci) 1692 { 1693 const struct cpu_cpuid_nameclass *cpup = NULL; 1694 unsigned int i; 1695 1696 if (ci->ci_max_cpuid < 1) 1697 return; 1698 1699 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1700 if (!strncmp((char *)ci->ci_vendor, 1701 i386_cpuid_cpus[i].cpu_id, 12)) { 1702 cpup = &i386_cpuid_cpus[i]; 1703 break; 1704 } 1705 } 1706 1707 if (cpup == NULL) 1708 return; 1709 1710 i = ci->ci_family - CPU_MINFAMILY; 1711 1712 if (i >= __arraycount(cpup->cpu_family)) 1713 i = __arraycount(cpup->cpu_family) - 1; 1714 1715 if (cpup->cpu_family[i].cpu_probe == NULL) 1716 return; 1717 1718 (*cpup->cpu_family[i].cpu_probe)(ci); 1719 } 1720 1721 static void 1722 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1723 { 1724 char buf[32 * 16]; 1725 char *bp; 1726 1727 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1728 1729 if (val == 0 || fmt == NULL) 1730 return; 1731 1732 snprintb_m(buf, sizeof(buf), fmt, val, 1733 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1734 bp = buf; 1735 while (*bp != '\0') { 1736 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1737 bp += strlen(bp) + 1; 1738 } 1739 } 1740 #ifdef lint 1741 #define print_bits(cpuname, hdr, fmt, val) \ 1742 do { \ 1743 print_bits(cpuname, hdr, fmt, val); \ 1744 snprintb(NULL, 0, fmt, val); \ 1745 } while (0) 1746 #endif 1747 1748 static void 1749 dump_descs(uint32_t leafstart, uint32_t leafend, const char *cpuname, 1750 const char *blockname) 1751 { 1752 uint32_t descs[4]; 1753 uint32_t leaf; 1754 1755 aprint_verbose("%s: highest %s info %08x\n", cpuname, blockname, 1756 leafend); 1757 1758 if (verbose) { 1759 for (leaf = leafstart; leaf <= leafend; leaf++) { 1760 x86_cpuid(leaf, descs); 1761 printf("%s: %08x: %08x %08x %08x %08x\n", cpuname, 1762 leaf, descs[0], descs[1], descs[2], descs[3]); 1763 } 1764 } 1765 } 1766 1767 static void 1768 identifycpu_cpuids_intel_0x04(struct cpu_info *ci) 1769 { 1770 u_int lp_max = 1; /* logical processors per package */ 1771 u_int smt_max; /* smt per core */ 1772 u_int core_max = 1; /* core per package */ 1773 u_int smt_bits, core_bits; 1774 uint32_t descs[4]; 1775 1776 /* 1777 * 253668.pdf 7.10.2 1778 */ 1779 1780 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1781 x86_cpuid(1, descs); 1782 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1783 } 1784 x86_cpuid2(4, 0, descs); 1785 core_max = __SHIFTOUT(descs[0], CPUID_DCP_CORE_P_PKG) + 1; 1786 1787 assert(lp_max >= core_max); 1788 smt_max = lp_max / core_max; 1789 smt_bits = ilog2(smt_max - 1) + 1; 1790 core_bits = ilog2(core_max - 1) + 1; 1791 1792 if (smt_bits + core_bits) 1793 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 1794 1795 if (core_bits) 1796 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1797 __BITS(smt_bits, smt_bits + core_bits - 1)); 1798 1799 if (smt_bits) 1800 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1801 __BITS((int)0, (int)(smt_bits - 1))); 1802 } 1803 1804 static void 1805 identifycpu_cpuids_intel_0x0b(struct cpu_info *ci) 1806 { 1807 const char *cpuname = ci->ci_dev; 1808 u_int smt_bits, core_bits, core_shift = 0, pkg_shift = 0; 1809 uint32_t descs[4]; 1810 int i; 1811 1812 x86_cpuid(0x0b, descs); 1813 if (descs[1] == 0) { 1814 identifycpu_cpuids_intel_0x04(ci); 1815 return; 1816 } 1817 1818 for (i = 0; ; i++) { 1819 unsigned int shiftnum, lvltype; 1820 x86_cpuid2(0x0b, i, descs); 1821 1822 /* On invalid level, (EAX and) EBX return 0 */ 1823 if (descs[1] == 0) 1824 break; 1825 1826 shiftnum = __SHIFTOUT(descs[0], CPUID_TOP_SHIFTNUM); 1827 lvltype = __SHIFTOUT(descs[2], CPUID_TOP_LVLTYPE); 1828 switch (lvltype) { 1829 case CPUID_TOP_LVLTYPE_SMT: 1830 core_shift = shiftnum; 1831 break; 1832 case CPUID_TOP_LVLTYPE_CORE: 1833 pkg_shift = shiftnum; 1834 break; 1835 case CPUID_TOP_LVLTYPE_INVAL: 1836 aprint_verbose("%s: Invalid level type\n", cpuname); 1837 break; 1838 default: 1839 aprint_verbose("%s: Unknown level type(%d) \n", 1840 cpuname, lvltype); 1841 break; 1842 } 1843 } 1844 1845 assert(pkg_shift >= core_shift); 1846 smt_bits = core_shift; 1847 core_bits = pkg_shift - core_shift; 1848 1849 ci->ci_packageid = ci->ci_initapicid >> pkg_shift; 1850 1851 if (core_bits) 1852 ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid, 1853 __BITS(core_shift, pkg_shift - 1)); 1854 1855 if (smt_bits) 1856 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, 1857 __BITS((int)0, core_shift - 1)); 1858 } 1859 1860 static void 1861 identifycpu_cpuids_intel(struct cpu_info *ci) 1862 { 1863 const char *cpuname = ci->ci_dev; 1864 1865 if (ci->ci_max_cpuid >= 0x0b) 1866 identifycpu_cpuids_intel_0x0b(ci); 1867 else if (ci->ci_max_cpuid >= 4) 1868 identifycpu_cpuids_intel_0x04(ci); 1869 1870 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1871 ci->ci_packageid); 1872 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1873 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1874 } 1875 1876 static void 1877 identifycpu_cpuids_amd(struct cpu_info *ci) 1878 { 1879 const char *cpuname = ci->ci_dev; 1880 u_int lp_max, core_max; 1881 int n, cpu_family, apic_id, smt_bits, core_bits = 0; 1882 uint32_t descs[4]; 1883 1884 apic_id = ci->ci_initapicid; 1885 cpu_family = CPUID_TO_FAMILY(ci->ci_signature); 1886 1887 if (cpu_family < 0xf) 1888 return; 1889 1890 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 1891 x86_cpuid(1, descs); 1892 lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES); 1893 1894 if (cpu_family >= 0x10 && ci->ci_max_ext_cpuid >= 0x8000008) { 1895 x86_cpuid(0x8000008, descs); 1896 core_max = (descs[2] & 0xff) + 1; 1897 n = (descs[2] >> 12) & 0x0f; 1898 if (n != 0) 1899 core_bits = n; 1900 } 1901 } else { 1902 lp_max = 1; 1903 } 1904 core_max = lp_max; 1905 1906 smt_bits = ilog2((lp_max / core_max) - 1) + 1; 1907 if (core_bits == 0) 1908 core_bits = ilog2(core_max - 1) + 1; 1909 1910 #if 0 /* MSRs need kernel mode */ 1911 if (cpu_family < 0x11) { 1912 const uint64_t reg = rdmsr(MSR_NB_CFG); 1913 if ((reg & NB_CFG_INITAPICCPUIDLO) == 0) { 1914 const u_int node_id = apic_id & __BITS(0, 2); 1915 apic_id = (cpu_family == 0xf) ? 1916 (apic_id >> core_bits) | (node_id << core_bits) : 1917 (apic_id >> 5) | (node_id << 2); 1918 } 1919 } 1920 #endif 1921 1922 if (cpu_family >= 0x17) { 1923 x86_cpuid(0x8000001e, descs); 1924 const u_int threads = ((descs[1] >> 8) & 0xff) + 1; 1925 smt_bits = ilog2(threads); 1926 core_bits -= smt_bits; 1927 } 1928 1929 if (smt_bits + core_bits) { 1930 if (smt_bits + core_bits < 32) 1931 ci->ci_packageid = 0; 1932 } 1933 if (core_bits) { 1934 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 1935 ci->ci_coreid = __SHIFTOUT(apic_id, core_mask); 1936 } 1937 if (smt_bits) { 1938 u_int smt_mask = __BITS(0, smt_bits - 1); 1939 ci->ci_smtid = __SHIFTOUT(apic_id, smt_mask); 1940 } 1941 1942 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 1943 ci->ci_packageid); 1944 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 1945 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 1946 } 1947 1948 static void 1949 identifycpu_cpuids(struct cpu_info *ci) 1950 { 1951 const char *cpuname = ci->ci_dev; 1952 1953 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 1954 ci->ci_packageid = ci->ci_initapicid; 1955 ci->ci_coreid = 0; 1956 ci->ci_smtid = 0; 1957 1958 if (cpu_vendor == CPUVENDOR_INTEL) 1959 identifycpu_cpuids_intel(ci); 1960 else if (cpu_vendor == CPUVENDOR_AMD) 1961 identifycpu_cpuids_amd(ci); 1962 } 1963 1964 void 1965 identifycpu(int fd, const char *cpuname) 1966 { 1967 const char *name = "", *modifier, *vendorname, *brand = ""; 1968 int class = CPUCLASS_386; 1969 unsigned int i; 1970 int modif, family; 1971 const struct cpu_cpuid_nameclass *cpup = NULL; 1972 const struct cpu_cpuid_family *cpufam; 1973 struct cpu_info *ci, cistore; 1974 u_int descs[4]; 1975 size_t sz; 1976 struct cpu_ucode_version ucode; 1977 union { 1978 struct cpu_ucode_version_amd amd; 1979 struct cpu_ucode_version_intel1 intel1; 1980 } ucvers; 1981 1982 ci = &cistore; 1983 cpu_probe_base_features(ci, cpuname); 1984 dump_descs(0x00000000, ci->ci_max_cpuid, cpuname, "basic"); 1985 if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) { 1986 x86_cpuid(0x40000000, descs); 1987 dump_descs(0x40000000, descs[0], cpuname, "hypervisor"); 1988 } 1989 dump_descs(0x80000000, ci->ci_max_ext_cpuid, cpuname, "extended"); 1990 1991 cpu_probe_hv_features(ci, cpuname); 1992 cpu_probe_features(ci); 1993 1994 if (ci->ci_cpu_type >= 0) { 1995 /* Old pre-cpuid instruction cpu */ 1996 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1997 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1998 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1999 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 2000 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 2001 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 2002 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 2003 modifier = ""; 2004 } else { 2005 /* CPU which support cpuid instruction */ 2006 modif = (ci->ci_signature >> 12) & 0x3; 2007 family = ci->ci_family; 2008 if (family < CPU_MINFAMILY) 2009 errx(1, "identifycpu: strange family value"); 2010 if (family > CPU_MAXFAMILY) 2011 family = CPU_MAXFAMILY; 2012 2013 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 2014 if (!strncmp((char *)ci->ci_vendor, 2015 i386_cpuid_cpus[i].cpu_id, 12)) { 2016 cpup = &i386_cpuid_cpus[i]; 2017 break; 2018 } 2019 } 2020 2021 if (cpup == NULL) { 2022 cpu_vendor = CPUVENDOR_UNKNOWN; 2023 if (ci->ci_vendor[0] != '\0') 2024 vendorname = (char *)&ci->ci_vendor[0]; 2025 else 2026 vendorname = "Unknown"; 2027 class = family - 3; 2028 modifier = ""; 2029 name = ""; 2030 ci->ci_info = NULL; 2031 } else { 2032 cpu_vendor = cpup->cpu_vendor; 2033 vendorname = cpup->cpu_vendorname; 2034 modifier = modifiers[modif]; 2035 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 2036 name = cpufam->cpu_models[ci->ci_model]; 2037 if (name == NULL || *name == '\0') 2038 name = cpufam->cpu_model_default; 2039 class = cpufam->cpu_class; 2040 ci->ci_info = cpufam->cpu_info; 2041 2042 if (cpu_vendor == CPUVENDOR_INTEL) { 2043 if (ci->ci_family == 6 && ci->ci_model >= 5) { 2044 const char *tmp; 2045 tmp = intel_family6_name(ci); 2046 if (tmp != NULL) 2047 name = tmp; 2048 } 2049 if (ci->ci_family == 15 && 2050 ci->ci_brand_id < 2051 __arraycount(i386_intel_brand) && 2052 i386_intel_brand[ci->ci_brand_id]) 2053 name = 2054 i386_intel_brand[ci->ci_brand_id]; 2055 } 2056 2057 if (cpu_vendor == CPUVENDOR_AMD) { 2058 if (ci->ci_family == 6 && ci->ci_model >= 6) { 2059 if (ci->ci_brand_id == 1) 2060 /* 2061 * It's Duron. We override the 2062 * name, since it might have 2063 * been misidentified as Athlon. 2064 */ 2065 name = 2066 amd_brand[ci->ci_brand_id]; 2067 else 2068 brand = amd_brand_name; 2069 } 2070 if (CPUID_TO_BASEFAMILY(ci->ci_signature) 2071 == 0xf) { 2072 /* Identify AMD64 CPU names. */ 2073 const char *tmp; 2074 tmp = amd_amd64_name(ci); 2075 if (tmp != NULL) 2076 name = tmp; 2077 } 2078 } 2079 2080 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 2081 vendorname = "VIA"; 2082 } 2083 } 2084 2085 ci->ci_cpu_class = class; 2086 2087 sz = sizeof(ci->ci_tsc_freq); 2088 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 2089 sz = sizeof(use_pae); 2090 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 2091 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 2092 2093 /* 2094 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 2095 * we try to determine from the family/model values. 2096 */ 2097 if (*cpu_brand_string != '\0') 2098 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 2099 2100 aprint_normal("%s: %s", cpuname, vendorname); 2101 if (*modifier) 2102 aprint_normal(" %s", modifier); 2103 if (*name) 2104 aprint_normal(" %s", name); 2105 if (*brand) 2106 aprint_normal(" %s", brand); 2107 aprint_normal(" (%s-class)", classnames[class]); 2108 2109 if (ci->ci_tsc_freq != 0) 2110 aprint_normal(", %ju.%02ju MHz", 2111 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 2112 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 2113 aprint_normal("\n"); 2114 2115 (void)cpu_tsc_freq_cpuid(ci); 2116 2117 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 2118 ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature)); 2119 if (ci->ci_signature != 0) 2120 aprint_normal(" (id %#x)", ci->ci_signature); 2121 aprint_normal("\n"); 2122 2123 if (ci->ci_info) 2124 (*ci->ci_info)(ci); 2125 2126 /* 2127 * display CPU feature flags 2128 */ 2129 2130 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 2131 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 2132 2133 /* These next two are actually common definitions! */ 2134 print_bits(cpuname, "features2", 2135 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 2136 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 2137 print_bits(cpuname, "features3", 2138 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 2139 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 2140 2141 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 2142 ci->ci_feat_val[4]); 2143 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2144 print_bits(cpuname, "features5", CPUID_SEF_FLAGS, 2145 ci->ci_feat_val[5]); 2146 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) 2147 print_bits(cpuname, "features6", CPUID_SEF_FLAGS1, 2148 ci->ci_feat_val[6]); 2149 2150 if (cpu_vendor == CPUVENDOR_INTEL) 2151 print_bits(cpuname, "features7", CPUID_SEF_FLAGS2, 2152 ci->ci_feat_val[7]); 2153 2154 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[8]); 2155 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 2156 ci->ci_feat_val[9]); 2157 2158 if (ci->ci_max_xsave != 0) { 2159 aprint_normal("%s: xsave area size: current %d, maximum %d", 2160 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 2161 aprint_normal(", xgetbv %sabled\n", 2162 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 2163 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 2164 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 2165 x86_xgetbv()); 2166 } 2167 2168 x86_print_cache_and_tlb_info(ci); 2169 2170 if (ci->ci_max_cpuid >= 3 && (ci->ci_feat_val[0] & CPUID_PSN)) { 2171 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 2172 cpuname, 2173 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 2174 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 2175 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 2176 } 2177 2178 if (ci->ci_cpu_class == CPUCLASS_386) 2179 errx(1, "NetBSD requires an 80486 or later processor"); 2180 2181 if (ci->ci_cpu_type == CPU_486DLC) { 2182 #ifndef CYRIX_CACHE_WORKS 2183 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 2184 #else 2185 #ifndef CYRIX_CACHE_REALLY_WORKS 2186 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 2187 #else 2188 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 2189 #endif 2190 #endif 2191 } 2192 2193 /* 2194 * Everything past this point requires a Pentium or later. 2195 */ 2196 if (ci->ci_max_cpuid < 0) 2197 return; 2198 2199 identifycpu_cpuids(ci); 2200 2201 if ((ci->ci_max_cpuid >= 5) 2202 && ((cpu_vendor == CPUVENDOR_INTEL) 2203 || (cpu_vendor == CPUVENDOR_AMD))) { 2204 uint16_t lmin, lmax; 2205 x86_cpuid(5, descs); 2206 2207 print_bits(cpuname, "MONITOR/MWAIT extensions", 2208 CPUID_MON_FLAGS, descs[2]); 2209 lmin = __SHIFTOUT(descs[0], CPUID_MON_MINSIZE); 2210 lmax = __SHIFTOUT(descs[1], CPUID_MON_MAXSIZE); 2211 aprint_normal("%s: monitor-line size %hu", cpuname, lmin); 2212 if (lmin != lmax) 2213 aprint_normal("-%hu", lmax); 2214 aprint_normal("\n"); 2215 2216 for (i = 0; i <= 7; i++) { 2217 unsigned int num = CPUID_MON_SUBSTATE(descs[3], i); 2218 2219 if (num != 0) 2220 aprint_normal("%s: C%u substates %u\n", 2221 cpuname, i, num); 2222 } 2223 } 2224 if ((ci->ci_max_cpuid >= 6) 2225 && ((cpu_vendor == CPUVENDOR_INTEL) 2226 || (cpu_vendor == CPUVENDOR_AMD))) { 2227 x86_cpuid(6, descs); 2228 print_bits(cpuname, "DSPM-eax", CPUID_DSPM_FLAGS, descs[0]); 2229 print_bits(cpuname, "DSPM-ecx", CPUID_DSPM_FLAGS1, descs[2]); 2230 } 2231 if ((ci->ci_max_cpuid >= 7) 2232 && ((cpu_vendor == CPUVENDOR_INTEL) 2233 || (cpu_vendor == CPUVENDOR_AMD))) { 2234 unsigned int maxsubleaf; 2235 2236 x86_cpuid(7, descs); 2237 maxsubleaf = descs[0]; 2238 aprint_verbose("%s: SEF highest subleaf %08x\n", 2239 cpuname, maxsubleaf); 2240 if (maxsubleaf >= 1) { 2241 x86_cpuid2(7, 1, descs); 2242 print_bits(cpuname, "SEF-subleaf1-eax", 2243 CPUID_SEF1_FLAGS_A, descs[0]); 2244 print_bits(cpuname, "SEF-subleaf1-ebx", 2245 CPUID_SEF1_FLAGS_B, descs[1]); 2246 print_bits(cpuname, "SEF-subleaf1-edx", 2247 CPUID_SEF1_FLAGS_D, descs[3]); 2248 } 2249 if (maxsubleaf >= 2) { 2250 x86_cpuid2(7, 2, descs); 2251 print_bits(cpuname, "SEF-subleaf2-edx", 2252 CPUID_SEF2_FLAGS_D, descs[3]); 2253 } 2254 } 2255 2256 if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD)) { 2257 if (ci->ci_max_ext_cpuid >= 0x80000007) 2258 powernow_probe(ci); 2259 2260 if (ci->ci_max_ext_cpuid >= 0x80000008) { 2261 x86_cpuid(0x80000008, descs); 2262 print_bits(cpuname, "AMD Extended features", 2263 CPUID_CAPEX_FLAGS, descs[1]); 2264 } 2265 } 2266 2267 if (cpu_vendor == CPUVENDOR_AMD) { 2268 if (ci->ci_max_ext_cpuid >= 0x80000021) { 2269 x86_cpuid(0x80000021, descs); 2270 print_bits(cpuname, "AMD Extended features2", 2271 CPUID_AMDEXT2_FLAGS, descs[0]); 2272 } 2273 2274 if (ci->ci_max_ext_cpuid >= 0x80000007) { 2275 x86_cpuid(0x80000007, descs); 2276 print_bits(cpuname, "RAS features", 2277 CPUID_RAS_FLAGS, descs[1]); 2278 } 2279 if ((ci->ci_max_ext_cpuid >= 0x8000000a) 2280 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 2281 x86_cpuid(0x8000000a, descs); 2282 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 2283 descs[0] & 0xf); 2284 aprint_verbose("%s: SVM NASID %d\n", cpuname, 2285 descs[1]); 2286 print_bits(cpuname, "SVM features", 2287 CPUID_AMD_SVM_FLAGS, descs[3]); 2288 } 2289 if (ci->ci_max_ext_cpuid >= 0x8000001b) { 2290 x86_cpuid(0x8000001b, descs); 2291 print_bits(cpuname, "IBS features", 2292 CPUID_IBS_FLAGS, descs[0]); 2293 } 2294 if (ci->ci_max_ext_cpuid >= 0x8000001f) { 2295 x86_cpuid(0x8000001f, descs); 2296 print_bits(cpuname, "Encrypted Memory features", 2297 CPUID_AMD_ENCMEM_FLAGS, descs[0]); 2298 } 2299 if (ci->ci_max_ext_cpuid >= 0x80000022) { 2300 uint8_t ncore, nnb, numc, nlbrs; 2301 2302 x86_cpuid(0x80000022, descs); 2303 print_bits(cpuname, "Perfmon:", 2304 CPUID_AXPERF_FLAGS, descs[0]); 2305 2306 ncore = __SHIFTOUT(descs[1], CPUID_AXPERF_NCPC); 2307 nnb = __SHIFTOUT(descs[1], CPUID_AXPERF_NNBPC); 2308 numc = __SHIFTOUT(descs[1], CPUID_AXPERF_NUMCPC); 2309 nlbrs = __SHIFTOUT(descs[1], CPUID_AXPERF_NLBRSTACK); 2310 aprint_verbose("%s: Perfmon: counters: " 2311 "Core %hhu, Northbridge %hhu, UMC %hhu\n", cpuname, 2312 ncore, nnb, numc); 2313 aprint_verbose("%s: Perfmon: LBR Stack %hhu entries\n", 2314 cpuname, nlbrs); 2315 } 2316 if (ci->ci_max_ext_cpuid >= 0x80000027) { 2317 uint8_t classes; 2318 2319 x86_cpuid(0x80000027, descs); 2320 classes = __SHIFTOUT(descs[0], CPUID_HWC_NWC); 2321 aprint_verbose("%s: Hetero workload class: " 2322 "%hhu classes\n", cpuname, classes); 2323 } 2324 } else if (cpu_vendor == CPUVENDOR_INTEL) { 2325 if (ci->ci_max_cpuid >= 0x0a) { 2326 unsigned int pmcver, ncounter, veclen; 2327 2328 x86_cpuid(0x0a, descs); 2329 pmcver = __SHIFTOUT(descs[0], CPUID_PERF_VERSION); 2330 ncounter = __SHIFTOUT(descs[0], CPUID_PERF_NGPPC); 2331 veclen = __SHIFTOUT(descs[0], CPUID_PERF_BVECLEN); 2332 aprint_verbose("%s: Perfmon: Ver. %u", 2333 cpuname, pmcver); 2334 if (((pmcver >= 3) && (pmcver <= 4)) || 2335 ((pmcver >= 5) && 2336 (descs[3] & CPUID_PERF_ANYTHREADDEPR) == 0)) 2337 aprint_verbose(" <ANYTHREAD>\n"); 2338 else 2339 aprint_verbose("\n"); 2340 2341 aprint_verbose("%s: Perfmon: General: " 2342 "bitwidth %u, %u counters\n", cpuname, 2343 (uint32_t)__SHIFTOUT(descs[0], CPUID_PERF_NBWGPPC), 2344 ncounter); 2345 /* Invert logic for the output */ 2346 descs[1] ^= __BITS(veclen - 1, 0); 2347 /* 2348 * Mask unrelated bits. An hypervisor reduces the 2349 * vector and set bit(s) out of the vector. 2350 */ 2351 descs[1] &= __BITS(veclen - 1, 0); 2352 print_bits(cpuname, "Perfmon: General: avail", 2353 CPUID_PERF_FLAGS1, descs[1]); 2354 2355 if (pmcver >= 2) { 2356 ncounter = __SHIFTOUT(descs[3], 2357 CPUID_PERF_NFFPC); 2358 aprint_verbose("%s: Perfmon: Fixed: " 2359 "bitwidth %u, %u counters\n", cpuname, 2360 (uint32_t)__SHIFTOUT(descs[3], 2361 CPUID_PERF_NBWFFPC), 2362 ncounter); 2363 if (pmcver <= 4) 2364 descs[2] = __BITS(ncounter - 1, 0); 2365 print_bits(cpuname, "Perfmon: Fixed: avail", 2366 CPUID_PERF_FLAGS2, descs[2]); 2367 } 2368 } 2369 if (ci->ci_max_cpuid >= 0x1a) { 2370 x86_cpuid(0x1a, descs); 2371 if (descs[0] != 0) { 2372 aprint_verbose("%s: Hybrid: Core type %02x, " 2373 "Native Model ID %07x\n", 2374 cpuname, 2375 (uint8_t)__SHIFTOUT(descs[0], 2376 CPUID_HYBRID_CORETYPE), 2377 (uint32_t)__SHIFTOUT(descs[0], 2378 CPUID_HYBRID_NATIVEID)); 2379 } 2380 } 2381 } 2382 2383 #ifdef INTEL_ONDEMAND_CLOCKMOD 2384 clockmod_init(); 2385 #endif 2386 2387 if (cpu_vendor == CPUVENDOR_AMD) 2388 ucode.loader_version = CPU_UCODE_LOADER_AMD; 2389 else if (cpu_vendor == CPUVENDOR_INTEL) 2390 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 2391 else 2392 return; 2393 2394 ucode.data = &ucvers; 2395 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 2396 #ifdef __i386__ 2397 struct cpu_ucode_version_64 ucode_64; 2398 if (errno != ENOTTY) 2399 return; 2400 /* Try the 64 bit ioctl */ 2401 memset(&ucode_64, 0, sizeof ucode_64); 2402 ucode_64.data = &ucvers; 2403 ucode_64.loader_version = ucode.loader_version; 2404 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 2405 return; 2406 #else 2407 return; 2408 #endif 2409 } 2410 2411 if (cpu_vendor == CPUVENDOR_AMD) 2412 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 2413 else if (cpu_vendor == CPUVENDOR_INTEL) 2414 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 2415 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 2416 } 2417 2418 static const char * 2419 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 2420 const char *sep) 2421 { 2422 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2423 char human_num[HUMAN_BUFSIZE]; 2424 2425 if (cai->cai_totalsize == 0) 2426 return sep; 2427 2428 if (sep == NULL) 2429 aprint_verbose_dev(ci->ci_dev, ""); 2430 else 2431 aprint_verbose("%s", sep); 2432 if (name != NULL) 2433 aprint_verbose("%s ", name); 2434 2435 if (cai->cai_string != NULL) { 2436 aprint_verbose("%s ", cai->cai_string); 2437 } else { 2438 (void)humanize_number(human_num, sizeof(human_num), 2439 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 2440 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 2441 } 2442 switch (cai->cai_associativity) { 2443 case 0: 2444 aprint_verbose("disabled"); 2445 break; 2446 case 1: 2447 aprint_verbose("direct-mapped"); 2448 break; 2449 case 0xff: 2450 aprint_verbose("fully associative"); 2451 break; 2452 default: 2453 aprint_verbose("%d-way", cai->cai_associativity); 2454 break; 2455 } 2456 return ", "; 2457 } 2458 2459 static const char * 2460 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 2461 const char *sep) 2462 { 2463 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 2464 char human_num[HUMAN_BUFSIZE]; 2465 2466 if (cai->cai_totalsize == 0) 2467 return sep; 2468 2469 if (sep == NULL) 2470 aprint_verbose_dev(ci->ci_dev, ""); 2471 else 2472 aprint_verbose("%s", sep); 2473 if ((name != NULL) && (sep == NULL)) 2474 aprint_verbose("%s ", name); 2475 2476 if (cai->cai_string != NULL) { 2477 aprint_verbose("%s", cai->cai_string); 2478 } else { 2479 (void)humanize_number(human_num, sizeof(human_num), 2480 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 2481 aprint_verbose("%d %s entries ", cai->cai_totalsize, 2482 human_num); 2483 switch (cai->cai_associativity) { 2484 case 0: 2485 aprint_verbose("disabled"); 2486 break; 2487 case 1: 2488 aprint_verbose("direct-mapped"); 2489 break; 2490 case 0xff: 2491 aprint_verbose("fully associative"); 2492 break; 2493 default: 2494 aprint_verbose("%d-way", cai->cai_associativity); 2495 break; 2496 } 2497 } 2498 return ", "; 2499 } 2500 2501 static void 2502 x86_print_cache_and_tlb_info(struct cpu_info *ci) 2503 { 2504 const char *sep = NULL; 2505 2506 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 2507 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 2508 sep = print_cache_config(ci, CAI_ICACHE, "I-cache:", NULL); 2509 sep = print_cache_config(ci, CAI_DCACHE, "D-cache:", sep); 2510 if (sep != NULL) 2511 aprint_verbose("\n"); 2512 } 2513 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 2514 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache:", NULL); 2515 if (sep != NULL) 2516 aprint_verbose("\n"); 2517 } 2518 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 2519 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache:", NULL); 2520 if (sep != NULL) 2521 aprint_verbose("\n"); 2522 } 2523 if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) { 2524 aprint_verbose_dev(ci->ci_dev, "%dB prefetching", 2525 ci->ci_cinfo[CAI_PREFETCH].cai_linesize); 2526 if (sep != NULL) 2527 aprint_verbose("\n"); 2528 } 2529 2530 sep = print_tlb_config(ci, CAI_ITLB, "ITLB:", NULL); 2531 sep = print_tlb_config(ci, CAI_ITLB2, "ITLB:", sep); 2532 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "ITLB:", sep); 2533 if (sep != NULL) 2534 aprint_verbose("\n"); 2535 2536 sep = print_tlb_config(ci, CAI_DTLB, "DTLB:", NULL); 2537 sep = print_tlb_config(ci, CAI_DTLB2, "DTLB:", sep); 2538 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "DTLB:", sep); 2539 if (sep != NULL) 2540 aprint_verbose("\n"); 2541 2542 sep = print_tlb_config(ci, CAI_L1_LD_TLB, "Load only TLB:", NULL); 2543 if (sep != NULL) 2544 aprint_verbose("\n"); 2545 2546 sep = print_tlb_config(ci, CAI_L1_ST_TLB, "Store only TLB:", NULL); 2547 if (sep != NULL) 2548 aprint_verbose("\n"); 2549 2550 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB:", NULL); 2551 sep = print_tlb_config(ci, CAI_L2_ITLB2, "L2 ITLB:", sep); 2552 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 ITLB:", sep); 2553 if (sep != NULL) 2554 aprint_verbose("\n"); 2555 2556 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB:", NULL); 2557 sep = print_tlb_config(ci, CAI_L2_DTLB2, "L2 DTLB:", sep); 2558 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 DTLB:", sep); 2559 if (sep != NULL) 2560 aprint_verbose("\n"); 2561 2562 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB:", NULL); 2563 sep = print_tlb_config(ci, CAI_L2_STLB2, "L2 STLB:", sep); 2564 sep = print_tlb_config(ci, CAI_L2_STLB3, "L2 STLB:", sep); 2565 if (sep != NULL) 2566 aprint_verbose("\n"); 2567 } 2568 2569 static void 2570 powernow_probe(struct cpu_info *ci) 2571 { 2572 uint32_t regs[4]; 2573 char buf[256]; 2574 2575 x86_cpuid(0x80000007, regs); 2576 2577 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2578 aprint_normal_dev(ci->ci_dev, "Power Management features: %s\n", buf); 2579 } 2580 2581 bool 2582 identifycpu_bind(void) 2583 { 2584 2585 return true; 2586 } 2587 2588 int 2589 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2590 { 2591 struct cpu_info ci; 2592 int loader_version, res; 2593 struct cpu_ucode_version versreq; 2594 2595 cpu_probe_base_features(&ci, "unknown"); 2596 2597 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2598 loader_version = CPU_UCODE_LOADER_AMD; 2599 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2600 loader_version = CPU_UCODE_LOADER_INTEL1; 2601 else 2602 return -1; 2603 2604 /* check whether the kernel understands this loader version */ 2605 versreq.loader_version = loader_version; 2606 versreq.data = 0; 2607 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2608 if (res) 2609 return -1; 2610 2611 switch (loader_version) { 2612 case CPU_UCODE_LOADER_AMD: 2613 if (uc->cpu_nr != -1) { 2614 warnx("ucode updates on AMD can only be done on all CPUs at once"); 2615 return -1; 2616 } 2617 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2618 break; 2619 case CPU_UCODE_LOADER_INTEL1: 2620 if (uc->cpu_nr == -1) 2621 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2622 else 2623 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2624 break; 2625 default: /* can't happen */ 2626 return -1; 2627 } 2628 uc->loader_version = loader_version; 2629 return 0; 2630 } 2631
Indexes created Fri Sep 26 20:09:58 GMT 2025