i386.c revision 1.19
1 /* $NetBSD: i386.c,v 1.19 2009/05/14 20:16:10 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.19 2009/05/14 20:16:10 pgoyette Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 68 #include <string.h> 69 #include <stdio.h> 70 #include <stdlib.h> 71 #include <err.h> 72 #include <assert.h> 73 #include <math.h> 74 #include <util.h> 75 76 #include <machine/specialreg.h> 77 #include <machine/cpu.h> 78 79 #include <x86/cpuvar.h> 80 #include <x86/cputypes.h> 81 #include <x86/cacheinfo.h> 82 83 #include "../cpuctl.h" 84 85 /* Size of buffer for printing humanized numbers */ 86 #define HUMAN_BUFSIZE sizeof("999KB") 87 88 #define x86_cpuid(a,b) x86_cpuid2((a),0,(b)) 89 90 void x86_cpuid2(uint32_t, uint32_t, uint32_t *); 91 void x86_identify(void); 92 93 struct cpu_info { 94 const char *ci_dev; 95 int32_t ci_cpuid_level; 96 uint32_t ci_signature; /* X86 cpuid type */ 97 uint32_t ci_feat_val[5]; /* X86 CPUID feature bits 98 * [0] basic features %edx 99 * [1] basic features %ecx 100 * [2] extended features %edx 101 * [3] extended features %ecx 102 * [4] VIA padlock features 103 */ 104 uint32_t ci_cpu_class; /* CPU class */ 105 uint32_t ci_brand_id; /* Intel brand id */ 106 uint32_t ci_vendor[4]; /* vendor string */ 107 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 108 uint64_t ci_tsc_freq; /* cpu cycles/second */ 109 uint8_t ci_packageid; 110 uint8_t ci_coreid; 111 uint8_t ci_smtid; 112 uint32_t ci_initapicid; 113 struct x86_cache_info ci_cinfo[CAI_COUNT]; 114 void (*ci_info)(struct cpu_info *); 115 }; 116 117 struct cpu_nocpuid_nameclass { 118 int cpu_vendor; 119 const char *cpu_vendorname; 120 const char *cpu_name; 121 int cpu_class; 122 void (*cpu_setup)(struct cpu_info *); 123 void (*cpu_cacheinfo)(struct cpu_info *); 124 void (*cpu_info)(struct cpu_info *); 125 }; 126 127 struct cpu_extend_nameclass { 128 int ext_model; 129 const char *cpu_models[CPU_MAXMODEL+1]; 130 }; 131 132 struct cpu_cpuid_nameclass { 133 const char *cpu_id; 134 int cpu_vendor; 135 const char *cpu_vendorname; 136 struct cpu_cpuid_family { 137 int cpu_class; 138 const char *cpu_models[CPU_MAXMODEL+2]; 139 void (*cpu_setup)(struct cpu_info *); 140 void (*cpu_probe)(struct cpu_info *); 141 void (*cpu_info)(struct cpu_info *); 142 struct cpu_extend_nameclass *cpu_extended_names; 143 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 144 }; 145 146 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 147 148 /* 149 * Map Brand ID from cpuid instruction to brand name. 150 * Source: Intel Processor Identification and the CPUID Instruction, AP-485 151 */ 152 static const char * const i386_intel_brand[] = { 153 "", /* Unsupported */ 154 "Celeron", /* Intel (R) Celeron (TM) processor */ 155 "Pentium III", /* Intel (R) Pentium (R) III processor */ 156 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 157 "Pentium III", /* Intel (R) Pentium (R) III processor */ 158 "", /* Reserved */ 159 "Mobile Pentium III", /* Mobile Intel (R) Pentium (R) III processor-M */ 160 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 161 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 162 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 163 "Celeron", /* Intel (R) Celeron (TM) processor */ 164 "Xeon", /* Intel (R) Xeon (TM) processor */ 165 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 166 "", /* Reserved */ 167 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 168 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 169 }; 170 171 /* 172 * AMD processors don't have Brand IDs, so we need these names for probe. 173 */ 174 static const char * const amd_brand[] = { 175 "", 176 "Duron", /* AMD Duron(tm) */ 177 "MP", /* AMD Athlon(tm) MP */ 178 "XP", /* AMD Athlon(tm) XP */ 179 "4" /* AMD Athlon(tm) 4 */ 180 }; 181 182 static int cpu_vendor; 183 static char cpu_brand_string[49]; 184 static char amd_brand_name[48]; 185 186 static void via_cpu_probe(struct cpu_info *); 187 static void amd_family6_probe(struct cpu_info *); 188 static void intel_family_new_probe(struct cpu_info *); 189 static const char *intel_family6_name(struct cpu_info *); 190 static const char *amd_amd64_name(struct cpu_info *); 191 static void amd_family5_setup(struct cpu_info *); 192 static void transmeta_cpu_info(struct cpu_info *); 193 static const char *print_cache_config(struct cpu_info *, int, const char *, 194 const char *); 195 static const char *print_tlb_config(struct cpu_info *, int, const char *, 196 const char *); 197 static void amd_cpu_cacheinfo(struct cpu_info *); 198 static void via_cpu_cacheinfo(struct cpu_info *); 199 static void x86_print_cacheinfo(struct cpu_info *); 200 static const struct x86_cache_info *cache_info_lookup( 201 const struct x86_cache_info *, uint8_t); 202 static void cyrix6x86_cpu_setup(struct cpu_info *); 203 static void winchip_cpu_setup(struct cpu_info *); 204 static void amd_family5_setup(struct cpu_info *); 205 static void powernow_probe(struct cpu_info *); 206 207 /* 208 * Info for CTL_HW 209 */ 210 static char cpu_model[120]; 211 212 /* 213 * Note: these are just the ones that may not have a cpuid instruction. 214 * We deal with the rest in a different way. 215 */ 216 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 217 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 218 NULL, NULL, NULL }, /* CPU_386SX */ 219 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 220 NULL, NULL, NULL }, /* CPU_386 */ 221 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 222 NULL, NULL, NULL }, /* CPU_486SX */ 223 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 224 NULL, NULL, NULL }, /* CPU_486 */ 225 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 226 NULL, NULL, NULL }, /* CPU_486DLC */ 227 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 228 NULL, NULL, NULL }, /* CPU_6x86 */ 229 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 230 NULL, NULL, NULL }, /* CPU_NX586 */ 231 }; 232 233 const char *classnames[] = { 234 "386", 235 "486", 236 "586", 237 "686" 238 }; 239 240 const char *modifiers[] = { 241 "", 242 "OverDrive", 243 "Dual", 244 "" 245 }; 246 247 struct cpu_extend_nameclass intel_family6_ext_models[] = { 248 { /* Extended models 1x */ 249 0x01, { NULL, NULL, 250 NULL, NULL, 251 NULL, "EP80579 Integrated Processor", 252 "Celeron (45nm)", "Core 2 Extreme", 253 NULL, NULL, 254 "Core i7 (Nehalem)", NULL, 255 "Atom", "XeonMP (Nehalem)", 256 NULL, NULL} }, 257 { /* End of list */ 258 0x00, { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 259 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL} } 260 }; 261 262 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 263 { 264 "GenuineIntel", 265 CPUVENDOR_INTEL, 266 "Intel", 267 /* Family 4 */ 268 { { 269 CPUCLASS_486, 270 { 271 "486DX", "486DX", "486SX", "486DX2", "486SL", 272 "486SX2", 0, "486DX2 W/B Enhanced", 273 "486DX4", 0, 0, 0, 0, 0, 0, 0, 274 "486" /* Default */ 275 }, 276 NULL, 277 NULL, 278 NULL, 279 NULL, 280 }, 281 /* Family 5 */ 282 { 283 CPUCLASS_586, 284 { 285 "Pentium (P5 A-step)", "Pentium (P5)", 286 "Pentium (P54C)", "Pentium (P24T)", 287 "Pentium/MMX", "Pentium", 0, 288 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 289 0, 0, 0, 0, 0, 0, 0, 290 "Pentium" /* Default */ 291 }, 292 NULL, 293 NULL, 294 NULL, 295 NULL, 296 }, 297 /* Family 6 */ 298 { 299 CPUCLASS_686, 300 { 301 "Pentium Pro (A-step)", "Pentium Pro", 0, 302 "Pentium II (Klamath)", "Pentium Pro", 303 "Pentium II/Celeron (Deschutes)", 304 "Celeron (Mendocino)", 305 "Pentium III (Katmai)", 306 "Pentium III (Coppermine)", 307 "Pentium M (Banias)", 308 "Pentium III Xeon (Cascades)", 309 "Pentium III (Tualatin)", 0, 310 "Pentium M (Dothan)", 311 "Pentium M (Yonah)", 312 "Core 2 (Merom)", 313 "Pentium Pro, II or III" /* Default */ 314 }, 315 NULL, 316 intel_family_new_probe, 317 NULL, 318 &intel_family6_ext_models[0], 319 }, 320 /* Family > 6 */ 321 { 322 CPUCLASS_686, 323 { 324 0, 0, 0, 0, 0, 0, 0, 0, 325 0, 0, 0, 0, 0, 0, 0, 0, 326 "Pentium 4" /* Default */ 327 }, 328 NULL, 329 intel_family_new_probe, 330 NULL, 331 NULL, 332 } } 333 }, 334 { 335 "AuthenticAMD", 336 CPUVENDOR_AMD, 337 "AMD", 338 /* Family 4 */ 339 { { 340 CPUCLASS_486, 341 { 342 0, 0, 0, "Am486DX2 W/T", 343 0, 0, 0, "Am486DX2 W/B", 344 "Am486DX4 W/T or Am5x86 W/T 150", 345 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 346 0, 0, "Am5x86 W/T 133/160", 347 "Am5x86 W/B 133/160", 348 "Am486 or Am5x86" /* Default */ 349 }, 350 NULL, 351 NULL, 352 NULL, 353 NULL, 354 }, 355 /* Family 5 */ 356 { 357 CPUCLASS_586, 358 { 359 "K5", "K5", "K5", "K5", 0, 0, "K6", 360 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 361 "K6-2+/III+", 0, 0, 362 "K5 or K6" /* Default */ 363 }, 364 amd_family5_setup, 365 NULL, 366 amd_cpu_cacheinfo, 367 NULL, 368 }, 369 /* Family 6 */ 370 { 371 CPUCLASS_686, 372 { 373 0, "Athlon Model 1", "Athlon Model 2", 374 "Duron", "Athlon Model 4 (Thunderbird)", 375 0, "Athlon", "Duron", "Athlon", 0, 376 "Athlon", 0, 0, 0, 0, 0, 377 "K7 (Athlon)" /* Default */ 378 }, 379 NULL, 380 amd_family6_probe, 381 amd_cpu_cacheinfo, 382 NULL, 383 }, 384 /* Family > 6 */ 385 { 386 CPUCLASS_686, 387 { 388 0, 0, 0, 0, 0, 0, 0, 0, 389 0, 0, 0, 0, 0, 0, 0, 0, 390 "Unknown K8 (Athlon)" /* Default */ 391 }, 392 NULL, 393 amd_family6_probe, 394 amd_cpu_cacheinfo, 395 NULL, 396 } } 397 }, 398 { 399 "CyrixInstead", 400 CPUVENDOR_CYRIX, 401 "Cyrix", 402 /* Family 4 */ 403 { { 404 CPUCLASS_486, 405 { 406 0, 0, 0, 407 "MediaGX", 408 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 409 "486" /* Default */ 410 }, 411 cyrix6x86_cpu_setup, /* XXX ?? */ 412 NULL, 413 NULL, 414 NULL, 415 }, 416 /* Family 5 */ 417 { 418 CPUCLASS_586, 419 { 420 0, 0, "6x86", 0, 421 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 422 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 423 "6x86" /* Default */ 424 }, 425 cyrix6x86_cpu_setup, 426 NULL, 427 NULL, 428 NULL, 429 }, 430 /* Family 6 */ 431 { 432 CPUCLASS_686, 433 { 434 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 435 0, 0, 0, 0, 0, 0, 0, 0, 436 "6x86MX" /* Default */ 437 }, 438 cyrix6x86_cpu_setup, 439 NULL, 440 NULL, 441 NULL, 442 }, 443 /* Family > 6 */ 444 { 445 CPUCLASS_686, 446 { 447 0, 0, 0, 0, 0, 0, 0, 0, 448 0, 0, 0, 0, 0, 0, 0, 0, 449 "Unknown 6x86MX" /* Default */ 450 }, 451 NULL, 452 NULL, 453 NULL, 454 NULL, 455 } } 456 }, 457 { /* MediaGX is now owned by National Semiconductor */ 458 "Geode by NSC", 459 CPUVENDOR_CYRIX, /* XXX */ 460 "National Semiconductor", 461 /* Family 4, NSC never had any of these */ 462 { { 463 CPUCLASS_486, 464 { 465 0, 0, 0, 0, 0, 0, 0, 0, 466 0, 0, 0, 0, 0, 0, 0, 0, 467 "486 compatible" /* Default */ 468 }, 469 NULL, 470 NULL, 471 NULL, 472 NULL, 473 }, 474 /* Family 5: Geode family, formerly MediaGX */ 475 { 476 CPUCLASS_586, 477 { 478 0, 0, 0, 0, 479 "Geode GX1", 480 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 481 "Geode" /* Default */ 482 }, 483 cyrix6x86_cpu_setup, 484 NULL, 485 amd_cpu_cacheinfo, 486 NULL, 487 }, 488 /* Family 6, not yet available from NSC */ 489 { 490 CPUCLASS_686, 491 { 492 0, 0, 0, 0, 0, 0, 0, 0, 493 0, 0, 0, 0, 0, 0, 0, 0, 494 "Pentium Pro compatible" /* Default */ 495 }, 496 NULL, 497 NULL, 498 NULL, 499 NULL, 500 }, 501 /* Family > 6, not yet available from NSC */ 502 { 503 CPUCLASS_686, 504 { 505 0, 0, 0, 0, 0, 0, 0, 0, 506 0, 0, 0, 0, 0, 0, 0, 0, 507 "Pentium Pro compatible" /* Default */ 508 }, 509 NULL, 510 NULL, 511 NULL, 512 NULL, 513 } } 514 }, 515 { 516 "CentaurHauls", 517 CPUVENDOR_IDT, 518 "IDT", 519 /* Family 4, IDT never had any of these */ 520 { { 521 CPUCLASS_486, 522 { 523 0, 0, 0, 0, 0, 0, 0, 0, 524 0, 0, 0, 0, 0, 0, 0, 0, 525 "486 compatible" /* Default */ 526 }, 527 NULL, 528 NULL, 529 NULL, 530 NULL, 531 }, 532 /* Family 5 */ 533 { 534 CPUCLASS_586, 535 { 536 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 537 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 538 "WinChip" /* Default */ 539 }, 540 winchip_cpu_setup, 541 NULL, 542 NULL, 543 NULL, 544 }, 545 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 546 { 547 CPUCLASS_686, 548 { 549 0, 0, 0, 0, 0, 0, "C3 Samuel", 550 "C3 Samuel 2/Ezra", "C3 Ezra-T", 551 "C3 Nehemiah", "C7 Esther", 0, 0, 0, 0, 0, 552 "C3" /* Default */ 553 }, 554 NULL, 555 via_cpu_probe, 556 via_cpu_cacheinfo, 557 NULL, 558 }, 559 /* Family > 6, not yet available from VIA */ 560 { 561 CPUCLASS_686, 562 { 563 0, 0, 0, 0, 0, 0, 0, 0, 564 0, 0, 0, 0, 0, 0, 0, 0, 565 "Pentium Pro compatible" /* Default */ 566 }, 567 NULL, 568 NULL, 569 NULL, 570 NULL, 571 } } 572 }, 573 { 574 "GenuineTMx86", 575 CPUVENDOR_TRANSMETA, 576 "Transmeta", 577 /* Family 4, Transmeta never had any of these */ 578 { { 579 CPUCLASS_486, 580 { 581 0, 0, 0, 0, 0, 0, 0, 0, 582 0, 0, 0, 0, 0, 0, 0, 0, 583 "486 compatible" /* Default */ 584 }, 585 NULL, 586 NULL, 587 NULL, 588 NULL, 589 }, 590 /* Family 5 */ 591 { 592 CPUCLASS_586, 593 { 594 0, 0, 0, 0, 0, 0, 0, 0, 595 0, 0, 0, 0, 0, 0, 0, 0, 596 "Crusoe" /* Default */ 597 }, 598 NULL, 599 NULL, 600 transmeta_cpu_info, 601 NULL, 602 }, 603 /* Family 6, not yet available from Transmeta */ 604 { 605 CPUCLASS_686, 606 { 607 0, 0, 0, 0, 0, 0, 0, 0, 608 0, 0, 0, 0, 0, 0, 0, 0, 609 "Pentium Pro compatible" /* Default */ 610 }, 611 NULL, 612 NULL, 613 NULL, 614 NULL, 615 }, 616 /* Family > 6, not yet available from Transmeta */ 617 { 618 CPUCLASS_686, 619 { 620 0, 0, 0, 0, 0, 0, 0, 0, 621 0, 0, 0, 0, 0, 0, 0, 0, 622 "Pentium Pro compatible" /* Default */ 623 }, 624 NULL, 625 NULL, 626 NULL, 627 NULL, 628 } } 629 } 630 }; 631 632 /* 633 * disable the TSC such that we don't use the TSC in microtime(9) 634 * because some CPUs got the implementation wrong. 635 */ 636 static void 637 disable_tsc(struct cpu_info *ci) 638 { 639 if (ci->ci_feat_val[0] & CPUID_TSC) { 640 ci->ci_feat_val[0] &= ~CPUID_TSC; 641 aprint_error("WARNING: broken TSC disabled\n"); 642 } 643 } 644 645 static void 646 cyrix6x86_cpu_setup(struct cpu_info *ci) 647 { 648 649 /* 650 * Do not disable the TSC on the Geode GX, it's reported to 651 * work fine. 652 */ 653 if (ci->ci_signature != 0x552) 654 disable_tsc(ci); 655 } 656 657 void 658 winchip_cpu_setup(struct cpu_info *ci) 659 { 660 switch (CPUID2MODEL(ci->ci_signature)) { /* model */ 661 case 4: /* WinChip C6 */ 662 disable_tsc(ci); 663 } 664 } 665 666 667 static void 668 identifycpu_cpuids(struct cpu_info *ci) 669 { 670 const char *cpuname = ci->ci_dev; 671 u_int lp_max = 1; /* logical processors per package */ 672 u_int smt_max; /* smt per core */ 673 u_int core_max = 1; /* core per package */ 674 u_int smt_bits, core_bits; 675 uint32_t descs[4]; 676 677 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 678 ci->ci_packageid = ci->ci_initapicid; 679 ci->ci_coreid = 0; 680 ci->ci_smtid = 0; 681 if (cpu_vendor != CPUVENDOR_INTEL) { 682 return; 683 } 684 685 /* 686 * 253668.pdf 7.10.2 687 */ 688 689 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 690 x86_cpuid(1, descs); 691 lp_max = (descs[1] >> 16) & 0xff; 692 } 693 x86_cpuid(0, descs); 694 if (descs[0] >= 4) { 695 x86_cpuid2(4, 0, descs); 696 core_max = (descs[0] >> 26) + 1; 697 } 698 assert(lp_max >= core_max); 699 smt_max = lp_max / core_max; 700 smt_bits = ilog2(smt_max - 1) + 1; 701 core_bits = ilog2(core_max - 1) + 1; 702 if (smt_bits + core_bits) { 703 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 704 } 705 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 706 ci->ci_packageid); 707 if (core_bits) { 708 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 709 710 ci->ci_coreid = 711 __SHIFTOUT(ci->ci_initapicid, core_mask); 712 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 713 } 714 if (smt_bits) { 715 u_int smt_mask = __BITS((int)0, (int)(smt_bits - 1)); 716 717 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, smt_mask); 718 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 719 } 720 } 721 722 static void 723 via_cpu_probe(struct cpu_info *ci) 724 { 725 u_int model = CPUID2MODEL(ci->ci_signature); 726 u_int stepping = CPUID2STEPPING(ci->ci_signature); 727 u_int descs[4]; 728 u_int lfunc; 729 730 /* 731 * Determine the largest extended function value. 732 */ 733 x86_cpuid(0x80000000, descs); 734 lfunc = descs[0]; 735 736 /* 737 * Determine the extended feature flags. 738 */ 739 if (lfunc >= 0x80000001) { 740 x86_cpuid(0x80000001, descs); 741 ci->ci_feat_val[2] |= descs[3]; 742 } 743 744 if (model < 0x9) 745 return; 746 747 /* Nehemiah or Esther */ 748 x86_cpuid(0xc0000000, descs); 749 lfunc = descs[0]; 750 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 751 return; 752 753 x86_cpuid(0xc0000001, descs); 754 lfunc = descs[3]; 755 if (model > 0x9 || stepping >= 8) { /* ACE */ 756 if (lfunc & CPUID_VIA_HAS_ACE) { 757 ci->ci_feat_val[4] = lfunc; 758 } 759 } 760 } 761 762 static const char * 763 intel_family6_name(struct cpu_info *ci) 764 { 765 int model = CPUID2MODEL(ci->ci_signature); 766 const char *ret = NULL; 767 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 768 769 if (model == 5) { 770 switch (l2cache) { 771 case 0: 772 case 128 * 1024: 773 ret = "Celeron (Covington)"; 774 break; 775 case 256 * 1024: 776 ret = "Mobile Pentium II (Dixon)"; 777 break; 778 case 512 * 1024: 779 ret = "Pentium II"; 780 break; 781 case 1 * 1024 * 1024: 782 case 2 * 1024 * 1024: 783 ret = "Pentium II Xeon"; 784 break; 785 } 786 } else if (model == 6) { 787 switch (l2cache) { 788 case 256 * 1024: 789 case 512 * 1024: 790 ret = "Mobile Pentium II"; 791 break; 792 } 793 } else if (model == 7) { 794 switch (l2cache) { 795 case 512 * 1024: 796 ret = "Pentium III"; 797 break; 798 case 1 * 1024 * 1024: 799 case 2 * 1024 * 1024: 800 ret = "Pentium III Xeon"; 801 break; 802 } 803 } else if (model >= 8) { 804 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 805 switch (ci->ci_brand_id) { 806 case 0x3: 807 if (ci->ci_signature == 0x6B1) 808 ret = "Celeron"; 809 break; 810 case 0x8: 811 if (ci->ci_signature >= 0xF13) 812 ret = "genuine processor"; 813 break; 814 case 0xB: 815 if (ci->ci_signature >= 0xF13) 816 ret = "Xeon MP"; 817 break; 818 case 0xE: 819 if (ci->ci_signature < 0xF13) 820 ret = "Xeon"; 821 break; 822 } 823 if (ret == NULL) 824 ret = i386_intel_brand[ci->ci_brand_id]; 825 } 826 } 827 828 return ret; 829 } 830 831 /* 832 * Identify AMD64 CPU names from cpuid. 833 * 834 * Based on: 835 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 836 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 837 * "Revision Guide for AMD NPT Family 0Fh Processors" 838 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 839 * and other miscellaneous reports. 840 */ 841 static const char * 842 amd_amd64_name(struct cpu_info *ci) 843 { 844 int extfamily, extmodel, model; 845 const char *ret = NULL; 846 847 model = CPUID2MODEL(ci->ci_signature); 848 extfamily = CPUID2EXTFAMILY(ci->ci_signature); 849 extmodel = CPUID2EXTMODEL(ci->ci_signature); 850 851 switch (extfamily) { 852 case 0x00: 853 switch (model) { 854 case 0x1: 855 switch (extmodel) { 856 case 0x2: /* rev JH-E1/E6 */ 857 case 0x4: /* rev JH-F2 */ 858 ret = "Dual-Core Opteron"; 859 break; 860 } 861 break; 862 case 0x3: 863 switch (extmodel) { 864 case 0x2: /* rev JH-E6 (Toledo) */ 865 ret = "Dual-Core Opteron or Athlon 64 X2"; 866 break; 867 case 0x4: /* rev JH-F2 (Windsor) */ 868 ret = "Athlon 64 FX or Athlon 64 X2"; 869 break; 870 } 871 break; 872 case 0x4: 873 switch (extmodel) { 874 case 0x0: /* rev SH-B0/C0/CG (ClawHammer) */ 875 case 0x1: /* rev SH-D0 */ 876 ret = "Athlon 64"; 877 break; 878 case 0x2: /* rev SH-E5 (Lancaster?) */ 879 ret = "Mobile Athlon 64 or Turion 64"; 880 break; 881 } 882 break; 883 case 0x5: 884 switch (extmodel) { 885 case 0x0: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 886 ret = "Opteron or Athlon 64 FX"; 887 break; 888 case 0x1: /* rev SH-D0 */ 889 case 0x2: /* rev SH-E4 */ 890 ret = "Opteron"; 891 break; 892 } 893 break; 894 case 0x7: 895 switch (extmodel) { 896 case 0x0: /* rev SH-CG (ClawHammer) */ 897 case 0x1: /* rev SH-D0 */ 898 ret = "Athlon 64"; 899 break; 900 case 0x2: /* rev DH-E4, SH-E4 */ 901 ret = "Athlon 64 or Athlon 64 FX or Opteron"; 902 break; 903 } 904 break; 905 case 0x8: 906 switch (extmodel) { 907 case 0x0: /* rev CH-CG */ 908 case 0x1: /* rev CH-D0 */ 909 ret = "Athlon 64 or Sempron"; 910 break; 911 case 0x4: /* rev BH-F2 */ 912 ret = "Turion 64 X2"; 913 break; 914 } 915 break; 916 case 0xb: 917 switch (extmodel) { 918 case 0x0: /* rev CH-CG */ 919 case 0x1: /* rev CH-D0 */ 920 ret = "Athlon 64"; 921 break; 922 case 0x2: /* rev BH-E4 (Manchester) */ 923 case 0x4: /* rev BH-F2 (Windsor) */ 924 ret = "Athlon 64 X2"; 925 break; 926 case 0x6: /* rev BH-G1 (Brisbane) */ 927 ret = "Athlon X2 or Athlon 64 X2"; 928 break; 929 } 930 break; 931 case 0xc: 932 switch (extmodel) { 933 case 0x0: /* rev DH-CG (Newcastle) */ 934 case 0x1: /* rev DH-D0 (Winchester) */ 935 case 0x2: /* rev DH-E3/E6 */ 936 ret = "Athlon 64 or Sempron"; 937 break; 938 } 939 break; 940 case 0xe: 941 switch (extmodel) { 942 case 0x0: /* rev DH-CG (Newcastle?) */ 943 ret = "Athlon 64 or Sempron"; 944 break; 945 } 946 break; 947 case 0xf: 948 switch (extmodel) { 949 case 0x0: /* rev DH-CG (Newcastle/Paris) */ 950 case 0x1: /* rev DH-D0 (Winchester/Victoria) */ 951 case 0x2: /* rev DH-E3/E6 (Venice/Palermo) */ 952 case 0x4: /* rev DH-F2 (Orleans/Manila) */ 953 case 0x5: /* rev DH-F2 (Orleans/Manila) */ 954 case 0x6: /* rev DH-G1 */ 955 ret = "Athlon 64 or Sempron"; 956 break; 957 } 958 break; 959 default: 960 ret = "Unknown AMD64 CPU"; 961 } 962 break; 963 case 0x01: 964 switch (model) { 965 case 0x02: 966 ret = "Family 10h"; 967 break; 968 default: 969 ret = "Unknown AMD64 CPU"; 970 break; 971 } 972 break; 973 } 974 975 return ret; 976 } 977 978 static void 979 cpu_probe_base_features(struct cpu_info *ci) 980 { 981 const struct x86_cache_info *cai; 982 u_int descs[4]; 983 int iterations, i, j; 984 uint8_t desc; 985 uint32_t miscbytes; 986 uint32_t brand[12]; 987 988 if (ci->ci_cpuid_level < 0) 989 return; 990 991 x86_cpuid(0, descs); 992 ci->ci_cpuid_level = descs[0]; 993 ci->ci_vendor[0] = descs[1]; 994 ci->ci_vendor[2] = descs[2]; 995 ci->ci_vendor[1] = descs[3]; 996 ci->ci_vendor[3] = 0; 997 998 x86_cpuid(0x80000000, brand); 999 if (brand[0] >= 0x80000004) { 1000 x86_cpuid(0x80000002, brand); 1001 x86_cpuid(0x80000003, brand + 4); 1002 x86_cpuid(0x80000004, brand + 8); 1003 for (i = 0; i < 48; i++) 1004 if (((char *) brand)[i] != ' ') 1005 break; 1006 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1007 } 1008 1009 if (ci->ci_cpuid_level < 1) 1010 return; 1011 1012 x86_cpuid(1, descs); 1013 ci->ci_signature = descs[0]; 1014 miscbytes = descs[1]; 1015 ci->ci_feat_val[1] = descs[2]; 1016 ci->ci_feat_val[0] = descs[3]; 1017 1018 /* Brand is low order 8 bits of ebx */ 1019 ci->ci_brand_id = miscbytes & 0xff; 1020 ci->ci_initapicid = (miscbytes >> 24) & 0xff; 1021 if (ci->ci_cpuid_level < 2) 1022 return; 1023 1024 /* 1025 * Parse the cache info from `cpuid', if we have it. 1026 * XXX This is kinda ugly, but hey, so is the architecture... 1027 */ 1028 1029 x86_cpuid(2, descs); 1030 1031 iterations = descs[0] & 0xff; 1032 while (iterations-- > 0) { 1033 for (i = 0; i < 4; i++) { 1034 if (descs[i] & 0x80000000) 1035 continue; 1036 for (j = 0; j < 4; j++) { 1037 if (i == 0 && j == 0) 1038 continue; 1039 desc = (descs[i] >> (j * 8)) & 0xff; 1040 if (desc == 0) 1041 continue; 1042 cai = cache_info_lookup(intel_cpuid_cache_info, 1043 desc); 1044 if (cai != NULL) 1045 ci->ci_cinfo[cai->cai_index] = *cai; 1046 } 1047 } 1048 x86_cpuid(2, descs); 1049 } 1050 1051 if (ci->ci_cpuid_level < 3) 1052 return; 1053 1054 /* 1055 * If the processor serial number misfeature is present and supported, 1056 * extract it here. 1057 */ 1058 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1059 ci->ci_cpu_serial[0] = ci->ci_signature; 1060 x86_cpuid(3, descs); 1061 ci->ci_cpu_serial[2] = descs[2]; 1062 ci->ci_cpu_serial[1] = descs[3]; 1063 } 1064 } 1065 1066 static void 1067 cpu_probe_features(struct cpu_info *ci) 1068 { 1069 const struct cpu_cpuid_nameclass *cpup = NULL; 1070 int i, xmax, family; 1071 1072 cpu_probe_base_features(ci); 1073 1074 if (ci->ci_cpuid_level < 1) 1075 return; 1076 1077 xmax = __arraycount(i386_cpuid_cpus); 1078 for (i = 0; i < xmax; i++) { 1079 if (!strncmp((char *)ci->ci_vendor, 1080 i386_cpuid_cpus[i].cpu_id, 12)) { 1081 cpup = &i386_cpuid_cpus[i]; 1082 break; 1083 } 1084 } 1085 1086 if (cpup == NULL) 1087 return; 1088 1089 family = (ci->ci_signature >> 8) & 0xf; 1090 1091 if (family > CPU_MAXFAMILY) { 1092 family = CPU_MAXFAMILY; 1093 } 1094 i = family - CPU_MINFAMILY; 1095 1096 if (cpup->cpu_family[i].cpu_probe == NULL) 1097 return; 1098 1099 (*cpup->cpu_family[i].cpu_probe)(ci); 1100 } 1101 1102 static void 1103 intel_family_new_probe(struct cpu_info *ci) 1104 { 1105 uint32_t descs[4]; 1106 1107 x86_cpuid(0x80000000, descs); 1108 1109 /* 1110 * Determine extended feature flags. 1111 */ 1112 if (descs[0] >= 0x80000001) { 1113 x86_cpuid(0x80000001, descs); 1114 ci->ci_feat_val[2] |= descs[3]; 1115 ci->ci_feat_val[3] |= descs[2]; 1116 } 1117 } 1118 1119 static void 1120 amd_family6_probe(struct cpu_info *ci) 1121 { 1122 uint32_t descs[4]; 1123 char *p; 1124 size_t i; 1125 1126 x86_cpuid(0x80000000, descs); 1127 1128 /* 1129 * Determine the extended feature flags. 1130 */ 1131 if (descs[0] >= 0x80000001) { 1132 x86_cpuid(0x80000001, descs); 1133 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 1134 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 1135 } 1136 1137 if (*cpu_brand_string == '\0') 1138 return; 1139 1140 for (i = 1; i < __arraycount(amd_brand); i++) 1141 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 1142 ci->ci_brand_id = i; 1143 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 1144 break; 1145 } 1146 } 1147 1148 static void 1149 amd_family5_setup(struct cpu_info *ci) 1150 { 1151 1152 switch (CPUID2MODEL(ci->ci_signature)) { 1153 case 0: /* AMD-K5 Model 0 */ 1154 /* 1155 * According to the AMD Processor Recognition App Note, 1156 * the AMD-K5 Model 0 uses the wrong bit to indicate 1157 * support for global PTEs, instead using bit 9 (APIC) 1158 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 1159 */ 1160 if (ci->ci_feat_val[0] & CPUID_APIC) 1161 ci->ci_feat_val[0] = 1162 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 1163 /* 1164 * XXX But pmap_pg_g is already initialized -- need to kick 1165 * XXX the pmap somehow. How does the MP branch do this? 1166 */ 1167 break; 1168 } 1169 } 1170 1171 static void 1172 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1173 { 1174 u_int descs[4]; 1175 1176 x86_cpuid(0x80860007, descs); 1177 *frequency = descs[0]; 1178 *voltage = descs[1]; 1179 *percentage = descs[2]; 1180 } 1181 1182 static void 1183 transmeta_cpu_info(struct cpu_info *ci) 1184 { 1185 u_int descs[4], nreg; 1186 u_int frequency, voltage, percentage; 1187 1188 x86_cpuid(0x80860000, descs); 1189 nreg = descs[0]; 1190 if (nreg >= 0x80860001) { 1191 x86_cpuid(0x80860001, descs); 1192 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1193 (descs[1] >> 24) & 0xff, 1194 (descs[1] >> 16) & 0xff, 1195 (descs[1] >> 8) & 0xff, 1196 descs[1] & 0xff); 1197 } 1198 if (nreg >= 0x80860002) { 1199 x86_cpuid(0x80860002, descs); 1200 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1201 (descs[1] >> 24) & 0xff, 1202 (descs[1] >> 16) & 0xff, 1203 (descs[1] >> 8) & 0xff, 1204 descs[1] & 0xff, 1205 descs[2]); 1206 } 1207 if (nreg >= 0x80860006) { 1208 union { 1209 char text[65]; 1210 u_int descs[4][4]; 1211 } info; 1212 int i; 1213 1214 for (i=0; i<4; i++) { 1215 x86_cpuid(0x80860003 + i, info.descs[i]); 1216 } 1217 info.text[64] = '\0'; 1218 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1219 } 1220 1221 if (nreg >= 0x80860007) { 1222 tmx86_get_longrun_status(&frequency, 1223 &voltage, &percentage); 1224 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1225 frequency, voltage, percentage); 1226 } 1227 } 1228 1229 void 1230 identifycpu(const char *cpuname) 1231 { 1232 const char *name = "", *modifier, *vendorname, *brand = ""; 1233 int class = CPUCLASS_386, i, xmax; 1234 int modif, family, model, ext_model; 1235 const struct cpu_extend_nameclass *modlist; 1236 const struct cpu_cpuid_nameclass *cpup = NULL; 1237 const struct cpu_cpuid_family *cpufam; 1238 const char *feature_str[5]; 1239 struct cpu_info *ci, cistore; 1240 extern int cpu; 1241 extern int cpu_info_level; 1242 size_t sz; 1243 char buf[512]; 1244 char *bp; 1245 1246 ci = &cistore; 1247 memset(ci, 0, sizeof(*ci)); 1248 ci->ci_dev = cpuname; 1249 1250 x86_identify(); 1251 ci->ci_cpuid_level = cpu_info_level; 1252 cpu_probe_features(ci); 1253 1254 if (ci->ci_cpuid_level == -1) { 1255 if ((size_t)cpu >= __arraycount(i386_nocpuid_cpus)) 1256 errx(1, "unknown cpu type %d", cpu); 1257 name = i386_nocpuid_cpus[cpu].cpu_name; 1258 cpu_vendor = i386_nocpuid_cpus[cpu].cpu_vendor; 1259 vendorname = i386_nocpuid_cpus[cpu].cpu_vendorname; 1260 class = i386_nocpuid_cpus[cpu].cpu_class; 1261 ci->ci_info = i386_nocpuid_cpus[cpu].cpu_info; 1262 modifier = ""; 1263 } else { 1264 xmax = __arraycount(i386_cpuid_cpus); 1265 modif = (ci->ci_signature >> 12) & 0x3; 1266 family = CPUID2FAMILY(ci->ci_signature); 1267 if (family < CPU_MINFAMILY) 1268 errx(1, "identifycpu: strange family value"); 1269 model = CPUID2MODEL(ci->ci_signature); 1270 ext_model = CPUID2EXTMODEL(ci->ci_signature); 1271 1272 for (i = 0; i < xmax; i++) { 1273 if (!strncmp((char *)ci->ci_vendor, 1274 i386_cpuid_cpus[i].cpu_id, 12)) { 1275 cpup = &i386_cpuid_cpus[i]; 1276 break; 1277 } 1278 } 1279 1280 if (cpup == NULL) { 1281 cpu_vendor = CPUVENDOR_UNKNOWN; 1282 if (ci->ci_vendor[0] != '\0') 1283 vendorname = (char *)&ci->ci_vendor[0]; 1284 else 1285 vendorname = "Unknown"; 1286 if (family >= CPU_MAXFAMILY) 1287 family = CPU_MINFAMILY; 1288 class = family - 3; 1289 modifier = ""; 1290 name = ""; 1291 ci->ci_info = NULL; 1292 } else { 1293 cpu_vendor = cpup->cpu_vendor; 1294 vendorname = cpup->cpu_vendorname; 1295 modifier = modifiers[modif]; 1296 if (family > CPU_MAXFAMILY) { 1297 family = CPU_MAXFAMILY; 1298 model = CPU_DEFMODEL; 1299 } else if (model > CPU_MAXMODEL) { 1300 model = CPU_DEFMODEL; 1301 ext_model = 0; 1302 } 1303 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 1304 if (cpufam->cpu_extended_names == NULL || 1305 ext_model == 0) 1306 name = cpufam->cpu_models[model]; 1307 else { 1308 /* 1309 * Scan list(s) of extended model names 1310 */ 1311 modlist = cpufam->cpu_extended_names; 1312 while (modlist->ext_model != 0) { 1313 if (modlist->ext_model == ext_model) { 1314 name = 1315 modlist->cpu_models[model]; 1316 break; 1317 } 1318 modlist++; 1319 } 1320 } 1321 if (name == NULL || *name == '\0') 1322 name = cpufam->cpu_models[CPU_DEFMODEL]; 1323 class = cpufam->cpu_class; 1324 ci->ci_info = cpufam->cpu_info; 1325 1326 if (cpu_vendor == CPUVENDOR_INTEL) { 1327 if (family == 6 && model >= 5) { 1328 const char *tmp; 1329 tmp = intel_family6_name(ci); 1330 if (tmp != NULL) 1331 name = tmp; 1332 } 1333 if (family == CPU_MAXFAMILY && 1334 ci->ci_brand_id < 1335 __arraycount(i386_intel_brand) && 1336 i386_intel_brand[ci->ci_brand_id]) 1337 name = 1338 i386_intel_brand[ci->ci_brand_id]; 1339 } 1340 1341 if (cpu_vendor == CPUVENDOR_AMD) { 1342 if (family == 6 && model >= 6) { 1343 if (ci->ci_brand_id == 1) 1344 /* 1345 * It's Duron. We override the 1346 * name, since it might have 1347 * been misidentified as Athlon. 1348 */ 1349 name = 1350 amd_brand[ci->ci_brand_id]; 1351 else 1352 brand = amd_brand_name; 1353 } 1354 if (CPUID2FAMILY(ci->ci_signature) == 0xf) { 1355 /* 1356 * Identify AMD64 CPU names. 1357 * Note family value is clipped by 1358 * CPU_MAXFAMILY. 1359 */ 1360 const char *tmp; 1361 tmp = amd_amd64_name(ci); 1362 if (tmp != NULL) 1363 name = tmp; 1364 } 1365 } 1366 1367 if (cpu_vendor == CPUVENDOR_IDT && family >= 6) 1368 vendorname = "VIA"; 1369 } 1370 } 1371 1372 ci->ci_cpu_class = class; 1373 1374 sz = sizeof(ci->ci_tsc_freq); 1375 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 1376 1377 snprintf(cpu_model, sizeof(cpu_model), "%s%s%s%s%s%s%s (%s-class)", 1378 vendorname, 1379 *modifier ? " " : "", modifier, 1380 *name ? " " : "", name, 1381 *brand ? " " : "", brand, 1382 classnames[class]); 1383 aprint_normal("%s: %s", cpuname, cpu_model); 1384 1385 if (ci->ci_tsc_freq != 0) 1386 aprint_normal(", %qd.%02qd MHz", 1387 (ci->ci_tsc_freq + 4999) / 1000000, 1388 ((ci->ci_tsc_freq + 4999) / 10000) % 100); 1389 if (ci->ci_signature != 0) 1390 aprint_normal(", id 0x%x", ci->ci_signature); 1391 aprint_normal("\n"); 1392 1393 if (ci->ci_info) 1394 (*ci->ci_info)(ci); 1395 1396 /* 1397 * display CPU feature flags 1398 */ 1399 1400 #define MAX_FEATURE_LEN 60 /* XXX Need to find a better way to set this */ 1401 1402 feature_str[0] = CPUID_FLAGS1; 1403 feature_str[1] = CPUID2_FLAGS1; 1404 feature_str[2] = CPUID_EXT_FLAGS; 1405 feature_str[3] = NULL; 1406 feature_str[4] = NULL; 1407 1408 switch (cpu_vendor) { 1409 case CPUVENDOR_AMD: 1410 feature_str[3] = CPUID_AMD_FLAGS4; 1411 break; 1412 case CPUVENDOR_INTEL: 1413 feature_str[2] = CPUID_INTEL_EXT_FLAGS; 1414 feature_str[3] = CPUID_INTEL_FLAGS4; 1415 break; 1416 case CPUVENDOR_CYRIX: 1417 feature_str[4] = CPUID_FLAGS_PADLOCK; 1418 /* FALLTHRU */ 1419 default: 1420 break; 1421 } 1422 1423 for (i = 0; i <= 4; i++) { 1424 if (ci->ci_feat_val[i] && feature_str[i] != NULL) { 1425 snprintb_m(buf, sizeof(buf), feature_str[i], 1426 ci->ci_feat_val[i], MAX_FEATURE_LEN); 1427 bp = buf; 1428 while (*bp != '\0') { 1429 aprint_verbose("%s: %sfeatures%c %s\n", 1430 cpuname, (i == 4)?"padlock ":"", 1431 (i == 4 || i == 0)?' ':'1' + i, bp); 1432 bp += strlen(bp) + 1; 1433 } 1434 } 1435 } 1436 1437 if (*cpu_brand_string != '\0') 1438 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 1439 1440 x86_print_cacheinfo(ci); 1441 1442 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 1443 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 1444 cpuname, 1445 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 1446 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 1447 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 1448 } 1449 1450 if (ci->ci_cpu_class == CPUCLASS_386) { 1451 errx(1, "NetBSD requires an 80486 or later processor"); 1452 } 1453 1454 if (cpu == CPU_486DLC) { 1455 #ifndef CYRIX_CACHE_WORKS 1456 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 1457 #else 1458 #ifndef CYRIX_CACHE_REALLY_WORKS 1459 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 1460 #else 1461 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 1462 #endif 1463 #endif 1464 } 1465 1466 /* 1467 * Everything past this point requires a Pentium or later. 1468 */ 1469 if (ci->ci_cpuid_level < 0) 1470 return; 1471 1472 identifycpu_cpuids(ci); 1473 1474 #ifdef INTEL_CORETEMP 1475 if (cpu_vendor == CPUVENDOR_INTEL && ci->ci_cpuid_level >= 0x06) 1476 coretemp_register(ci); 1477 #endif 1478 1479 if (cpu_vendor == CPUVENDOR_AMD) { 1480 powernow_probe(ci); 1481 1482 if ((ci->ci_feat_val[3] & CPUID_SVM) != 0) { 1483 uint32_t data[4]; 1484 1485 x86_cpuid(0x8000000a, data); 1486 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 1487 data[0] & 0xf); 1488 aprint_verbose("%s: SVM NASID %d\n", cpuname, data[1]); 1489 snprintb(buf, sizeof(buf), CPUID_AMD_SVM_FLAGS, 1490 data[3]); 1491 aprint_verbose("%s: SVM features %s\n", cpuname, buf); 1492 } 1493 } 1494 1495 #ifdef INTEL_ONDEMAND_CLOCKMOD 1496 clockmod_init(); 1497 #endif 1498 1499 aprint_normal_dev(ci->ci_dev, "family %02x model %02x " 1500 "extfamily %02x extmodel %02x\n", CPUID2FAMILY(ci->ci_signature), 1501 CPUID2MODEL(ci->ci_signature), CPUID2EXTFAMILY(ci->ci_signature), 1502 CPUID2EXTMODEL(ci->ci_signature)); 1503 } 1504 1505 static const char * 1506 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 1507 const char *sep) 1508 { 1509 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1510 char human_num[HUMAN_BUFSIZE]; 1511 1512 if (cai->cai_totalsize == 0) 1513 return sep; 1514 1515 if (sep == NULL) 1516 aprint_verbose_dev(ci->ci_dev, ""); 1517 else 1518 aprint_verbose("%s", sep); 1519 if (name != NULL) 1520 aprint_verbose("%s ", name); 1521 1522 if (cai->cai_string != NULL) { 1523 aprint_verbose("%s ", cai->cai_string); 1524 } else { 1525 (void)humanize_number(human_num, sizeof(human_num), 1526 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 1527 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 1528 } 1529 switch (cai->cai_associativity) { 1530 case 0: 1531 aprint_verbose("disabled"); 1532 break; 1533 case 1: 1534 aprint_verbose("direct-mapped"); 1535 break; 1536 case 0xff: 1537 aprint_verbose("fully associative"); 1538 break; 1539 default: 1540 aprint_verbose("%d-way", cai->cai_associativity); 1541 break; 1542 } 1543 return ", "; 1544 } 1545 1546 static const char * 1547 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 1548 const char *sep) 1549 { 1550 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1551 char human_num[HUMAN_BUFSIZE]; 1552 1553 if (cai->cai_totalsize == 0) 1554 return sep; 1555 1556 if (sep == NULL) 1557 aprint_verbose_dev(ci->ci_dev, ""); 1558 else 1559 aprint_verbose("%s", sep); 1560 if (name != NULL) 1561 aprint_verbose("%s ", name); 1562 1563 if (cai->cai_string != NULL) { 1564 aprint_verbose("%s", cai->cai_string); 1565 } else { 1566 (void)humanize_number(human_num, sizeof(human_num), 1567 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 1568 aprint_verbose("%d %s entries ", cai->cai_totalsize, 1569 human_num); 1570 switch (cai->cai_associativity) { 1571 case 0: 1572 aprint_verbose("disabled"); 1573 break; 1574 case 1: 1575 aprint_verbose("direct-mapped"); 1576 break; 1577 case 0xff: 1578 aprint_verbose("fully associative"); 1579 break; 1580 default: 1581 aprint_verbose("%d-way", cai->cai_associativity); 1582 break; 1583 } 1584 } 1585 return ", "; 1586 } 1587 1588 static const struct x86_cache_info * 1589 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 1590 { 1591 int i; 1592 1593 for (i = 0; cai[i].cai_desc != 0; i++) { 1594 if (cai[i].cai_desc == desc) 1595 return (&cai[i]); 1596 } 1597 1598 return (NULL); 1599 } 1600 1601 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 1602 AMD_L2CACHE_INFO; 1603 1604 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 1605 AMD_L3CACHE_INFO; 1606 1607 static void 1608 amd_cpu_cacheinfo(struct cpu_info *ci) 1609 { 1610 const struct x86_cache_info *cp; 1611 struct x86_cache_info *cai; 1612 int family, model; 1613 u_int descs[4]; 1614 u_int lfunc; 1615 1616 family = (ci->ci_signature >> 8) & 15; 1617 model = CPUID2MODEL(ci->ci_signature); 1618 1619 /* 1620 * K5 model 0 has none of this info. 1621 */ 1622 if (family == 5 && model == 0) 1623 return; 1624 1625 /* 1626 * Get extended values for K8 and up. 1627 */ 1628 if (family == 0xf) { 1629 family += CPUID2EXTFAMILY(ci->ci_signature); 1630 model += CPUID2EXTMODEL(ci->ci_signature); 1631 } 1632 1633 /* 1634 * Determine the largest extended function value. 1635 */ 1636 x86_cpuid(0x80000000, descs); 1637 lfunc = descs[0]; 1638 1639 /* 1640 * Determine L1 cache/TLB info. 1641 */ 1642 if (lfunc < 0x80000005) { 1643 /* No L1 cache info available. */ 1644 return; 1645 } 1646 1647 x86_cpuid(0x80000005, descs); 1648 1649 /* 1650 * K6-III and higher have large page TLBs. 1651 */ 1652 if ((family == 5 && model >= 9) || family >= 6) { 1653 cai = &ci->ci_cinfo[CAI_ITLB2]; 1654 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1655 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1656 cai->cai_linesize = (4 * 1024 * 1024); 1657 1658 cai = &ci->ci_cinfo[CAI_DTLB2]; 1659 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1660 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1661 cai->cai_linesize = (4 * 1024 * 1024); 1662 } 1663 1664 cai = &ci->ci_cinfo[CAI_ITLB]; 1665 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1666 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1667 cai->cai_linesize = (4 * 1024); 1668 1669 cai = &ci->ci_cinfo[CAI_DTLB]; 1670 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1671 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1672 cai->cai_linesize = (4 * 1024); 1673 1674 cai = &ci->ci_cinfo[CAI_DCACHE]; 1675 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1676 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1677 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[2]); 1678 1679 cai = &ci->ci_cinfo[CAI_ICACHE]; 1680 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1681 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1682 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1683 1684 /* 1685 * Determine L2 cache/TLB info. 1686 */ 1687 if (lfunc < 0x80000006) { 1688 /* No L2 cache info available. */ 1689 return; 1690 } 1691 1692 x86_cpuid(0x80000006, descs); 1693 1694 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1695 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1696 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1697 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1698 1699 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1700 cai->cai_associativity); 1701 if (cp != NULL) 1702 cai->cai_associativity = cp->cai_associativity; 1703 else 1704 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1705 1706 /* 1707 * Determine L3 cache info on AMD Family 10h processors 1708 */ 1709 if (family == 0x10) { 1710 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1711 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1712 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1713 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1714 1715 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1716 cai->cai_associativity); 1717 if (cp != NULL) 1718 cai->cai_associativity = cp->cai_associativity; 1719 else 1720 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1721 } 1722 } 1723 1724 static void 1725 via_cpu_cacheinfo(struct cpu_info *ci) 1726 { 1727 struct x86_cache_info *cai; 1728 int family, model, stepping; 1729 u_int descs[4]; 1730 u_int lfunc; 1731 1732 family = (ci->ci_signature >> 8) & 15; 1733 model = CPUID2MODEL(ci->ci_signature); 1734 stepping = CPUID2STEPPING(ci->ci_signature); 1735 1736 /* 1737 * Determine the largest extended function value. 1738 */ 1739 x86_cpuid(0x80000000, descs); 1740 lfunc = descs[0]; 1741 1742 /* 1743 * Determine L1 cache/TLB info. 1744 */ 1745 if (lfunc < 0x80000005) { 1746 /* No L1 cache info available. */ 1747 return; 1748 } 1749 1750 x86_cpuid(0x80000005, descs); 1751 1752 cai = &ci->ci_cinfo[CAI_ITLB]; 1753 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1754 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1755 cai->cai_linesize = (4 * 1024); 1756 1757 cai = &ci->ci_cinfo[CAI_DTLB]; 1758 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1759 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1760 cai->cai_linesize = (4 * 1024); 1761 1762 cai = &ci->ci_cinfo[CAI_DCACHE]; 1763 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1764 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1765 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1766 if (model == 9 && stepping == 8) { 1767 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1768 cai->cai_associativity = 2; 1769 } 1770 1771 cai = &ci->ci_cinfo[CAI_ICACHE]; 1772 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1773 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1774 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1775 if (model == 9 && stepping == 8) { 1776 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1777 cai->cai_associativity = 2; 1778 } 1779 1780 /* 1781 * Determine L2 cache/TLB info. 1782 */ 1783 if (lfunc < 0x80000006) { 1784 /* No L2 cache info available. */ 1785 return; 1786 } 1787 1788 x86_cpuid(0x80000006, descs); 1789 1790 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1791 if (model >= 9) { 1792 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1793 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1794 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1795 } else { 1796 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1797 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1798 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1799 } 1800 } 1801 1802 static void 1803 x86_print_cacheinfo(struct cpu_info *ci) 1804 { 1805 const char *sep; 1806 1807 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 1808 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 1809 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 1810 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 1811 if (sep != NULL) 1812 aprint_verbose("\n"); 1813 } 1814 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 1815 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 1816 if (sep != NULL) 1817 aprint_verbose("\n"); 1818 } 1819 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 1820 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 1821 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 1822 if (sep != NULL) 1823 aprint_verbose("\n"); 1824 } 1825 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 1826 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 1827 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 1828 if (sep != NULL) 1829 aprint_verbose("\n"); 1830 } 1831 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 1832 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 1833 if (sep != NULL) 1834 aprint_verbose("\n"); 1835 } 1836 } 1837 1838 static void 1839 powernow_probe(struct cpu_info *ci) 1840 { 1841 uint32_t regs[4]; 1842 char buf[256]; 1843 1844 x86_cpuid(0x80000000, regs); 1845 1846 /* We need CPUID(0x80000007) */ 1847 if (regs[0] < 0x80000007) 1848 return; 1849 x86_cpuid(0x80000007, regs); 1850 1851 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 1852 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 1853 buf); 1854 } 1855
Indexes created Thu Sep 25 16:09:42 GMT 2025