i386.c revision 1.25.4.3
1 /* $NetBSD: i386.c,v 1.25.4.3 2012/10/30 19:00:31 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.25.4.3 2012/10/30 19:00:31 yamt Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/cpuio.h> 68 69 #include <string.h> 70 #include <stdio.h> 71 #include <stdlib.h> 72 #include <err.h> 73 #include <assert.h> 74 #include <math.h> 75 #include <util.h> 76 77 #include <machine/specialreg.h> 78 #include <machine/cpu.h> 79 80 #include <x86/cpuvar.h> 81 #include <x86/cputypes.h> 82 #include <x86/cacheinfo.h> 83 #include <x86/cpu_ucode.h> 84 85 #include "../cpuctl.h" 86 87 /* Size of buffer for printing humanized numbers */ 88 #define HUMAN_BUFSIZE sizeof("999KB") 89 90 #define x86_cpuid(a,b) x86_cpuid2((a),0,(b)) 91 92 void x86_cpuid2(uint32_t, uint32_t, uint32_t *); 93 void x86_identify(void); 94 95 struct cpu_info { 96 const char *ci_dev; 97 int32_t ci_cpuid_level; 98 uint32_t ci_signature; /* X86 cpuid type */ 99 uint32_t ci_feat_val[5]; /* X86 CPUID feature bits 100 * [0] basic features %edx 101 * [1] basic features %ecx 102 * [2] extended features %edx 103 * [3] extended features %ecx 104 * [4] VIA padlock features 105 */ 106 uint32_t ci_cpu_class; /* CPU class */ 107 uint32_t ci_brand_id; /* Intel brand id */ 108 uint32_t ci_vendor[4]; /* vendor string */ 109 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 110 uint64_t ci_tsc_freq; /* cpu cycles/second */ 111 uint8_t ci_packageid; 112 uint8_t ci_coreid; 113 uint8_t ci_smtid; 114 uint32_t ci_initapicid; 115 struct x86_cache_info ci_cinfo[CAI_COUNT]; 116 void (*ci_info)(struct cpu_info *); 117 }; 118 119 struct cpu_nocpuid_nameclass { 120 int cpu_vendor; 121 const char *cpu_vendorname; 122 const char *cpu_name; 123 int cpu_class; 124 void (*cpu_setup)(struct cpu_info *); 125 void (*cpu_cacheinfo)(struct cpu_info *); 126 void (*cpu_info)(struct cpu_info *); 127 }; 128 129 struct cpu_extend_nameclass { 130 int ext_model; 131 const char *cpu_models[CPU_MAXMODEL+1]; 132 }; 133 134 struct cpu_cpuid_nameclass { 135 const char *cpu_id; 136 int cpu_vendor; 137 const char *cpu_vendorname; 138 struct cpu_cpuid_family { 139 int cpu_class; 140 const char *cpu_models[CPU_MAXMODEL+2]; 141 void (*cpu_setup)(struct cpu_info *); 142 void (*cpu_probe)(struct cpu_info *); 143 void (*cpu_info)(struct cpu_info *); 144 struct cpu_extend_nameclass *cpu_extended_names; 145 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 146 }; 147 148 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 149 150 /* 151 * Map Brand ID from cpuid instruction to brand name. 152 * Source: Intel Processor Identification and the CPUID Instruction, AP-485 153 */ 154 static const char * const i386_intel_brand[] = { 155 "", /* Unsupported */ 156 "Celeron", /* Intel (R) Celeron (TM) processor */ 157 "Pentium III", /* Intel (R) Pentium (R) III processor */ 158 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 159 "Pentium III", /* Intel (R) Pentium (R) III processor */ 160 "", /* Reserved */ 161 "Mobile Pentium III", /* Mobile Intel (R) Pentium (R) III processor-M */ 162 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 163 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 164 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 165 "Celeron", /* Intel (R) Celeron (TM) processor */ 166 "Xeon", /* Intel (R) Xeon (TM) processor */ 167 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 168 "", /* Reserved */ 169 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 170 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 171 }; 172 173 /* 174 * AMD processors don't have Brand IDs, so we need these names for probe. 175 */ 176 static const char * const amd_brand[] = { 177 "", 178 "Duron", /* AMD Duron(tm) */ 179 "MP", /* AMD Athlon(tm) MP */ 180 "XP", /* AMD Athlon(tm) XP */ 181 "4" /* AMD Athlon(tm) 4 */ 182 }; 183 184 static int cpu_vendor; 185 static char cpu_brand_string[49]; 186 static char amd_brand_name[48]; 187 static int use_pae, largepagesize; 188 189 static void via_cpu_probe(struct cpu_info *); 190 static void amd_family6_probe(struct cpu_info *); 191 static void intel_family_new_probe(struct cpu_info *); 192 static const char *intel_family6_name(struct cpu_info *); 193 static const char *amd_amd64_name(struct cpu_info *); 194 static void amd_family5_setup(struct cpu_info *); 195 static void transmeta_cpu_info(struct cpu_info *); 196 static const char *print_cache_config(struct cpu_info *, int, const char *, 197 const char *); 198 static const char *print_tlb_config(struct cpu_info *, int, const char *, 199 const char *); 200 static void amd_cpu_cacheinfo(struct cpu_info *); 201 static void via_cpu_cacheinfo(struct cpu_info *); 202 static void x86_print_cacheinfo(struct cpu_info *); 203 static const struct x86_cache_info *cache_info_lookup( 204 const struct x86_cache_info *, uint8_t); 205 static void cyrix6x86_cpu_setup(struct cpu_info *); 206 static void winchip_cpu_setup(struct cpu_info *); 207 static void amd_family5_setup(struct cpu_info *); 208 static void powernow_probe(struct cpu_info *); 209 210 /* 211 * Info for CTL_HW 212 */ 213 static char cpu_model[120]; 214 215 /* 216 * Note: these are just the ones that may not have a cpuid instruction. 217 * We deal with the rest in a different way. 218 */ 219 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 220 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 221 NULL, NULL, NULL }, /* CPU_386SX */ 222 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 223 NULL, NULL, NULL }, /* CPU_386 */ 224 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 225 NULL, NULL, NULL }, /* CPU_486SX */ 226 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 227 NULL, NULL, NULL }, /* CPU_486 */ 228 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 229 NULL, NULL, NULL }, /* CPU_486DLC */ 230 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 231 NULL, NULL, NULL }, /* CPU_6x86 */ 232 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 233 NULL, NULL, NULL }, /* CPU_NX586 */ 234 }; 235 236 const char *classnames[] = { 237 "386", 238 "486", 239 "586", 240 "686" 241 }; 242 243 const char *modifiers[] = { 244 "", 245 "OverDrive", 246 "Dual", 247 "" 248 }; 249 250 struct cpu_extend_nameclass intel_family6_ext_models[] = { 251 { /* Extended models 1x */ 252 0x01, { NULL, NULL, 253 NULL, NULL, 254 NULL, "EP80579 Integrated Processor", 255 "Celeron (45nm)", "Core 2 Extreme", 256 NULL, NULL, 257 "Core i7 (Nehalem)", NULL, 258 "Atom", "XeonMP (Nehalem)", 259 NULL, NULL} }, 260 { /* End of list */ 261 0x00, { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 262 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL} } 263 }; 264 265 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 266 { 267 "GenuineIntel", 268 CPUVENDOR_INTEL, 269 "Intel", 270 /* Family 4 */ 271 { { 272 CPUCLASS_486, 273 { 274 "486DX", "486DX", "486SX", "486DX2", "486SL", 275 "486SX2", 0, "486DX2 W/B Enhanced", 276 "486DX4", 0, 0, 0, 0, 0, 0, 0, 277 "486" /* Default */ 278 }, 279 NULL, 280 NULL, 281 NULL, 282 NULL, 283 }, 284 /* Family 5 */ 285 { 286 CPUCLASS_586, 287 { 288 "Pentium (P5 A-step)", "Pentium (P5)", 289 "Pentium (P54C)", "Pentium (P24T)", 290 "Pentium/MMX", "Pentium", 0, 291 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 292 0, 0, 0, 0, 0, 0, 0, 293 "Pentium" /* Default */ 294 }, 295 NULL, 296 NULL, 297 NULL, 298 NULL, 299 }, 300 /* Family 6 */ 301 { 302 CPUCLASS_686, 303 { 304 "Pentium Pro (A-step)", "Pentium Pro", 0, 305 "Pentium II (Klamath)", "Pentium Pro", 306 "Pentium II/Celeron (Deschutes)", 307 "Celeron (Mendocino)", 308 "Pentium III (Katmai)", 309 "Pentium III (Coppermine)", 310 "Pentium M (Banias)", 311 "Pentium III Xeon (Cascades)", 312 "Pentium III (Tualatin)", 0, 313 "Pentium M (Dothan)", 314 "Pentium M (Yonah)", 315 "Core 2", 316 "Pentium Pro, II or III" /* Default */ 317 }, 318 NULL, 319 intel_family_new_probe, 320 NULL, 321 &intel_family6_ext_models[0], 322 }, 323 /* Family > 6 */ 324 { 325 CPUCLASS_686, 326 { 327 0, 0, 0, 0, 0, 0, 0, 0, 328 0, 0, 0, 0, 0, 0, 0, 0, 329 "Pentium 4" /* Default */ 330 }, 331 NULL, 332 intel_family_new_probe, 333 NULL, 334 NULL, 335 } } 336 }, 337 { 338 "AuthenticAMD", 339 CPUVENDOR_AMD, 340 "AMD", 341 /* Family 4 */ 342 { { 343 CPUCLASS_486, 344 { 345 0, 0, 0, "Am486DX2 W/T", 346 0, 0, 0, "Am486DX2 W/B", 347 "Am486DX4 W/T or Am5x86 W/T 150", 348 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 349 0, 0, "Am5x86 W/T 133/160", 350 "Am5x86 W/B 133/160", 351 "Am486 or Am5x86" /* Default */ 352 }, 353 NULL, 354 NULL, 355 NULL, 356 NULL, 357 }, 358 /* Family 5 */ 359 { 360 CPUCLASS_586, 361 { 362 "K5", "K5", "K5", "K5", 0, 0, "K6", 363 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 364 "K6-2+/III+", 0, 0, 365 "K5 or K6" /* Default */ 366 }, 367 amd_family5_setup, 368 NULL, 369 amd_cpu_cacheinfo, 370 NULL, 371 }, 372 /* Family 6 */ 373 { 374 CPUCLASS_686, 375 { 376 0, "Athlon Model 1", "Athlon Model 2", 377 "Duron", "Athlon Model 4 (Thunderbird)", 378 0, "Athlon", "Duron", "Athlon", 0, 379 "Athlon", 0, 0, 0, 0, 0, 380 "K7 (Athlon)" /* Default */ 381 }, 382 NULL, 383 amd_family6_probe, 384 amd_cpu_cacheinfo, 385 NULL, 386 }, 387 /* Family > 6 */ 388 { 389 CPUCLASS_686, 390 { 391 0, 0, 0, 0, 0, 0, 0, 0, 392 0, 0, 0, 0, 0, 0, 0, 0, 393 "Unknown K8 (Athlon)" /* Default */ 394 }, 395 NULL, 396 amd_family6_probe, 397 amd_cpu_cacheinfo, 398 NULL, 399 } } 400 }, 401 { 402 "CyrixInstead", 403 CPUVENDOR_CYRIX, 404 "Cyrix", 405 /* Family 4 */ 406 { { 407 CPUCLASS_486, 408 { 409 0, 0, 0, 410 "MediaGX", 411 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 412 "486" /* Default */ 413 }, 414 cyrix6x86_cpu_setup, /* XXX ?? */ 415 NULL, 416 NULL, 417 NULL, 418 }, 419 /* Family 5 */ 420 { 421 CPUCLASS_586, 422 { 423 0, 0, "6x86", 0, 424 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 425 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 426 "6x86" /* Default */ 427 }, 428 cyrix6x86_cpu_setup, 429 NULL, 430 NULL, 431 NULL, 432 }, 433 /* Family 6 */ 434 { 435 CPUCLASS_686, 436 { 437 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 438 0, 0, 0, 0, 0, 0, 0, 0, 439 "6x86MX" /* Default */ 440 }, 441 cyrix6x86_cpu_setup, 442 NULL, 443 NULL, 444 NULL, 445 }, 446 /* Family > 6 */ 447 { 448 CPUCLASS_686, 449 { 450 0, 0, 0, 0, 0, 0, 0, 0, 451 0, 0, 0, 0, 0, 0, 0, 0, 452 "Unknown 6x86MX" /* Default */ 453 }, 454 NULL, 455 NULL, 456 NULL, 457 NULL, 458 } } 459 }, 460 { /* MediaGX is now owned by National Semiconductor */ 461 "Geode by NSC", 462 CPUVENDOR_CYRIX, /* XXX */ 463 "National Semiconductor", 464 /* Family 4, NSC never had any of these */ 465 { { 466 CPUCLASS_486, 467 { 468 0, 0, 0, 0, 0, 0, 0, 0, 469 0, 0, 0, 0, 0, 0, 0, 0, 470 "486 compatible" /* Default */ 471 }, 472 NULL, 473 NULL, 474 NULL, 475 NULL, 476 }, 477 /* Family 5: Geode family, formerly MediaGX */ 478 { 479 CPUCLASS_586, 480 { 481 0, 0, 0, 0, 482 "Geode GX1", 483 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 484 "Geode" /* Default */ 485 }, 486 cyrix6x86_cpu_setup, 487 NULL, 488 amd_cpu_cacheinfo, 489 NULL, 490 }, 491 /* Family 6, not yet available from NSC */ 492 { 493 CPUCLASS_686, 494 { 495 0, 0, 0, 0, 0, 0, 0, 0, 496 0, 0, 0, 0, 0, 0, 0, 0, 497 "Pentium Pro compatible" /* Default */ 498 }, 499 NULL, 500 NULL, 501 NULL, 502 NULL, 503 }, 504 /* Family > 6, not yet available from NSC */ 505 { 506 CPUCLASS_686, 507 { 508 0, 0, 0, 0, 0, 0, 0, 0, 509 0, 0, 0, 0, 0, 0, 0, 0, 510 "Pentium Pro compatible" /* Default */ 511 }, 512 NULL, 513 NULL, 514 NULL, 515 NULL, 516 } } 517 }, 518 { 519 "CentaurHauls", 520 CPUVENDOR_IDT, 521 "IDT", 522 /* Family 4, IDT never had any of these */ 523 { { 524 CPUCLASS_486, 525 { 526 0, 0, 0, 0, 0, 0, 0, 0, 527 0, 0, 0, 0, 0, 0, 0, 0, 528 "486 compatible" /* Default */ 529 }, 530 NULL, 531 NULL, 532 NULL, 533 NULL, 534 }, 535 /* Family 5 */ 536 { 537 CPUCLASS_586, 538 { 539 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 540 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 541 "WinChip" /* Default */ 542 }, 543 winchip_cpu_setup, 544 NULL, 545 NULL, 546 NULL, 547 }, 548 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 549 { 550 CPUCLASS_686, 551 { 552 0, 0, 0, 0, 0, 0, "C3 Samuel", 553 "C3 Samuel 2/Ezra", "C3 Ezra-T", 554 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 555 0, "VIA Nano", 556 "Unknown VIA/IDT" /* Default */ 557 }, 558 NULL, 559 via_cpu_probe, 560 via_cpu_cacheinfo, 561 NULL, 562 }, 563 /* Family > 6, not yet available from VIA */ 564 { 565 CPUCLASS_686, 566 { 567 0, 0, 0, 0, 0, 0, 0, 0, 568 0, 0, 0, 0, 0, 0, 0, 0, 569 "Pentium Pro compatible" /* Default */ 570 }, 571 NULL, 572 NULL, 573 NULL, 574 NULL, 575 } } 576 }, 577 { 578 "GenuineTMx86", 579 CPUVENDOR_TRANSMETA, 580 "Transmeta", 581 /* Family 4, Transmeta never had any of these */ 582 { { 583 CPUCLASS_486, 584 { 585 0, 0, 0, 0, 0, 0, 0, 0, 586 0, 0, 0, 0, 0, 0, 0, 0, 587 "486 compatible" /* Default */ 588 }, 589 NULL, 590 NULL, 591 NULL, 592 NULL, 593 }, 594 /* Family 5 */ 595 { 596 CPUCLASS_586, 597 { 598 0, 0, 0, 0, 0, 0, 0, 0, 599 0, 0, 0, 0, 0, 0, 0, 0, 600 "Crusoe" /* Default */ 601 }, 602 NULL, 603 NULL, 604 transmeta_cpu_info, 605 NULL, 606 }, 607 /* Family 6, not yet available from Transmeta */ 608 { 609 CPUCLASS_686, 610 { 611 0, 0, 0, 0, 0, 0, 0, 0, 612 0, 0, 0, 0, 0, 0, 0, 0, 613 "Pentium Pro compatible" /* Default */ 614 }, 615 NULL, 616 NULL, 617 NULL, 618 NULL, 619 }, 620 /* Family > 6, not yet available from Transmeta */ 621 { 622 CPUCLASS_686, 623 { 624 0, 0, 0, 0, 0, 0, 0, 0, 625 0, 0, 0, 0, 0, 0, 0, 0, 626 "Pentium Pro compatible" /* Default */ 627 }, 628 NULL, 629 NULL, 630 NULL, 631 NULL, 632 } } 633 } 634 }; 635 636 /* 637 * disable the TSC such that we don't use the TSC in microtime(9) 638 * because some CPUs got the implementation wrong. 639 */ 640 static void 641 disable_tsc(struct cpu_info *ci) 642 { 643 if (ci->ci_feat_val[0] & CPUID_TSC) { 644 ci->ci_feat_val[0] &= ~CPUID_TSC; 645 aprint_error("WARNING: broken TSC disabled\n"); 646 } 647 } 648 649 static void 650 cyrix6x86_cpu_setup(struct cpu_info *ci) 651 { 652 653 /* 654 * Do not disable the TSC on the Geode GX, it's reported to 655 * work fine. 656 */ 657 if (ci->ci_signature != 0x552) 658 disable_tsc(ci); 659 } 660 661 void 662 winchip_cpu_setup(struct cpu_info *ci) 663 { 664 switch (CPUID2MODEL(ci->ci_signature)) { /* model */ 665 case 4: /* WinChip C6 */ 666 disable_tsc(ci); 667 } 668 } 669 670 671 static void 672 identifycpu_cpuids(struct cpu_info *ci) 673 { 674 const char *cpuname = ci->ci_dev; 675 u_int lp_max = 1; /* logical processors per package */ 676 u_int smt_max; /* smt per core */ 677 u_int core_max = 1; /* core per package */ 678 u_int smt_bits, core_bits; 679 uint32_t descs[4]; 680 681 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 682 ci->ci_packageid = ci->ci_initapicid; 683 ci->ci_coreid = 0; 684 ci->ci_smtid = 0; 685 if (cpu_vendor != CPUVENDOR_INTEL) { 686 return; 687 } 688 689 /* 690 * 253668.pdf 7.10.2 691 */ 692 693 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 694 x86_cpuid(1, descs); 695 lp_max = (descs[1] >> 16) & 0xff; 696 } 697 x86_cpuid(0, descs); 698 if (descs[0] >= 4) { 699 x86_cpuid2(4, 0, descs); 700 core_max = (descs[0] >> 26) + 1; 701 } 702 assert(lp_max >= core_max); 703 smt_max = lp_max / core_max; 704 smt_bits = ilog2(smt_max - 1) + 1; 705 core_bits = ilog2(core_max - 1) + 1; 706 if (smt_bits + core_bits) { 707 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 708 } 709 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 710 ci->ci_packageid); 711 if (core_bits) { 712 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 713 714 ci->ci_coreid = 715 __SHIFTOUT(ci->ci_initapicid, core_mask); 716 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 717 } 718 if (smt_bits) { 719 u_int smt_mask = __BITS((int)0, (int)(smt_bits - 1)); 720 721 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, smt_mask); 722 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 723 } 724 } 725 726 static void 727 via_cpu_probe(struct cpu_info *ci) 728 { 729 u_int model = CPUID2MODEL(ci->ci_signature); 730 u_int stepping = CPUID2STEPPING(ci->ci_signature); 731 u_int descs[4]; 732 u_int lfunc; 733 734 /* 735 * Determine the largest extended function value. 736 */ 737 x86_cpuid(0x80000000, descs); 738 lfunc = descs[0]; 739 740 /* 741 * Determine the extended feature flags. 742 */ 743 if (lfunc >= 0x80000001) { 744 x86_cpuid(0x80000001, descs); 745 ci->ci_feat_val[2] |= descs[3]; 746 } 747 748 if (model < 0x9 || (model == 0x9 && stepping < 3)) 749 return; 750 751 /* Nehemiah or Esther */ 752 x86_cpuid(0xc0000000, descs); 753 lfunc = descs[0]; 754 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 755 return; 756 757 x86_cpuid(0xc0000001, descs); 758 lfunc = descs[3]; 759 ci->ci_feat_val[4] = lfunc; 760 } 761 762 static const char * 763 intel_family6_name(struct cpu_info *ci) 764 { 765 int model = CPUID2MODEL(ci->ci_signature); 766 const char *ret = NULL; 767 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 768 769 if (model == 5) { 770 switch (l2cache) { 771 case 0: 772 case 128 * 1024: 773 ret = "Celeron (Covington)"; 774 break; 775 case 256 * 1024: 776 ret = "Mobile Pentium II (Dixon)"; 777 break; 778 case 512 * 1024: 779 ret = "Pentium II"; 780 break; 781 case 1 * 1024 * 1024: 782 case 2 * 1024 * 1024: 783 ret = "Pentium II Xeon"; 784 break; 785 } 786 } else if (model == 6) { 787 switch (l2cache) { 788 case 256 * 1024: 789 case 512 * 1024: 790 ret = "Mobile Pentium II"; 791 break; 792 } 793 } else if (model == 7) { 794 switch (l2cache) { 795 case 512 * 1024: 796 ret = "Pentium III"; 797 break; 798 case 1 * 1024 * 1024: 799 case 2 * 1024 * 1024: 800 ret = "Pentium III Xeon"; 801 break; 802 } 803 } else if (model >= 8) { 804 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 805 switch (ci->ci_brand_id) { 806 case 0x3: 807 if (ci->ci_signature == 0x6B1) 808 ret = "Celeron"; 809 break; 810 case 0x8: 811 if (ci->ci_signature >= 0xF13) 812 ret = "genuine processor"; 813 break; 814 case 0xB: 815 if (ci->ci_signature >= 0xF13) 816 ret = "Xeon MP"; 817 break; 818 case 0xE: 819 if (ci->ci_signature < 0xF13) 820 ret = "Xeon"; 821 break; 822 } 823 if (ret == NULL) 824 ret = i386_intel_brand[ci->ci_brand_id]; 825 } 826 } 827 828 return ret; 829 } 830 831 /* 832 * Identify AMD64 CPU names from cpuid. 833 * 834 * Based on: 835 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 836 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 837 * "Revision Guide for AMD NPT Family 0Fh Processors" 838 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 839 * and other miscellaneous reports. 840 */ 841 static const char * 842 amd_amd64_name(struct cpu_info *ci) 843 { 844 int extfamily, extmodel, model; 845 const char *ret = NULL; 846 847 model = CPUID2MODEL(ci->ci_signature); 848 extfamily = CPUID2EXTFAMILY(ci->ci_signature); 849 extmodel = CPUID2EXTMODEL(ci->ci_signature); 850 851 switch (extfamily) { 852 case 0x00: 853 switch (model) { 854 case 0x1: 855 switch (extmodel) { 856 case 0x2: /* rev JH-E1/E6 */ 857 case 0x4: /* rev JH-F2 */ 858 ret = "Dual-Core Opteron"; 859 break; 860 } 861 break; 862 case 0x3: 863 switch (extmodel) { 864 case 0x2: /* rev JH-E6 (Toledo) */ 865 ret = "Dual-Core Opteron or Athlon 64 X2"; 866 break; 867 case 0x4: /* rev JH-F2 (Windsor) */ 868 ret = "Athlon 64 FX or Athlon 64 X2"; 869 break; 870 } 871 break; 872 case 0x4: 873 switch (extmodel) { 874 case 0x0: /* rev SH-B0/C0/CG (ClawHammer) */ 875 case 0x1: /* rev SH-D0 */ 876 ret = "Athlon 64"; 877 break; 878 case 0x2: /* rev SH-E5 (Lancaster?) */ 879 ret = "Mobile Athlon 64 or Turion 64"; 880 break; 881 } 882 break; 883 case 0x5: 884 switch (extmodel) { 885 case 0x0: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 886 ret = "Opteron or Athlon 64 FX"; 887 break; 888 case 0x1: /* rev SH-D0 */ 889 case 0x2: /* rev SH-E4 */ 890 ret = "Opteron"; 891 break; 892 } 893 break; 894 case 0x7: 895 switch (extmodel) { 896 case 0x0: /* rev SH-CG (ClawHammer) */ 897 case 0x1: /* rev SH-D0 */ 898 ret = "Athlon 64"; 899 break; 900 case 0x2: /* rev DH-E4, SH-E4 */ 901 ret = "Athlon 64 or Athlon 64 FX or Opteron"; 902 break; 903 } 904 break; 905 case 0x8: 906 switch (extmodel) { 907 case 0x0: /* rev CH-CG */ 908 case 0x1: /* rev CH-D0 */ 909 ret = "Athlon 64 or Sempron"; 910 break; 911 case 0x4: /* rev BH-F2 */ 912 ret = "Turion 64 X2"; 913 break; 914 } 915 break; 916 case 0xb: 917 switch (extmodel) { 918 case 0x0: /* rev CH-CG */ 919 case 0x1: /* rev CH-D0 */ 920 ret = "Athlon 64"; 921 break; 922 case 0x2: /* rev BH-E4 (Manchester) */ 923 case 0x4: /* rev BH-F2 (Windsor) */ 924 ret = "Athlon 64 X2"; 925 break; 926 case 0x6: /* rev BH-G1 (Brisbane) */ 927 ret = "Athlon X2 or Athlon 64 X2"; 928 break; 929 } 930 break; 931 case 0xc: 932 switch (extmodel) { 933 case 0x0: /* rev DH-CG (Newcastle) */ 934 case 0x1: /* rev DH-D0 (Winchester) */ 935 case 0x2: /* rev DH-E3/E6 */ 936 ret = "Athlon 64 or Sempron"; 937 break; 938 } 939 break; 940 case 0xe: 941 switch (extmodel) { 942 case 0x0: /* rev DH-CG (Newcastle?) */ 943 ret = "Athlon 64 or Sempron"; 944 break; 945 } 946 break; 947 case 0xf: 948 switch (extmodel) { 949 case 0x0: /* rev DH-CG (Newcastle/Paris) */ 950 case 0x1: /* rev DH-D0 (Winchester/Victoria) */ 951 case 0x2: /* rev DH-E3/E6 (Venice/Palermo) */ 952 case 0x4: /* rev DH-F2 (Orleans/Manila) */ 953 case 0x5: /* rev DH-F2 (Orleans/Manila) */ 954 case 0x6: /* rev DH-G1 */ 955 ret = "Athlon 64 or Sempron"; 956 break; 957 } 958 break; 959 default: 960 ret = "Unknown AMD64 CPU"; 961 } 962 break; 963 case 0x01: 964 ret = "Family 10h"; 965 break; 966 case 0x02: 967 ret = "Family 11h"; 968 break; 969 case 0x03: 970 ret = "Family 12h"; 971 break; 972 case 0x05: 973 ret = "Family 14h"; 974 break; 975 case 0x06: 976 ret = "Family 15h"; 977 break; 978 default: 979 ret = "Unknown AMD64 CPU"; 980 break; 981 } 982 983 return ret; 984 } 985 986 static void 987 cpu_probe_base_features(struct cpu_info *ci) 988 { 989 const struct x86_cache_info *cai; 990 u_int descs[4]; 991 int iterations, i, j; 992 uint8_t desc; 993 uint32_t miscbytes; 994 uint32_t brand[12]; 995 996 if (ci->ci_cpuid_level < 0) 997 return; 998 999 x86_cpuid(0, descs); 1000 ci->ci_cpuid_level = descs[0]; 1001 ci->ci_vendor[0] = descs[1]; 1002 ci->ci_vendor[2] = descs[2]; 1003 ci->ci_vendor[1] = descs[3]; 1004 ci->ci_vendor[3] = 0; 1005 1006 x86_cpuid(0x80000000, brand); 1007 if (brand[0] >= 0x80000004) { 1008 x86_cpuid(0x80000002, brand); 1009 x86_cpuid(0x80000003, brand + 4); 1010 x86_cpuid(0x80000004, brand + 8); 1011 for (i = 0; i < 48; i++) 1012 if (((char *) brand)[i] != ' ') 1013 break; 1014 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1015 } 1016 1017 if (ci->ci_cpuid_level < 1) 1018 return; 1019 1020 x86_cpuid(1, descs); 1021 ci->ci_signature = descs[0]; 1022 miscbytes = descs[1]; 1023 ci->ci_feat_val[1] = descs[2]; 1024 ci->ci_feat_val[0] = descs[3]; 1025 1026 /* Brand is low order 8 bits of ebx */ 1027 ci->ci_brand_id = miscbytes & 0xff; 1028 ci->ci_initapicid = (miscbytes >> 24) & 0xff; 1029 if (ci->ci_cpuid_level < 2) 1030 return; 1031 1032 /* 1033 * Parse the cache info from `cpuid', if we have it. 1034 * XXX This is kinda ugly, but hey, so is the architecture... 1035 */ 1036 1037 x86_cpuid(2, descs); 1038 1039 iterations = descs[0] & 0xff; 1040 while (iterations-- > 0) { 1041 for (i = 0; i < 4; i++) { 1042 if (descs[i] & 0x80000000) 1043 continue; 1044 for (j = 0; j < 4; j++) { 1045 if (i == 0 && j == 0) 1046 continue; 1047 desc = (descs[i] >> (j * 8)) & 0xff; 1048 if (desc == 0) 1049 continue; 1050 cai = cache_info_lookup(intel_cpuid_cache_info, 1051 desc); 1052 if (cai != NULL) 1053 ci->ci_cinfo[cai->cai_index] = *cai; 1054 } 1055 } 1056 x86_cpuid(2, descs); 1057 } 1058 1059 if (ci->ci_cpuid_level < 3) 1060 return; 1061 1062 /* 1063 * If the processor serial number misfeature is present and supported, 1064 * extract it here. 1065 */ 1066 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1067 ci->ci_cpu_serial[0] = ci->ci_signature; 1068 x86_cpuid(3, descs); 1069 ci->ci_cpu_serial[2] = descs[2]; 1070 ci->ci_cpu_serial[1] = descs[3]; 1071 } 1072 } 1073 1074 static void 1075 cpu_probe_features(struct cpu_info *ci) 1076 { 1077 const struct cpu_cpuid_nameclass *cpup = NULL; 1078 int i, xmax, family; 1079 1080 cpu_probe_base_features(ci); 1081 1082 if (ci->ci_cpuid_level < 1) 1083 return; 1084 1085 xmax = __arraycount(i386_cpuid_cpus); 1086 for (i = 0; i < xmax; i++) { 1087 if (!strncmp((char *)ci->ci_vendor, 1088 i386_cpuid_cpus[i].cpu_id, 12)) { 1089 cpup = &i386_cpuid_cpus[i]; 1090 break; 1091 } 1092 } 1093 1094 if (cpup == NULL) 1095 return; 1096 1097 family = (ci->ci_signature >> 8) & 0xf; 1098 1099 if (family > CPU_MAXFAMILY) { 1100 family = CPU_MAXFAMILY; 1101 } 1102 i = family - CPU_MINFAMILY; 1103 1104 if (cpup->cpu_family[i].cpu_probe == NULL) 1105 return; 1106 1107 (*cpup->cpu_family[i].cpu_probe)(ci); 1108 } 1109 1110 static void 1111 intel_family_new_probe(struct cpu_info *ci) 1112 { 1113 uint32_t descs[4]; 1114 1115 x86_cpuid(0x80000000, descs); 1116 1117 /* 1118 * Determine extended feature flags. 1119 */ 1120 if (descs[0] >= 0x80000001) { 1121 x86_cpuid(0x80000001, descs); 1122 ci->ci_feat_val[2] |= descs[3]; 1123 ci->ci_feat_val[3] |= descs[2]; 1124 } 1125 } 1126 1127 static void 1128 amd_family6_probe(struct cpu_info *ci) 1129 { 1130 uint32_t descs[4]; 1131 char *p; 1132 size_t i; 1133 1134 x86_cpuid(0x80000000, descs); 1135 1136 /* 1137 * Determine the extended feature flags. 1138 */ 1139 if (descs[0] >= 0x80000001) { 1140 x86_cpuid(0x80000001, descs); 1141 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 1142 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 1143 } 1144 1145 if (*cpu_brand_string == '\0') 1146 return; 1147 1148 for (i = 1; i < __arraycount(amd_brand); i++) 1149 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 1150 ci->ci_brand_id = i; 1151 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 1152 break; 1153 } 1154 } 1155 1156 static void 1157 amd_family5_setup(struct cpu_info *ci) 1158 { 1159 1160 switch (CPUID2MODEL(ci->ci_signature)) { 1161 case 0: /* AMD-K5 Model 0 */ 1162 /* 1163 * According to the AMD Processor Recognition App Note, 1164 * the AMD-K5 Model 0 uses the wrong bit to indicate 1165 * support for global PTEs, instead using bit 9 (APIC) 1166 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 1167 */ 1168 if (ci->ci_feat_val[0] & CPUID_APIC) 1169 ci->ci_feat_val[0] = 1170 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 1171 /* 1172 * XXX But pmap_pg_g is already initialized -- need to kick 1173 * XXX the pmap somehow. How does the MP branch do this? 1174 */ 1175 break; 1176 } 1177 } 1178 1179 static void 1180 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1181 { 1182 u_int descs[4]; 1183 1184 x86_cpuid(0x80860007, descs); 1185 *frequency = descs[0]; 1186 *voltage = descs[1]; 1187 *percentage = descs[2]; 1188 } 1189 1190 static void 1191 transmeta_cpu_info(struct cpu_info *ci) 1192 { 1193 u_int descs[4], nreg; 1194 u_int frequency, voltage, percentage; 1195 1196 x86_cpuid(0x80860000, descs); 1197 nreg = descs[0]; 1198 if (nreg >= 0x80860001) { 1199 x86_cpuid(0x80860001, descs); 1200 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1201 (descs[1] >> 24) & 0xff, 1202 (descs[1] >> 16) & 0xff, 1203 (descs[1] >> 8) & 0xff, 1204 descs[1] & 0xff); 1205 } 1206 if (nreg >= 0x80860002) { 1207 x86_cpuid(0x80860002, descs); 1208 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1209 (descs[1] >> 24) & 0xff, 1210 (descs[1] >> 16) & 0xff, 1211 (descs[1] >> 8) & 0xff, 1212 descs[1] & 0xff, 1213 descs[2]); 1214 } 1215 if (nreg >= 0x80860006) { 1216 union { 1217 char text[65]; 1218 u_int descs[4][4]; 1219 } info; 1220 int i; 1221 1222 for (i=0; i<4; i++) { 1223 x86_cpuid(0x80860003 + i, info.descs[i]); 1224 } 1225 info.text[64] = '\0'; 1226 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1227 } 1228 1229 if (nreg >= 0x80860007) { 1230 tmx86_get_longrun_status(&frequency, 1231 &voltage, &percentage); 1232 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1233 frequency, voltage, percentage); 1234 } 1235 } 1236 1237 void 1238 identifycpu(int fd, const char *cpuname) 1239 { 1240 const char *name = "", *modifier, *vendorname, *brand = ""; 1241 int class = CPUCLASS_386, i, xmax; 1242 int modif, family, model, ext_model; 1243 const struct cpu_extend_nameclass *modlist; 1244 const struct cpu_cpuid_nameclass *cpup = NULL; 1245 const struct cpu_cpuid_family *cpufam; 1246 const char *feature_str[5]; 1247 struct cpu_info *ci, cistore; 1248 extern int cpu; 1249 extern int cpu_info_level; 1250 size_t sz; 1251 char buf[512]; 1252 char *bp; 1253 struct cpu_ucode_version ucode; 1254 union { 1255 struct cpu_ucode_version_amd amd; 1256 struct cpu_ucode_version_intel1 intel1; 1257 } ucvers; 1258 1259 ci = &cistore; 1260 memset(ci, 0, sizeof(*ci)); 1261 ci->ci_dev = cpuname; 1262 1263 x86_identify(); 1264 ci->ci_cpuid_level = cpu_info_level; 1265 cpu_probe_features(ci); 1266 1267 if (ci->ci_cpuid_level == -1) { 1268 if ((size_t)cpu >= __arraycount(i386_nocpuid_cpus)) 1269 errx(1, "unknown cpu type %d", cpu); 1270 name = i386_nocpuid_cpus[cpu].cpu_name; 1271 cpu_vendor = i386_nocpuid_cpus[cpu].cpu_vendor; 1272 vendorname = i386_nocpuid_cpus[cpu].cpu_vendorname; 1273 class = i386_nocpuid_cpus[cpu].cpu_class; 1274 ci->ci_info = i386_nocpuid_cpus[cpu].cpu_info; 1275 modifier = ""; 1276 } else { 1277 xmax = __arraycount(i386_cpuid_cpus); 1278 modif = (ci->ci_signature >> 12) & 0x3; 1279 family = CPUID2FAMILY(ci->ci_signature); 1280 if (family < CPU_MINFAMILY) 1281 errx(1, "identifycpu: strange family value"); 1282 model = CPUID2MODEL(ci->ci_signature); 1283 ext_model = CPUID2EXTMODEL(ci->ci_signature); 1284 1285 for (i = 0; i < xmax; i++) { 1286 if (!strncmp((char *)ci->ci_vendor, 1287 i386_cpuid_cpus[i].cpu_id, 12)) { 1288 cpup = &i386_cpuid_cpus[i]; 1289 break; 1290 } 1291 } 1292 1293 if (cpup == NULL) { 1294 cpu_vendor = CPUVENDOR_UNKNOWN; 1295 if (ci->ci_vendor[0] != '\0') 1296 vendorname = (char *)&ci->ci_vendor[0]; 1297 else 1298 vendorname = "Unknown"; 1299 if (family >= CPU_MAXFAMILY) 1300 family = CPU_MINFAMILY; 1301 class = family - 3; 1302 modifier = ""; 1303 name = ""; 1304 ci->ci_info = NULL; 1305 } else { 1306 cpu_vendor = cpup->cpu_vendor; 1307 vendorname = cpup->cpu_vendorname; 1308 modifier = modifiers[modif]; 1309 if (family > CPU_MAXFAMILY) { 1310 family = CPU_MAXFAMILY; 1311 model = CPU_DEFMODEL; 1312 } else if (model > CPU_MAXMODEL) { 1313 model = CPU_DEFMODEL; 1314 ext_model = 0; 1315 } 1316 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 1317 if (cpufam->cpu_extended_names == NULL || 1318 ext_model == 0) 1319 name = cpufam->cpu_models[model]; 1320 else { 1321 /* 1322 * Scan list(s) of extended model names 1323 */ 1324 modlist = cpufam->cpu_extended_names; 1325 while (modlist->ext_model != 0) { 1326 if (modlist->ext_model == ext_model) { 1327 name = 1328 modlist->cpu_models[model]; 1329 break; 1330 } 1331 modlist++; 1332 } 1333 } 1334 if (name == NULL || *name == '\0') 1335 name = cpufam->cpu_models[CPU_DEFMODEL]; 1336 class = cpufam->cpu_class; 1337 ci->ci_info = cpufam->cpu_info; 1338 1339 if (cpu_vendor == CPUVENDOR_INTEL) { 1340 if (family == 6 && model >= 5) { 1341 const char *tmp; 1342 tmp = intel_family6_name(ci); 1343 if (tmp != NULL) 1344 name = tmp; 1345 } 1346 if (family == CPU_MAXFAMILY && 1347 ci->ci_brand_id < 1348 __arraycount(i386_intel_brand) && 1349 i386_intel_brand[ci->ci_brand_id]) 1350 name = 1351 i386_intel_brand[ci->ci_brand_id]; 1352 } 1353 1354 if (cpu_vendor == CPUVENDOR_AMD) { 1355 if (family == 6 && model >= 6) { 1356 if (ci->ci_brand_id == 1) 1357 /* 1358 * It's Duron. We override the 1359 * name, since it might have 1360 * been misidentified as Athlon. 1361 */ 1362 name = 1363 amd_brand[ci->ci_brand_id]; 1364 else 1365 brand = amd_brand_name; 1366 } 1367 if (CPUID2FAMILY(ci->ci_signature) == 0xf) { 1368 /* 1369 * Identify AMD64 CPU names. 1370 * Note family value is clipped by 1371 * CPU_MAXFAMILY. 1372 */ 1373 const char *tmp; 1374 tmp = amd_amd64_name(ci); 1375 if (tmp != NULL) 1376 name = tmp; 1377 } 1378 } 1379 1380 if (cpu_vendor == CPUVENDOR_IDT && family >= 6) 1381 vendorname = "VIA"; 1382 } 1383 } 1384 1385 ci->ci_cpu_class = class; 1386 1387 sz = sizeof(ci->ci_tsc_freq); 1388 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 1389 sz = sizeof(use_pae); 1390 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 1391 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 1392 1393 snprintf(cpu_model, sizeof(cpu_model), "%s%s%s%s%s%s%s (%s-class)", 1394 vendorname, 1395 *modifier ? " " : "", modifier, 1396 *name ? " " : "", name, 1397 *brand ? " " : "", brand, 1398 classnames[class]); 1399 aprint_normal("%s: %s", cpuname, cpu_model); 1400 1401 if (ci->ci_tsc_freq != 0) 1402 aprint_normal(", %ju.%02ju MHz", 1403 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 1404 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 1405 if (ci->ci_signature != 0) 1406 aprint_normal(", id 0x%x", ci->ci_signature); 1407 aprint_normal("\n"); 1408 1409 if (ci->ci_info) 1410 (*ci->ci_info)(ci); 1411 1412 /* 1413 * display CPU feature flags 1414 */ 1415 1416 #define MAX_FEATURE_LEN 60 /* XXX Need to find a better way to set this */ 1417 1418 feature_str[0] = CPUID_FLAGS1; 1419 feature_str[1] = CPUID2_FLAGS1; 1420 feature_str[2] = CPUID_EXT_FLAGS; 1421 feature_str[3] = NULL; 1422 feature_str[4] = NULL; 1423 1424 switch (cpu_vendor) { 1425 case CPUVENDOR_AMD: 1426 feature_str[3] = CPUID_AMD_FLAGS4; 1427 break; 1428 case CPUVENDOR_INTEL: 1429 feature_str[2] = CPUID_INTEL_EXT_FLAGS; 1430 feature_str[3] = CPUID_INTEL_FLAGS4; 1431 break; 1432 case CPUVENDOR_IDT: 1433 feature_str[4] = CPUID_FLAGS_PADLOCK; 1434 break; 1435 default: 1436 break; 1437 } 1438 1439 for (i = 0; i <= 4; i++) { 1440 if (ci->ci_feat_val[i] && feature_str[i] != NULL) { 1441 snprintb_m(buf, sizeof(buf), feature_str[i], 1442 ci->ci_feat_val[i], MAX_FEATURE_LEN); 1443 bp = buf; 1444 while (*bp != '\0') { 1445 aprint_verbose("%s: %sfeatures%c %s\n", 1446 cpuname, (i == 4)?"padlock ":"", 1447 (i == 4 || i == 0)?' ':'1' + i, bp); 1448 bp += strlen(bp) + 1; 1449 } 1450 } 1451 } 1452 1453 if (*cpu_brand_string != '\0') 1454 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 1455 1456 x86_print_cacheinfo(ci); 1457 1458 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 1459 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 1460 cpuname, 1461 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 1462 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 1463 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 1464 } 1465 1466 if (ci->ci_cpu_class == CPUCLASS_386) { 1467 errx(1, "NetBSD requires an 80486 or later processor"); 1468 } 1469 1470 if (cpu == CPU_486DLC) { 1471 #ifndef CYRIX_CACHE_WORKS 1472 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 1473 #else 1474 #ifndef CYRIX_CACHE_REALLY_WORKS 1475 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 1476 #else 1477 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 1478 #endif 1479 #endif 1480 } 1481 1482 /* 1483 * Everything past this point requires a Pentium or later. 1484 */ 1485 if (ci->ci_cpuid_level < 0) 1486 return; 1487 1488 identifycpu_cpuids(ci); 1489 1490 #ifdef INTEL_CORETEMP 1491 if (cpu_vendor == CPUVENDOR_INTEL && ci->ci_cpuid_level >= 0x06) 1492 coretemp_register(ci); 1493 #endif 1494 1495 if (cpu_vendor == CPUVENDOR_AMD) { 1496 uint32_t data[4]; 1497 1498 x86_cpuid(0x80000000, data); 1499 if (data[0] >= 0x80000007) 1500 powernow_probe(ci); 1501 1502 if ((data[0] >= 0x8000000a) 1503 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 1504 1505 x86_cpuid(0x8000000a, data); 1506 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 1507 data[0] & 0xf); 1508 aprint_verbose("%s: SVM NASID %d\n", cpuname, data[1]); 1509 snprintb_m(buf, sizeof(buf), CPUID_AMD_SVM_FLAGS, 1510 data[3], MAX_FEATURE_LEN); 1511 bp = buf; 1512 while (*bp != '\0') { 1513 aprint_verbose("%s: SVM features %s\n", 1514 cpuname, bp); 1515 bp += strlen(bp) + 1; 1516 } 1517 } 1518 } 1519 1520 #ifdef INTEL_ONDEMAND_CLOCKMOD 1521 clockmod_init(); 1522 #endif 1523 1524 aprint_normal_dev(ci->ci_dev, "family %02x model %02x " 1525 "extfamily %02x extmodel %02x stepping %02x\n", 1526 CPUID2FAMILY(ci->ci_signature), CPUID2MODEL(ci->ci_signature), 1527 CPUID2EXTFAMILY(ci->ci_signature), CPUID2EXTMODEL(ci->ci_signature), 1528 CPUID2STEPPING(ci->ci_signature)); 1529 1530 if (cpu_vendor == CPUVENDOR_AMD) 1531 ucode.loader_version = CPU_UCODE_LOADER_AMD; 1532 else if (cpu_vendor == CPUVENDOR_INTEL) 1533 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 1534 else 1535 return; 1536 ucode.data = &ucvers; 1537 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) 1538 return; 1539 if (cpu_vendor == CPUVENDOR_AMD) 1540 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 1541 else if (cpu_vendor == CPUVENDOR_INTEL) 1542 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 1543 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 1544 } 1545 1546 static const char * 1547 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 1548 const char *sep) 1549 { 1550 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1551 char human_num[HUMAN_BUFSIZE]; 1552 1553 if (cai->cai_totalsize == 0) 1554 return sep; 1555 1556 if (sep == NULL) 1557 aprint_verbose_dev(ci->ci_dev, ""); 1558 else 1559 aprint_verbose("%s", sep); 1560 if (name != NULL) 1561 aprint_verbose("%s ", name); 1562 1563 if (cai->cai_string != NULL) { 1564 aprint_verbose("%s ", cai->cai_string); 1565 } else { 1566 (void)humanize_number(human_num, sizeof(human_num), 1567 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 1568 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 1569 } 1570 switch (cai->cai_associativity) { 1571 case 0: 1572 aprint_verbose("disabled"); 1573 break; 1574 case 1: 1575 aprint_verbose("direct-mapped"); 1576 break; 1577 case 0xff: 1578 aprint_verbose("fully associative"); 1579 break; 1580 default: 1581 aprint_verbose("%d-way", cai->cai_associativity); 1582 break; 1583 } 1584 return ", "; 1585 } 1586 1587 static const char * 1588 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 1589 const char *sep) 1590 { 1591 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1592 char human_num[HUMAN_BUFSIZE]; 1593 1594 if (cai->cai_totalsize == 0) 1595 return sep; 1596 1597 if (sep == NULL) 1598 aprint_verbose_dev(ci->ci_dev, ""); 1599 else 1600 aprint_verbose("%s", sep); 1601 if (name != NULL) 1602 aprint_verbose("%s ", name); 1603 1604 if (cai->cai_string != NULL) { 1605 aprint_verbose("%s", cai->cai_string); 1606 } else { 1607 (void)humanize_number(human_num, sizeof(human_num), 1608 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 1609 aprint_verbose("%d %s entries ", cai->cai_totalsize, 1610 human_num); 1611 switch (cai->cai_associativity) { 1612 case 0: 1613 aprint_verbose("disabled"); 1614 break; 1615 case 1: 1616 aprint_verbose("direct-mapped"); 1617 break; 1618 case 0xff: 1619 aprint_verbose("fully associative"); 1620 break; 1621 default: 1622 aprint_verbose("%d-way", cai->cai_associativity); 1623 break; 1624 } 1625 } 1626 return ", "; 1627 } 1628 1629 static const struct x86_cache_info * 1630 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 1631 { 1632 int i; 1633 1634 for (i = 0; cai[i].cai_desc != 0; i++) { 1635 if (cai[i].cai_desc == desc) 1636 return (&cai[i]); 1637 } 1638 1639 return (NULL); 1640 } 1641 1642 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 1643 AMD_L2CACHE_INFO; 1644 1645 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 1646 AMD_L3CACHE_INFO; 1647 1648 static void 1649 amd_cpu_cacheinfo(struct cpu_info *ci) 1650 { 1651 const struct x86_cache_info *cp; 1652 struct x86_cache_info *cai; 1653 int family, model; 1654 u_int descs[4]; 1655 u_int lfunc; 1656 1657 family = (ci->ci_signature >> 8) & 15; 1658 model = CPUID2MODEL(ci->ci_signature); 1659 1660 /* 1661 * K5 model 0 has none of this info. 1662 */ 1663 if (family == 5 && model == 0) 1664 return; 1665 1666 /* 1667 * Get extended values for K8 and up. 1668 */ 1669 if (family == 0xf) { 1670 family += CPUID2EXTFAMILY(ci->ci_signature); 1671 model += CPUID2EXTMODEL(ci->ci_signature); 1672 } 1673 1674 /* 1675 * Determine the largest extended function value. 1676 */ 1677 x86_cpuid(0x80000000, descs); 1678 lfunc = descs[0]; 1679 1680 /* 1681 * Determine L1 cache/TLB info. 1682 */ 1683 if (lfunc < 0x80000005) { 1684 /* No L1 cache info available. */ 1685 return; 1686 } 1687 1688 x86_cpuid(0x80000005, descs); 1689 1690 /* 1691 * K6-III and higher have large page TLBs. 1692 */ 1693 if ((family == 5 && model >= 9) || family >= 6) { 1694 cai = &ci->ci_cinfo[CAI_ITLB2]; 1695 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1696 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1697 cai->cai_linesize = largepagesize; 1698 1699 cai = &ci->ci_cinfo[CAI_DTLB2]; 1700 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1701 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1702 cai->cai_linesize = largepagesize; 1703 } 1704 1705 cai = &ci->ci_cinfo[CAI_ITLB]; 1706 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1707 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1708 cai->cai_linesize = (4 * 1024); 1709 1710 cai = &ci->ci_cinfo[CAI_DTLB]; 1711 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1712 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1713 cai->cai_linesize = (4 * 1024); 1714 1715 cai = &ci->ci_cinfo[CAI_DCACHE]; 1716 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1717 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1718 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1719 1720 cai = &ci->ci_cinfo[CAI_ICACHE]; 1721 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1722 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1723 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1724 1725 /* 1726 * Determine L2 cache/TLB info. 1727 */ 1728 if (lfunc < 0x80000006) { 1729 /* No L2 cache info available. */ 1730 return; 1731 } 1732 1733 x86_cpuid(0x80000006, descs); 1734 1735 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1736 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1737 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1738 cai->cai_linesize = (4 * 1024); 1739 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1740 cai->cai_associativity); 1741 if (cp != NULL) 1742 cai->cai_associativity = cp->cai_associativity; 1743 else 1744 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1745 1746 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1747 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1748 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1749 cai->cai_linesize = largepagesize; 1750 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1751 cai->cai_associativity); 1752 if (cp != NULL) 1753 cai->cai_associativity = cp->cai_associativity; 1754 else 1755 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1756 1757 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1758 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1759 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1760 cai->cai_linesize = (4 * 1024); 1761 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1762 cai->cai_associativity); 1763 if (cp != NULL) 1764 cai->cai_associativity = cp->cai_associativity; 1765 else 1766 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1767 1768 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1769 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1770 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1771 cai->cai_linesize = largepagesize; 1772 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1773 cai->cai_associativity); 1774 if (cp != NULL) 1775 cai->cai_associativity = cp->cai_associativity; 1776 else 1777 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1778 1779 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1780 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1781 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1782 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1783 1784 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1785 cai->cai_associativity); 1786 if (cp != NULL) 1787 cai->cai_associativity = cp->cai_associativity; 1788 else 1789 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1790 1791 /* 1792 * Determine L3 cache info on AMD Family 10h and newer processors 1793 */ 1794 if (family >= 0x10) { 1795 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1796 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1797 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1798 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1799 1800 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1801 cai->cai_associativity); 1802 if (cp != NULL) 1803 cai->cai_associativity = cp->cai_associativity; 1804 else 1805 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1806 } 1807 1808 /* 1809 * Determine 1GB TLB info. 1810 */ 1811 if (lfunc < 0x80000019) { 1812 /* No 1GB TLB info available. */ 1813 return; 1814 } 1815 1816 x86_cpuid(0x80000019, descs); 1817 1818 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1819 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1820 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1821 cai->cai_linesize = (1024 * 1024 * 1024); 1822 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1823 cai->cai_associativity); 1824 if (cp != NULL) 1825 cai->cai_associativity = cp->cai_associativity; 1826 else 1827 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1828 1829 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1830 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1831 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1832 cai->cai_linesize = (1024 * 1024 * 1024); 1833 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1834 cai->cai_associativity); 1835 if (cp != NULL) 1836 cai->cai_associativity = cp->cai_associativity; 1837 else 1838 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1839 1840 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1841 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1842 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1843 cai->cai_linesize = (1024 * 1024 * 1024); 1844 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1845 cai->cai_associativity); 1846 if (cp != NULL) 1847 cai->cai_associativity = cp->cai_associativity; 1848 else 1849 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1850 1851 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1852 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1853 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1854 cai->cai_linesize = (1024 * 1024 * 1024); 1855 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1856 cai->cai_associativity); 1857 if (cp != NULL) 1858 cai->cai_associativity = cp->cai_associativity; 1859 else 1860 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1861 } 1862 1863 static void 1864 via_cpu_cacheinfo(struct cpu_info *ci) 1865 { 1866 struct x86_cache_info *cai; 1867 int family, model, stepping; 1868 u_int descs[4]; 1869 u_int lfunc; 1870 1871 family = (ci->ci_signature >> 8) & 15; 1872 model = CPUID2MODEL(ci->ci_signature); 1873 stepping = CPUID2STEPPING(ci->ci_signature); 1874 1875 /* 1876 * Determine the largest extended function value. 1877 */ 1878 x86_cpuid(0x80000000, descs); 1879 lfunc = descs[0]; 1880 1881 /* 1882 * Determine L1 cache/TLB info. 1883 */ 1884 if (lfunc < 0x80000005) { 1885 /* No L1 cache info available. */ 1886 return; 1887 } 1888 1889 x86_cpuid(0x80000005, descs); 1890 1891 cai = &ci->ci_cinfo[CAI_ITLB]; 1892 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1893 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1894 cai->cai_linesize = (4 * 1024); 1895 1896 cai = &ci->ci_cinfo[CAI_DTLB]; 1897 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1898 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1899 cai->cai_linesize = (4 * 1024); 1900 1901 cai = &ci->ci_cinfo[CAI_DCACHE]; 1902 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1903 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1904 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1905 if (model == 9 && stepping == 8) { 1906 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1907 cai->cai_associativity = 2; 1908 } 1909 1910 cai = &ci->ci_cinfo[CAI_ICACHE]; 1911 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1912 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1913 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1914 if (model == 9 && stepping == 8) { 1915 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1916 cai->cai_associativity = 2; 1917 } 1918 1919 /* 1920 * Determine L2 cache/TLB info. 1921 */ 1922 if (lfunc < 0x80000006) { 1923 /* No L2 cache info available. */ 1924 return; 1925 } 1926 1927 x86_cpuid(0x80000006, descs); 1928 1929 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1930 if (model >= 9) { 1931 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1932 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1933 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1934 } else { 1935 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1936 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1937 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1938 } 1939 } 1940 1941 static void 1942 x86_print_cacheinfo(struct cpu_info *ci) 1943 { 1944 const char *sep; 1945 1946 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 1947 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 1948 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 1949 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 1950 if (sep != NULL) 1951 aprint_verbose("\n"); 1952 } 1953 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 1954 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 1955 if (sep != NULL) 1956 aprint_verbose("\n"); 1957 } 1958 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 1959 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 1960 if (sep != NULL) 1961 aprint_verbose("\n"); 1962 } 1963 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 1964 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 1965 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 1966 if (sep != NULL) 1967 aprint_verbose("\n"); 1968 } 1969 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 1970 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 1971 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 1972 if (sep != NULL) 1973 aprint_verbose("\n"); 1974 } 1975 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 1976 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 1977 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 1978 if (sep != NULL) 1979 aprint_verbose("\n"); 1980 } 1981 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 1982 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 1983 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 1984 if (sep != NULL) 1985 aprint_verbose("\n"); 1986 } 1987 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 1988 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", NULL); 1989 if (sep != NULL) 1990 aprint_verbose("\n"); 1991 } 1992 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 1993 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", NULL); 1994 if (sep != NULL) 1995 aprint_verbose("\n"); 1996 } 1997 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 1998 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", NULL); 1999 if (sep != NULL) 2000 aprint_verbose("\n"); 2001 } 2002 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 2003 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", NULL); 2004 if (sep != NULL) 2005 aprint_verbose("\n"); 2006 } 2007 } 2008 2009 static void 2010 powernow_probe(struct cpu_info *ci) 2011 { 2012 uint32_t regs[4]; 2013 char buf[256]; 2014 2015 x86_cpuid(0x80000007, regs); 2016 2017 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2018 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 2019 buf); 2020 } 2021 2022 int 2023 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2024 { 2025 struct cpu_info ci; 2026 int loader_version, res; 2027 struct cpu_ucode_version versreq; 2028 extern int cpu_info_level; 2029 2030 x86_identify(); 2031 ci.ci_cpuid_level = cpu_info_level; 2032 cpu_probe_base_features(&ci); 2033 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2034 loader_version = CPU_UCODE_LOADER_AMD; 2035 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2036 loader_version = CPU_UCODE_LOADER_INTEL1; 2037 else 2038 return -1; 2039 2040 /* check whether the kernel understands this loader version */ 2041 versreq.loader_version = loader_version; 2042 versreq.data = 0; 2043 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2044 if (res) 2045 return -1; 2046 2047 switch (loader_version) { 2048 case CPU_UCODE_LOADER_AMD: 2049 if (uc->cpu_nr != -1) { 2050 /* printf? */ 2051 return -1; 2052 } 2053 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2054 break; 2055 case CPU_UCODE_LOADER_INTEL1: 2056 if (uc->cpu_nr == -1) 2057 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2058 else 2059 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2060 break; 2061 default: /* can't happen */ 2062 return -1; 2063 } 2064 uc->loader_version = loader_version; 2065 return 0; 2066 } 2067
Indexes created Thu Oct 23 22:10:10 GMT 2025