i386.c revision 1.3
1 /* $NetBSD: i386.c,v 1.3 2008/05/15 23:31:56 chris Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.3 2008/05/15 23:31:56 chris Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 68 #include <string.h> 69 #include <stdio.h> 70 #include <stdlib.h> 71 #include <err.h> 72 #include <assert.h> 73 #include <math.h> 74 75 #include <machine/specialreg.h> 76 #include <machine/cpu.h> 77 78 #include <x86/cpuvar.h> 79 #include <x86/cputypes.h> 80 81 #include "../cpuctl.h" 82 83 #define x86_cpuid(a,b) x86_cpuid2((a),0,(b)) 84 85 void x86_cpuid2(uint32_t, uint32_t, uint32_t *); 86 void x86_identify(void); 87 88 struct x86_cache_info { 89 uint8_t cai_index; 90 uint8_t cai_desc; 91 uint8_t cai_associativity; 92 u_int cai_totalsize; /* #entries for TLB, bytes for cache */ 93 u_int cai_linesize; /* or page size for TLB */ 94 const char *cai_string; 95 }; 96 97 #define CAI_ITLB 0 /* Instruction TLB (4K pages) */ 98 #define CAI_ITLB2 1 /* Instruction TLB (2/4M pages) */ 99 #define CAI_DTLB 2 /* Data TLB (4K pages) */ 100 #define CAI_DTLB2 3 /* Data TLB (2/4M pages) */ 101 #define CAI_ICACHE 4 /* Instruction cache */ 102 #define CAI_DCACHE 5 /* Data cache */ 103 #define CAI_L2CACHE 6 /* Level 2 cache */ 104 105 #define CAI_COUNT 7 106 107 /* 108 * AMD Cache Info: 109 * 110 * Athlon, Duron: 111 * 112 * Function 8000.0005 L1 TLB/Cache Information 113 * EAX -- L1 TLB 2/4MB pages 114 * EBX -- L1 TLB 4K pages 115 * ECX -- L1 D-cache 116 * EDX -- L1 I-cache 117 * 118 * Function 8000.0006 L2 TLB/Cache Information 119 * EAX -- L2 TLB 2/4MB pages 120 * EBX -- L2 TLB 4K pages 121 * ECX -- L2 Unified cache 122 * EDX -- reserved 123 * 124 * K5, K6: 125 * 126 * Function 8000.0005 L1 TLB/Cache Information 127 * EAX -- reserved 128 * EBX -- TLB 4K pages 129 * ECX -- L1 D-cache 130 * EDX -- L1 I-cache 131 * 132 * K6-III: 133 * 134 * Function 8000.0006 L2 Cache Information 135 * EAX -- reserved 136 * EBX -- reserved 137 * ECX -- L2 Unified cache 138 * EDX -- reserved 139 */ 140 141 /* L1 TLB 2/4MB pages */ 142 #define AMD_L1_EAX_DTLB_ASSOC(x) (((x) >> 24) & 0xff) 143 #define AMD_L1_EAX_DTLB_ENTRIES(x) (((x) >> 16) & 0xff) 144 #define AMD_L1_EAX_ITLB_ASSOC(x) (((x) >> 8) & 0xff) 145 #define AMD_L1_EAX_ITLB_ENTRIES(x) ( (x) & 0xff) 146 147 /* L1 TLB 4K pages */ 148 #define AMD_L1_EBX_DTLB_ASSOC(x) (((x) >> 24) & 0xff) 149 #define AMD_L1_EBX_DTLB_ENTRIES(x) (((x) >> 16) & 0xff) 150 #define AMD_L1_EBX_ITLB_ASSOC(x) (((x) >> 8) & 0xff) 151 #define AMD_L1_EBX_ITLB_ENTRIES(x) ( (x) & 0xff) 152 153 /* L1 Data Cache */ 154 #define AMD_L1_ECX_DC_SIZE(x) ((((x) >> 24) & 0xff) * 1024) 155 #define AMD_L1_ECX_DC_ASSOC(x) (((x) >> 16) & 0xff) 156 #define AMD_L1_ECX_DC_LPT(x) (((x) >> 8) & 0xff) 157 #define AMD_L1_ECX_DC_LS(x) ( (x) & 0xff) 158 159 /* L1 Instruction Cache */ 160 #define AMD_L1_EDX_IC_SIZE(x) ((((x) >> 24) & 0xff) * 1024) 161 #define AMD_L1_EDX_IC_ASSOC(x) (((x) >> 16) & 0xff) 162 #define AMD_L1_EDX_IC_LPT(x) (((x) >> 8) & 0xff) 163 #define AMD_L1_EDX_IC_LS(x) ( (x) & 0xff) 164 165 /* Note for L2 TLB -- if the upper 16 bits are 0, it is a unified TLB */ 166 167 /* L2 TLB 2/4MB pages */ 168 #define AMD_L2_EAX_DTLB_ASSOC(x) (((x) >> 28) & 0xf) 169 #define AMD_L2_EAX_DTLB_ENTRIES(x) (((x) >> 16) & 0xfff) 170 #define AMD_L2_EAX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf) 171 #define AMD_L2_EAX_IUTLB_ENTRIES(x) ( (x) & 0xfff) 172 173 /* L2 TLB 4K pages */ 174 #define AMD_L2_EBX_DTLB_ASSOC(x) (((x) >> 28) & 0xf) 175 #define AMD_L2_EBX_DTLB_ENTRIES(x) (((x) >> 16) & 0xfff) 176 #define AMD_L2_EBX_IUTLB_ASSOC(x) (((x) >> 12) & 0xf) 177 #define AMD_L2_EBX_IUTLB_ENTRIES(x) ( (x) & 0xfff) 178 179 /* L2 Cache */ 180 #define AMD_L2_ECX_C_SIZE(x) ((((x) >> 16) & 0xffff) * 1024) 181 #define AMD_L2_ECX_C_ASSOC(x) (((x) >> 12) & 0xf) 182 #define AMD_L2_ECX_C_LPT(x) (((x) >> 8) & 0xf) 183 #define AMD_L2_ECX_C_LS(x) ( (x) & 0xff) 184 185 /* 186 * VIA Cache Info: 187 * 188 * Nehemiah (at least) 189 * 190 * Function 8000.0005 L1 TLB/Cache Information 191 * EAX -- reserved 192 * EBX -- L1 TLB 4K pages 193 * ECX -- L1 D-cache 194 * EDX -- L1 I-cache 195 * 196 * Function 8000.0006 L2 Cache Information 197 * EAX -- reserved 198 * EBX -- reserved 199 * ECX -- L2 Unified cache 200 * EDX -- reserved 201 */ 202 203 /* L1 TLB 4K pages */ 204 #define VIA_L1_EBX_DTLB_ASSOC(x) (((x) >> 24) & 0xff) 205 #define VIA_L1_EBX_DTLB_ENTRIES(x) (((x) >> 16) & 0xff) 206 #define VIA_L1_EBX_ITLB_ASSOC(x) (((x) >> 8) & 0xff) 207 #define VIA_L1_EBX_ITLB_ENTRIES(x) ( (x) & 0xff) 208 209 /* L1 Data Cache */ 210 #define VIA_L1_ECX_DC_SIZE(x) ((((x) >> 24) & 0xff) * 1024) 211 #define VIA_L1_ECX_DC_ASSOC(x) (((x) >> 16) & 0xff) 212 #define VIA_L1_ECX_DC_LPT(x) (((x) >> 8) & 0xff) 213 #define VIA_L1_ECX_DC_LS(x) ( (x) & 0xff) 214 215 /* L1 Instruction Cache */ 216 #define VIA_L1_EDX_IC_SIZE(x) ((((x) >> 24) & 0xff) * 1024) 217 #define VIA_L1_EDX_IC_ASSOC(x) (((x) >> 16) & 0xff) 218 #define VIA_L1_EDX_IC_LPT(x) (((x) >> 8) & 0xff) 219 #define VIA_L1_EDX_IC_LS(x) ( (x) & 0xff) 220 221 /* L2 Cache (pre-Nehemiah) */ 222 #define VIA_L2_ECX_C_SIZE(x) ((((x) >> 24) & 0xff) * 1024) 223 #define VIA_L2_ECX_C_ASSOC(x) (((x) >> 16) & 0xff) 224 #define VIA_L2_ECX_C_LPT(x) (((x) >> 8) & 0xff) 225 #define VIA_L2_ECX_C_LS(x) ( (x) & 0xff) 226 227 /* L2 Cache (Nehemiah and newer) */ 228 #define VIA_L2N_ECX_C_SIZE(x) ((((x) >> 16) & 0xffff) * 1024) 229 #define VIA_L2N_ECX_C_ASSOC(x) (((x) >> 12) & 0xf) 230 #define VIA_L2N_ECX_C_LPT(x) (((x) >> 8) & 0xf) 231 #define VIA_L2N_ECX_C_LS(x) ( (x) & 0xff) 232 233 struct cpu_info { 234 const char *ci_dev; 235 int32_t ci_cpuid_level; 236 uint32_t ci_signature; /* X86 cpuid type */ 237 uint32_t ci_feature_flags;/* X86 %edx CPUID feature bits */ 238 uint32_t ci_feature2_flags;/* X86 %ecx CPUID feature bits */ 239 uint32_t ci_feature3_flags;/* X86 extended feature bits */ 240 uint32_t ci_padlock_flags;/* VIA PadLock feature bits */ 241 uint32_t ci_cpu_class; /* CPU class */ 242 uint32_t ci_brand_id; /* Intel brand id */ 243 uint32_t ci_vendor[4]; /* vendor string */ 244 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 245 uint64_t ci_tsc_freq; /* cpu cycles/second */ 246 uint8_t ci_packageid; 247 uint8_t ci_coreid; 248 uint8_t ci_smtid; 249 uint32_t ci_initapicid; 250 struct x86_cache_info ci_cinfo[CAI_COUNT]; 251 void (*ci_info)(struct cpu_info *); 252 }; 253 254 struct cpu_nocpuid_nameclass { 255 int cpu_vendor; 256 const char *cpu_vendorname; 257 const char *cpu_name; 258 int cpu_class; 259 void (*cpu_setup)(struct cpu_info *); 260 void (*cpu_cacheinfo)(struct cpu_info *); 261 void (*cpu_info)(struct cpu_info *); 262 }; 263 264 265 struct cpu_cpuid_nameclass { 266 const char *cpu_id; 267 int cpu_vendor; 268 const char *cpu_vendorname; 269 struct cpu_cpuid_family { 270 int cpu_class; 271 const char *cpu_models[CPU_MAXMODEL+2]; 272 void (*cpu_setup)(struct cpu_info *); 273 void (*cpu_probe)(struct cpu_info *); 274 void (*cpu_info)(struct cpu_info *); 275 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 276 }; 277 278 static const struct x86_cache_info intel_cpuid_cache_info[] = { 279 { CAI_ITLB, 0x01, 4, 32, 4 * 1024, NULL }, 280 { CAI_ITLB, 0xb0, 4,128, 4 * 1024, NULL }, 281 { CAI_ITLB2, 0x02, 0xff, 2, 4 * 1024 * 1024, NULL }, 282 { CAI_DTLB, 0x03, 4, 64, 4 * 1024, NULL }, 283 { CAI_DTLB, 0xb3, 4,128, 4 * 1024, NULL }, 284 { CAI_DTLB2, 0x04, 4, 8, 4 * 1024 * 1024, NULL }, 285 { CAI_ITLB, 0x50, 0xff, 64, 4 * 1024, "4K/4M: 64 entries" }, 286 { CAI_ITLB, 0x51, 0xff, 64, 4 * 1024, "4K/4M: 128 entries" }, 287 { CAI_ITLB, 0x52, 0xff, 64, 4 * 1024, "4K/4M: 256 entries" }, 288 { CAI_DTLB, 0x5b, 0xff, 64, 4 * 1024, "4K/4M: 64 entries" }, 289 { CAI_DTLB, 0x5c, 0xff, 64, 4 * 1024, "4K/4M: 128 entries" }, 290 { CAI_DTLB, 0x5d, 0xff, 64, 4 * 1024, "4K/4M: 256 entries" }, 291 { CAI_ICACHE, 0x06, 4, 8 * 1024, 32, NULL }, 292 { CAI_ICACHE, 0x08, 4, 16 * 1024, 32, NULL }, 293 { CAI_ICACHE, 0x30, 8, 32 * 1024, 64, NULL }, 294 { CAI_DCACHE, 0x0a, 2, 8 * 1024, 32, NULL }, 295 { CAI_DCACHE, 0x0c, 4, 16 * 1024, 32, NULL }, 296 { CAI_L2CACHE, 0x40, 0, 0, 0, "not present" }, 297 { CAI_L2CACHE, 0x41, 4, 128 * 1024, 32, NULL }, 298 { CAI_L2CACHE, 0x42, 4, 256 * 1024, 32, NULL }, 299 { CAI_L2CACHE, 0x43, 4, 512 * 1024, 32, NULL }, 300 { CAI_L2CACHE, 0x44, 4, 1 * 1024 * 1024, 32, NULL }, 301 { CAI_L2CACHE, 0x45, 4, 2 * 1024 * 1024, 32, NULL }, 302 { CAI_L2CACHE, 0x49, 16, 4 * 1024 * 1024, 64, NULL }, 303 { CAI_DCACHE, 0x66, 4, 8 * 1024, 64, NULL }, 304 { CAI_DCACHE, 0x67, 4, 16 * 1024, 64, NULL }, 305 { CAI_DCACHE, 0x2c, 8, 32 * 1024, 64, NULL }, 306 { CAI_DCACHE, 0x68, 4, 32 * 1024, 64, NULL }, 307 { CAI_ICACHE, 0x70, 8, 12 * 1024, 64, "12K uOp cache"}, 308 { CAI_ICACHE, 0x71, 8, 16 * 1024, 64, "16K uOp cache"}, 309 { CAI_ICACHE, 0x72, 8, 32 * 1024, 64, "32K uOp cache"}, 310 { CAI_L2CACHE, 0x79, 8, 128 * 1024, 64, NULL }, 311 { CAI_L2CACHE, 0x7a, 8, 256 * 1024, 64, NULL }, 312 { CAI_L2CACHE, 0x7b, 8, 512 * 1024, 64, NULL }, 313 { CAI_L2CACHE, 0x7c, 8, 1 * 1024 * 1024, 64, NULL }, 314 { CAI_L2CACHE, 0x7d, 8, 2 * 1024 * 1024, 64, NULL }, 315 { CAI_L2CACHE, 0x82, 8, 256 * 1024, 32, NULL }, 316 { CAI_L2CACHE, 0x83, 8, 512 * 1024, 32, NULL }, 317 { CAI_L2CACHE, 0x84, 8, 1 * 1024 * 1024, 32, NULL }, 318 { CAI_L2CACHE, 0x85, 8, 2 * 1024 * 1024, 32, NULL }, 319 { CAI_L2CACHE, 0x86, 4, 512 * 1024, 64, NULL }, 320 { 0, 0, 0, 0, 0, NULL }, 321 }; 322 323 /* 324 * Map Brand ID from cpuid instruction to brand name. 325 * Source: Intel Processor Identification and the CPUID Instruction, AP-485 326 */ 327 static const char * const i386_intel_brand[] = { 328 "", /* Unsupported */ 329 "Celeron", /* Intel (R) Celeron (TM) processor */ 330 "Pentium III", /* Intel (R) Pentium (R) III processor */ 331 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 332 "Pentium III", /* Intel (R) Pentium (R) III processor */ 333 "", /* Reserved */ 334 "Mobile Pentium III", /* Mobile Intel (R) Pentium (R) III processor-M */ 335 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 336 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 337 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 338 "Celeron", /* Intel (R) Celeron (TM) processor */ 339 "Xeon", /* Intel (R) Xeon (TM) processor */ 340 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 341 "", /* Reserved */ 342 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 343 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 344 }; 345 346 /* 347 * AMD processors don't have Brand IDs, so we need these names for probe. 348 */ 349 static const char * const amd_brand[] = { 350 "", 351 "Duron", /* AMD Duron(tm) */ 352 "MP", /* AMD Athlon(tm) MP */ 353 "XP", /* AMD Athlon(tm) XP */ 354 "4" /* AMD Athlon(tm) 4 */ 355 }; 356 357 static int cpu_vendor; 358 static char cpu_brand_string[49]; 359 static char amd_brand_name[48]; 360 361 static void via_cpu_probe(struct cpu_info *); 362 static void amd_family6_probe(struct cpu_info *); 363 static void intel_family_new_probe(struct cpu_info *); 364 static const char *intel_family6_name(struct cpu_info *); 365 static const char *amd_amd64_name(struct cpu_info *); 366 static void amd_family5_setup(struct cpu_info *); 367 static void transmeta_cpu_info(struct cpu_info *); 368 static const char *print_cache_config(struct cpu_info *, int, const char *, 369 const char *); 370 static const char *print_tlb_config(struct cpu_info *, int, const char *, 371 const char *); 372 static void amd_cpu_cacheinfo(struct cpu_info *); 373 static void via_cpu_cacheinfo(struct cpu_info *); 374 static void x86_print_cacheinfo(struct cpu_info *); 375 static const struct x86_cache_info *cache_info_lookup( 376 const struct x86_cache_info *, uint8_t); 377 static void cyrix6x86_cpu_setup(struct cpu_info *); 378 static void winchip_cpu_setup(struct cpu_info *); 379 static void amd_family5_setup(struct cpu_info *); 380 381 /* 382 * Info for CTL_HW 383 */ 384 static char cpu_model[120]; 385 386 /* 387 * Note: these are just the ones that may not have a cpuid instruction. 388 * We deal with the rest in a different way. 389 */ 390 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 391 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 392 NULL, NULL, NULL }, /* CPU_386SX */ 393 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 394 NULL, NULL, NULL }, /* CPU_386 */ 395 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 396 NULL, NULL, NULL }, /* CPU_486SX */ 397 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 398 NULL, NULL, NULL }, /* CPU_486 */ 399 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 400 NULL, NULL, NULL }, /* CPU_486DLC */ 401 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 402 NULL, NULL, NULL }, /* CPU_6x86 */ 403 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 404 NULL, NULL, NULL }, /* CPU_NX586 */ 405 }; 406 407 const char *classnames[] = { 408 "386", 409 "486", 410 "586", 411 "686" 412 }; 413 414 const char *modifiers[] = { 415 "", 416 "OverDrive", 417 "Dual", 418 "" 419 }; 420 421 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 422 { 423 "GenuineIntel", 424 CPUVENDOR_INTEL, 425 "Intel", 426 /* Family 4 */ 427 { { 428 CPUCLASS_486, 429 { 430 "486DX", "486DX", "486SX", "486DX2", "486SL", 431 "486SX2", 0, "486DX2 W/B Enhanced", 432 "486DX4", 0, 0, 0, 0, 0, 0, 0, 433 "486" /* Default */ 434 }, 435 NULL, 436 NULL, 437 NULL, 438 }, 439 /* Family 5 */ 440 { 441 CPUCLASS_586, 442 { 443 "Pentium (P5 A-step)", "Pentium (P5)", 444 "Pentium (P54C)", "Pentium (P24T)", 445 "Pentium/MMX", "Pentium", 0, 446 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 447 0, 0, 0, 0, 0, 0, 0, 448 "Pentium" /* Default */ 449 }, 450 NULL, 451 NULL, 452 NULL, 453 }, 454 /* Family 6 */ 455 { 456 CPUCLASS_686, 457 { 458 "Pentium Pro (A-step)", "Pentium Pro", 0, 459 "Pentium II (Klamath)", "Pentium Pro", 460 "Pentium II/Celeron (Deschutes)", 461 "Celeron (Mendocino)", 462 "Pentium III (Katmai)", 463 "Pentium III (Coppermine)", 464 "Pentium M (Banias)", 465 "Pentium III Xeon (Cascades)", 466 "Pentium III (Tualatin)", 0, 467 "Pentium M (Dothan)", 468 "Pentium M (Yonah)", 469 "Core 2 (Merom)", 470 "Pentium Pro, II or III" /* Default */ 471 }, 472 NULL, 473 intel_family_new_probe, 474 NULL, 475 }, 476 /* Family > 6 */ 477 { 478 CPUCLASS_686, 479 { 480 0, 0, 0, 0, 0, 0, 0, 0, 481 0, 0, 0, 0, 0, 0, 0, 0, 482 "Pentium 4" /* Default */ 483 }, 484 NULL, 485 intel_family_new_probe, 486 NULL, 487 } } 488 }, 489 { 490 "AuthenticAMD", 491 CPUVENDOR_AMD, 492 "AMD", 493 /* Family 4 */ 494 { { 495 CPUCLASS_486, 496 { 497 0, 0, 0, "Am486DX2 W/T", 498 0, 0, 0, "Am486DX2 W/B", 499 "Am486DX4 W/T or Am5x86 W/T 150", 500 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 501 0, 0, "Am5x86 W/T 133/160", 502 "Am5x86 W/B 133/160", 503 "Am486 or Am5x86" /* Default */ 504 }, 505 NULL, 506 NULL, 507 NULL, 508 }, 509 /* Family 5 */ 510 { 511 CPUCLASS_586, 512 { 513 "K5", "K5", "K5", "K5", 0, 0, "K6", 514 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 515 "K6-2+/III+", 0, 0, 516 "K5 or K6" /* Default */ 517 }, 518 amd_family5_setup, 519 NULL, 520 amd_cpu_cacheinfo, 521 }, 522 /* Family 6 */ 523 { 524 CPUCLASS_686, 525 { 526 0, "Athlon Model 1", "Athlon Model 2", 527 "Duron", "Athlon Model 4 (Thunderbird)", 528 0, "Athlon", "Duron", "Athlon", 0, 529 "Athlon", 0, 0, 0, 0, 0, 530 "K7 (Athlon)" /* Default */ 531 }, 532 NULL, 533 amd_family6_probe, 534 amd_cpu_cacheinfo, 535 }, 536 /* Family > 6 */ 537 { 538 CPUCLASS_686, 539 { 540 0, 0, 0, 0, 0, 0, 0, 0, 541 0, 0, 0, 0, 0, 0, 0, 0, 542 "Unknown K8 (Athlon)" /* Default */ 543 }, 544 NULL, 545 amd_family6_probe, 546 amd_cpu_cacheinfo, 547 } } 548 }, 549 { 550 "CyrixInstead", 551 CPUVENDOR_CYRIX, 552 "Cyrix", 553 /* Family 4 */ 554 { { 555 CPUCLASS_486, 556 { 557 0, 0, 0, 558 "MediaGX", 559 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 560 "486" /* Default */ 561 }, 562 cyrix6x86_cpu_setup, /* XXX ?? */ 563 NULL, 564 NULL, 565 }, 566 /* Family 5 */ 567 { 568 CPUCLASS_586, 569 { 570 0, 0, "6x86", 0, 571 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 572 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 573 "6x86" /* Default */ 574 }, 575 cyrix6x86_cpu_setup, 576 NULL, 577 NULL, 578 }, 579 /* Family 6 */ 580 { 581 CPUCLASS_686, 582 { 583 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 584 0, 0, 0, 0, 0, 0, 0, 0, 585 "6x86MX" /* Default */ 586 }, 587 cyrix6x86_cpu_setup, 588 NULL, 589 NULL, 590 }, 591 /* Family > 6 */ 592 { 593 CPUCLASS_686, 594 { 595 0, 0, 0, 0, 0, 0, 0, 0, 596 0, 0, 0, 0, 0, 0, 0, 0, 597 "Unknown 6x86MX" /* Default */ 598 }, 599 NULL, 600 NULL, 601 NULL, 602 } } 603 }, 604 { /* MediaGX is now owned by National Semiconductor */ 605 "Geode by NSC", 606 CPUVENDOR_CYRIX, /* XXX */ 607 "National Semiconductor", 608 /* Family 4, NSC never had any of these */ 609 { { 610 CPUCLASS_486, 611 { 612 0, 0, 0, 0, 0, 0, 0, 0, 613 0, 0, 0, 0, 0, 0, 0, 0, 614 "486 compatible" /* Default */ 615 }, 616 NULL, 617 NULL, 618 NULL, 619 }, 620 /* Family 5: Geode family, formerly MediaGX */ 621 { 622 CPUCLASS_586, 623 { 624 0, 0, 0, 0, 625 "Geode GX1", 626 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 627 "Geode" /* Default */ 628 }, 629 cyrix6x86_cpu_setup, 630 NULL, 631 amd_cpu_cacheinfo, 632 }, 633 /* Family 6, not yet available from NSC */ 634 { 635 CPUCLASS_686, 636 { 637 0, 0, 0, 0, 0, 0, 0, 0, 638 0, 0, 0, 0, 0, 0, 0, 0, 639 "Pentium Pro compatible" /* Default */ 640 }, 641 NULL, 642 NULL, 643 NULL, 644 }, 645 /* Family > 6, not yet available from NSC */ 646 { 647 CPUCLASS_686, 648 { 649 0, 0, 0, 0, 0, 0, 0, 0, 650 0, 0, 0, 0, 0, 0, 0, 0, 651 "Pentium Pro compatible" /* Default */ 652 }, 653 NULL, 654 NULL, 655 NULL, 656 } } 657 }, 658 { 659 "CentaurHauls", 660 CPUVENDOR_IDT, 661 "IDT", 662 /* Family 4, IDT never had any of these */ 663 { { 664 CPUCLASS_486, 665 { 666 0, 0, 0, 0, 0, 0, 0, 0, 667 0, 0, 0, 0, 0, 0, 0, 0, 668 "486 compatible" /* Default */ 669 }, 670 NULL, 671 NULL, 672 NULL, 673 }, 674 /* Family 5 */ 675 { 676 CPUCLASS_586, 677 { 678 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 679 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 680 "WinChip" /* Default */ 681 }, 682 winchip_cpu_setup, 683 NULL, 684 NULL, 685 }, 686 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 687 { 688 CPUCLASS_686, 689 { 690 0, 0, 0, 0, 0, 0, "C3 Samuel", 691 "C3 Samuel 2/Ezra", "C3 Ezra-T", 692 "C3 Nehemiah", "C7 Esther", 0, 0, 0, 0, 0, 693 "C3" /* Default */ 694 }, 695 NULL, 696 via_cpu_probe, 697 via_cpu_cacheinfo, 698 }, 699 /* Family > 6, not yet available from VIA */ 700 { 701 CPUCLASS_686, 702 { 703 0, 0, 0, 0, 0, 0, 0, 0, 704 0, 0, 0, 0, 0, 0, 0, 0, 705 "Pentium Pro compatible" /* Default */ 706 }, 707 NULL, 708 NULL, 709 NULL, 710 } } 711 }, 712 { 713 "GenuineTMx86", 714 CPUVENDOR_TRANSMETA, 715 "Transmeta", 716 /* Family 4, Transmeta never had any of these */ 717 { { 718 CPUCLASS_486, 719 { 720 0, 0, 0, 0, 0, 0, 0, 0, 721 0, 0, 0, 0, 0, 0, 0, 0, 722 "486 compatible" /* Default */ 723 }, 724 NULL, 725 NULL, 726 NULL, 727 }, 728 /* Family 5 */ 729 { 730 CPUCLASS_586, 731 { 732 0, 0, 0, 0, 0, 0, 0, 0, 733 0, 0, 0, 0, 0, 0, 0, 0, 734 "Crusoe" /* Default */ 735 }, 736 NULL, 737 NULL, 738 transmeta_cpu_info, 739 }, 740 /* Family 6, not yet available from Transmeta */ 741 { 742 CPUCLASS_686, 743 { 744 0, 0, 0, 0, 0, 0, 0, 0, 745 0, 0, 0, 0, 0, 0, 0, 0, 746 "Pentium Pro compatible" /* Default */ 747 }, 748 NULL, 749 NULL, 750 NULL, 751 }, 752 /* Family > 6, not yet available from Transmeta */ 753 { 754 CPUCLASS_686, 755 { 756 0, 0, 0, 0, 0, 0, 0, 0, 757 0, 0, 0, 0, 0, 0, 0, 0, 758 "Pentium Pro compatible" /* Default */ 759 }, 760 NULL, 761 NULL, 762 NULL, 763 } } 764 } 765 }; 766 767 /* 768 * disable the TSC such that we don't use the TSC in microtime(9) 769 * because some CPUs got the implementation wrong. 770 */ 771 static void 772 disable_tsc(struct cpu_info *ci) 773 { 774 if (ci->ci_feature_flags & CPUID_TSC) { 775 ci->ci_feature_flags &= ~CPUID_TSC; 776 aprint_error("WARNING: broken TSC disabled\n"); 777 } 778 } 779 780 static void 781 cyrix6x86_cpu_setup(struct cpu_info *ci) 782 { 783 784 /* 785 * Do not disable the TSC on the Geode GX, it's reported to 786 * work fine. 787 */ 788 if (ci->ci_signature != 0x552) 789 disable_tsc(ci); 790 } 791 792 void 793 winchip_cpu_setup(struct cpu_info *ci) 794 { 795 switch (CPUID2MODEL(ci->ci_signature)) { /* model */ 796 case 4: /* WinChip C6 */ 797 disable_tsc(ci); 798 } 799 } 800 801 802 static void 803 identifycpu_cpuids(struct cpu_info *ci) 804 { 805 const char *cpuname = ci->ci_dev; 806 u_int lp_max = 1; /* logical processors per package */ 807 u_int smt_max; /* smt per core */ 808 u_int core_max = 1; /* core per package */ 809 int smt_bits, core_bits; 810 uint32_t descs[4]; 811 812 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 813 ci->ci_packageid = ci->ci_initapicid; 814 ci->ci_coreid = 0; 815 ci->ci_smtid = 0; 816 if (cpu_vendor != CPUVENDOR_INTEL) { 817 return; 818 } 819 820 /* 821 * 253668.pdf 7.10.2 822 */ 823 824 if ((ci->ci_feature_flags & CPUID_HTT) != 0) { 825 x86_cpuid(1, descs); 826 lp_max = (descs[1] >> 16) & 0xff; 827 } 828 x86_cpuid(0, descs); 829 if (descs[0] >= 4) { 830 x86_cpuid2(4, 0, descs); 831 core_max = (descs[0] >> 26) + 1; 832 } 833 assert(lp_max >= core_max); 834 smt_max = lp_max / core_max; 835 smt_bits = ilog2(smt_max - 1) + 1; 836 core_bits = ilog2(core_max - 1) + 1; 837 if (smt_bits + core_bits) { 838 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 839 } 840 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 841 ci->ci_packageid); 842 if (core_bits) { 843 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 844 845 ci->ci_coreid = 846 __SHIFTOUT(ci->ci_initapicid, core_mask); 847 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 848 } 849 if (smt_bits) { 850 u_int smt_mask = __BITS(0, smt_bits - 1); 851 852 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, smt_mask); 853 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 854 } 855 } 856 857 static void 858 via_cpu_probe(struct cpu_info *ci) 859 { 860 u_int model = CPUID2MODEL(ci->ci_signature); 861 u_int stepping = CPUID2STEPPING(ci->ci_signature); 862 u_int descs[4]; 863 u_int lfunc; 864 865 /* 866 * Determine the largest extended function value. 867 */ 868 x86_cpuid(0x80000000, descs); 869 lfunc = descs[0]; 870 871 /* 872 * Determine the extended feature flags. 873 */ 874 if (lfunc >= 0x80000001) { 875 x86_cpuid(0x80000001, descs); 876 ci->ci_feature_flags |= descs[3]; 877 } 878 879 if (model < 0x9) 880 return; 881 882 /* Nehemiah or Esther */ 883 x86_cpuid(0xc0000000, descs); 884 lfunc = descs[0]; 885 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 886 return; 887 888 x86_cpuid(0xc0000001, descs); 889 lfunc = descs[3]; 890 if (model > 0x9 || stepping >= 8) { /* ACE */ 891 if (lfunc & CPUID_VIA_HAS_ACE) { 892 ci->ci_padlock_flags = lfunc; 893 } 894 } 895 } 896 897 static const char * 898 intel_family6_name(struct cpu_info *ci) 899 { 900 int model = CPUID2MODEL(ci->ci_signature); 901 const char *ret = NULL; 902 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 903 904 if (model == 5) { 905 switch (l2cache) { 906 case 0: 907 case 128 * 1024: 908 ret = "Celeron (Covington)"; 909 break; 910 case 256 * 1024: 911 ret = "Mobile Pentium II (Dixon)"; 912 break; 913 case 512 * 1024: 914 ret = "Pentium II"; 915 break; 916 case 1 * 1024 * 1024: 917 case 2 * 1024 * 1024: 918 ret = "Pentium II Xeon"; 919 break; 920 } 921 } else if (model == 6) { 922 switch (l2cache) { 923 case 256 * 1024: 924 case 512 * 1024: 925 ret = "Mobile Pentium II"; 926 break; 927 } 928 } else if (model == 7) { 929 switch (l2cache) { 930 case 512 * 1024: 931 ret = "Pentium III"; 932 break; 933 case 1 * 1024 * 1024: 934 case 2 * 1024 * 1024: 935 ret = "Pentium III Xeon"; 936 break; 937 } 938 } else if (model >= 8) { 939 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 940 switch (ci->ci_brand_id) { 941 case 0x3: 942 if (ci->ci_signature == 0x6B1) 943 ret = "Celeron"; 944 break; 945 case 0x8: 946 if (ci->ci_signature >= 0xF13) 947 ret = "genuine processor"; 948 break; 949 case 0xB: 950 if (ci->ci_signature >= 0xF13) 951 ret = "Xeon MP"; 952 break; 953 case 0xE: 954 if (ci->ci_signature < 0xF13) 955 ret = "Xeon"; 956 break; 957 } 958 if (ret == NULL) 959 ret = i386_intel_brand[ci->ci_brand_id]; 960 } 961 } 962 963 return ret; 964 } 965 966 /* 967 * Identify AMD64 CPU names from cpuid. 968 * 969 * Based on: 970 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 971 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 972 * "Revision Guide for AMD NPT Family 0Fh Processors" 973 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 974 * and other miscellaneous reports. 975 */ 976 static const char * 977 amd_amd64_name(struct cpu_info *ci) 978 { 979 int extfamily, extmodel, model; 980 const char *ret = NULL; 981 982 model = CPUID2MODEL(ci->ci_signature); 983 extfamily = CPUID2EXTFAMILY(ci->ci_signature); 984 extmodel = CPUID2EXTMODEL(ci->ci_signature); 985 986 if (extfamily == 0x00) { 987 switch (model) { 988 case 0x1: 989 switch (extmodel) { 990 case 0x2: /* rev JH-E1/E6 */ 991 case 0x4: /* rev JH-F2 */ 992 ret = "Dual-Core Opteron"; 993 break; 994 } 995 break; 996 case 0x3: 997 switch (extmodel) { 998 case 0x2: /* rev JH-E6 (Toledo) */ 999 ret = "Dual-Core Opteron or Athlon 64 X2"; 1000 break; 1001 case 0x4: /* rev JH-F2 (Windsor) */ 1002 ret = "Athlon 64 FX or Athlon 64 X2"; 1003 break; 1004 } 1005 break; 1006 case 0x4: 1007 switch (extmodel) { 1008 case 0x0: /* rev SH-B0/C0/CG (ClawHammer) */ 1009 case 0x1: /* rev SH-D0 */ 1010 ret = "Athlon 64"; 1011 break; 1012 case 0x2: /* rev SH-E5 (Lancaster?) */ 1013 ret = "Mobile Athlon 64 or Turion 64"; 1014 break; 1015 } 1016 break; 1017 case 0x5: 1018 switch (extmodel) { 1019 case 0x0: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 1020 ret = "Opteron or Athlon 64 FX"; 1021 break; 1022 case 0x1: /* rev SH-D0 */ 1023 case 0x2: /* rev SH-E4 */ 1024 ret = "Opteron"; 1025 break; 1026 } 1027 break; 1028 case 0x7: 1029 switch (extmodel) { 1030 case 0x0: /* rev SH-CG (ClawHammer) */ 1031 case 0x1: /* rev SH-D0 */ 1032 ret = "Athlon 64"; 1033 break; 1034 case 0x2: /* rev DH-E4, SH-E4 */ 1035 ret = "Athlon 64 or Athlon 64 FX or Opteron"; 1036 break; 1037 } 1038 break; 1039 case 0x8: 1040 switch (extmodel) { 1041 case 0x0: /* rev CH-CG */ 1042 case 0x1: /* rev CH-D0 */ 1043 ret = "Athlon 64 or Sempron"; 1044 break; 1045 case 0x4: /* rev BH-F2 */ 1046 ret = "Turion 64 X2"; 1047 break; 1048 } 1049 break; 1050 case 0xb: 1051 switch (extmodel) { 1052 case 0x0: /* rev CH-CG */ 1053 case 0x1: /* rev CH-D0 */ 1054 ret = "Athlon 64"; 1055 break; 1056 case 0x2: /* rev BH-E4 (Manchester) */ 1057 case 0x4: /* rev BH-F2 (Windsor) */ 1058 ret = "Athlon 64 X2"; 1059 break; 1060 case 0x6: /* rev BH-G1 (Brisbane) */ 1061 ret = "Athlon X2 or Athlon 64 X2"; 1062 break; 1063 } 1064 break; 1065 case 0xc: 1066 switch (extmodel) { 1067 case 0x0: /* rev DH-CG (Newcastle) */ 1068 case 0x1: /* rev DH-D0 (Winchester) */ 1069 case 0x2: /* rev DH-E3/E6 */ 1070 ret = "Athlon 64 or Sempron"; 1071 break; 1072 } 1073 break; 1074 case 0xe: 1075 switch (extmodel) { 1076 case 0x0: /* rev DH-CG (Newcastle?) */ 1077 ret = "Athlon 64 or Sempron"; 1078 break; 1079 } 1080 break; 1081 case 0xf: 1082 switch (extmodel) { 1083 case 0x0: /* rev DH-CG (Newcastle/Paris) */ 1084 case 0x1: /* rev DH-D0 (Winchester/Victoria) */ 1085 case 0x2: /* rev DH-E3/E6 (Venice/Palermo) */ 1086 case 0x4: /* rev DH-F2 (Orleans/Manila) */ 1087 case 0x5: /* rev DH-F2 (Orleans/Manila) */ 1088 case 0x6: /* rev DH-G1 */ 1089 ret = "Athlon 64 or Sempron"; 1090 break; 1091 } 1092 break; 1093 default: 1094 ret = "Unknown AMD64 CPU"; 1095 } 1096 } 1097 1098 return ret; 1099 } 1100 1101 static void 1102 cpu_probe_base_features(struct cpu_info *ci) 1103 { 1104 const struct x86_cache_info *cai; 1105 u_int descs[4]; 1106 int iterations, i, j; 1107 uint8_t desc; 1108 uint32_t miscbytes; 1109 uint32_t brand[12]; 1110 1111 if (ci->ci_cpuid_level < 0) 1112 return; 1113 1114 x86_cpuid(0, descs); 1115 ci->ci_cpuid_level = descs[0]; 1116 ci->ci_vendor[0] = descs[1]; 1117 ci->ci_vendor[2] = descs[2]; 1118 ci->ci_vendor[1] = descs[3]; 1119 ci->ci_vendor[3] = 0; 1120 1121 x86_cpuid(0x80000000, brand); 1122 if (brand[0] >= 0x80000004) { 1123 x86_cpuid(0x80000002, brand); 1124 x86_cpuid(0x80000003, brand + 4); 1125 x86_cpuid(0x80000004, brand + 8); 1126 for (i = 0; i < 48; i++) 1127 if (((char *) brand)[i] != ' ') 1128 break; 1129 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1130 } 1131 1132 if (ci->ci_cpuid_level < 1) 1133 return; 1134 1135 x86_cpuid(1, descs); 1136 ci->ci_signature = descs[0]; 1137 miscbytes = descs[1]; 1138 ci->ci_feature2_flags = descs[2]; 1139 ci->ci_feature_flags = descs[3]; 1140 1141 /* Brand is low order 8 bits of ebx */ 1142 ci->ci_brand_id = miscbytes & 0xff; 1143 ci->ci_initapicid = (miscbytes >> 24) & 0xff; 1144 if (ci->ci_cpuid_level < 2) 1145 return; 1146 1147 /* 1148 * Parse the cache info from `cpuid', if we have it. 1149 * XXX This is kinda ugly, but hey, so is the architecture... 1150 */ 1151 1152 x86_cpuid(2, descs); 1153 1154 iterations = descs[0] & 0xff; 1155 while (iterations-- > 0) { 1156 for (i = 0; i < 4; i++) { 1157 if (descs[i] & 0x80000000) 1158 continue; 1159 for (j = 0; j < 4; j++) { 1160 if (i == 0 && j == 0) 1161 continue; 1162 desc = (descs[i] >> (j * 8)) & 0xff; 1163 if (desc == 0) 1164 continue; 1165 cai = cache_info_lookup(intel_cpuid_cache_info, 1166 desc); 1167 if (cai != NULL) 1168 ci->ci_cinfo[cai->cai_index] = *cai; 1169 } 1170 } 1171 x86_cpuid(2, descs); 1172 } 1173 1174 if (ci->ci_cpuid_level < 3) 1175 return; 1176 1177 /* 1178 * If the processor serial number misfeature is present and supported, 1179 * extract it here. 1180 */ 1181 if ((ci->ci_feature_flags & CPUID_PN) != 0) { 1182 ci->ci_cpu_serial[0] = ci->ci_signature; 1183 x86_cpuid(3, descs); 1184 ci->ci_cpu_serial[2] = descs[2]; 1185 ci->ci_cpu_serial[1] = descs[3]; 1186 } 1187 } 1188 1189 static void 1190 cpu_probe_features(struct cpu_info *ci) 1191 { 1192 const struct cpu_cpuid_nameclass *cpup = NULL; 1193 int i, xmax, family; 1194 1195 cpu_probe_base_features(ci); 1196 1197 if (ci->ci_cpuid_level < 1) 1198 return; 1199 1200 xmax = __arraycount(i386_cpuid_cpus); 1201 for (i = 0; i < xmax; i++) { 1202 if (!strncmp((char *)ci->ci_vendor, 1203 i386_cpuid_cpus[i].cpu_id, 12)) { 1204 cpup = &i386_cpuid_cpus[i]; 1205 break; 1206 } 1207 } 1208 1209 if (cpup == NULL) 1210 return; 1211 1212 family = (ci->ci_signature >> 8) & 0xf; 1213 1214 if (family > CPU_MAXFAMILY) { 1215 family = CPU_MAXFAMILY; 1216 } 1217 i = family - CPU_MINFAMILY; 1218 1219 if (cpup->cpu_family[i].cpu_probe == NULL) 1220 return; 1221 1222 (*cpup->cpu_family[i].cpu_probe)(ci); 1223 } 1224 1225 static void 1226 intel_family_new_probe(struct cpu_info *ci) 1227 { 1228 uint32_t descs[4]; 1229 1230 x86_cpuid(0x80000000, descs); 1231 1232 /* 1233 * Determine extended feature flags. 1234 */ 1235 if (descs[0] >= 0x80000001) { 1236 x86_cpuid(0x80000001, descs); 1237 ci->ci_feature3_flags |= descs[3]; 1238 } 1239 } 1240 1241 static void 1242 amd_family6_probe(struct cpu_info *ci) 1243 { 1244 uint32_t descs[4]; 1245 char *p; 1246 int i; 1247 1248 x86_cpuid(0x80000000, descs); 1249 1250 /* 1251 * Determine the extended feature flags. 1252 */ 1253 if (descs[0] >= 0x80000001) { 1254 x86_cpuid(0x80000001, descs); 1255 ci->ci_feature_flags |= descs[3]; 1256 } 1257 1258 if (*cpu_brand_string == '\0') 1259 return; 1260 1261 for (i = 1; i < __arraycount(amd_brand); i++) 1262 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 1263 ci->ci_brand_id = i; 1264 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 1265 break; 1266 } 1267 } 1268 1269 static void 1270 amd_family5_setup(struct cpu_info *ci) 1271 { 1272 1273 switch (CPUID2MODEL(ci->ci_signature)) { 1274 case 0: /* AMD-K5 Model 0 */ 1275 /* 1276 * According to the AMD Processor Recognition App Note, 1277 * the AMD-K5 Model 0 uses the wrong bit to indicate 1278 * support for global PTEs, instead using bit 9 (APIC) 1279 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 1280 */ 1281 if (ci->ci_feature_flags & CPUID_APIC) 1282 ci->ci_feature_flags = (ci->ci_feature_flags & ~CPUID_APIC) | CPUID_PGE; 1283 /* 1284 * XXX But pmap_pg_g is already initialized -- need to kick 1285 * XXX the pmap somehow. How does the MP branch do this? 1286 */ 1287 break; 1288 } 1289 } 1290 1291 static void 1292 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1293 { 1294 u_int descs[4]; 1295 1296 x86_cpuid(0x80860007, descs); 1297 *frequency = descs[0]; 1298 *voltage = descs[1]; 1299 *percentage = descs[2]; 1300 } 1301 1302 static void 1303 transmeta_cpu_info(struct cpu_info *ci) 1304 { 1305 u_int descs[4], nreg; 1306 u_int frequency, voltage, percentage; 1307 1308 x86_cpuid(0x80860000, descs); 1309 nreg = descs[0]; 1310 if (nreg >= 0x80860001) { 1311 x86_cpuid(0x80860001, descs); 1312 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1313 (descs[1] >> 24) & 0xff, 1314 (descs[1] >> 16) & 0xff, 1315 (descs[1] >> 8) & 0xff, 1316 descs[1] & 0xff); 1317 } 1318 if (nreg >= 0x80860002) { 1319 x86_cpuid(0x80860002, descs); 1320 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1321 (descs[1] >> 24) & 0xff, 1322 (descs[1] >> 16) & 0xff, 1323 (descs[1] >> 8) & 0xff, 1324 descs[1] & 0xff, 1325 descs[2]); 1326 } 1327 if (nreg >= 0x80860006) { 1328 union { 1329 char text[65]; 1330 u_int descs[4][4]; 1331 } info; 1332 int i; 1333 1334 for (i=0; i<4; i++) { 1335 x86_cpuid(0x80860003 + i, info.descs[i]); 1336 } 1337 info.text[64] = '\0'; 1338 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1339 } 1340 1341 if (nreg >= 0x80860007) { 1342 tmx86_get_longrun_status(&frequency, 1343 &voltage, &percentage); 1344 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1345 frequency, voltage, percentage); 1346 } 1347 } 1348 1349 void 1350 identifycpu(const char *cpuname) 1351 { 1352 const char *name, *modifier, *vendorname, *brand = ""; 1353 int class = CPUCLASS_386, i, xmax; 1354 int modif, family, model; 1355 const struct cpu_cpuid_nameclass *cpup = NULL; 1356 const struct cpu_cpuid_family *cpufam; 1357 char *buf; 1358 const char *feature_str[3]; 1359 struct cpu_info *ci, cistore; 1360 extern int cpu; 1361 extern int cpu_info_level; 1362 size_t sz; 1363 1364 ci = &cistore; 1365 memset(ci, 0, sizeof(*ci)); 1366 ci->ci_dev = cpuname; 1367 1368 x86_identify(); 1369 ci->ci_cpuid_level = cpu_info_level; 1370 cpu_probe_features(ci); 1371 1372 buf = malloc(MAXPATHLEN); 1373 if (ci->ci_cpuid_level == -1) { 1374 if (cpu < 0 || cpu >= __arraycount(i386_nocpuid_cpus)) 1375 errx(1, "unknown cpu type %d", cpu); 1376 name = i386_nocpuid_cpus[cpu].cpu_name; 1377 cpu_vendor = i386_nocpuid_cpus[cpu].cpu_vendor; 1378 vendorname = i386_nocpuid_cpus[cpu].cpu_vendorname; 1379 class = i386_nocpuid_cpus[cpu].cpu_class; 1380 ci->ci_info = i386_nocpuid_cpus[cpu].cpu_info; 1381 modifier = ""; 1382 } else { 1383 xmax = __arraycount(i386_cpuid_cpus); 1384 modif = (ci->ci_signature >> 12) & 0x3; 1385 family = CPUID2FAMILY(ci->ci_signature); 1386 if (family < CPU_MINFAMILY) 1387 errx(1, "identifycpu: strange family value"); 1388 model = CPUID2MODEL(ci->ci_signature); 1389 1390 for (i = 0; i < xmax; i++) { 1391 if (!strncmp((char *)ci->ci_vendor, 1392 i386_cpuid_cpus[i].cpu_id, 12)) { 1393 cpup = &i386_cpuid_cpus[i]; 1394 break; 1395 } 1396 } 1397 1398 if (cpup == NULL) { 1399 cpu_vendor = CPUVENDOR_UNKNOWN; 1400 if (ci->ci_vendor[0] != '\0') 1401 vendorname = (char *)&ci->ci_vendor[0]; 1402 else 1403 vendorname = "Unknown"; 1404 if (family >= CPU_MAXFAMILY) 1405 family = CPU_MINFAMILY; 1406 class = family - 3; 1407 modifier = ""; 1408 name = ""; 1409 ci->ci_info = NULL; 1410 } else { 1411 cpu_vendor = cpup->cpu_vendor; 1412 vendorname = cpup->cpu_vendorname; 1413 modifier = modifiers[modif]; 1414 if (family > CPU_MAXFAMILY) { 1415 family = CPU_MAXFAMILY; 1416 model = CPU_DEFMODEL; 1417 } else if (model > CPU_MAXMODEL) 1418 model = CPU_DEFMODEL; 1419 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 1420 name = cpufam->cpu_models[model]; 1421 if (name == NULL) 1422 name = cpufam->cpu_models[CPU_DEFMODEL]; 1423 class = cpufam->cpu_class; 1424 ci->ci_info = cpufam->cpu_info; 1425 1426 if (cpu_vendor == CPUVENDOR_INTEL) { 1427 if (family == 6 && model >= 5) { 1428 const char *tmp; 1429 tmp = intel_family6_name(ci); 1430 if (tmp != NULL) 1431 name = tmp; 1432 } 1433 if (family == CPU_MAXFAMILY && 1434 ci->ci_brand_id < 1435 __arraycount(i386_intel_brand) && 1436 i386_intel_brand[ci->ci_brand_id]) 1437 name = 1438 i386_intel_brand[ci->ci_brand_id]; 1439 } 1440 1441 if (cpu_vendor == CPUVENDOR_AMD) { 1442 if (family == 6 && model >= 6) { 1443 if (ci->ci_brand_id == 1) 1444 /* 1445 * It's Duron. We override the 1446 * name, since it might have 1447 * been misidentified as Athlon. 1448 */ 1449 name = 1450 amd_brand[ci->ci_brand_id]; 1451 else 1452 brand = amd_brand_name; 1453 } 1454 if (CPUID2FAMILY(ci->ci_signature) == 0xf) { 1455 /* 1456 * Identify AMD64 CPU names. 1457 * Note family value is clipped by 1458 * CPU_MAXFAMILY. 1459 */ 1460 const char *tmp; 1461 tmp = amd_amd64_name(ci); 1462 if (tmp != NULL) 1463 name = tmp; 1464 } 1465 } 1466 1467 if (cpu_vendor == CPUVENDOR_IDT && family >= 6) 1468 vendorname = "VIA"; 1469 } 1470 } 1471 1472 ci->ci_cpu_class = class; 1473 1474 sz = sizeof(ci->ci_tsc_freq); 1475 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 1476 1477 snprintf(cpu_model, sizeof(cpu_model), "%s%s%s%s%s%s%s (%s-class)", 1478 vendorname, 1479 *modifier ? " " : "", modifier, 1480 *name ? " " : "", name, 1481 *brand ? " " : "", brand, 1482 classnames[class]); 1483 aprint_normal("%s: %s", cpuname, cpu_model); 1484 1485 if (ci->ci_tsc_freq != 0) 1486 aprint_normal(", %qd.%02qd MHz", 1487 (ci->ci_tsc_freq + 4999) / 1000000, 1488 ((ci->ci_tsc_freq + 4999) / 10000) % 100); 1489 if (ci->ci_signature != 0) 1490 aprint_normal(", id 0x%x", ci->ci_signature); 1491 aprint_normal("\n"); 1492 1493 if (ci->ci_info) 1494 (*ci->ci_info)(ci); 1495 1496 if (cpu_vendor == CPUVENDOR_INTEL) { 1497 feature_str[0] = CPUID_FLAGS1; 1498 feature_str[1] = CPUID_FLAGS2; 1499 feature_str[2] = CPUID_FLAGS3; 1500 } else { 1501 feature_str[0] = CPUID_FLAGS1; 1502 feature_str[1] = CPUID_EXT_FLAGS2; 1503 feature_str[2] = CPUID_EXT_FLAGS3; 1504 } 1505 1506 if (ci->ci_feature_flags) { 1507 if ((ci->ci_feature_flags & CPUID_MASK1) != 0) { 1508 bitmask_snprintf(ci->ci_feature_flags, 1509 feature_str[0], buf, MAXPATHLEN); 1510 aprint_verbose("%s: features %s\n", cpuname, buf); 1511 } 1512 if ((ci->ci_feature_flags & CPUID_MASK2) != 0) { 1513 bitmask_snprintf(ci->ci_feature_flags, 1514 feature_str[1], buf, MAXPATHLEN); 1515 aprint_verbose("%s: features %s\n", cpuname, buf); 1516 } 1517 if ((ci->ci_feature_flags & CPUID_MASK3) != 0) { 1518 bitmask_snprintf(ci->ci_feature_flags, 1519 feature_str[2], buf, MAXPATHLEN); 1520 aprint_verbose("%s: features %s\n", cpuname, buf); 1521 } 1522 } 1523 1524 if (ci->ci_feature2_flags) { 1525 bitmask_snprintf(ci->ci_feature2_flags, 1526 CPUID2_FLAGS, buf, MAXPATHLEN); 1527 aprint_verbose("%s: features2 %s\n", cpuname, buf); 1528 } 1529 1530 if (ci->ci_feature3_flags) { 1531 bitmask_snprintf(ci->ci_feature3_flags, 1532 CPUID_FLAGS4, buf, MAXPATHLEN); 1533 aprint_verbose("%s: features3 %s\n", cpuname, buf); 1534 } 1535 1536 if (ci->ci_padlock_flags) { 1537 bitmask_snprintf(ci->ci_padlock_flags, 1538 CPUID_FLAGS_PADLOCK, buf, MAXPATHLEN); 1539 aprint_verbose("%s: padlock features %s\n", cpuname, buf); 1540 } 1541 1542 free(buf); 1543 1544 if (*cpu_brand_string != '\0') 1545 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 1546 1547 x86_print_cacheinfo(ci); 1548 1549 if (ci->ci_cpuid_level >= 3 && (ci->ci_feature_flags & CPUID_PN)) { 1550 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 1551 cpuname, 1552 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 1553 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 1554 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 1555 } 1556 1557 if (ci->ci_cpu_class == CPUCLASS_386) { 1558 errx(1, "NetBSD requires an 80486 or later processor"); 1559 } 1560 1561 if (cpu == CPU_486DLC) { 1562 #ifndef CYRIX_CACHE_WORKS 1563 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 1564 #else 1565 #ifndef CYRIX_CACHE_REALLY_WORKS 1566 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 1567 #else 1568 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 1569 #endif 1570 #endif 1571 } 1572 1573 /* 1574 * Everything past this point requires a Pentium or later. 1575 */ 1576 if (ci->ci_cpuid_level < 0) 1577 return; 1578 1579 identifycpu_cpuids(ci); 1580 1581 #ifdef INTEL_CORETEMP 1582 if (cpu_vendor == CPUVENDOR_INTEL && ci->ci_cpuid_level >= 0x06) 1583 coretemp_register(ci); 1584 #endif 1585 1586 #if defined(POWERNOW_K7) || defined(POWERNOW_K8) 1587 if (cpu_vendor == CPUVENDOR_AMD && powernow_probe(ci)) { 1588 switch (CPUID2FAMILY(ci->ci_signature)) { 1589 #ifdef POWERNOW_K7 1590 case 6: 1591 k7_powernow_init(); 1592 break; 1593 #endif 1594 #ifdef POWERNOW_K8 1595 case 15: 1596 k8_powernow_init(); 1597 break; 1598 #endif 1599 default: 1600 break; 1601 } 1602 } 1603 #endif /* POWERNOW_K7 || POWERNOW_K8 */ 1604 1605 #ifdef INTEL_ONDEMAND_CLOCKMOD 1606 clockmod_init(); 1607 #endif 1608 1609 aprint_normal_dev(ci->ci_dev, "family %02x model %02x " 1610 "extfamily %02x extmodel %02x\n", CPUID2FAMILY(ci->ci_signature), 1611 CPUID2MODEL(ci->ci_signature), CPUID2EXTFAMILY(ci->ci_signature), 1612 CPUID2EXTMODEL(ci->ci_signature)); 1613 } 1614 1615 static const char * 1616 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 1617 const char *sep) 1618 { 1619 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1620 1621 if (cai->cai_totalsize == 0) 1622 return sep; 1623 1624 if (sep == NULL) 1625 aprint_verbose_dev(ci->ci_dev, ""); 1626 else 1627 aprint_verbose("%s", sep); 1628 if (name != NULL) 1629 aprint_verbose("%s ", name); 1630 1631 if (cai->cai_string != NULL) { 1632 aprint_verbose("%s ", cai->cai_string); 1633 } else { 1634 aprint_verbose("%dkB %dB/line ", cai->cai_totalsize / 1024, 1635 cai->cai_linesize); 1636 } 1637 switch (cai->cai_associativity) { 1638 case 0: 1639 aprint_verbose("disabled"); 1640 break; 1641 case 1: 1642 aprint_verbose("direct-mapped"); 1643 break; 1644 case 0xff: 1645 aprint_verbose("fully associative"); 1646 break; 1647 default: 1648 aprint_verbose("%d-way", cai->cai_associativity); 1649 break; 1650 } 1651 return ", "; 1652 } 1653 1654 static const char * 1655 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 1656 const char *sep) 1657 { 1658 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1659 1660 if (cai->cai_totalsize == 0) 1661 return sep; 1662 1663 if (sep == NULL) 1664 aprint_verbose_dev(ci->ci_dev, ""); 1665 else 1666 aprint_verbose("%s", sep); 1667 if (name != NULL) 1668 aprint_verbose("%s ", name); 1669 1670 if (cai->cai_string != NULL) { 1671 aprint_verbose("%s", cai->cai_string); 1672 } else { 1673 aprint_verbose("%d %dB entries ", cai->cai_totalsize, 1674 cai->cai_linesize); 1675 switch (cai->cai_associativity) { 1676 case 0: 1677 aprint_verbose("disabled"); 1678 break; 1679 case 1: 1680 aprint_verbose("direct-mapped"); 1681 break; 1682 case 0xff: 1683 aprint_verbose("fully associative"); 1684 break; 1685 default: 1686 aprint_verbose("%d-way", cai->cai_associativity); 1687 break; 1688 } 1689 } 1690 return ", "; 1691 } 1692 1693 static const struct x86_cache_info * 1694 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 1695 { 1696 int i; 1697 1698 for (i = 0; cai[i].cai_desc != 0; i++) { 1699 if (cai[i].cai_desc == desc) 1700 return (&cai[i]); 1701 } 1702 1703 return (NULL); 1704 } 1705 1706 1707 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = { 1708 { 0, 0x01, 1, 0, 0, NULL }, 1709 { 0, 0x02, 2, 0, 0, NULL }, 1710 { 0, 0x04, 4, 0, 0, NULL }, 1711 { 0, 0x06, 8, 0, 0, NULL }, 1712 { 0, 0x08, 16, 0, 0, NULL }, 1713 { 0, 0x0f, 0xff, 0, 0, NULL }, 1714 { 0, 0x00, 0, 0, 0, NULL }, 1715 }; 1716 1717 static void 1718 amd_cpu_cacheinfo(struct cpu_info *ci) 1719 { 1720 const struct x86_cache_info *cp; 1721 struct x86_cache_info *cai; 1722 int family, model; 1723 u_int descs[4]; 1724 u_int lfunc; 1725 1726 family = (ci->ci_signature >> 8) & 15; 1727 model = CPUID2MODEL(ci->ci_signature); 1728 1729 /* 1730 * K5 model 0 has none of this info. 1731 */ 1732 if (family == 5 && model == 0) 1733 return; 1734 1735 /* 1736 * Get extended values for K8 and up. 1737 */ 1738 if (family == 0xf) { 1739 family += CPUID2EXTFAMILY(ci->ci_signature); 1740 model += CPUID2EXTMODEL(ci->ci_signature); 1741 } 1742 1743 /* 1744 * Determine the largest extended function value. 1745 */ 1746 x86_cpuid(0x80000000, descs); 1747 lfunc = descs[0]; 1748 1749 /* 1750 * Determine L1 cache/TLB info. 1751 */ 1752 if (lfunc < 0x80000005) { 1753 /* No L1 cache info available. */ 1754 return; 1755 } 1756 1757 x86_cpuid(0x80000005, descs); 1758 1759 /* 1760 * K6-III and higher have large page TLBs. 1761 */ 1762 if ((family == 5 && model >= 9) || family >= 6) { 1763 cai = &ci->ci_cinfo[CAI_ITLB2]; 1764 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1765 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1766 cai->cai_linesize = (4 * 1024 * 1024); 1767 1768 cai = &ci->ci_cinfo[CAI_DTLB2]; 1769 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1770 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1771 cai->cai_linesize = (4 * 1024 * 1024); 1772 } 1773 1774 cai = &ci->ci_cinfo[CAI_ITLB]; 1775 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1776 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1777 cai->cai_linesize = (4 * 1024); 1778 1779 cai = &ci->ci_cinfo[CAI_DTLB]; 1780 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1781 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1782 cai->cai_linesize = (4 * 1024); 1783 1784 cai = &ci->ci_cinfo[CAI_DCACHE]; 1785 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1786 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1787 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[2]); 1788 1789 cai = &ci->ci_cinfo[CAI_ICACHE]; 1790 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1791 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1792 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1793 1794 /* 1795 * Determine L2 cache/TLB info. 1796 */ 1797 if (lfunc < 0x80000006) { 1798 /* No L2 cache info available. */ 1799 return; 1800 } 1801 1802 x86_cpuid(0x80000006, descs); 1803 1804 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1805 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1806 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1807 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1808 1809 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1810 cai->cai_associativity); 1811 if (cp != NULL) 1812 cai->cai_associativity = cp->cai_associativity; 1813 else 1814 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1815 } 1816 1817 static void 1818 via_cpu_cacheinfo(struct cpu_info *ci) 1819 { 1820 struct x86_cache_info *cai; 1821 int family, model, stepping; 1822 u_int descs[4]; 1823 u_int lfunc; 1824 1825 family = (ci->ci_signature >> 8) & 15; 1826 model = CPUID2MODEL(ci->ci_signature); 1827 stepping = CPUID2STEPPING(ci->ci_signature); 1828 1829 /* 1830 * Determine the largest extended function value. 1831 */ 1832 x86_cpuid(0x80000000, descs); 1833 lfunc = descs[0]; 1834 1835 /* 1836 * Determine L1 cache/TLB info. 1837 */ 1838 if (lfunc < 0x80000005) { 1839 /* No L1 cache info available. */ 1840 return; 1841 } 1842 1843 x86_cpuid(0x80000005, descs); 1844 1845 cai = &ci->ci_cinfo[CAI_ITLB]; 1846 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1847 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1848 cai->cai_linesize = (4 * 1024); 1849 1850 cai = &ci->ci_cinfo[CAI_DTLB]; 1851 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1852 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1853 cai->cai_linesize = (4 * 1024); 1854 1855 cai = &ci->ci_cinfo[CAI_DCACHE]; 1856 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1857 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1858 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1859 if (model == 9 && stepping == 8) { 1860 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1861 cai->cai_associativity = 2; 1862 } 1863 1864 cai = &ci->ci_cinfo[CAI_ICACHE]; 1865 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1866 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1867 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1868 if (model == 9 && stepping == 8) { 1869 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1870 cai->cai_associativity = 2; 1871 } 1872 1873 /* 1874 * Determine L2 cache/TLB info. 1875 */ 1876 if (lfunc < 0x80000006) { 1877 /* No L2 cache info available. */ 1878 return; 1879 } 1880 1881 x86_cpuid(0x80000006, descs); 1882 1883 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1884 if (model >= 9) { 1885 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1886 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1887 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1888 } else { 1889 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1890 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1891 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1892 } 1893 } 1894 1895 static void 1896 x86_print_cacheinfo(struct cpu_info *ci) 1897 { 1898 const char *sep; 1899 1900 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 1901 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 1902 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 1903 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 1904 if (sep != NULL) 1905 aprint_verbose("\n"); 1906 } 1907 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 1908 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 1909 if (sep != NULL) 1910 aprint_verbose("\n"); 1911 } 1912 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 1913 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 1914 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 1915 if (sep != NULL) 1916 aprint_verbose("\n"); 1917 } 1918 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 1919 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 1920 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 1921 if (sep != NULL) 1922 aprint_verbose("\n"); 1923 } 1924 } 1925
Indexes created Wed Sep 24 05:09:52 GMT 2025