i386.c revision 1.34
1 /* $NetBSD: i386.c,v 1.34 2013/01/05 15:27:45 dsl Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.34 2013/01/05 15:27:45 dsl Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <string.h> 71 #include <stdio.h> 72 #include <stdlib.h> 73 #include <err.h> 74 #include <assert.h> 75 #include <math.h> 76 #include <util.h> 77 78 #include <machine/specialreg.h> 79 #include <machine/cpu.h> 80 81 #include <x86/cpuvar.h> 82 #include <x86/cputypes.h> 83 #include <x86/cacheinfo.h> 84 #include <x86/cpu_ucode.h> 85 86 #include "../cpuctl.h" 87 #include "cpuctl_i386.h" 88 89 /* Size of buffer for printing humanized numbers */ 90 #define HUMAN_BUFSIZE sizeof("999KB") 91 92 struct cpu_info { 93 const char *ci_dev; 94 int32_t ci_cpu_type; /* for cpu's without cpuid */ 95 int32_t ci_cpuid_level; /* highest cpuid supported */ 96 uint32_t ci_signature; /* X86 cpuid type */ 97 uint32_t ci_feat_val[5]; /* X86 CPUID feature bits 98 * [0] basic features %edx 99 * [1] basic features %ecx 100 * [2] extended features %edx 101 * [3] extended features %ecx 102 * [4] VIA padlock features 103 */ 104 uint32_t ci_cpu_class; /* CPU class */ 105 uint32_t ci_brand_id; /* Intel brand id */ 106 uint32_t ci_vendor[4]; /* vendor string */ 107 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 108 uint64_t ci_tsc_freq; /* cpu cycles/second */ 109 uint8_t ci_packageid; 110 uint8_t ci_coreid; 111 uint8_t ci_smtid; 112 uint32_t ci_initapicid; 113 struct x86_cache_info ci_cinfo[CAI_COUNT]; 114 void (*ci_info)(struct cpu_info *); 115 }; 116 117 struct cpu_nocpuid_nameclass { 118 int cpu_vendor; 119 const char *cpu_vendorname; 120 const char *cpu_name; 121 int cpu_class; 122 void (*cpu_setup)(struct cpu_info *); 123 void (*cpu_cacheinfo)(struct cpu_info *); 124 void (*cpu_info)(struct cpu_info *); 125 }; 126 127 struct cpu_extend_nameclass { 128 int ext_model; 129 const char *cpu_models[CPU_MAXMODEL+1]; 130 }; 131 132 struct cpu_cpuid_nameclass { 133 const char *cpu_id; 134 int cpu_vendor; 135 const char *cpu_vendorname; 136 struct cpu_cpuid_family { 137 int cpu_class; 138 const char *cpu_models[CPU_MAXMODEL+2]; 139 void (*cpu_setup)(struct cpu_info *); 140 void (*cpu_probe)(struct cpu_info *); 141 void (*cpu_info)(struct cpu_info *); 142 struct cpu_extend_nameclass *cpu_extended_names; 143 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 144 }; 145 146 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 147 148 /* 149 * Map Brand ID from cpuid instruction to brand name. 150 * Source: Intel Processor Identification and the CPUID Instruction, AP-485 151 */ 152 static const char * const i386_intel_brand[] = { 153 "", /* Unsupported */ 154 "Celeron", /* Intel (R) Celeron (TM) processor */ 155 "Pentium III", /* Intel (R) Pentium (R) III processor */ 156 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 157 "Pentium III", /* Intel (R) Pentium (R) III processor */ 158 "", /* Reserved */ 159 "Mobile Pentium III", /* Mobile Intel (R) Pentium (R) III processor-M */ 160 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 161 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 162 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 163 "Celeron", /* Intel (R) Celeron (TM) processor */ 164 "Xeon", /* Intel (R) Xeon (TM) processor */ 165 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 166 "", /* Reserved */ 167 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 168 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 169 }; 170 171 /* 172 * AMD processors don't have Brand IDs, so we need these names for probe. 173 */ 174 static const char * const amd_brand[] = { 175 "", 176 "Duron", /* AMD Duron(tm) */ 177 "MP", /* AMD Athlon(tm) MP */ 178 "XP", /* AMD Athlon(tm) XP */ 179 "4" /* AMD Athlon(tm) 4 */ 180 }; 181 182 static int cpu_vendor; 183 static char cpu_brand_string[49]; 184 static char amd_brand_name[48]; 185 static int use_pae, largepagesize; 186 187 static void via_cpu_probe(struct cpu_info *); 188 static void amd_family6_probe(struct cpu_info *); 189 static void intel_family_new_probe(struct cpu_info *); 190 static const char *intel_family6_name(struct cpu_info *); 191 static const char *amd_amd64_name(struct cpu_info *); 192 static void amd_family5_setup(struct cpu_info *); 193 static void transmeta_cpu_info(struct cpu_info *); 194 static const char *print_cache_config(struct cpu_info *, int, const char *, 195 const char *); 196 static const char *print_tlb_config(struct cpu_info *, int, const char *, 197 const char *); 198 static void amd_cpu_cacheinfo(struct cpu_info *); 199 static void via_cpu_cacheinfo(struct cpu_info *); 200 static void x86_print_cacheinfo(struct cpu_info *); 201 static const struct x86_cache_info *cache_info_lookup( 202 const struct x86_cache_info *, uint8_t); 203 static void cyrix6x86_cpu_setup(struct cpu_info *); 204 static void winchip_cpu_setup(struct cpu_info *); 205 static void amd_family5_setup(struct cpu_info *); 206 static void powernow_probe(struct cpu_info *); 207 208 /* 209 * Info for CTL_HW 210 */ 211 static char cpu_model[120]; 212 213 /* 214 * Note: these are just the ones that may not have a cpuid instruction. 215 * We deal with the rest in a different way. 216 */ 217 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 218 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 219 NULL, NULL, NULL }, /* CPU_386SX */ 220 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 221 NULL, NULL, NULL }, /* CPU_386 */ 222 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 223 NULL, NULL, NULL }, /* CPU_486SX */ 224 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 225 NULL, NULL, NULL }, /* CPU_486 */ 226 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 227 NULL, NULL, NULL }, /* CPU_486DLC */ 228 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 229 NULL, NULL, NULL }, /* CPU_6x86 */ 230 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 231 NULL, NULL, NULL }, /* CPU_NX586 */ 232 }; 233 234 const char *classnames[] = { 235 "386", 236 "486", 237 "586", 238 "686" 239 }; 240 241 const char *modifiers[] = { 242 "", 243 "OverDrive", 244 "Dual", 245 "" 246 }; 247 248 struct cpu_extend_nameclass intel_family6_ext_models[] = { 249 { /* Extended models 1x */ 250 0x01, { NULL, NULL, 251 NULL, NULL, 252 NULL, "EP80579 Integrated Processor", 253 "Celeron (45nm)", "Core 2 Extreme", 254 NULL, NULL, 255 "Core i7 (Nehalem)", NULL, 256 "Atom", "XeonMP (Nehalem)", 257 NULL, NULL} }, 258 { /* End of list */ 259 0x00, { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 260 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL} } 261 }; 262 263 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 264 { 265 "GenuineIntel", 266 CPUVENDOR_INTEL, 267 "Intel", 268 /* Family 4 */ 269 { { 270 CPUCLASS_486, 271 { 272 "486DX", "486DX", "486SX", "486DX2", "486SL", 273 "486SX2", 0, "486DX2 W/B Enhanced", 274 "486DX4", 0, 0, 0, 0, 0, 0, 0, 275 "486" /* Default */ 276 }, 277 NULL, 278 NULL, 279 NULL, 280 NULL, 281 }, 282 /* Family 5 */ 283 { 284 CPUCLASS_586, 285 { 286 "Pentium (P5 A-step)", "Pentium (P5)", 287 "Pentium (P54C)", "Pentium (P24T)", 288 "Pentium/MMX", "Pentium", 0, 289 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 290 0, 0, 0, 0, 0, 0, 0, 291 "Pentium" /* Default */ 292 }, 293 NULL, 294 NULL, 295 NULL, 296 NULL, 297 }, 298 /* Family 6 */ 299 { 300 CPUCLASS_686, 301 { 302 "Pentium Pro (A-step)", "Pentium Pro", 0, 303 "Pentium II (Klamath)", "Pentium Pro", 304 "Pentium II/Celeron (Deschutes)", 305 "Celeron (Mendocino)", 306 "Pentium III (Katmai)", 307 "Pentium III (Coppermine)", 308 "Pentium M (Banias)", 309 "Pentium III Xeon (Cascades)", 310 "Pentium III (Tualatin)", 0, 311 "Pentium M (Dothan)", 312 "Pentium M (Yonah)", 313 "Core 2", 314 "Pentium Pro, II or III" /* Default */ 315 }, 316 NULL, 317 intel_family_new_probe, 318 NULL, 319 &intel_family6_ext_models[0], 320 }, 321 /* Family > 6 */ 322 { 323 CPUCLASS_686, 324 { 325 0, 0, 0, 0, 0, 0, 0, 0, 326 0, 0, 0, 0, 0, 0, 0, 0, 327 "Pentium 4" /* Default */ 328 }, 329 NULL, 330 intel_family_new_probe, 331 NULL, 332 NULL, 333 } } 334 }, 335 { 336 "AuthenticAMD", 337 CPUVENDOR_AMD, 338 "AMD", 339 /* Family 4 */ 340 { { 341 CPUCLASS_486, 342 { 343 0, 0, 0, "Am486DX2 W/T", 344 0, 0, 0, "Am486DX2 W/B", 345 "Am486DX4 W/T or Am5x86 W/T 150", 346 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 347 0, 0, "Am5x86 W/T 133/160", 348 "Am5x86 W/B 133/160", 349 "Am486 or Am5x86" /* Default */ 350 }, 351 NULL, 352 NULL, 353 NULL, 354 NULL, 355 }, 356 /* Family 5 */ 357 { 358 CPUCLASS_586, 359 { 360 "K5", "K5", "K5", "K5", 0, 0, "K6", 361 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 362 "K6-2+/III+", 0, 0, 363 "K5 or K6" /* Default */ 364 }, 365 amd_family5_setup, 366 NULL, 367 amd_cpu_cacheinfo, 368 NULL, 369 }, 370 /* Family 6 */ 371 { 372 CPUCLASS_686, 373 { 374 0, "Athlon Model 1", "Athlon Model 2", 375 "Duron", "Athlon Model 4 (Thunderbird)", 376 0, "Athlon", "Duron", "Athlon", 0, 377 "Athlon", 0, 0, 0, 0, 0, 378 "K7 (Athlon)" /* Default */ 379 }, 380 NULL, 381 amd_family6_probe, 382 amd_cpu_cacheinfo, 383 NULL, 384 }, 385 /* Family > 6 */ 386 { 387 CPUCLASS_686, 388 { 389 0, 0, 0, 0, 0, 0, 0, 0, 390 0, 0, 0, 0, 0, 0, 0, 0, 391 "Unknown K8 (Athlon)" /* Default */ 392 }, 393 NULL, 394 amd_family6_probe, 395 amd_cpu_cacheinfo, 396 NULL, 397 } } 398 }, 399 { 400 "CyrixInstead", 401 CPUVENDOR_CYRIX, 402 "Cyrix", 403 /* Family 4 */ 404 { { 405 CPUCLASS_486, 406 { 407 0, 0, 0, 408 "MediaGX", 409 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 410 "486" /* Default */ 411 }, 412 cyrix6x86_cpu_setup, /* XXX ?? */ 413 NULL, 414 NULL, 415 NULL, 416 }, 417 /* Family 5 */ 418 { 419 CPUCLASS_586, 420 { 421 0, 0, "6x86", 0, 422 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 423 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 424 "6x86" /* Default */ 425 }, 426 cyrix6x86_cpu_setup, 427 NULL, 428 NULL, 429 NULL, 430 }, 431 /* Family 6 */ 432 { 433 CPUCLASS_686, 434 { 435 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 436 0, 0, 0, 0, 0, 0, 0, 0, 437 "6x86MX" /* Default */ 438 }, 439 cyrix6x86_cpu_setup, 440 NULL, 441 NULL, 442 NULL, 443 }, 444 /* Family > 6 */ 445 { 446 CPUCLASS_686, 447 { 448 0, 0, 0, 0, 0, 0, 0, 0, 449 0, 0, 0, 0, 0, 0, 0, 0, 450 "Unknown 6x86MX" /* Default */ 451 }, 452 NULL, 453 NULL, 454 NULL, 455 NULL, 456 } } 457 }, 458 { /* MediaGX is now owned by National Semiconductor */ 459 "Geode by NSC", 460 CPUVENDOR_CYRIX, /* XXX */ 461 "National Semiconductor", 462 /* Family 4, NSC never had any of these */ 463 { { 464 CPUCLASS_486, 465 { 466 0, 0, 0, 0, 0, 0, 0, 0, 467 0, 0, 0, 0, 0, 0, 0, 0, 468 "486 compatible" /* Default */ 469 }, 470 NULL, 471 NULL, 472 NULL, 473 NULL, 474 }, 475 /* Family 5: Geode family, formerly MediaGX */ 476 { 477 CPUCLASS_586, 478 { 479 0, 0, 0, 0, 480 "Geode GX1", 481 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 482 "Geode" /* Default */ 483 }, 484 cyrix6x86_cpu_setup, 485 NULL, 486 amd_cpu_cacheinfo, 487 NULL, 488 }, 489 /* Family 6, not yet available from NSC */ 490 { 491 CPUCLASS_686, 492 { 493 0, 0, 0, 0, 0, 0, 0, 0, 494 0, 0, 0, 0, 0, 0, 0, 0, 495 "Pentium Pro compatible" /* Default */ 496 }, 497 NULL, 498 NULL, 499 NULL, 500 NULL, 501 }, 502 /* Family > 6, not yet available from NSC */ 503 { 504 CPUCLASS_686, 505 { 506 0, 0, 0, 0, 0, 0, 0, 0, 507 0, 0, 0, 0, 0, 0, 0, 0, 508 "Pentium Pro compatible" /* Default */ 509 }, 510 NULL, 511 NULL, 512 NULL, 513 NULL, 514 } } 515 }, 516 { 517 "CentaurHauls", 518 CPUVENDOR_IDT, 519 "IDT", 520 /* Family 4, IDT never had any of these */ 521 { { 522 CPUCLASS_486, 523 { 524 0, 0, 0, 0, 0, 0, 0, 0, 525 0, 0, 0, 0, 0, 0, 0, 0, 526 "486 compatible" /* Default */ 527 }, 528 NULL, 529 NULL, 530 NULL, 531 NULL, 532 }, 533 /* Family 5 */ 534 { 535 CPUCLASS_586, 536 { 537 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 538 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 539 "WinChip" /* Default */ 540 }, 541 winchip_cpu_setup, 542 NULL, 543 NULL, 544 NULL, 545 }, 546 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 547 { 548 CPUCLASS_686, 549 { 550 0, 0, 0, 0, 0, 0, "C3 Samuel", 551 "C3 Samuel 2/Ezra", "C3 Ezra-T", 552 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 553 0, "VIA Nano", 554 "Unknown VIA/IDT" /* Default */ 555 }, 556 NULL, 557 via_cpu_probe, 558 via_cpu_cacheinfo, 559 NULL, 560 }, 561 /* Family > 6, not yet available from VIA */ 562 { 563 CPUCLASS_686, 564 { 565 0, 0, 0, 0, 0, 0, 0, 0, 566 0, 0, 0, 0, 0, 0, 0, 0, 567 "Pentium Pro compatible" /* Default */ 568 }, 569 NULL, 570 NULL, 571 NULL, 572 NULL, 573 } } 574 }, 575 { 576 "GenuineTMx86", 577 CPUVENDOR_TRANSMETA, 578 "Transmeta", 579 /* Family 4, Transmeta never had any of these */ 580 { { 581 CPUCLASS_486, 582 { 583 0, 0, 0, 0, 0, 0, 0, 0, 584 0, 0, 0, 0, 0, 0, 0, 0, 585 "486 compatible" /* Default */ 586 }, 587 NULL, 588 NULL, 589 NULL, 590 NULL, 591 }, 592 /* Family 5 */ 593 { 594 CPUCLASS_586, 595 { 596 0, 0, 0, 0, 0, 0, 0, 0, 597 0, 0, 0, 0, 0, 0, 0, 0, 598 "Crusoe" /* Default */ 599 }, 600 NULL, 601 NULL, 602 transmeta_cpu_info, 603 NULL, 604 }, 605 /* Family 6, not yet available from Transmeta */ 606 { 607 CPUCLASS_686, 608 { 609 0, 0, 0, 0, 0, 0, 0, 0, 610 0, 0, 0, 0, 0, 0, 0, 0, 611 "Pentium Pro compatible" /* Default */ 612 }, 613 NULL, 614 NULL, 615 NULL, 616 NULL, 617 }, 618 /* Family > 6, not yet available from Transmeta */ 619 { 620 CPUCLASS_686, 621 { 622 0, 0, 0, 0, 0, 0, 0, 0, 623 0, 0, 0, 0, 0, 0, 0, 0, 624 "Pentium Pro compatible" /* Default */ 625 }, 626 NULL, 627 NULL, 628 NULL, 629 NULL, 630 } } 631 } 632 }; 633 634 /* 635 * disable the TSC such that we don't use the TSC in microtime(9) 636 * because some CPUs got the implementation wrong. 637 */ 638 static void 639 disable_tsc(struct cpu_info *ci) 640 { 641 if (ci->ci_feat_val[0] & CPUID_TSC) { 642 ci->ci_feat_val[0] &= ~CPUID_TSC; 643 aprint_error("WARNING: broken TSC disabled\n"); 644 } 645 } 646 647 static void 648 cyrix6x86_cpu_setup(struct cpu_info *ci) 649 { 650 651 /* 652 * Do not disable the TSC on the Geode GX, it's reported to 653 * work fine. 654 */ 655 if (ci->ci_signature != 0x552) 656 disable_tsc(ci); 657 } 658 659 void 660 winchip_cpu_setup(struct cpu_info *ci) 661 { 662 switch (CPUID2MODEL(ci->ci_signature)) { /* model */ 663 case 4: /* WinChip C6 */ 664 disable_tsc(ci); 665 } 666 } 667 668 669 static void 670 identifycpu_cpuids(struct cpu_info *ci) 671 { 672 const char *cpuname = ci->ci_dev; 673 u_int lp_max = 1; /* logical processors per package */ 674 u_int smt_max; /* smt per core */ 675 u_int core_max = 1; /* core per package */ 676 u_int smt_bits, core_bits; 677 uint32_t descs[4]; 678 679 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 680 ci->ci_packageid = ci->ci_initapicid; 681 ci->ci_coreid = 0; 682 ci->ci_smtid = 0; 683 if (cpu_vendor != CPUVENDOR_INTEL) { 684 return; 685 } 686 687 /* 688 * 253668.pdf 7.10.2 689 */ 690 691 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 692 x86_cpuid(1, descs); 693 lp_max = (descs[1] >> 16) & 0xff; 694 } 695 x86_cpuid(0, descs); 696 if (descs[0] >= 4) { 697 x86_cpuid2(4, 0, descs); 698 core_max = (descs[0] >> 26) + 1; 699 } 700 assert(lp_max >= core_max); 701 smt_max = lp_max / core_max; 702 smt_bits = ilog2(smt_max - 1) + 1; 703 core_bits = ilog2(core_max - 1) + 1; 704 if (smt_bits + core_bits) { 705 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 706 } 707 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 708 ci->ci_packageid); 709 if (core_bits) { 710 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 711 712 ci->ci_coreid = 713 __SHIFTOUT(ci->ci_initapicid, core_mask); 714 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 715 } 716 if (smt_bits) { 717 u_int smt_mask = __BITS((int)0, (int)(smt_bits - 1)); 718 719 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, smt_mask); 720 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 721 } 722 } 723 724 static void 725 via_cpu_probe(struct cpu_info *ci) 726 { 727 u_int model = CPUID2MODEL(ci->ci_signature); 728 u_int stepping = CPUID2STEPPING(ci->ci_signature); 729 u_int descs[4]; 730 u_int lfunc; 731 732 /* 733 * Determine the largest extended function value. 734 */ 735 x86_cpuid(0x80000000, descs); 736 lfunc = descs[0]; 737 738 /* 739 * Determine the extended feature flags. 740 */ 741 if (lfunc >= 0x80000001) { 742 x86_cpuid(0x80000001, descs); 743 ci->ci_feat_val[2] |= descs[3]; 744 } 745 746 if (model < 0x9 || (model == 0x9 && stepping < 3)) 747 return; 748 749 /* Nehemiah or Esther */ 750 x86_cpuid(0xc0000000, descs); 751 lfunc = descs[0]; 752 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 753 return; 754 755 x86_cpuid(0xc0000001, descs); 756 lfunc = descs[3]; 757 ci->ci_feat_val[4] = lfunc; 758 } 759 760 static const char * 761 intel_family6_name(struct cpu_info *ci) 762 { 763 int model = CPUID2MODEL(ci->ci_signature); 764 const char *ret = NULL; 765 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 766 767 if (model == 5) { 768 switch (l2cache) { 769 case 0: 770 case 128 * 1024: 771 ret = "Celeron (Covington)"; 772 break; 773 case 256 * 1024: 774 ret = "Mobile Pentium II (Dixon)"; 775 break; 776 case 512 * 1024: 777 ret = "Pentium II"; 778 break; 779 case 1 * 1024 * 1024: 780 case 2 * 1024 * 1024: 781 ret = "Pentium II Xeon"; 782 break; 783 } 784 } else if (model == 6) { 785 switch (l2cache) { 786 case 256 * 1024: 787 case 512 * 1024: 788 ret = "Mobile Pentium II"; 789 break; 790 } 791 } else if (model == 7) { 792 switch (l2cache) { 793 case 512 * 1024: 794 ret = "Pentium III"; 795 break; 796 case 1 * 1024 * 1024: 797 case 2 * 1024 * 1024: 798 ret = "Pentium III Xeon"; 799 break; 800 } 801 } else if (model >= 8) { 802 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 803 switch (ci->ci_brand_id) { 804 case 0x3: 805 if (ci->ci_signature == 0x6B1) 806 ret = "Celeron"; 807 break; 808 case 0x8: 809 if (ci->ci_signature >= 0xF13) 810 ret = "genuine processor"; 811 break; 812 case 0xB: 813 if (ci->ci_signature >= 0xF13) 814 ret = "Xeon MP"; 815 break; 816 case 0xE: 817 if (ci->ci_signature < 0xF13) 818 ret = "Xeon"; 819 break; 820 } 821 if (ret == NULL) 822 ret = i386_intel_brand[ci->ci_brand_id]; 823 } 824 } 825 826 return ret; 827 } 828 829 /* 830 * Identify AMD64 CPU names from cpuid. 831 * 832 * Based on: 833 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 834 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 835 * "Revision Guide for AMD NPT Family 0Fh Processors" 836 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 837 * and other miscellaneous reports. 838 */ 839 static const char * 840 amd_amd64_name(struct cpu_info *ci) 841 { 842 int extfamily, extmodel, model; 843 const char *ret = NULL; 844 845 model = CPUID2MODEL(ci->ci_signature); 846 extfamily = CPUID2EXTFAMILY(ci->ci_signature); 847 extmodel = CPUID2EXTMODEL(ci->ci_signature); 848 849 switch (extfamily) { 850 case 0x00: 851 switch (model) { 852 case 0x1: 853 switch (extmodel) { 854 case 0x2: /* rev JH-E1/E6 */ 855 case 0x4: /* rev JH-F2 */ 856 ret = "Dual-Core Opteron"; 857 break; 858 } 859 break; 860 case 0x3: 861 switch (extmodel) { 862 case 0x2: /* rev JH-E6 (Toledo) */ 863 ret = "Dual-Core Opteron or Athlon 64 X2"; 864 break; 865 case 0x4: /* rev JH-F2 (Windsor) */ 866 ret = "Athlon 64 FX or Athlon 64 X2"; 867 break; 868 } 869 break; 870 case 0x4: 871 switch (extmodel) { 872 case 0x0: /* rev SH-B0/C0/CG (ClawHammer) */ 873 case 0x1: /* rev SH-D0 */ 874 ret = "Athlon 64"; 875 break; 876 case 0x2: /* rev SH-E5 (Lancaster?) */ 877 ret = "Mobile Athlon 64 or Turion 64"; 878 break; 879 } 880 break; 881 case 0x5: 882 switch (extmodel) { 883 case 0x0: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 884 ret = "Opteron or Athlon 64 FX"; 885 break; 886 case 0x1: /* rev SH-D0 */ 887 case 0x2: /* rev SH-E4 */ 888 ret = "Opteron"; 889 break; 890 } 891 break; 892 case 0x7: 893 switch (extmodel) { 894 case 0x0: /* rev SH-CG (ClawHammer) */ 895 case 0x1: /* rev SH-D0 */ 896 ret = "Athlon 64"; 897 break; 898 case 0x2: /* rev DH-E4, SH-E4 */ 899 ret = "Athlon 64 or Athlon 64 FX or Opteron"; 900 break; 901 } 902 break; 903 case 0x8: 904 switch (extmodel) { 905 case 0x0: /* rev CH-CG */ 906 case 0x1: /* rev CH-D0 */ 907 ret = "Athlon 64 or Sempron"; 908 break; 909 case 0x4: /* rev BH-F2 */ 910 ret = "Turion 64 X2"; 911 break; 912 } 913 break; 914 case 0xb: 915 switch (extmodel) { 916 case 0x0: /* rev CH-CG */ 917 case 0x1: /* rev CH-D0 */ 918 ret = "Athlon 64"; 919 break; 920 case 0x2: /* rev BH-E4 (Manchester) */ 921 case 0x4: /* rev BH-F2 (Windsor) */ 922 ret = "Athlon 64 X2"; 923 break; 924 case 0x6: /* rev BH-G1 (Brisbane) */ 925 ret = "Athlon X2 or Athlon 64 X2"; 926 break; 927 } 928 break; 929 case 0xc: 930 switch (extmodel) { 931 case 0x0: /* rev DH-CG (Newcastle) */ 932 case 0x1: /* rev DH-D0 (Winchester) */ 933 case 0x2: /* rev DH-E3/E6 */ 934 ret = "Athlon 64 or Sempron"; 935 break; 936 } 937 break; 938 case 0xe: 939 switch (extmodel) { 940 case 0x0: /* rev DH-CG (Newcastle?) */ 941 ret = "Athlon 64 or Sempron"; 942 break; 943 } 944 break; 945 case 0xf: 946 switch (extmodel) { 947 case 0x0: /* rev DH-CG (Newcastle/Paris) */ 948 case 0x1: /* rev DH-D0 (Winchester/Victoria) */ 949 case 0x2: /* rev DH-E3/E6 (Venice/Palermo) */ 950 case 0x4: /* rev DH-F2 (Orleans/Manila) */ 951 case 0x5: /* rev DH-F2 (Orleans/Manila) */ 952 case 0x6: /* rev DH-G1 */ 953 ret = "Athlon 64 or Sempron"; 954 break; 955 } 956 break; 957 default: 958 ret = "Unknown AMD64 CPU"; 959 } 960 break; 961 case 0x01: 962 ret = "Family 10h"; 963 break; 964 case 0x02: 965 ret = "Family 11h"; 966 break; 967 case 0x03: 968 ret = "Family 12h"; 969 break; 970 case 0x05: 971 ret = "Family 14h"; 972 break; 973 case 0x06: 974 ret = "Family 15h"; 975 break; 976 default: 977 ret = "Unknown AMD64 CPU"; 978 break; 979 } 980 981 return ret; 982 } 983 984 static void 985 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 986 { 987 const struct x86_cache_info *cai; 988 u_int descs[4]; 989 int iterations, i, j; 990 uint8_t desc; 991 uint32_t miscbytes; 992 uint32_t brand[12]; 993 994 memset(ci, 0, sizeof(*ci)); 995 ci->ci_dev = cpuname; 996 997 ci->ci_cpu_type = x86_identify(); 998 if (ci->ci_cpu_type >= 0) { 999 /* Old pre-cpuid instruction cpu */ 1000 ci->ci_cpuid_level = -1; 1001 return; 1002 } 1003 1004 x86_cpuid(0, descs); 1005 ci->ci_cpuid_level = descs[0]; 1006 ci->ci_vendor[0] = descs[1]; 1007 ci->ci_vendor[2] = descs[2]; 1008 ci->ci_vendor[1] = descs[3]; 1009 ci->ci_vendor[3] = 0; 1010 1011 x86_cpuid(0x80000000, brand); 1012 if (brand[0] >= 0x80000004) { 1013 x86_cpuid(0x80000002, brand); 1014 x86_cpuid(0x80000003, brand + 4); 1015 x86_cpuid(0x80000004, brand + 8); 1016 for (i = 0; i < 48; i++) 1017 if (((char *) brand)[i] != ' ') 1018 break; 1019 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1020 } 1021 1022 if (ci->ci_cpuid_level < 1) 1023 return; 1024 1025 x86_cpuid(1, descs); 1026 ci->ci_signature = descs[0]; 1027 miscbytes = descs[1]; 1028 ci->ci_feat_val[1] = descs[2]; 1029 ci->ci_feat_val[0] = descs[3]; 1030 1031 /* Brand is low order 8 bits of ebx */ 1032 ci->ci_brand_id = miscbytes & 0xff; 1033 ci->ci_initapicid = (miscbytes >> 24) & 0xff; 1034 if (ci->ci_cpuid_level < 2) 1035 return; 1036 1037 /* 1038 * Parse the cache info from `cpuid', if we have it. 1039 * XXX This is kinda ugly, but hey, so is the architecture... 1040 */ 1041 1042 x86_cpuid(2, descs); 1043 1044 iterations = descs[0] & 0xff; 1045 while (iterations-- > 0) { 1046 for (i = 0; i < 4; i++) { 1047 if (descs[i] & 0x80000000) 1048 continue; 1049 for (j = 0; j < 4; j++) { 1050 if (i == 0 && j == 0) 1051 continue; 1052 desc = (descs[i] >> (j * 8)) & 0xff; 1053 if (desc == 0) 1054 continue; 1055 cai = cache_info_lookup(intel_cpuid_cache_info, 1056 desc); 1057 if (cai != NULL) 1058 ci->ci_cinfo[cai->cai_index] = *cai; 1059 } 1060 } 1061 x86_cpuid(2, descs); 1062 } 1063 1064 if (ci->ci_cpuid_level < 3) 1065 return; 1066 1067 /* 1068 * If the processor serial number misfeature is present and supported, 1069 * extract it here. 1070 */ 1071 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1072 ci->ci_cpu_serial[0] = ci->ci_signature; 1073 x86_cpuid(3, descs); 1074 ci->ci_cpu_serial[2] = descs[2]; 1075 ci->ci_cpu_serial[1] = descs[3]; 1076 } 1077 } 1078 1079 static void 1080 cpu_probe_features(struct cpu_info *ci) 1081 { 1082 const struct cpu_cpuid_nameclass *cpup = NULL; 1083 int i, xmax, family; 1084 1085 if (ci->ci_cpuid_level < 1) 1086 return; 1087 1088 xmax = __arraycount(i386_cpuid_cpus); 1089 for (i = 0; i < xmax; i++) { 1090 if (!strncmp((char *)ci->ci_vendor, 1091 i386_cpuid_cpus[i].cpu_id, 12)) { 1092 cpup = &i386_cpuid_cpus[i]; 1093 break; 1094 } 1095 } 1096 1097 if (cpup == NULL) 1098 return; 1099 1100 family = (ci->ci_signature >> 8) & 0xf; 1101 1102 if (family > CPU_MAXFAMILY) { 1103 family = CPU_MAXFAMILY; 1104 } 1105 i = family - CPU_MINFAMILY; 1106 1107 if (cpup->cpu_family[i].cpu_probe == NULL) 1108 return; 1109 1110 (*cpup->cpu_family[i].cpu_probe)(ci); 1111 } 1112 1113 static void 1114 intel_family_new_probe(struct cpu_info *ci) 1115 { 1116 uint32_t descs[4]; 1117 1118 x86_cpuid(0x80000000, descs); 1119 1120 /* 1121 * Determine extended feature flags. 1122 */ 1123 if (descs[0] >= 0x80000001) { 1124 x86_cpuid(0x80000001, descs); 1125 ci->ci_feat_val[2] |= descs[3]; 1126 ci->ci_feat_val[3] |= descs[2]; 1127 } 1128 } 1129 1130 static void 1131 amd_family6_probe(struct cpu_info *ci) 1132 { 1133 uint32_t descs[4]; 1134 char *p; 1135 size_t i; 1136 1137 x86_cpuid(0x80000000, descs); 1138 1139 /* 1140 * Determine the extended feature flags. 1141 */ 1142 if (descs[0] >= 0x80000001) { 1143 x86_cpuid(0x80000001, descs); 1144 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 1145 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 1146 } 1147 1148 if (*cpu_brand_string == '\0') 1149 return; 1150 1151 for (i = 1; i < __arraycount(amd_brand); i++) 1152 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 1153 ci->ci_brand_id = i; 1154 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 1155 break; 1156 } 1157 } 1158 1159 static void 1160 amd_family5_setup(struct cpu_info *ci) 1161 { 1162 1163 switch (CPUID2MODEL(ci->ci_signature)) { 1164 case 0: /* AMD-K5 Model 0 */ 1165 /* 1166 * According to the AMD Processor Recognition App Note, 1167 * the AMD-K5 Model 0 uses the wrong bit to indicate 1168 * support for global PTEs, instead using bit 9 (APIC) 1169 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 1170 */ 1171 if (ci->ci_feat_val[0] & CPUID_APIC) 1172 ci->ci_feat_val[0] = 1173 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 1174 /* 1175 * XXX But pmap_pg_g is already initialized -- need to kick 1176 * XXX the pmap somehow. How does the MP branch do this? 1177 */ 1178 break; 1179 } 1180 } 1181 1182 static void 1183 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1184 { 1185 u_int descs[4]; 1186 1187 x86_cpuid(0x80860007, descs); 1188 *frequency = descs[0]; 1189 *voltage = descs[1]; 1190 *percentage = descs[2]; 1191 } 1192 1193 static void 1194 transmeta_cpu_info(struct cpu_info *ci) 1195 { 1196 u_int descs[4], nreg; 1197 u_int frequency, voltage, percentage; 1198 1199 x86_cpuid(0x80860000, descs); 1200 nreg = descs[0]; 1201 if (nreg >= 0x80860001) { 1202 x86_cpuid(0x80860001, descs); 1203 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1204 (descs[1] >> 24) & 0xff, 1205 (descs[1] >> 16) & 0xff, 1206 (descs[1] >> 8) & 0xff, 1207 descs[1] & 0xff); 1208 } 1209 if (nreg >= 0x80860002) { 1210 x86_cpuid(0x80860002, descs); 1211 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1212 (descs[1] >> 24) & 0xff, 1213 (descs[1] >> 16) & 0xff, 1214 (descs[1] >> 8) & 0xff, 1215 descs[1] & 0xff, 1216 descs[2]); 1217 } 1218 if (nreg >= 0x80860006) { 1219 union { 1220 char text[65]; 1221 u_int descs[4][4]; 1222 } info; 1223 int i; 1224 1225 for (i=0; i<4; i++) { 1226 x86_cpuid(0x80860003 + i, info.descs[i]); 1227 } 1228 info.text[64] = '\0'; 1229 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1230 } 1231 1232 if (nreg >= 0x80860007) { 1233 tmx86_get_longrun_status(&frequency, 1234 &voltage, &percentage); 1235 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1236 frequency, voltage, percentage); 1237 } 1238 } 1239 1240 void 1241 identifycpu(int fd, const char *cpuname) 1242 { 1243 const char *name = "", *modifier, *vendorname, *brand = ""; 1244 int class = CPUCLASS_386, i, xmax; 1245 int modif, family, model, ext_model; 1246 const struct cpu_extend_nameclass *modlist; 1247 const struct cpu_cpuid_nameclass *cpup = NULL; 1248 const struct cpu_cpuid_family *cpufam; 1249 const char *feature_str[5]; 1250 struct cpu_info *ci, cistore; 1251 size_t sz; 1252 char buf[512]; 1253 char *bp; 1254 struct cpu_ucode_version ucode; 1255 union { 1256 struct cpu_ucode_version_amd amd; 1257 struct cpu_ucode_version_intel1 intel1; 1258 } ucvers; 1259 1260 ci = &cistore; 1261 cpu_probe_base_features(ci, cpuname); 1262 cpu_probe_features(ci); 1263 1264 if (ci->ci_cpu_type >= 0) { 1265 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1266 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1267 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1268 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1269 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1270 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1271 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1272 modifier = ""; 1273 } else { 1274 xmax = __arraycount(i386_cpuid_cpus); 1275 modif = (ci->ci_signature >> 12) & 0x3; 1276 family = CPUID2FAMILY(ci->ci_signature); 1277 if (family < CPU_MINFAMILY) 1278 errx(1, "identifycpu: strange family value"); 1279 model = CPUID2MODEL(ci->ci_signature); 1280 ext_model = CPUID2EXTMODEL(ci->ci_signature); 1281 1282 for (i = 0; i < xmax; i++) { 1283 if (!strncmp((char *)ci->ci_vendor, 1284 i386_cpuid_cpus[i].cpu_id, 12)) { 1285 cpup = &i386_cpuid_cpus[i]; 1286 break; 1287 } 1288 } 1289 1290 if (cpup == NULL) { 1291 cpu_vendor = CPUVENDOR_UNKNOWN; 1292 if (ci->ci_vendor[0] != '\0') 1293 vendorname = (char *)&ci->ci_vendor[0]; 1294 else 1295 vendorname = "Unknown"; 1296 if (family >= CPU_MAXFAMILY) 1297 family = CPU_MINFAMILY; 1298 class = family - 3; 1299 modifier = ""; 1300 name = ""; 1301 ci->ci_info = NULL; 1302 } else { 1303 cpu_vendor = cpup->cpu_vendor; 1304 vendorname = cpup->cpu_vendorname; 1305 modifier = modifiers[modif]; 1306 if (family > CPU_MAXFAMILY) { 1307 family = CPU_MAXFAMILY; 1308 model = CPU_DEFMODEL; 1309 } else if (model > CPU_MAXMODEL) { 1310 model = CPU_DEFMODEL; 1311 ext_model = 0; 1312 } 1313 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 1314 if (cpufam->cpu_extended_names == NULL || 1315 ext_model == 0) 1316 name = cpufam->cpu_models[model]; 1317 else { 1318 /* 1319 * Scan list(s) of extended model names 1320 */ 1321 modlist = cpufam->cpu_extended_names; 1322 while (modlist->ext_model != 0) { 1323 if (modlist->ext_model == ext_model) { 1324 name = 1325 modlist->cpu_models[model]; 1326 break; 1327 } 1328 modlist++; 1329 } 1330 } 1331 if (name == NULL || *name == '\0') 1332 name = cpufam->cpu_models[CPU_DEFMODEL]; 1333 class = cpufam->cpu_class; 1334 ci->ci_info = cpufam->cpu_info; 1335 1336 if (cpu_vendor == CPUVENDOR_INTEL) { 1337 if (family == 6 && model >= 5) { 1338 const char *tmp; 1339 tmp = intel_family6_name(ci); 1340 if (tmp != NULL) 1341 name = tmp; 1342 } 1343 if (family == CPU_MAXFAMILY && 1344 ci->ci_brand_id < 1345 __arraycount(i386_intel_brand) && 1346 i386_intel_brand[ci->ci_brand_id]) 1347 name = 1348 i386_intel_brand[ci->ci_brand_id]; 1349 } 1350 1351 if (cpu_vendor == CPUVENDOR_AMD) { 1352 if (family == 6 && model >= 6) { 1353 if (ci->ci_brand_id == 1) 1354 /* 1355 * It's Duron. We override the 1356 * name, since it might have 1357 * been misidentified as Athlon. 1358 */ 1359 name = 1360 amd_brand[ci->ci_brand_id]; 1361 else 1362 brand = amd_brand_name; 1363 } 1364 if (CPUID2FAMILY(ci->ci_signature) == 0xf) { 1365 /* 1366 * Identify AMD64 CPU names. 1367 * Note family value is clipped by 1368 * CPU_MAXFAMILY. 1369 */ 1370 const char *tmp; 1371 tmp = amd_amd64_name(ci); 1372 if (tmp != NULL) 1373 name = tmp; 1374 } 1375 } 1376 1377 if (cpu_vendor == CPUVENDOR_IDT && family >= 6) 1378 vendorname = "VIA"; 1379 } 1380 } 1381 1382 ci->ci_cpu_class = class; 1383 1384 sz = sizeof(ci->ci_tsc_freq); 1385 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 1386 sz = sizeof(use_pae); 1387 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 1388 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 1389 1390 snprintf(cpu_model, sizeof(cpu_model), "%s%s%s%s%s%s%s (%s-class)", 1391 vendorname, 1392 *modifier ? " " : "", modifier, 1393 *name ? " " : "", name, 1394 *brand ? " " : "", brand, 1395 classnames[class]); 1396 aprint_normal("%s: %s", cpuname, cpu_model); 1397 1398 if (ci->ci_tsc_freq != 0) 1399 aprint_normal(", %ju.%02ju MHz", 1400 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 1401 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 1402 if (ci->ci_signature != 0) 1403 aprint_normal(", id 0x%x", ci->ci_signature); 1404 aprint_normal("\n"); 1405 1406 if (ci->ci_info) 1407 (*ci->ci_info)(ci); 1408 1409 /* 1410 * display CPU feature flags 1411 */ 1412 1413 #define MAX_FEATURE_LEN 60 /* XXX Need to find a better way to set this */ 1414 1415 feature_str[0] = CPUID_FLAGS1; 1416 feature_str[1] = CPUID2_FLAGS1; 1417 feature_str[2] = CPUID_EXT_FLAGS; 1418 feature_str[3] = NULL; 1419 feature_str[4] = NULL; 1420 1421 switch (cpu_vendor) { 1422 case CPUVENDOR_AMD: 1423 feature_str[3] = CPUID_AMD_FLAGS4; 1424 break; 1425 case CPUVENDOR_INTEL: 1426 feature_str[2] = CPUID_INTEL_EXT_FLAGS; 1427 feature_str[3] = CPUID_INTEL_FLAGS4; 1428 break; 1429 case CPUVENDOR_IDT: 1430 feature_str[4] = CPUID_FLAGS_PADLOCK; 1431 break; 1432 default: 1433 break; 1434 } 1435 1436 for (i = 0; i <= 4; i++) { 1437 if (ci->ci_feat_val[i] && feature_str[i] != NULL) { 1438 snprintb_m(buf, sizeof(buf), feature_str[i], 1439 ci->ci_feat_val[i], MAX_FEATURE_LEN); 1440 bp = buf; 1441 while (*bp != '\0') { 1442 aprint_verbose("%s: %sfeatures%c %s\n", 1443 cpuname, (i == 4)?"padlock ":"", 1444 (i == 4 || i == 0)?' ':'1' + i, bp); 1445 bp += strlen(bp) + 1; 1446 } 1447 } 1448 } 1449 1450 if (*cpu_brand_string != '\0') 1451 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 1452 1453 x86_print_cacheinfo(ci); 1454 1455 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 1456 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 1457 cpuname, 1458 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 1459 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 1460 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 1461 } 1462 1463 if (ci->ci_cpu_class == CPUCLASS_386) { 1464 errx(1, "NetBSD requires an 80486 or later processor"); 1465 } 1466 1467 if (ci->ci_cpu_type == CPU_486DLC) { 1468 #ifndef CYRIX_CACHE_WORKS 1469 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 1470 #else 1471 #ifndef CYRIX_CACHE_REALLY_WORKS 1472 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 1473 #else 1474 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 1475 #endif 1476 #endif 1477 } 1478 1479 /* 1480 * Everything past this point requires a Pentium or later. 1481 */ 1482 if (ci->ci_cpuid_level < 0) 1483 return; 1484 1485 identifycpu_cpuids(ci); 1486 1487 #ifdef INTEL_CORETEMP 1488 if (cpu_vendor == CPUVENDOR_INTEL && ci->ci_cpuid_level >= 0x06) 1489 coretemp_register(ci); 1490 #endif 1491 1492 if (cpu_vendor == CPUVENDOR_AMD) { 1493 uint32_t data[4]; 1494 1495 x86_cpuid(0x80000000, data); 1496 if (data[0] >= 0x80000007) 1497 powernow_probe(ci); 1498 1499 if ((data[0] >= 0x8000000a) 1500 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 1501 1502 x86_cpuid(0x8000000a, data); 1503 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 1504 data[0] & 0xf); 1505 aprint_verbose("%s: SVM NASID %d\n", cpuname, data[1]); 1506 snprintb_m(buf, sizeof(buf), CPUID_AMD_SVM_FLAGS, 1507 data[3], MAX_FEATURE_LEN); 1508 bp = buf; 1509 while (*bp != '\0') { 1510 aprint_verbose("%s: SVM features %s\n", 1511 cpuname, bp); 1512 bp += strlen(bp) + 1; 1513 } 1514 } 1515 } 1516 1517 #ifdef INTEL_ONDEMAND_CLOCKMOD 1518 clockmod_init(); 1519 #endif 1520 1521 aprint_normal_dev(ci->ci_dev, "family %02x model %02x " 1522 "extfamily %02x extmodel %02x stepping %02x\n", 1523 CPUID2FAMILY(ci->ci_signature), CPUID2MODEL(ci->ci_signature), 1524 CPUID2EXTFAMILY(ci->ci_signature), CPUID2EXTMODEL(ci->ci_signature), 1525 CPUID2STEPPING(ci->ci_signature)); 1526 1527 if (cpu_vendor == CPUVENDOR_AMD) 1528 ucode.loader_version = CPU_UCODE_LOADER_AMD; 1529 else if (cpu_vendor == CPUVENDOR_INTEL) 1530 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 1531 else 1532 return; 1533 ucode.data = &ucvers; 1534 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) 1535 return; 1536 if (cpu_vendor == CPUVENDOR_AMD) 1537 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 1538 else if (cpu_vendor == CPUVENDOR_INTEL) 1539 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 1540 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 1541 } 1542 1543 static const char * 1544 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 1545 const char *sep) 1546 { 1547 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1548 char human_num[HUMAN_BUFSIZE]; 1549 1550 if (cai->cai_totalsize == 0) 1551 return sep; 1552 1553 if (sep == NULL) 1554 aprint_verbose_dev(ci->ci_dev, ""); 1555 else 1556 aprint_verbose("%s", sep); 1557 if (name != NULL) 1558 aprint_verbose("%s ", name); 1559 1560 if (cai->cai_string != NULL) { 1561 aprint_verbose("%s ", cai->cai_string); 1562 } else { 1563 (void)humanize_number(human_num, sizeof(human_num), 1564 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 1565 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 1566 } 1567 switch (cai->cai_associativity) { 1568 case 0: 1569 aprint_verbose("disabled"); 1570 break; 1571 case 1: 1572 aprint_verbose("direct-mapped"); 1573 break; 1574 case 0xff: 1575 aprint_verbose("fully associative"); 1576 break; 1577 default: 1578 aprint_verbose("%d-way", cai->cai_associativity); 1579 break; 1580 } 1581 return ", "; 1582 } 1583 1584 static const char * 1585 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 1586 const char *sep) 1587 { 1588 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1589 char human_num[HUMAN_BUFSIZE]; 1590 1591 if (cai->cai_totalsize == 0) 1592 return sep; 1593 1594 if (sep == NULL) 1595 aprint_verbose_dev(ci->ci_dev, ""); 1596 else 1597 aprint_verbose("%s", sep); 1598 if (name != NULL) 1599 aprint_verbose("%s ", name); 1600 1601 if (cai->cai_string != NULL) { 1602 aprint_verbose("%s", cai->cai_string); 1603 } else { 1604 (void)humanize_number(human_num, sizeof(human_num), 1605 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 1606 aprint_verbose("%d %s entries ", cai->cai_totalsize, 1607 human_num); 1608 switch (cai->cai_associativity) { 1609 case 0: 1610 aprint_verbose("disabled"); 1611 break; 1612 case 1: 1613 aprint_verbose("direct-mapped"); 1614 break; 1615 case 0xff: 1616 aprint_verbose("fully associative"); 1617 break; 1618 default: 1619 aprint_verbose("%d-way", cai->cai_associativity); 1620 break; 1621 } 1622 } 1623 return ", "; 1624 } 1625 1626 static const struct x86_cache_info * 1627 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 1628 { 1629 int i; 1630 1631 for (i = 0; cai[i].cai_desc != 0; i++) { 1632 if (cai[i].cai_desc == desc) 1633 return (&cai[i]); 1634 } 1635 1636 return (NULL); 1637 } 1638 1639 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 1640 AMD_L2CACHE_INFO; 1641 1642 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 1643 AMD_L3CACHE_INFO; 1644 1645 static void 1646 amd_cpu_cacheinfo(struct cpu_info *ci) 1647 { 1648 const struct x86_cache_info *cp; 1649 struct x86_cache_info *cai; 1650 int family, model; 1651 u_int descs[4]; 1652 u_int lfunc; 1653 1654 family = (ci->ci_signature >> 8) & 15; 1655 model = CPUID2MODEL(ci->ci_signature); 1656 1657 /* 1658 * K5 model 0 has none of this info. 1659 */ 1660 if (family == 5 && model == 0) 1661 return; 1662 1663 /* 1664 * Get extended values for K8 and up. 1665 */ 1666 if (family == 0xf) { 1667 family += CPUID2EXTFAMILY(ci->ci_signature); 1668 model += CPUID2EXTMODEL(ci->ci_signature); 1669 } 1670 1671 /* 1672 * Determine the largest extended function value. 1673 */ 1674 x86_cpuid(0x80000000, descs); 1675 lfunc = descs[0]; 1676 1677 /* 1678 * Determine L1 cache/TLB info. 1679 */ 1680 if (lfunc < 0x80000005) { 1681 /* No L1 cache info available. */ 1682 return; 1683 } 1684 1685 x86_cpuid(0x80000005, descs); 1686 1687 /* 1688 * K6-III and higher have large page TLBs. 1689 */ 1690 if ((family == 5 && model >= 9) || family >= 6) { 1691 cai = &ci->ci_cinfo[CAI_ITLB2]; 1692 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1693 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1694 cai->cai_linesize = largepagesize; 1695 1696 cai = &ci->ci_cinfo[CAI_DTLB2]; 1697 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1698 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1699 cai->cai_linesize = largepagesize; 1700 } 1701 1702 cai = &ci->ci_cinfo[CAI_ITLB]; 1703 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1704 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1705 cai->cai_linesize = (4 * 1024); 1706 1707 cai = &ci->ci_cinfo[CAI_DTLB]; 1708 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1709 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1710 cai->cai_linesize = (4 * 1024); 1711 1712 cai = &ci->ci_cinfo[CAI_DCACHE]; 1713 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1714 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1715 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1716 1717 cai = &ci->ci_cinfo[CAI_ICACHE]; 1718 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1719 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1720 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1721 1722 /* 1723 * Determine L2 cache/TLB info. 1724 */ 1725 if (lfunc < 0x80000006) { 1726 /* No L2 cache info available. */ 1727 return; 1728 } 1729 1730 x86_cpuid(0x80000006, descs); 1731 1732 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1733 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1734 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1735 cai->cai_linesize = (4 * 1024); 1736 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1737 cai->cai_associativity); 1738 if (cp != NULL) 1739 cai->cai_associativity = cp->cai_associativity; 1740 else 1741 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1742 1743 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1744 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1745 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1746 cai->cai_linesize = largepagesize; 1747 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1748 cai->cai_associativity); 1749 if (cp != NULL) 1750 cai->cai_associativity = cp->cai_associativity; 1751 else 1752 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1753 1754 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1755 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1756 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1757 cai->cai_linesize = (4 * 1024); 1758 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1759 cai->cai_associativity); 1760 if (cp != NULL) 1761 cai->cai_associativity = cp->cai_associativity; 1762 else 1763 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1764 1765 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1766 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1767 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1768 cai->cai_linesize = largepagesize; 1769 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1770 cai->cai_associativity); 1771 if (cp != NULL) 1772 cai->cai_associativity = cp->cai_associativity; 1773 else 1774 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1775 1776 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1777 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1778 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1779 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1780 1781 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1782 cai->cai_associativity); 1783 if (cp != NULL) 1784 cai->cai_associativity = cp->cai_associativity; 1785 else 1786 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1787 1788 /* 1789 * Determine L3 cache info on AMD Family 10h and newer processors 1790 */ 1791 if (family >= 0x10) { 1792 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1793 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1794 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1795 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1796 1797 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1798 cai->cai_associativity); 1799 if (cp != NULL) 1800 cai->cai_associativity = cp->cai_associativity; 1801 else 1802 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1803 } 1804 1805 /* 1806 * Determine 1GB TLB info. 1807 */ 1808 if (lfunc < 0x80000019) { 1809 /* No 1GB TLB info available. */ 1810 return; 1811 } 1812 1813 x86_cpuid(0x80000019, descs); 1814 1815 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1816 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1817 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1818 cai->cai_linesize = (1024 * 1024 * 1024); 1819 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1820 cai->cai_associativity); 1821 if (cp != NULL) 1822 cai->cai_associativity = cp->cai_associativity; 1823 else 1824 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1825 1826 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1827 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1828 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1829 cai->cai_linesize = (1024 * 1024 * 1024); 1830 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1831 cai->cai_associativity); 1832 if (cp != NULL) 1833 cai->cai_associativity = cp->cai_associativity; 1834 else 1835 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1836 1837 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1838 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1839 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1840 cai->cai_linesize = (1024 * 1024 * 1024); 1841 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1842 cai->cai_associativity); 1843 if (cp != NULL) 1844 cai->cai_associativity = cp->cai_associativity; 1845 else 1846 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1847 1848 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1849 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1850 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1851 cai->cai_linesize = (1024 * 1024 * 1024); 1852 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1853 cai->cai_associativity); 1854 if (cp != NULL) 1855 cai->cai_associativity = cp->cai_associativity; 1856 else 1857 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1858 } 1859 1860 static void 1861 via_cpu_cacheinfo(struct cpu_info *ci) 1862 { 1863 struct x86_cache_info *cai; 1864 int family, model, stepping; 1865 u_int descs[4]; 1866 u_int lfunc; 1867 1868 family = (ci->ci_signature >> 8) & 15; 1869 model = CPUID2MODEL(ci->ci_signature); 1870 stepping = CPUID2STEPPING(ci->ci_signature); 1871 1872 /* 1873 * Determine the largest extended function value. 1874 */ 1875 x86_cpuid(0x80000000, descs); 1876 lfunc = descs[0]; 1877 1878 /* 1879 * Determine L1 cache/TLB info. 1880 */ 1881 if (lfunc < 0x80000005) { 1882 /* No L1 cache info available. */ 1883 return; 1884 } 1885 1886 x86_cpuid(0x80000005, descs); 1887 1888 cai = &ci->ci_cinfo[CAI_ITLB]; 1889 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1890 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1891 cai->cai_linesize = (4 * 1024); 1892 1893 cai = &ci->ci_cinfo[CAI_DTLB]; 1894 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1895 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1896 cai->cai_linesize = (4 * 1024); 1897 1898 cai = &ci->ci_cinfo[CAI_DCACHE]; 1899 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1900 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1901 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1902 if (model == 9 && stepping == 8) { 1903 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1904 cai->cai_associativity = 2; 1905 } 1906 1907 cai = &ci->ci_cinfo[CAI_ICACHE]; 1908 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1909 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1910 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1911 if (model == 9 && stepping == 8) { 1912 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1913 cai->cai_associativity = 2; 1914 } 1915 1916 /* 1917 * Determine L2 cache/TLB info. 1918 */ 1919 if (lfunc < 0x80000006) { 1920 /* No L2 cache info available. */ 1921 return; 1922 } 1923 1924 x86_cpuid(0x80000006, descs); 1925 1926 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1927 if (model >= 9) { 1928 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1929 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1930 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1931 } else { 1932 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1933 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1934 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1935 } 1936 } 1937 1938 static void 1939 x86_print_cacheinfo(struct cpu_info *ci) 1940 { 1941 const char *sep; 1942 1943 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 1944 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 1945 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 1946 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 1947 if (sep != NULL) 1948 aprint_verbose("\n"); 1949 } 1950 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 1951 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 1952 if (sep != NULL) 1953 aprint_verbose("\n"); 1954 } 1955 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 1956 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 1957 if (sep != NULL) 1958 aprint_verbose("\n"); 1959 } 1960 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 1961 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 1962 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 1963 if (sep != NULL) 1964 aprint_verbose("\n"); 1965 } 1966 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 1967 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 1968 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 1969 if (sep != NULL) 1970 aprint_verbose("\n"); 1971 } 1972 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 1973 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 1974 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 1975 if (sep != NULL) 1976 aprint_verbose("\n"); 1977 } 1978 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 1979 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 1980 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 1981 if (sep != NULL) 1982 aprint_verbose("\n"); 1983 } 1984 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 1985 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", NULL); 1986 if (sep != NULL) 1987 aprint_verbose("\n"); 1988 } 1989 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 1990 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", NULL); 1991 if (sep != NULL) 1992 aprint_verbose("\n"); 1993 } 1994 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 1995 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", NULL); 1996 if (sep != NULL) 1997 aprint_verbose("\n"); 1998 } 1999 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 2000 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", NULL); 2001 if (sep != NULL) 2002 aprint_verbose("\n"); 2003 } 2004 } 2005 2006 static void 2007 powernow_probe(struct cpu_info *ci) 2008 { 2009 uint32_t regs[4]; 2010 char buf[256]; 2011 2012 x86_cpuid(0x80000007, regs); 2013 2014 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2015 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 2016 buf); 2017 } 2018 2019 int 2020 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2021 { 2022 struct cpu_info ci; 2023 int loader_version, res; 2024 struct cpu_ucode_version versreq; 2025 2026 cpu_probe_base_features(&ci, "unknown"); 2027 2028 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2029 loader_version = CPU_UCODE_LOADER_AMD; 2030 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2031 loader_version = CPU_UCODE_LOADER_INTEL1; 2032 else 2033 return -1; 2034 2035 /* check whether the kernel understands this loader version */ 2036 versreq.loader_version = loader_version; 2037 versreq.data = 0; 2038 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2039 if (res) 2040 return -1; 2041 2042 switch (loader_version) { 2043 case CPU_UCODE_LOADER_AMD: 2044 if (uc->cpu_nr != -1) { 2045 /* printf? */ 2046 return -1; 2047 } 2048 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2049 break; 2050 case CPU_UCODE_LOADER_INTEL1: 2051 if (uc->cpu_nr == -1) 2052 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2053 else 2054 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2055 break; 2056 default: /* can't happen */ 2057 return -1; 2058 } 2059 uc->loader_version = loader_version; 2060 return 0; 2061 } 2062
Indexes created Mon Sep 29 21:09:56 GMT 2025