i386.c revision 1.35
1 /* $NetBSD: i386.c,v 1.35 2013/01/05 16:38:12 dsl Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.35 2013/01/05 16:38:12 dsl Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cacheinfo.h> 85 #include <x86/cpu_ucode.h> 86 87 #include "../cpuctl.h" 88 #include "cpuctl_i386.h" 89 90 /* Size of buffer for printing humanized numbers */ 91 #define HUMAN_BUFSIZE sizeof("999KB") 92 93 struct cpu_info { 94 const char *ci_dev; 95 int32_t ci_cpu_type; /* for cpu's without cpuid */ 96 int32_t ci_cpuid_level; /* highest cpuid supported */ 97 uint32_t ci_signature; /* X86 cpuid type */ 98 uint32_t ci_feat_val[5]; /* X86 CPUID feature bits 99 * [0] basic features %edx 100 * [1] basic features %ecx 101 * [2] extended features %edx 102 * [3] extended features %ecx 103 * [4] VIA padlock features 104 */ 105 uint32_t ci_cpu_class; /* CPU class */ 106 uint32_t ci_brand_id; /* Intel brand id */ 107 uint32_t ci_vendor[4]; /* vendor string */ 108 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 109 uint64_t ci_tsc_freq; /* cpu cycles/second */ 110 uint8_t ci_packageid; 111 uint8_t ci_coreid; 112 uint8_t ci_smtid; 113 uint32_t ci_initapicid; 114 struct x86_cache_info ci_cinfo[CAI_COUNT]; 115 void (*ci_info)(struct cpu_info *); 116 }; 117 118 struct cpu_nocpuid_nameclass { 119 int cpu_vendor; 120 const char *cpu_vendorname; 121 const char *cpu_name; 122 int cpu_class; 123 void (*cpu_setup)(struct cpu_info *); 124 void (*cpu_cacheinfo)(struct cpu_info *); 125 void (*cpu_info)(struct cpu_info *); 126 }; 127 128 struct cpu_extend_nameclass { 129 int ext_model; 130 const char *cpu_models[CPU_MAXMODEL+1]; 131 }; 132 133 struct cpu_cpuid_nameclass { 134 const char *cpu_id; 135 int cpu_vendor; 136 const char *cpu_vendorname; 137 struct cpu_cpuid_family { 138 int cpu_class; 139 const char *cpu_models[CPU_MAXMODEL+2]; 140 void (*cpu_setup)(struct cpu_info *); 141 void (*cpu_probe)(struct cpu_info *); 142 void (*cpu_info)(struct cpu_info *); 143 struct cpu_extend_nameclass *cpu_extended_names; 144 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 145 }; 146 147 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 148 149 /* 150 * Map Brand ID from cpuid instruction to brand name. 151 * Source: Intel Processor Identification and the CPUID Instruction, AP-485 152 */ 153 static const char * const i386_intel_brand[] = { 154 "", /* Unsupported */ 155 "Celeron", /* Intel (R) Celeron (TM) processor */ 156 "Pentium III", /* Intel (R) Pentium (R) III processor */ 157 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 158 "Pentium III", /* Intel (R) Pentium (R) III processor */ 159 "", /* Reserved */ 160 "Mobile Pentium III", /* Mobile Intel (R) Pentium (R) III processor-M */ 161 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 162 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 163 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 164 "Celeron", /* Intel (R) Celeron (TM) processor */ 165 "Xeon", /* Intel (R) Xeon (TM) processor */ 166 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 167 "", /* Reserved */ 168 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 169 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 170 }; 171 172 /* 173 * AMD processors don't have Brand IDs, so we need these names for probe. 174 */ 175 static const char * const amd_brand[] = { 176 "", 177 "Duron", /* AMD Duron(tm) */ 178 "MP", /* AMD Athlon(tm) MP */ 179 "XP", /* AMD Athlon(tm) XP */ 180 "4" /* AMD Athlon(tm) 4 */ 181 }; 182 183 static int cpu_vendor; 184 static char cpu_brand_string[49]; 185 static char amd_brand_name[48]; 186 static int use_pae, largepagesize; 187 188 static void via_cpu_probe(struct cpu_info *); 189 static void amd_family6_probe(struct cpu_info *); 190 static void intel_family_new_probe(struct cpu_info *); 191 static const char *intel_family6_name(struct cpu_info *); 192 static const char *amd_amd64_name(struct cpu_info *); 193 static void amd_family5_setup(struct cpu_info *); 194 static void transmeta_cpu_info(struct cpu_info *); 195 static const char *print_cache_config(struct cpu_info *, int, const char *, 196 const char *); 197 static const char *print_tlb_config(struct cpu_info *, int, const char *, 198 const char *); 199 static void amd_cpu_cacheinfo(struct cpu_info *); 200 static void via_cpu_cacheinfo(struct cpu_info *); 201 static void x86_print_cacheinfo(struct cpu_info *); 202 static const struct x86_cache_info *cache_info_lookup( 203 const struct x86_cache_info *, uint8_t); 204 static void cyrix6x86_cpu_setup(struct cpu_info *); 205 static void winchip_cpu_setup(struct cpu_info *); 206 static void amd_family5_setup(struct cpu_info *); 207 static void powernow_probe(struct cpu_info *); 208 209 /* 210 * Info for CTL_HW 211 */ 212 static char cpu_model[120]; 213 214 /* 215 * Note: these are just the ones that may not have a cpuid instruction. 216 * We deal with the rest in a different way. 217 */ 218 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 219 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 220 NULL, NULL, NULL }, /* CPU_386SX */ 221 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 222 NULL, NULL, NULL }, /* CPU_386 */ 223 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 224 NULL, NULL, NULL }, /* CPU_486SX */ 225 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 226 NULL, NULL, NULL }, /* CPU_486 */ 227 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 228 NULL, NULL, NULL }, /* CPU_486DLC */ 229 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 230 NULL, NULL, NULL }, /* CPU_6x86 */ 231 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 232 NULL, NULL, NULL }, /* CPU_NX586 */ 233 }; 234 235 const char *classnames[] = { 236 "386", 237 "486", 238 "586", 239 "686" 240 }; 241 242 const char *modifiers[] = { 243 "", 244 "OverDrive", 245 "Dual", 246 "" 247 }; 248 249 struct cpu_extend_nameclass intel_family6_ext_models[] = { 250 { /* Extended models 1x */ 251 0x01, { NULL, NULL, 252 NULL, NULL, 253 NULL, "EP80579 Integrated Processor", 254 "Celeron (45nm)", "Core 2 Extreme", 255 NULL, NULL, 256 "Core i7 (Nehalem)", NULL, 257 "Atom", "XeonMP (Nehalem)", 258 NULL, NULL} }, 259 { /* End of list */ 260 0x00, { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 261 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL} } 262 }; 263 264 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 265 { 266 "GenuineIntel", 267 CPUVENDOR_INTEL, 268 "Intel", 269 /* Family 4 */ 270 { { 271 CPUCLASS_486, 272 { 273 "486DX", "486DX", "486SX", "486DX2", "486SL", 274 "486SX2", 0, "486DX2 W/B Enhanced", 275 "486DX4", 0, 0, 0, 0, 0, 0, 0, 276 "486" /* Default */ 277 }, 278 NULL, 279 NULL, 280 NULL, 281 NULL, 282 }, 283 /* Family 5 */ 284 { 285 CPUCLASS_586, 286 { 287 "Pentium (P5 A-step)", "Pentium (P5)", 288 "Pentium (P54C)", "Pentium (P24T)", 289 "Pentium/MMX", "Pentium", 0, 290 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 291 0, 0, 0, 0, 0, 0, 0, 292 "Pentium" /* Default */ 293 }, 294 NULL, 295 NULL, 296 NULL, 297 NULL, 298 }, 299 /* Family 6 */ 300 { 301 CPUCLASS_686, 302 { 303 "Pentium Pro (A-step)", "Pentium Pro", 0, 304 "Pentium II (Klamath)", "Pentium Pro", 305 "Pentium II/Celeron (Deschutes)", 306 "Celeron (Mendocino)", 307 "Pentium III (Katmai)", 308 "Pentium III (Coppermine)", 309 "Pentium M (Banias)", 310 "Pentium III Xeon (Cascades)", 311 "Pentium III (Tualatin)", 0, 312 "Pentium M (Dothan)", 313 "Pentium M (Yonah)", 314 "Core 2", 315 "Pentium Pro, II or III" /* Default */ 316 }, 317 NULL, 318 intel_family_new_probe, 319 NULL, 320 &intel_family6_ext_models[0], 321 }, 322 /* Family > 6 */ 323 { 324 CPUCLASS_686, 325 { 326 0, 0, 0, 0, 0, 0, 0, 0, 327 0, 0, 0, 0, 0, 0, 0, 0, 328 "Pentium 4" /* Default */ 329 }, 330 NULL, 331 intel_family_new_probe, 332 NULL, 333 NULL, 334 } } 335 }, 336 { 337 "AuthenticAMD", 338 CPUVENDOR_AMD, 339 "AMD", 340 /* Family 4 */ 341 { { 342 CPUCLASS_486, 343 { 344 0, 0, 0, "Am486DX2 W/T", 345 0, 0, 0, "Am486DX2 W/B", 346 "Am486DX4 W/T or Am5x86 W/T 150", 347 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 348 0, 0, "Am5x86 W/T 133/160", 349 "Am5x86 W/B 133/160", 350 "Am486 or Am5x86" /* Default */ 351 }, 352 NULL, 353 NULL, 354 NULL, 355 NULL, 356 }, 357 /* Family 5 */ 358 { 359 CPUCLASS_586, 360 { 361 "K5", "K5", "K5", "K5", 0, 0, "K6", 362 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 363 "K6-2+/III+", 0, 0, 364 "K5 or K6" /* Default */ 365 }, 366 amd_family5_setup, 367 NULL, 368 amd_cpu_cacheinfo, 369 NULL, 370 }, 371 /* Family 6 */ 372 { 373 CPUCLASS_686, 374 { 375 0, "Athlon Model 1", "Athlon Model 2", 376 "Duron", "Athlon Model 4 (Thunderbird)", 377 0, "Athlon", "Duron", "Athlon", 0, 378 "Athlon", 0, 0, 0, 0, 0, 379 "K7 (Athlon)" /* Default */ 380 }, 381 NULL, 382 amd_family6_probe, 383 amd_cpu_cacheinfo, 384 NULL, 385 }, 386 /* Family > 6 */ 387 { 388 CPUCLASS_686, 389 { 390 0, 0, 0, 0, 0, 0, 0, 0, 391 0, 0, 0, 0, 0, 0, 0, 0, 392 "Unknown K8 (Athlon)" /* Default */ 393 }, 394 NULL, 395 amd_family6_probe, 396 amd_cpu_cacheinfo, 397 NULL, 398 } } 399 }, 400 { 401 "CyrixInstead", 402 CPUVENDOR_CYRIX, 403 "Cyrix", 404 /* Family 4 */ 405 { { 406 CPUCLASS_486, 407 { 408 0, 0, 0, 409 "MediaGX", 410 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 411 "486" /* Default */ 412 }, 413 cyrix6x86_cpu_setup, /* XXX ?? */ 414 NULL, 415 NULL, 416 NULL, 417 }, 418 /* Family 5 */ 419 { 420 CPUCLASS_586, 421 { 422 0, 0, "6x86", 0, 423 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 424 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 425 "6x86" /* Default */ 426 }, 427 cyrix6x86_cpu_setup, 428 NULL, 429 NULL, 430 NULL, 431 }, 432 /* Family 6 */ 433 { 434 CPUCLASS_686, 435 { 436 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 437 0, 0, 0, 0, 0, 0, 0, 0, 438 "6x86MX" /* Default */ 439 }, 440 cyrix6x86_cpu_setup, 441 NULL, 442 NULL, 443 NULL, 444 }, 445 /* Family > 6 */ 446 { 447 CPUCLASS_686, 448 { 449 0, 0, 0, 0, 0, 0, 0, 0, 450 0, 0, 0, 0, 0, 0, 0, 0, 451 "Unknown 6x86MX" /* Default */ 452 }, 453 NULL, 454 NULL, 455 NULL, 456 NULL, 457 } } 458 }, 459 { /* MediaGX is now owned by National Semiconductor */ 460 "Geode by NSC", 461 CPUVENDOR_CYRIX, /* XXX */ 462 "National Semiconductor", 463 /* Family 4, NSC never had any of these */ 464 { { 465 CPUCLASS_486, 466 { 467 0, 0, 0, 0, 0, 0, 0, 0, 468 0, 0, 0, 0, 0, 0, 0, 0, 469 "486 compatible" /* Default */ 470 }, 471 NULL, 472 NULL, 473 NULL, 474 NULL, 475 }, 476 /* Family 5: Geode family, formerly MediaGX */ 477 { 478 CPUCLASS_586, 479 { 480 0, 0, 0, 0, 481 "Geode GX1", 482 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 483 "Geode" /* Default */ 484 }, 485 cyrix6x86_cpu_setup, 486 NULL, 487 amd_cpu_cacheinfo, 488 NULL, 489 }, 490 /* Family 6, not yet available from NSC */ 491 { 492 CPUCLASS_686, 493 { 494 0, 0, 0, 0, 0, 0, 0, 0, 495 0, 0, 0, 0, 0, 0, 0, 0, 496 "Pentium Pro compatible" /* Default */ 497 }, 498 NULL, 499 NULL, 500 NULL, 501 NULL, 502 }, 503 /* Family > 6, not yet available from NSC */ 504 { 505 CPUCLASS_686, 506 { 507 0, 0, 0, 0, 0, 0, 0, 0, 508 0, 0, 0, 0, 0, 0, 0, 0, 509 "Pentium Pro compatible" /* Default */ 510 }, 511 NULL, 512 NULL, 513 NULL, 514 NULL, 515 } } 516 }, 517 { 518 "CentaurHauls", 519 CPUVENDOR_IDT, 520 "IDT", 521 /* Family 4, IDT never had any of these */ 522 { { 523 CPUCLASS_486, 524 { 525 0, 0, 0, 0, 0, 0, 0, 0, 526 0, 0, 0, 0, 0, 0, 0, 0, 527 "486 compatible" /* Default */ 528 }, 529 NULL, 530 NULL, 531 NULL, 532 NULL, 533 }, 534 /* Family 5 */ 535 { 536 CPUCLASS_586, 537 { 538 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 539 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 540 "WinChip" /* Default */ 541 }, 542 winchip_cpu_setup, 543 NULL, 544 NULL, 545 NULL, 546 }, 547 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 548 { 549 CPUCLASS_686, 550 { 551 0, 0, 0, 0, 0, 0, "C3 Samuel", 552 "C3 Samuel 2/Ezra", "C3 Ezra-T", 553 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 554 0, "VIA Nano", 555 "Unknown VIA/IDT" /* Default */ 556 }, 557 NULL, 558 via_cpu_probe, 559 via_cpu_cacheinfo, 560 NULL, 561 }, 562 /* Family > 6, not yet available from VIA */ 563 { 564 CPUCLASS_686, 565 { 566 0, 0, 0, 0, 0, 0, 0, 0, 567 0, 0, 0, 0, 0, 0, 0, 0, 568 "Pentium Pro compatible" /* Default */ 569 }, 570 NULL, 571 NULL, 572 NULL, 573 NULL, 574 } } 575 }, 576 { 577 "GenuineTMx86", 578 CPUVENDOR_TRANSMETA, 579 "Transmeta", 580 /* Family 4, Transmeta never had any of these */ 581 { { 582 CPUCLASS_486, 583 { 584 0, 0, 0, 0, 0, 0, 0, 0, 585 0, 0, 0, 0, 0, 0, 0, 0, 586 "486 compatible" /* Default */ 587 }, 588 NULL, 589 NULL, 590 NULL, 591 NULL, 592 }, 593 /* Family 5 */ 594 { 595 CPUCLASS_586, 596 { 597 0, 0, 0, 0, 0, 0, 0, 0, 598 0, 0, 0, 0, 0, 0, 0, 0, 599 "Crusoe" /* Default */ 600 }, 601 NULL, 602 NULL, 603 transmeta_cpu_info, 604 NULL, 605 }, 606 /* Family 6, not yet available from Transmeta */ 607 { 608 CPUCLASS_686, 609 { 610 0, 0, 0, 0, 0, 0, 0, 0, 611 0, 0, 0, 0, 0, 0, 0, 0, 612 "Pentium Pro compatible" /* Default */ 613 }, 614 NULL, 615 NULL, 616 NULL, 617 NULL, 618 }, 619 /* Family > 6, not yet available from Transmeta */ 620 { 621 CPUCLASS_686, 622 { 623 0, 0, 0, 0, 0, 0, 0, 0, 624 0, 0, 0, 0, 0, 0, 0, 0, 625 "Pentium Pro compatible" /* Default */ 626 }, 627 NULL, 628 NULL, 629 NULL, 630 NULL, 631 } } 632 } 633 }; 634 635 /* 636 * disable the TSC such that we don't use the TSC in microtime(9) 637 * because some CPUs got the implementation wrong. 638 */ 639 static void 640 disable_tsc(struct cpu_info *ci) 641 { 642 if (ci->ci_feat_val[0] & CPUID_TSC) { 643 ci->ci_feat_val[0] &= ~CPUID_TSC; 644 aprint_error("WARNING: broken TSC disabled\n"); 645 } 646 } 647 648 static void 649 cyrix6x86_cpu_setup(struct cpu_info *ci) 650 { 651 652 /* 653 * Do not disable the TSC on the Geode GX, it's reported to 654 * work fine. 655 */ 656 if (ci->ci_signature != 0x552) 657 disable_tsc(ci); 658 } 659 660 void 661 winchip_cpu_setup(struct cpu_info *ci) 662 { 663 switch (CPUID2MODEL(ci->ci_signature)) { /* model */ 664 case 4: /* WinChip C6 */ 665 disable_tsc(ci); 666 } 667 } 668 669 670 static void 671 identifycpu_cpuids(struct cpu_info *ci) 672 { 673 const char *cpuname = ci->ci_dev; 674 u_int lp_max = 1; /* logical processors per package */ 675 u_int smt_max; /* smt per core */ 676 u_int core_max = 1; /* core per package */ 677 u_int smt_bits, core_bits; 678 uint32_t descs[4]; 679 680 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 681 ci->ci_packageid = ci->ci_initapicid; 682 ci->ci_coreid = 0; 683 ci->ci_smtid = 0; 684 if (cpu_vendor != CPUVENDOR_INTEL) { 685 return; 686 } 687 688 /* 689 * 253668.pdf 7.10.2 690 */ 691 692 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 693 x86_cpuid(1, descs); 694 lp_max = (descs[1] >> 16) & 0xff; 695 } 696 x86_cpuid(0, descs); 697 if (descs[0] >= 4) { 698 x86_cpuid2(4, 0, descs); 699 core_max = (descs[0] >> 26) + 1; 700 } 701 assert(lp_max >= core_max); 702 smt_max = lp_max / core_max; 703 smt_bits = ilog2(smt_max - 1) + 1; 704 core_bits = ilog2(core_max - 1) + 1; 705 if (smt_bits + core_bits) { 706 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 707 } 708 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 709 ci->ci_packageid); 710 if (core_bits) { 711 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 712 713 ci->ci_coreid = 714 __SHIFTOUT(ci->ci_initapicid, core_mask); 715 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 716 } 717 if (smt_bits) { 718 u_int smt_mask = __BITS((int)0, (int)(smt_bits - 1)); 719 720 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, smt_mask); 721 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 722 } 723 } 724 725 static void 726 via_cpu_probe(struct cpu_info *ci) 727 { 728 u_int model = CPUID2MODEL(ci->ci_signature); 729 u_int stepping = CPUID2STEPPING(ci->ci_signature); 730 u_int descs[4]; 731 u_int lfunc; 732 733 /* 734 * Determine the largest extended function value. 735 */ 736 x86_cpuid(0x80000000, descs); 737 lfunc = descs[0]; 738 739 /* 740 * Determine the extended feature flags. 741 */ 742 if (lfunc >= 0x80000001) { 743 x86_cpuid(0x80000001, descs); 744 ci->ci_feat_val[2] |= descs[3]; 745 } 746 747 if (model < 0x9 || (model == 0x9 && stepping < 3)) 748 return; 749 750 /* Nehemiah or Esther */ 751 x86_cpuid(0xc0000000, descs); 752 lfunc = descs[0]; 753 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 754 return; 755 756 x86_cpuid(0xc0000001, descs); 757 lfunc = descs[3]; 758 ci->ci_feat_val[4] = lfunc; 759 } 760 761 static const char * 762 intel_family6_name(struct cpu_info *ci) 763 { 764 int model = CPUID2MODEL(ci->ci_signature); 765 const char *ret = NULL; 766 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 767 768 if (model == 5) { 769 switch (l2cache) { 770 case 0: 771 case 128 * 1024: 772 ret = "Celeron (Covington)"; 773 break; 774 case 256 * 1024: 775 ret = "Mobile Pentium II (Dixon)"; 776 break; 777 case 512 * 1024: 778 ret = "Pentium II"; 779 break; 780 case 1 * 1024 * 1024: 781 case 2 * 1024 * 1024: 782 ret = "Pentium II Xeon"; 783 break; 784 } 785 } else if (model == 6) { 786 switch (l2cache) { 787 case 256 * 1024: 788 case 512 * 1024: 789 ret = "Mobile Pentium II"; 790 break; 791 } 792 } else if (model == 7) { 793 switch (l2cache) { 794 case 512 * 1024: 795 ret = "Pentium III"; 796 break; 797 case 1 * 1024 * 1024: 798 case 2 * 1024 * 1024: 799 ret = "Pentium III Xeon"; 800 break; 801 } 802 } else if (model >= 8) { 803 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 804 switch (ci->ci_brand_id) { 805 case 0x3: 806 if (ci->ci_signature == 0x6B1) 807 ret = "Celeron"; 808 break; 809 case 0x8: 810 if (ci->ci_signature >= 0xF13) 811 ret = "genuine processor"; 812 break; 813 case 0xB: 814 if (ci->ci_signature >= 0xF13) 815 ret = "Xeon MP"; 816 break; 817 case 0xE: 818 if (ci->ci_signature < 0xF13) 819 ret = "Xeon"; 820 break; 821 } 822 if (ret == NULL) 823 ret = i386_intel_brand[ci->ci_brand_id]; 824 } 825 } 826 827 return ret; 828 } 829 830 /* 831 * Identify AMD64 CPU names from cpuid. 832 * 833 * Based on: 834 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 835 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 836 * "Revision Guide for AMD NPT Family 0Fh Processors" 837 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 838 * and other miscellaneous reports. 839 */ 840 static const char * 841 amd_amd64_name(struct cpu_info *ci) 842 { 843 int extfamily, extmodel, model; 844 const char *ret = NULL; 845 846 model = CPUID2MODEL(ci->ci_signature); 847 extfamily = CPUID2EXTFAMILY(ci->ci_signature); 848 extmodel = CPUID2EXTMODEL(ci->ci_signature); 849 850 switch (extfamily) { 851 case 0x00: 852 switch (model) { 853 case 0x1: 854 switch (extmodel) { 855 case 0x2: /* rev JH-E1/E6 */ 856 case 0x4: /* rev JH-F2 */ 857 ret = "Dual-Core Opteron"; 858 break; 859 } 860 break; 861 case 0x3: 862 switch (extmodel) { 863 case 0x2: /* rev JH-E6 (Toledo) */ 864 ret = "Dual-Core Opteron or Athlon 64 X2"; 865 break; 866 case 0x4: /* rev JH-F2 (Windsor) */ 867 ret = "Athlon 64 FX or Athlon 64 X2"; 868 break; 869 } 870 break; 871 case 0x4: 872 switch (extmodel) { 873 case 0x0: /* rev SH-B0/C0/CG (ClawHammer) */ 874 case 0x1: /* rev SH-D0 */ 875 ret = "Athlon 64"; 876 break; 877 case 0x2: /* rev SH-E5 (Lancaster?) */ 878 ret = "Mobile Athlon 64 or Turion 64"; 879 break; 880 } 881 break; 882 case 0x5: 883 switch (extmodel) { 884 case 0x0: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 885 ret = "Opteron or Athlon 64 FX"; 886 break; 887 case 0x1: /* rev SH-D0 */ 888 case 0x2: /* rev SH-E4 */ 889 ret = "Opteron"; 890 break; 891 } 892 break; 893 case 0x7: 894 switch (extmodel) { 895 case 0x0: /* rev SH-CG (ClawHammer) */ 896 case 0x1: /* rev SH-D0 */ 897 ret = "Athlon 64"; 898 break; 899 case 0x2: /* rev DH-E4, SH-E4 */ 900 ret = "Athlon 64 or Athlon 64 FX or Opteron"; 901 break; 902 } 903 break; 904 case 0x8: 905 switch (extmodel) { 906 case 0x0: /* rev CH-CG */ 907 case 0x1: /* rev CH-D0 */ 908 ret = "Athlon 64 or Sempron"; 909 break; 910 case 0x4: /* rev BH-F2 */ 911 ret = "Turion 64 X2"; 912 break; 913 } 914 break; 915 case 0xb: 916 switch (extmodel) { 917 case 0x0: /* rev CH-CG */ 918 case 0x1: /* rev CH-D0 */ 919 ret = "Athlon 64"; 920 break; 921 case 0x2: /* rev BH-E4 (Manchester) */ 922 case 0x4: /* rev BH-F2 (Windsor) */ 923 ret = "Athlon 64 X2"; 924 break; 925 case 0x6: /* rev BH-G1 (Brisbane) */ 926 ret = "Athlon X2 or Athlon 64 X2"; 927 break; 928 } 929 break; 930 case 0xc: 931 switch (extmodel) { 932 case 0x0: /* rev DH-CG (Newcastle) */ 933 case 0x1: /* rev DH-D0 (Winchester) */ 934 case 0x2: /* rev DH-E3/E6 */ 935 ret = "Athlon 64 or Sempron"; 936 break; 937 } 938 break; 939 case 0xe: 940 switch (extmodel) { 941 case 0x0: /* rev DH-CG (Newcastle?) */ 942 ret = "Athlon 64 or Sempron"; 943 break; 944 } 945 break; 946 case 0xf: 947 switch (extmodel) { 948 case 0x0: /* rev DH-CG (Newcastle/Paris) */ 949 case 0x1: /* rev DH-D0 (Winchester/Victoria) */ 950 case 0x2: /* rev DH-E3/E6 (Venice/Palermo) */ 951 case 0x4: /* rev DH-F2 (Orleans/Manila) */ 952 case 0x5: /* rev DH-F2 (Orleans/Manila) */ 953 case 0x6: /* rev DH-G1 */ 954 ret = "Athlon 64 or Sempron"; 955 break; 956 } 957 break; 958 default: 959 ret = "Unknown AMD64 CPU"; 960 } 961 break; 962 case 0x01: 963 ret = "Family 10h"; 964 break; 965 case 0x02: 966 ret = "Family 11h"; 967 break; 968 case 0x03: 969 ret = "Family 12h"; 970 break; 971 case 0x05: 972 ret = "Family 14h"; 973 break; 974 case 0x06: 975 ret = "Family 15h"; 976 break; 977 default: 978 ret = "Unknown AMD64 CPU"; 979 break; 980 } 981 982 return ret; 983 } 984 985 static void 986 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 987 { 988 const struct x86_cache_info *cai; 989 u_int descs[4]; 990 int iterations, i, j; 991 uint8_t desc; 992 uint32_t miscbytes; 993 uint32_t brand[12]; 994 995 memset(ci, 0, sizeof(*ci)); 996 ci->ci_dev = cpuname; 997 998 ci->ci_cpu_type = x86_identify(); 999 if (ci->ci_cpu_type >= 0) { 1000 /* Old pre-cpuid instruction cpu */ 1001 ci->ci_cpuid_level = -1; 1002 return; 1003 } 1004 1005 x86_cpuid(0, descs); 1006 ci->ci_cpuid_level = descs[0]; 1007 ci->ci_vendor[0] = descs[1]; 1008 ci->ci_vendor[2] = descs[2]; 1009 ci->ci_vendor[1] = descs[3]; 1010 ci->ci_vendor[3] = 0; 1011 1012 x86_cpuid(0x80000000, brand); 1013 if (brand[0] >= 0x80000004) { 1014 x86_cpuid(0x80000002, brand); 1015 x86_cpuid(0x80000003, brand + 4); 1016 x86_cpuid(0x80000004, brand + 8); 1017 for (i = 0; i < 48; i++) 1018 if (((char *) brand)[i] != ' ') 1019 break; 1020 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 1021 } 1022 1023 if (ci->ci_cpuid_level < 1) 1024 return; 1025 1026 x86_cpuid(1, descs); 1027 ci->ci_signature = descs[0]; 1028 miscbytes = descs[1]; 1029 ci->ci_feat_val[1] = descs[2]; 1030 ci->ci_feat_val[0] = descs[3]; 1031 1032 /* Brand is low order 8 bits of ebx */ 1033 ci->ci_brand_id = miscbytes & 0xff; 1034 ci->ci_initapicid = (miscbytes >> 24) & 0xff; 1035 if (ci->ci_cpuid_level < 2) 1036 return; 1037 1038 /* 1039 * Parse the cache info from `cpuid', if we have it. 1040 * XXX This is kinda ugly, but hey, so is the architecture... 1041 */ 1042 1043 x86_cpuid(2, descs); 1044 1045 iterations = descs[0] & 0xff; 1046 while (iterations-- > 0) { 1047 for (i = 0; i < 4; i++) { 1048 if (descs[i] & 0x80000000) 1049 continue; 1050 for (j = 0; j < 4; j++) { 1051 if (i == 0 && j == 0) 1052 continue; 1053 desc = (descs[i] >> (j * 8)) & 0xff; 1054 if (desc == 0) 1055 continue; 1056 cai = cache_info_lookup(intel_cpuid_cache_info, 1057 desc); 1058 if (cai != NULL) 1059 ci->ci_cinfo[cai->cai_index] = *cai; 1060 } 1061 } 1062 x86_cpuid(2, descs); 1063 } 1064 1065 if (ci->ci_cpuid_level < 3) 1066 return; 1067 1068 /* 1069 * If the processor serial number misfeature is present and supported, 1070 * extract it here. 1071 */ 1072 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1073 ci->ci_cpu_serial[0] = ci->ci_signature; 1074 x86_cpuid(3, descs); 1075 ci->ci_cpu_serial[2] = descs[2]; 1076 ci->ci_cpu_serial[1] = descs[3]; 1077 } 1078 } 1079 1080 static void 1081 cpu_probe_features(struct cpu_info *ci) 1082 { 1083 const struct cpu_cpuid_nameclass *cpup = NULL; 1084 int i, xmax, family; 1085 1086 if (ci->ci_cpuid_level < 1) 1087 return; 1088 1089 xmax = __arraycount(i386_cpuid_cpus); 1090 for (i = 0; i < xmax; i++) { 1091 if (!strncmp((char *)ci->ci_vendor, 1092 i386_cpuid_cpus[i].cpu_id, 12)) { 1093 cpup = &i386_cpuid_cpus[i]; 1094 break; 1095 } 1096 } 1097 1098 if (cpup == NULL) 1099 return; 1100 1101 family = (ci->ci_signature >> 8) & 0xf; 1102 1103 if (family > CPU_MAXFAMILY) { 1104 family = CPU_MAXFAMILY; 1105 } 1106 i = family - CPU_MINFAMILY; 1107 1108 if (cpup->cpu_family[i].cpu_probe == NULL) 1109 return; 1110 1111 (*cpup->cpu_family[i].cpu_probe)(ci); 1112 } 1113 1114 static void 1115 intel_family_new_probe(struct cpu_info *ci) 1116 { 1117 uint32_t descs[4]; 1118 1119 x86_cpuid(0x80000000, descs); 1120 1121 /* 1122 * Determine extended feature flags. 1123 */ 1124 if (descs[0] >= 0x80000001) { 1125 x86_cpuid(0x80000001, descs); 1126 ci->ci_feat_val[2] |= descs[3]; 1127 ci->ci_feat_val[3] |= descs[2]; 1128 } 1129 } 1130 1131 static void 1132 amd_family6_probe(struct cpu_info *ci) 1133 { 1134 uint32_t descs[4]; 1135 char *p; 1136 size_t i; 1137 1138 x86_cpuid(0x80000000, descs); 1139 1140 /* 1141 * Determine the extended feature flags. 1142 */ 1143 if (descs[0] >= 0x80000001) { 1144 x86_cpuid(0x80000001, descs); 1145 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 1146 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 1147 } 1148 1149 if (*cpu_brand_string == '\0') 1150 return; 1151 1152 for (i = 1; i < __arraycount(amd_brand); i++) 1153 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 1154 ci->ci_brand_id = i; 1155 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 1156 break; 1157 } 1158 } 1159 1160 static void 1161 amd_family5_setup(struct cpu_info *ci) 1162 { 1163 1164 switch (CPUID2MODEL(ci->ci_signature)) { 1165 case 0: /* AMD-K5 Model 0 */ 1166 /* 1167 * According to the AMD Processor Recognition App Note, 1168 * the AMD-K5 Model 0 uses the wrong bit to indicate 1169 * support for global PTEs, instead using bit 9 (APIC) 1170 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 1171 */ 1172 if (ci->ci_feat_val[0] & CPUID_APIC) 1173 ci->ci_feat_val[0] = 1174 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 1175 /* 1176 * XXX But pmap_pg_g is already initialized -- need to kick 1177 * XXX the pmap somehow. How does the MP branch do this? 1178 */ 1179 break; 1180 } 1181 } 1182 1183 static void 1184 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1185 { 1186 u_int descs[4]; 1187 1188 x86_cpuid(0x80860007, descs); 1189 *frequency = descs[0]; 1190 *voltage = descs[1]; 1191 *percentage = descs[2]; 1192 } 1193 1194 static void 1195 transmeta_cpu_info(struct cpu_info *ci) 1196 { 1197 u_int descs[4], nreg; 1198 u_int frequency, voltage, percentage; 1199 1200 x86_cpuid(0x80860000, descs); 1201 nreg = descs[0]; 1202 if (nreg >= 0x80860001) { 1203 x86_cpuid(0x80860001, descs); 1204 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1205 (descs[1] >> 24) & 0xff, 1206 (descs[1] >> 16) & 0xff, 1207 (descs[1] >> 8) & 0xff, 1208 descs[1] & 0xff); 1209 } 1210 if (nreg >= 0x80860002) { 1211 x86_cpuid(0x80860002, descs); 1212 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1213 (descs[1] >> 24) & 0xff, 1214 (descs[1] >> 16) & 0xff, 1215 (descs[1] >> 8) & 0xff, 1216 descs[1] & 0xff, 1217 descs[2]); 1218 } 1219 if (nreg >= 0x80860006) { 1220 union { 1221 char text[65]; 1222 u_int descs[4][4]; 1223 } info; 1224 int i; 1225 1226 for (i=0; i<4; i++) { 1227 x86_cpuid(0x80860003 + i, info.descs[i]); 1228 } 1229 info.text[64] = '\0'; 1230 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1231 } 1232 1233 if (nreg >= 0x80860007) { 1234 tmx86_get_longrun_status(&frequency, 1235 &voltage, &percentage); 1236 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1237 frequency, voltage, percentage); 1238 } 1239 } 1240 1241 void 1242 identifycpu(int fd, const char *cpuname) 1243 { 1244 const char *name = "", *modifier, *vendorname, *brand = ""; 1245 int class = CPUCLASS_386, i, xmax; 1246 int modif, family, model, ext_model; 1247 const struct cpu_extend_nameclass *modlist; 1248 const struct cpu_cpuid_nameclass *cpup = NULL; 1249 const struct cpu_cpuid_family *cpufam; 1250 const char *feature_str[5]; 1251 struct cpu_info *ci, cistore; 1252 size_t sz; 1253 char buf[512]; 1254 char *bp; 1255 struct cpu_ucode_version ucode; 1256 union { 1257 struct cpu_ucode_version_amd amd; 1258 struct cpu_ucode_version_intel1 intel1; 1259 } ucvers; 1260 1261 ci = &cistore; 1262 cpu_probe_base_features(ci, cpuname); 1263 cpu_probe_features(ci); 1264 1265 if (ci->ci_cpu_type >= 0) { 1266 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1267 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1268 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1269 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1270 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1271 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1272 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1273 modifier = ""; 1274 } else { 1275 xmax = __arraycount(i386_cpuid_cpus); 1276 modif = (ci->ci_signature >> 12) & 0x3; 1277 family = CPUID2FAMILY(ci->ci_signature); 1278 if (family < CPU_MINFAMILY) 1279 errx(1, "identifycpu: strange family value"); 1280 model = CPUID2MODEL(ci->ci_signature); 1281 ext_model = CPUID2EXTMODEL(ci->ci_signature); 1282 1283 for (i = 0; i < xmax; i++) { 1284 if (!strncmp((char *)ci->ci_vendor, 1285 i386_cpuid_cpus[i].cpu_id, 12)) { 1286 cpup = &i386_cpuid_cpus[i]; 1287 break; 1288 } 1289 } 1290 1291 if (cpup == NULL) { 1292 cpu_vendor = CPUVENDOR_UNKNOWN; 1293 if (ci->ci_vendor[0] != '\0') 1294 vendorname = (char *)&ci->ci_vendor[0]; 1295 else 1296 vendorname = "Unknown"; 1297 if (family >= CPU_MAXFAMILY) 1298 family = CPU_MINFAMILY; 1299 class = family - 3; 1300 modifier = ""; 1301 name = ""; 1302 ci->ci_info = NULL; 1303 } else { 1304 cpu_vendor = cpup->cpu_vendor; 1305 vendorname = cpup->cpu_vendorname; 1306 modifier = modifiers[modif]; 1307 if (family > CPU_MAXFAMILY) { 1308 family = CPU_MAXFAMILY; 1309 model = CPU_DEFMODEL; 1310 } else if (model > CPU_MAXMODEL) { 1311 model = CPU_DEFMODEL; 1312 ext_model = 0; 1313 } 1314 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 1315 if (cpufam->cpu_extended_names == NULL || 1316 ext_model == 0) 1317 name = cpufam->cpu_models[model]; 1318 else { 1319 /* 1320 * Scan list(s) of extended model names 1321 */ 1322 modlist = cpufam->cpu_extended_names; 1323 while (modlist->ext_model != 0) { 1324 if (modlist->ext_model == ext_model) { 1325 name = 1326 modlist->cpu_models[model]; 1327 break; 1328 } 1329 modlist++; 1330 } 1331 } 1332 if (name == NULL || *name == '\0') 1333 name = cpufam->cpu_models[CPU_DEFMODEL]; 1334 class = cpufam->cpu_class; 1335 ci->ci_info = cpufam->cpu_info; 1336 1337 if (cpu_vendor == CPUVENDOR_INTEL) { 1338 if (family == 6 && model >= 5) { 1339 const char *tmp; 1340 tmp = intel_family6_name(ci); 1341 if (tmp != NULL) 1342 name = tmp; 1343 } 1344 if (family == CPU_MAXFAMILY && 1345 ci->ci_brand_id < 1346 __arraycount(i386_intel_brand) && 1347 i386_intel_brand[ci->ci_brand_id]) 1348 name = 1349 i386_intel_brand[ci->ci_brand_id]; 1350 } 1351 1352 if (cpu_vendor == CPUVENDOR_AMD) { 1353 if (family == 6 && model >= 6) { 1354 if (ci->ci_brand_id == 1) 1355 /* 1356 * It's Duron. We override the 1357 * name, since it might have 1358 * been misidentified as Athlon. 1359 */ 1360 name = 1361 amd_brand[ci->ci_brand_id]; 1362 else 1363 brand = amd_brand_name; 1364 } 1365 if (CPUID2FAMILY(ci->ci_signature) == 0xf) { 1366 /* 1367 * Identify AMD64 CPU names. 1368 * Note family value is clipped by 1369 * CPU_MAXFAMILY. 1370 */ 1371 const char *tmp; 1372 tmp = amd_amd64_name(ci); 1373 if (tmp != NULL) 1374 name = tmp; 1375 } 1376 } 1377 1378 if (cpu_vendor == CPUVENDOR_IDT && family >= 6) 1379 vendorname = "VIA"; 1380 } 1381 } 1382 1383 ci->ci_cpu_class = class; 1384 1385 sz = sizeof(ci->ci_tsc_freq); 1386 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 1387 sz = sizeof(use_pae); 1388 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 1389 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 1390 1391 snprintf(cpu_model, sizeof(cpu_model), "%s%s%s%s%s%s%s (%s-class)", 1392 vendorname, 1393 *modifier ? " " : "", modifier, 1394 *name ? " " : "", name, 1395 *brand ? " " : "", brand, 1396 classnames[class]); 1397 aprint_normal("%s: %s", cpuname, cpu_model); 1398 1399 if (ci->ci_tsc_freq != 0) 1400 aprint_normal(", %ju.%02ju MHz", 1401 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 1402 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 1403 if (ci->ci_signature != 0) 1404 aprint_normal(", id 0x%x", ci->ci_signature); 1405 aprint_normal("\n"); 1406 1407 if (ci->ci_info) 1408 (*ci->ci_info)(ci); 1409 1410 /* 1411 * display CPU feature flags 1412 */ 1413 1414 #define MAX_FEATURE_LEN 60 /* XXX Need to find a better way to set this */ 1415 1416 feature_str[0] = CPUID_FLAGS1; 1417 feature_str[1] = CPUID2_FLAGS1; 1418 feature_str[2] = CPUID_EXT_FLAGS; 1419 feature_str[3] = NULL; 1420 feature_str[4] = NULL; 1421 1422 switch (cpu_vendor) { 1423 case CPUVENDOR_AMD: 1424 feature_str[3] = CPUID_AMD_FLAGS4; 1425 break; 1426 case CPUVENDOR_INTEL: 1427 feature_str[2] = CPUID_INTEL_EXT_FLAGS; 1428 feature_str[3] = CPUID_INTEL_FLAGS4; 1429 break; 1430 case CPUVENDOR_IDT: 1431 feature_str[4] = CPUID_FLAGS_PADLOCK; 1432 break; 1433 default: 1434 break; 1435 } 1436 1437 for (i = 0; i <= 4; i++) { 1438 if (ci->ci_feat_val[i] && feature_str[i] != NULL) { 1439 snprintb_m(buf, sizeof(buf), feature_str[i], 1440 ci->ci_feat_val[i], MAX_FEATURE_LEN); 1441 bp = buf; 1442 while (*bp != '\0') { 1443 aprint_verbose("%s: %sfeatures%c %s\n", 1444 cpuname, (i == 4)?"padlock ":"", 1445 (i == 4 || i == 0)?' ':'1' + i, bp); 1446 bp += strlen(bp) + 1; 1447 } 1448 } 1449 } 1450 1451 if (*cpu_brand_string != '\0') 1452 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 1453 1454 x86_print_cacheinfo(ci); 1455 1456 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 1457 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 1458 cpuname, 1459 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 1460 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 1461 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 1462 } 1463 1464 if (ci->ci_cpu_class == CPUCLASS_386) { 1465 errx(1, "NetBSD requires an 80486 or later processor"); 1466 } 1467 1468 if (ci->ci_cpu_type == CPU_486DLC) { 1469 #ifndef CYRIX_CACHE_WORKS 1470 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 1471 #else 1472 #ifndef CYRIX_CACHE_REALLY_WORKS 1473 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 1474 #else 1475 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 1476 #endif 1477 #endif 1478 } 1479 1480 /* 1481 * Everything past this point requires a Pentium or later. 1482 */ 1483 if (ci->ci_cpuid_level < 0) 1484 return; 1485 1486 identifycpu_cpuids(ci); 1487 1488 #ifdef INTEL_CORETEMP 1489 if (cpu_vendor == CPUVENDOR_INTEL && ci->ci_cpuid_level >= 0x06) 1490 coretemp_register(ci); 1491 #endif 1492 1493 if (cpu_vendor == CPUVENDOR_AMD) { 1494 uint32_t data[4]; 1495 1496 x86_cpuid(0x80000000, data); 1497 if (data[0] >= 0x80000007) 1498 powernow_probe(ci); 1499 1500 if ((data[0] >= 0x8000000a) 1501 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 1502 1503 x86_cpuid(0x8000000a, data); 1504 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 1505 data[0] & 0xf); 1506 aprint_verbose("%s: SVM NASID %d\n", cpuname, data[1]); 1507 snprintb_m(buf, sizeof(buf), CPUID_AMD_SVM_FLAGS, 1508 data[3], MAX_FEATURE_LEN); 1509 bp = buf; 1510 while (*bp != '\0') { 1511 aprint_verbose("%s: SVM features %s\n", 1512 cpuname, bp); 1513 bp += strlen(bp) + 1; 1514 } 1515 } 1516 } 1517 1518 #ifdef INTEL_ONDEMAND_CLOCKMOD 1519 clockmod_init(); 1520 #endif 1521 1522 aprint_normal_dev(ci->ci_dev, "family %02x model %02x " 1523 "extfamily %02x extmodel %02x stepping %02x\n", 1524 CPUID2FAMILY(ci->ci_signature), CPUID2MODEL(ci->ci_signature), 1525 CPUID2EXTFAMILY(ci->ci_signature), CPUID2EXTMODEL(ci->ci_signature), 1526 CPUID2STEPPING(ci->ci_signature)); 1527 1528 if (cpu_vendor == CPUVENDOR_AMD) 1529 ucode.loader_version = CPU_UCODE_LOADER_AMD; 1530 else if (cpu_vendor == CPUVENDOR_INTEL) 1531 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 1532 else 1533 return; 1534 1535 ucode.data = &ucvers; 1536 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 1537 #ifdef __i386__ 1538 struct cpu_ucode_version_64 ucode_64; 1539 if (errno != ENOTTY) 1540 return; 1541 /* Try the 64 bit ioctl */ 1542 memset(&ucode_64, 0, sizeof ucode_64); 1543 ucode_64.data = &ucvers; 1544 ucode_64.loader_version = ucode.loader_version; 1545 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 1546 return; 1547 #endif 1548 } 1549 1550 if (cpu_vendor == CPUVENDOR_AMD) 1551 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 1552 else if (cpu_vendor == CPUVENDOR_INTEL) 1553 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 1554 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 1555 } 1556 1557 static const char * 1558 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 1559 const char *sep) 1560 { 1561 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1562 char human_num[HUMAN_BUFSIZE]; 1563 1564 if (cai->cai_totalsize == 0) 1565 return sep; 1566 1567 if (sep == NULL) 1568 aprint_verbose_dev(ci->ci_dev, ""); 1569 else 1570 aprint_verbose("%s", sep); 1571 if (name != NULL) 1572 aprint_verbose("%s ", name); 1573 1574 if (cai->cai_string != NULL) { 1575 aprint_verbose("%s ", cai->cai_string); 1576 } else { 1577 (void)humanize_number(human_num, sizeof(human_num), 1578 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 1579 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 1580 } 1581 switch (cai->cai_associativity) { 1582 case 0: 1583 aprint_verbose("disabled"); 1584 break; 1585 case 1: 1586 aprint_verbose("direct-mapped"); 1587 break; 1588 case 0xff: 1589 aprint_verbose("fully associative"); 1590 break; 1591 default: 1592 aprint_verbose("%d-way", cai->cai_associativity); 1593 break; 1594 } 1595 return ", "; 1596 } 1597 1598 static const char * 1599 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 1600 const char *sep) 1601 { 1602 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1603 char human_num[HUMAN_BUFSIZE]; 1604 1605 if (cai->cai_totalsize == 0) 1606 return sep; 1607 1608 if (sep == NULL) 1609 aprint_verbose_dev(ci->ci_dev, ""); 1610 else 1611 aprint_verbose("%s", sep); 1612 if (name != NULL) 1613 aprint_verbose("%s ", name); 1614 1615 if (cai->cai_string != NULL) { 1616 aprint_verbose("%s", cai->cai_string); 1617 } else { 1618 (void)humanize_number(human_num, sizeof(human_num), 1619 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 1620 aprint_verbose("%d %s entries ", cai->cai_totalsize, 1621 human_num); 1622 switch (cai->cai_associativity) { 1623 case 0: 1624 aprint_verbose("disabled"); 1625 break; 1626 case 1: 1627 aprint_verbose("direct-mapped"); 1628 break; 1629 case 0xff: 1630 aprint_verbose("fully associative"); 1631 break; 1632 default: 1633 aprint_verbose("%d-way", cai->cai_associativity); 1634 break; 1635 } 1636 } 1637 return ", "; 1638 } 1639 1640 static const struct x86_cache_info * 1641 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 1642 { 1643 int i; 1644 1645 for (i = 0; cai[i].cai_desc != 0; i++) { 1646 if (cai[i].cai_desc == desc) 1647 return (&cai[i]); 1648 } 1649 1650 return (NULL); 1651 } 1652 1653 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 1654 AMD_L2CACHE_INFO; 1655 1656 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 1657 AMD_L3CACHE_INFO; 1658 1659 static void 1660 amd_cpu_cacheinfo(struct cpu_info *ci) 1661 { 1662 const struct x86_cache_info *cp; 1663 struct x86_cache_info *cai; 1664 int family, model; 1665 u_int descs[4]; 1666 u_int lfunc; 1667 1668 family = (ci->ci_signature >> 8) & 15; 1669 model = CPUID2MODEL(ci->ci_signature); 1670 1671 /* 1672 * K5 model 0 has none of this info. 1673 */ 1674 if (family == 5 && model == 0) 1675 return; 1676 1677 /* 1678 * Get extended values for K8 and up. 1679 */ 1680 if (family == 0xf) { 1681 family += CPUID2EXTFAMILY(ci->ci_signature); 1682 model += CPUID2EXTMODEL(ci->ci_signature); 1683 } 1684 1685 /* 1686 * Determine the largest extended function value. 1687 */ 1688 x86_cpuid(0x80000000, descs); 1689 lfunc = descs[0]; 1690 1691 /* 1692 * Determine L1 cache/TLB info. 1693 */ 1694 if (lfunc < 0x80000005) { 1695 /* No L1 cache info available. */ 1696 return; 1697 } 1698 1699 x86_cpuid(0x80000005, descs); 1700 1701 /* 1702 * K6-III and higher have large page TLBs. 1703 */ 1704 if ((family == 5 && model >= 9) || family >= 6) { 1705 cai = &ci->ci_cinfo[CAI_ITLB2]; 1706 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1707 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1708 cai->cai_linesize = largepagesize; 1709 1710 cai = &ci->ci_cinfo[CAI_DTLB2]; 1711 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1712 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1713 cai->cai_linesize = largepagesize; 1714 } 1715 1716 cai = &ci->ci_cinfo[CAI_ITLB]; 1717 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1718 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1719 cai->cai_linesize = (4 * 1024); 1720 1721 cai = &ci->ci_cinfo[CAI_DTLB]; 1722 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1723 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1724 cai->cai_linesize = (4 * 1024); 1725 1726 cai = &ci->ci_cinfo[CAI_DCACHE]; 1727 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1728 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1729 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1730 1731 cai = &ci->ci_cinfo[CAI_ICACHE]; 1732 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1733 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1734 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1735 1736 /* 1737 * Determine L2 cache/TLB info. 1738 */ 1739 if (lfunc < 0x80000006) { 1740 /* No L2 cache info available. */ 1741 return; 1742 } 1743 1744 x86_cpuid(0x80000006, descs); 1745 1746 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1747 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1748 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1749 cai->cai_linesize = (4 * 1024); 1750 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1751 cai->cai_associativity); 1752 if (cp != NULL) 1753 cai->cai_associativity = cp->cai_associativity; 1754 else 1755 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1756 1757 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1758 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1759 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1760 cai->cai_linesize = largepagesize; 1761 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1762 cai->cai_associativity); 1763 if (cp != NULL) 1764 cai->cai_associativity = cp->cai_associativity; 1765 else 1766 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1767 1768 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1769 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1770 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1771 cai->cai_linesize = (4 * 1024); 1772 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1773 cai->cai_associativity); 1774 if (cp != NULL) 1775 cai->cai_associativity = cp->cai_associativity; 1776 else 1777 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1778 1779 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1780 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1781 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1782 cai->cai_linesize = largepagesize; 1783 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1784 cai->cai_associativity); 1785 if (cp != NULL) 1786 cai->cai_associativity = cp->cai_associativity; 1787 else 1788 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1789 1790 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1791 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1792 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1793 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1794 1795 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1796 cai->cai_associativity); 1797 if (cp != NULL) 1798 cai->cai_associativity = cp->cai_associativity; 1799 else 1800 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1801 1802 /* 1803 * Determine L3 cache info on AMD Family 10h and newer processors 1804 */ 1805 if (family >= 0x10) { 1806 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1807 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1808 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1809 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1810 1811 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1812 cai->cai_associativity); 1813 if (cp != NULL) 1814 cai->cai_associativity = cp->cai_associativity; 1815 else 1816 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1817 } 1818 1819 /* 1820 * Determine 1GB TLB info. 1821 */ 1822 if (lfunc < 0x80000019) { 1823 /* No 1GB TLB info available. */ 1824 return; 1825 } 1826 1827 x86_cpuid(0x80000019, descs); 1828 1829 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1830 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1831 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1832 cai->cai_linesize = (1024 * 1024 * 1024); 1833 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1834 cai->cai_associativity); 1835 if (cp != NULL) 1836 cai->cai_associativity = cp->cai_associativity; 1837 else 1838 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1839 1840 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1841 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1842 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1843 cai->cai_linesize = (1024 * 1024 * 1024); 1844 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1845 cai->cai_associativity); 1846 if (cp != NULL) 1847 cai->cai_associativity = cp->cai_associativity; 1848 else 1849 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1850 1851 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1852 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1853 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1854 cai->cai_linesize = (1024 * 1024 * 1024); 1855 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1856 cai->cai_associativity); 1857 if (cp != NULL) 1858 cai->cai_associativity = cp->cai_associativity; 1859 else 1860 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1861 1862 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1863 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1864 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1865 cai->cai_linesize = (1024 * 1024 * 1024); 1866 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1867 cai->cai_associativity); 1868 if (cp != NULL) 1869 cai->cai_associativity = cp->cai_associativity; 1870 else 1871 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1872 } 1873 1874 static void 1875 via_cpu_cacheinfo(struct cpu_info *ci) 1876 { 1877 struct x86_cache_info *cai; 1878 int family, model, stepping; 1879 u_int descs[4]; 1880 u_int lfunc; 1881 1882 family = (ci->ci_signature >> 8) & 15; 1883 model = CPUID2MODEL(ci->ci_signature); 1884 stepping = CPUID2STEPPING(ci->ci_signature); 1885 1886 /* 1887 * Determine the largest extended function value. 1888 */ 1889 x86_cpuid(0x80000000, descs); 1890 lfunc = descs[0]; 1891 1892 /* 1893 * Determine L1 cache/TLB info. 1894 */ 1895 if (lfunc < 0x80000005) { 1896 /* No L1 cache info available. */ 1897 return; 1898 } 1899 1900 x86_cpuid(0x80000005, descs); 1901 1902 cai = &ci->ci_cinfo[CAI_ITLB]; 1903 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1904 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1905 cai->cai_linesize = (4 * 1024); 1906 1907 cai = &ci->ci_cinfo[CAI_DTLB]; 1908 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1909 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1910 cai->cai_linesize = (4 * 1024); 1911 1912 cai = &ci->ci_cinfo[CAI_DCACHE]; 1913 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1914 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1915 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1916 if (model == 9 && stepping == 8) { 1917 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1918 cai->cai_associativity = 2; 1919 } 1920 1921 cai = &ci->ci_cinfo[CAI_ICACHE]; 1922 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1923 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1924 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1925 if (model == 9 && stepping == 8) { 1926 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1927 cai->cai_associativity = 2; 1928 } 1929 1930 /* 1931 * Determine L2 cache/TLB info. 1932 */ 1933 if (lfunc < 0x80000006) { 1934 /* No L2 cache info available. */ 1935 return; 1936 } 1937 1938 x86_cpuid(0x80000006, descs); 1939 1940 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1941 if (model >= 9) { 1942 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1943 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1944 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1945 } else { 1946 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1947 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1948 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1949 } 1950 } 1951 1952 static void 1953 x86_print_cacheinfo(struct cpu_info *ci) 1954 { 1955 const char *sep; 1956 1957 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 1958 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 1959 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 1960 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 1961 if (sep != NULL) 1962 aprint_verbose("\n"); 1963 } 1964 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 1965 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 1966 if (sep != NULL) 1967 aprint_verbose("\n"); 1968 } 1969 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 1970 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 1971 if (sep != NULL) 1972 aprint_verbose("\n"); 1973 } 1974 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 1975 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 1976 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 1977 if (sep != NULL) 1978 aprint_verbose("\n"); 1979 } 1980 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 1981 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 1982 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 1983 if (sep != NULL) 1984 aprint_verbose("\n"); 1985 } 1986 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 1987 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 1988 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 1989 if (sep != NULL) 1990 aprint_verbose("\n"); 1991 } 1992 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 1993 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 1994 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 1995 if (sep != NULL) 1996 aprint_verbose("\n"); 1997 } 1998 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 1999 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", NULL); 2000 if (sep != NULL) 2001 aprint_verbose("\n"); 2002 } 2003 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 2004 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", NULL); 2005 if (sep != NULL) 2006 aprint_verbose("\n"); 2007 } 2008 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 2009 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", NULL); 2010 if (sep != NULL) 2011 aprint_verbose("\n"); 2012 } 2013 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 2014 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", NULL); 2015 if (sep != NULL) 2016 aprint_verbose("\n"); 2017 } 2018 } 2019 2020 static void 2021 powernow_probe(struct cpu_info *ci) 2022 { 2023 uint32_t regs[4]; 2024 char buf[256]; 2025 2026 x86_cpuid(0x80000007, regs); 2027 2028 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2029 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 2030 buf); 2031 } 2032 2033 int 2034 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2035 { 2036 struct cpu_info ci; 2037 int loader_version, res; 2038 struct cpu_ucode_version versreq; 2039 2040 cpu_probe_base_features(&ci, "unknown"); 2041 2042 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2043 loader_version = CPU_UCODE_LOADER_AMD; 2044 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2045 loader_version = CPU_UCODE_LOADER_INTEL1; 2046 else 2047 return -1; 2048 2049 /* check whether the kernel understands this loader version */ 2050 versreq.loader_version = loader_version; 2051 versreq.data = 0; 2052 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2053 if (res) 2054 return -1; 2055 2056 switch (loader_version) { 2057 case CPU_UCODE_LOADER_AMD: 2058 if (uc->cpu_nr != -1) { 2059 /* printf? */ 2060 return -1; 2061 } 2062 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2063 break; 2064 case CPU_UCODE_LOADER_INTEL1: 2065 if (uc->cpu_nr == -1) 2066 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2067 else 2068 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2069 break; 2070 default: /* can't happen */ 2071 return -1; 2072 } 2073 uc->loader_version = loader_version; 2074 return 0; 2075 } 2076
Indexes created Thu Sep 25 16:09:42 GMT 2025