i386.c revision 1.37
1 /* $NetBSD: i386.c,v 1.37 2013/01/06 23:17:35 dsl Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.37 2013/01/06 23:17:35 dsl Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cacheinfo.h> 85 #include <x86/cpu_ucode.h> 86 87 #include "../cpuctl.h" 88 #include "cpuctl_i386.h" 89 90 /* Size of buffer for printing humanized numbers */ 91 #define HUMAN_BUFSIZE sizeof("999KB") 92 93 struct cpu_info { 94 const char *ci_dev; 95 int32_t ci_cpu_type; /* for cpu's without cpuid */ 96 int32_t ci_cpuid_level; /* highest cpuid supported */ 97 uint32_t ci_signature; /* X86 cpuid type */ 98 uint32_t ci_family; /* from ci_signature */ 99 uint32_t ci_model; /* from ci_signature */ 100 uint32_t ci_feat_val[5]; /* X86 CPUID feature bits 101 * [0] basic features %edx 102 * [1] basic features %ecx 103 * [2] extended features %edx 104 * [3] extended features %ecx 105 * [4] VIA padlock features 106 */ 107 uint32_t ci_cpu_class; /* CPU class */ 108 uint32_t ci_brand_id; /* Intel brand id */ 109 uint32_t ci_vendor[4]; /* vendor string */ 110 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 111 uint64_t ci_tsc_freq; /* cpu cycles/second */ 112 uint8_t ci_packageid; 113 uint8_t ci_coreid; 114 uint8_t ci_smtid; 115 uint32_t ci_initapicid; 116 struct x86_cache_info ci_cinfo[CAI_COUNT]; 117 void (*ci_info)(struct cpu_info *); 118 }; 119 120 struct cpu_nocpuid_nameclass { 121 int cpu_vendor; 122 const char *cpu_vendorname; 123 const char *cpu_name; 124 int cpu_class; 125 void (*cpu_setup)(struct cpu_info *); 126 void (*cpu_cacheinfo)(struct cpu_info *); 127 void (*cpu_info)(struct cpu_info *); 128 }; 129 130 struct cpu_cpuid_nameclass { 131 const char *cpu_id; 132 int cpu_vendor; 133 const char *cpu_vendorname; 134 struct cpu_cpuid_family { 135 int cpu_class; 136 const char *cpu_models[256]; 137 const char *cpu_model_default; 138 void (*cpu_setup)(struct cpu_info *); 139 void (*cpu_probe)(struct cpu_info *); 140 void (*cpu_info)(struct cpu_info *); 141 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 142 }; 143 144 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 145 146 /* 147 * Map Brand ID from cpuid instruction to brand name. 148 * Source: Intel Processor Identification and the CPUID Instruction, AP-485 149 */ 150 static const char * const i386_intel_brand[] = { 151 "", /* Unsupported */ 152 "Celeron", /* Intel (R) Celeron (TM) processor */ 153 "Pentium III", /* Intel (R) Pentium (R) III processor */ 154 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 155 "Pentium III", /* Intel (R) Pentium (R) III processor */ 156 "", /* Reserved */ 157 "Mobile Pentium III", /* Mobile Intel (R) Pentium (R) III processor-M */ 158 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 159 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 160 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 161 "Celeron", /* Intel (R) Celeron (TM) processor */ 162 "Xeon", /* Intel (R) Xeon (TM) processor */ 163 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 164 "", /* Reserved */ 165 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 166 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 167 }; 168 169 /* 170 * AMD processors don't have Brand IDs, so we need these names for probe. 171 */ 172 static const char * const amd_brand[] = { 173 "", 174 "Duron", /* AMD Duron(tm) */ 175 "MP", /* AMD Athlon(tm) MP */ 176 "XP", /* AMD Athlon(tm) XP */ 177 "4" /* AMD Athlon(tm) 4 */ 178 }; 179 180 static int cpu_vendor; 181 static char cpu_brand_string[49]; 182 static char amd_brand_name[48]; 183 static int use_pae, largepagesize; 184 185 static void via_cpu_probe(struct cpu_info *); 186 static void amd_family6_probe(struct cpu_info *); 187 static void intel_family_new_probe(struct cpu_info *); 188 static const char *intel_family6_name(struct cpu_info *); 189 static const char *amd_amd64_name(struct cpu_info *); 190 static void amd_family5_setup(struct cpu_info *); 191 static void transmeta_cpu_info(struct cpu_info *); 192 static const char *print_cache_config(struct cpu_info *, int, const char *, 193 const char *); 194 static const char *print_tlb_config(struct cpu_info *, int, const char *, 195 const char *); 196 static void amd_cpu_cacheinfo(struct cpu_info *); 197 static void via_cpu_cacheinfo(struct cpu_info *); 198 static void x86_print_cacheinfo(struct cpu_info *); 199 static const struct x86_cache_info *cache_info_lookup( 200 const struct x86_cache_info *, uint8_t); 201 static void cyrix6x86_cpu_setup(struct cpu_info *); 202 static void winchip_cpu_setup(struct cpu_info *); 203 static void amd_family5_setup(struct cpu_info *); 204 static void powernow_probe(struct cpu_info *); 205 206 /* 207 * Info for CTL_HW 208 */ 209 static char cpu_model[120]; 210 211 /* 212 * Note: these are just the ones that may not have a cpuid instruction. 213 * We deal with the rest in a different way. 214 */ 215 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 216 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 217 NULL, NULL, NULL }, /* CPU_386SX */ 218 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 219 NULL, NULL, NULL }, /* CPU_386 */ 220 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 221 NULL, NULL, NULL }, /* CPU_486SX */ 222 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 223 NULL, NULL, NULL }, /* CPU_486 */ 224 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 225 NULL, NULL, NULL }, /* CPU_486DLC */ 226 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 227 NULL, NULL, NULL }, /* CPU_6x86 */ 228 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 229 NULL, NULL, NULL }, /* CPU_NX586 */ 230 }; 231 232 const char *classnames[] = { 233 "386", 234 "486", 235 "586", 236 "686" 237 }; 238 239 const char *modifiers[] = { 240 "", 241 "OverDrive", 242 "Dual", 243 "" 244 }; 245 246 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 247 { 248 "GenuineIntel", 249 CPUVENDOR_INTEL, 250 "Intel", 251 /* Family 4 */ 252 { { 253 CPUCLASS_486, 254 { 255 "486DX", "486DX", "486SX", "486DX2", "486SL", 256 "486SX2", 0, "486DX2 W/B Enhanced", 257 "486DX4", 0, 0, 0, 0, 0, 0, 0, 258 }, 259 "486", /* Default */ 260 NULL, 261 NULL, 262 NULL, 263 }, 264 /* Family 5 */ 265 { 266 CPUCLASS_586, 267 { 268 "Pentium (P5 A-step)", "Pentium (P5)", 269 "Pentium (P54C)", "Pentium (P24T)", 270 "Pentium/MMX", "Pentium", 0, 271 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 272 0, 0, 0, 0, 0, 0, 0, 273 }, 274 "Pentium", /* Default */ 275 NULL, 276 NULL, 277 NULL, 278 }, 279 /* Family 6 */ 280 { 281 CPUCLASS_686, 282 { 283 /* Updated from intel_x86_325486.pdf Aug 2012 */ 284 [0x00] = "Pentium Pro (A-step)", 285 [0x01] = "Pentium Pro", 286 [0x03] = "Pentium II (Klamath)", 287 [0x04] = "Pentium Pro", 288 [0x05] = "Pentium II/Celeron (Deschutes)", 289 [0x06] = "Celeron (Mendocino)", 290 [0x07] = "Pentium III (Katmai)", 291 [0x08] = "Pentium III (Coppermine)", 292 [0x09] = "Pentium M (Banias)", 293 [0x0a] = "Pentium III Xeon (Cascades)", 294 [0x0b] = "Pentium III (Tualatin)", 295 [0x0d] = "Pentium M (Dothan)", 296 [0x0e] = "Pentium Core Duo", // "M (Yonah)", 297 [0x0f] = "Core 2", 298 [0x15] = "EP80579 Integrated Processor", 299 [0x16] = "Celeron (45nm)", 300 [0x17] = "Core 2 Extreme", 301 [0x1a] = "Core i7 (Nehalem)", 302 [0x1c] = "Atom Family", 303 [0x1d] = "XeonMP 74xx (Nehalem)", 304 [0x1e] = "Core i7 and i5", 305 [0x1f] = "Core i7 and i5", 306 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 307 [0x26] = "Atom Family", 308 [0x27] = "Atom Family", 309 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, i3 2xxx", 310 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 311 [0x2e] = "Xeon 75xx & 65xx", 312 [0x2d] = "Xeon E5 Sandy bridy family", 313 [0x2f] = "Xeon E7 family", 314 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, Ivy bridge", 315 [0x3c] = "Next Intel Core", 316 [0x3e] = "Next gen Xeon E5, Ivy bridge", 317 [0x45] = "Next Intel Core", 318 }, 319 "Pentium Pro, II or III", /* Default */ 320 NULL, 321 intel_family_new_probe, 322 NULL, 323 }, 324 /* Family > 6 */ 325 { 326 CPUCLASS_686, 327 { 328 0, 0, 0, 0, 0, 0, 0, 0, 329 0, 0, 0, 0, 0, 0, 0, 0, 330 }, 331 "Pentium 4", /* Default */ 332 NULL, 333 intel_family_new_probe, 334 NULL, 335 } } 336 }, 337 { 338 "AuthenticAMD", 339 CPUVENDOR_AMD, 340 "AMD", 341 /* Family 4 */ 342 { { 343 CPUCLASS_486, 344 { 345 0, 0, 0, "Am486DX2 W/T", 346 0, 0, 0, "Am486DX2 W/B", 347 "Am486DX4 W/T or Am5x86 W/T 150", 348 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 349 0, 0, "Am5x86 W/T 133/160", 350 "Am5x86 W/B 133/160", 351 }, 352 "Am486 or Am5x86", /* Default */ 353 NULL, 354 NULL, 355 NULL, 356 }, 357 /* Family 5 */ 358 { 359 CPUCLASS_586, 360 { 361 "K5", "K5", "K5", "K5", 0, 0, "K6", 362 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 363 "K6-2+/III+", 0, 0, 364 }, 365 "K5 or K6", /* Default */ 366 amd_family5_setup, 367 NULL, 368 amd_cpu_cacheinfo, 369 }, 370 /* Family 6 */ 371 { 372 CPUCLASS_686, 373 { 374 0, "Athlon Model 1", "Athlon Model 2", 375 "Duron", "Athlon Model 4 (Thunderbird)", 376 0, "Athlon", "Duron", "Athlon", 0, 377 "Athlon", 0, 0, 0, 0, 0, 378 }, 379 "K7 (Athlon)", /* Default */ 380 NULL, 381 amd_family6_probe, 382 amd_cpu_cacheinfo, 383 }, 384 /* Family > 6 */ 385 { 386 CPUCLASS_686, 387 { 388 0, 0, 0, 0, 0, 0, 0, 0, 389 0, 0, 0, 0, 0, 0, 0, 0, 390 }, 391 "Unknown K8 (Athlon)", /* Default */ 392 NULL, 393 amd_family6_probe, 394 amd_cpu_cacheinfo, 395 } } 396 }, 397 { 398 "CyrixInstead", 399 CPUVENDOR_CYRIX, 400 "Cyrix", 401 /* Family 4 */ 402 { { 403 CPUCLASS_486, 404 { 405 0, 0, 0, 406 "MediaGX", 407 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 408 }, 409 "486", /* Default */ 410 cyrix6x86_cpu_setup, /* XXX ?? */ 411 NULL, 412 NULL, 413 }, 414 /* Family 5 */ 415 { 416 CPUCLASS_586, 417 { 418 0, 0, "6x86", 0, 419 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 420 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 421 }, 422 "6x86", /* Default */ 423 cyrix6x86_cpu_setup, 424 NULL, 425 NULL, 426 }, 427 /* Family 6 */ 428 { 429 CPUCLASS_686, 430 { 431 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 432 0, 0, 0, 0, 0, 0, 0, 0, 433 }, 434 "6x86MX", /* Default */ 435 cyrix6x86_cpu_setup, 436 NULL, 437 NULL, 438 }, 439 /* Family > 6 */ 440 { 441 CPUCLASS_686, 442 { 443 0, 0, 0, 0, 0, 0, 0, 0, 444 0, 0, 0, 0, 0, 0, 0, 0, 445 }, 446 "Unknown 6x86MX", /* Default */ 447 NULL, 448 NULL, 449 NULL, 450 } } 451 }, 452 { /* MediaGX is now owned by National Semiconductor */ 453 "Geode by NSC", 454 CPUVENDOR_CYRIX, /* XXX */ 455 "National Semiconductor", 456 /* Family 4, NSC never had any of these */ 457 { { 458 CPUCLASS_486, 459 { 460 0, 0, 0, 0, 0, 0, 0, 0, 461 0, 0, 0, 0, 0, 0, 0, 0, 462 }, 463 "486 compatible", /* Default */ 464 NULL, 465 NULL, 466 NULL, 467 }, 468 /* Family 5: Geode family, formerly MediaGX */ 469 { 470 CPUCLASS_586, 471 { 472 0, 0, 0, 0, 473 "Geode GX1", 474 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 475 }, 476 "Geode", /* Default */ 477 cyrix6x86_cpu_setup, 478 NULL, 479 amd_cpu_cacheinfo, 480 }, 481 /* Family 6, not yet available from NSC */ 482 { 483 CPUCLASS_686, 484 { 485 0, 0, 0, 0, 0, 0, 0, 0, 486 0, 0, 0, 0, 0, 0, 0, 0, 487 }, 488 "Pentium Pro compatible", /* Default */ 489 NULL, 490 NULL, 491 NULL, 492 }, 493 /* Family > 6, not yet available from NSC */ 494 { 495 CPUCLASS_686, 496 { 497 0, 0, 0, 0, 0, 0, 0, 0, 498 0, 0, 0, 0, 0, 0, 0, 0, 499 }, 500 "Pentium Pro compatible", /* Default */ 501 NULL, 502 NULL, 503 NULL, 504 } } 505 }, 506 { 507 "CentaurHauls", 508 CPUVENDOR_IDT, 509 "IDT", 510 /* Family 4, IDT never had any of these */ 511 { { 512 CPUCLASS_486, 513 { 514 0, 0, 0, 0, 0, 0, 0, 0, 515 0, 0, 0, 0, 0, 0, 0, 0, 516 }, 517 "486 compatible", /* Default */ 518 NULL, 519 NULL, 520 NULL, 521 }, 522 /* Family 5 */ 523 { 524 CPUCLASS_586, 525 { 526 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 527 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 528 }, 529 "WinChip", /* Default */ 530 winchip_cpu_setup, 531 NULL, 532 NULL, 533 }, 534 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 535 { 536 CPUCLASS_686, 537 { 538 0, 0, 0, 0, 0, 0, "C3 Samuel", 539 "C3 Samuel 2/Ezra", "C3 Ezra-T", 540 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 541 0, "VIA Nano", 542 }, 543 "Unknown VIA/IDT", /* Default */ 544 NULL, 545 via_cpu_probe, 546 via_cpu_cacheinfo, 547 }, 548 /* Family > 6, not yet available from VIA */ 549 { 550 CPUCLASS_686, 551 { 552 0, 0, 0, 0, 0, 0, 0, 0, 553 0, 0, 0, 0, 0, 0, 0, 0, 554 }, 555 "Pentium Pro compatible", /* Default */ 556 NULL, 557 NULL, 558 NULL, 559 } } 560 }, 561 { 562 "GenuineTMx86", 563 CPUVENDOR_TRANSMETA, 564 "Transmeta", 565 /* Family 4, Transmeta never had any of these */ 566 { { 567 CPUCLASS_486, 568 { 569 0, 0, 0, 0, 0, 0, 0, 0, 570 0, 0, 0, 0, 0, 0, 0, 0, 571 }, 572 "486 compatible", /* Default */ 573 NULL, 574 NULL, 575 NULL, 576 }, 577 /* Family 5 */ 578 { 579 CPUCLASS_586, 580 { 581 0, 0, 0, 0, 0, 0, 0, 0, 582 0, 0, 0, 0, 0, 0, 0, 0, 583 }, 584 "Crusoe", /* Default */ 585 NULL, 586 NULL, 587 transmeta_cpu_info, 588 }, 589 /* Family 6, not yet available from Transmeta */ 590 { 591 CPUCLASS_686, 592 { 593 0, 0, 0, 0, 0, 0, 0, 0, 594 0, 0, 0, 0, 0, 0, 0, 0, 595 }, 596 "Pentium Pro compatible", /* Default */ 597 NULL, 598 NULL, 599 NULL, 600 }, 601 /* Family > 6, not yet available from Transmeta */ 602 { 603 CPUCLASS_686, 604 { 605 0, 0, 0, 0, 0, 0, 0, 0, 606 0, 0, 0, 0, 0, 0, 0, 0, 607 }, 608 "Pentium Pro compatible", /* Default */ 609 NULL, 610 NULL, 611 NULL, 612 } } 613 } 614 }; 615 616 /* 617 * disable the TSC such that we don't use the TSC in microtime(9) 618 * because some CPUs got the implementation wrong. 619 */ 620 static void 621 disable_tsc(struct cpu_info *ci) 622 { 623 if (ci->ci_feat_val[0] & CPUID_TSC) { 624 ci->ci_feat_val[0] &= ~CPUID_TSC; 625 aprint_error("WARNING: broken TSC disabled\n"); 626 } 627 } 628 629 static void 630 cyrix6x86_cpu_setup(struct cpu_info *ci) 631 { 632 633 /* 634 * Do not disable the TSC on the Geode GX, it's reported to 635 * work fine. 636 */ 637 if (ci->ci_signature != 0x552) 638 disable_tsc(ci); 639 } 640 641 void 642 winchip_cpu_setup(struct cpu_info *ci) 643 { 644 switch (ci->ci_model) { 645 case 4: /* WinChip C6 */ 646 disable_tsc(ci); 647 } 648 } 649 650 651 static void 652 identifycpu_cpuids(struct cpu_info *ci) 653 { 654 const char *cpuname = ci->ci_dev; 655 u_int lp_max = 1; /* logical processors per package */ 656 u_int smt_max; /* smt per core */ 657 u_int core_max = 1; /* core per package */ 658 u_int smt_bits, core_bits; 659 uint32_t descs[4]; 660 661 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 662 ci->ci_packageid = ci->ci_initapicid; 663 ci->ci_coreid = 0; 664 ci->ci_smtid = 0; 665 if (cpu_vendor != CPUVENDOR_INTEL) { 666 return; 667 } 668 669 /* 670 * 253668.pdf 7.10.2 671 */ 672 673 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 674 x86_cpuid(1, descs); 675 lp_max = (descs[1] >> 16) & 0xff; 676 } 677 x86_cpuid(0, descs); 678 if (descs[0] >= 4) { 679 x86_cpuid2(4, 0, descs); 680 core_max = (descs[0] >> 26) + 1; 681 } 682 assert(lp_max >= core_max); 683 smt_max = lp_max / core_max; 684 smt_bits = ilog2(smt_max - 1) + 1; 685 core_bits = ilog2(core_max - 1) + 1; 686 if (smt_bits + core_bits) { 687 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 688 } 689 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 690 ci->ci_packageid); 691 if (core_bits) { 692 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 693 694 ci->ci_coreid = 695 __SHIFTOUT(ci->ci_initapicid, core_mask); 696 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 697 } 698 if (smt_bits) { 699 u_int smt_mask = __BITS((int)0, (int)(smt_bits - 1)); 700 701 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, smt_mask); 702 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 703 } 704 } 705 706 static void 707 via_cpu_probe(struct cpu_info *ci) 708 { 709 u_int stepping = CPUID2STEPPING(ci->ci_signature); 710 u_int descs[4]; 711 u_int lfunc; 712 713 /* 714 * Determine the largest extended function value. 715 */ 716 x86_cpuid(0x80000000, descs); 717 lfunc = descs[0]; 718 719 /* 720 * Determine the extended feature flags. 721 */ 722 if (lfunc >= 0x80000001) { 723 x86_cpuid(0x80000001, descs); 724 ci->ci_feat_val[2] |= descs[3]; 725 } 726 727 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 728 return; 729 730 /* Nehemiah or Esther */ 731 x86_cpuid(0xc0000000, descs); 732 lfunc = descs[0]; 733 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 734 return; 735 736 x86_cpuid(0xc0000001, descs); 737 lfunc = descs[3]; 738 ci->ci_feat_val[4] = lfunc; 739 } 740 741 static const char * 742 intel_family6_name(struct cpu_info *ci) 743 { 744 const char *ret = NULL; 745 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 746 747 if (ci->ci_model == 5) { 748 switch (l2cache) { 749 case 0: 750 case 128 * 1024: 751 ret = "Celeron (Covington)"; 752 break; 753 case 256 * 1024: 754 ret = "Mobile Pentium II (Dixon)"; 755 break; 756 case 512 * 1024: 757 ret = "Pentium II"; 758 break; 759 case 1 * 1024 * 1024: 760 case 2 * 1024 * 1024: 761 ret = "Pentium II Xeon"; 762 break; 763 } 764 } else if (ci->ci_model == 6) { 765 switch (l2cache) { 766 case 256 * 1024: 767 case 512 * 1024: 768 ret = "Mobile Pentium II"; 769 break; 770 } 771 } else if (ci->ci_model == 7) { 772 switch (l2cache) { 773 case 512 * 1024: 774 ret = "Pentium III"; 775 break; 776 case 1 * 1024 * 1024: 777 case 2 * 1024 * 1024: 778 ret = "Pentium III Xeon"; 779 break; 780 } 781 } else if (ci->ci_model >= 8) { 782 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 783 switch (ci->ci_brand_id) { 784 case 0x3: 785 if (ci->ci_signature == 0x6B1) 786 ret = "Celeron"; 787 break; 788 case 0x8: 789 if (ci->ci_signature >= 0xF13) 790 ret = "genuine processor"; 791 break; 792 case 0xB: 793 if (ci->ci_signature >= 0xF13) 794 ret = "Xeon MP"; 795 break; 796 case 0xE: 797 if (ci->ci_signature < 0xF13) 798 ret = "Xeon"; 799 break; 800 } 801 if (ret == NULL) 802 ret = i386_intel_brand[ci->ci_brand_id]; 803 } 804 } 805 806 return ret; 807 } 808 809 /* 810 * Identify AMD64 CPU names from cpuid. 811 * 812 * Based on: 813 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 814 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 815 * "Revision Guide for AMD NPT Family 0Fh Processors" 816 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 817 * and other miscellaneous reports. 818 * 819 * This is all rather pointless, these are cross 'brand' since the raw 820 * silicon is shared. 821 */ 822 static const char * 823 amd_amd64_name(struct cpu_info *ci) 824 { 825 static char family_str[32]; 826 827 /* Only called if family >= 15 */ 828 829 switch (ci->ci_family) { 830 case 15: 831 switch (ci->ci_model) { 832 case 0x21: /* rev JH-E1/E6 */ 833 case 0x41: /* rev JH-F2 */ 834 return "Dual-Core Opteron"; 835 case 0x23: /* rev JH-E6 (Toledo) */ 836 return "Dual-Core Opteron or Athlon 64 X2"; 837 case 0x43: /* rev JH-F2 (Windsor) */ 838 return "Athlon 64 FX or Athlon 64 X2"; 839 case 0x24: /* rev SH-E5 (Lancaster?) */ 840 return "Mobile Athlon 64 or Turion 64"; 841 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 842 return "Opteron or Athlon 64 FX"; 843 case 0x15: /* rev SH-D0 */ 844 case 0x25: /* rev SH-E4 */ 845 return "Opteron"; 846 case 0x27: /* rev DH-E4, SH-E4 */ 847 return "Athlon 64 or Athlon 64 FX or Opteron"; 848 case 0x48: /* rev BH-F2 */ 849 return "Turion 64 X2"; 850 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 851 case 0x07: /* rev SH-CG (ClawHammer) */ 852 case 0x0b: /* rev CH-CG */ 853 case 0x14: /* rev SH-D0 */ 854 case 0x17: /* rev SH-D0 */ 855 case 0x1b: /* rev CH-D0 */ 856 return "Athlon 64"; 857 case 0x2b: /* rev BH-E4 (Manchester) */ 858 case 0x4b: /* rev BH-F2 (Windsor) */ 859 return "Athlon 64 X2"; 860 case 0x6b: /* rev BH-G1 (Brisbane) */ 861 return "Athlon X2 or Athlon 64 X2"; 862 case 0x08: /* rev CH-CG */ 863 case 0x0c: /* rev DH-CG (Newcastle) */ 864 case 0x0e: /* rev DH-CG (Newcastle?) */ 865 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 866 case 0x18: /* rev CH-D0 */ 867 case 0x1c: /* rev DH-D0 (Winchester) */ 868 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 869 case 0x2c: /* rev DH-E3/E6 */ 870 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 871 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 872 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 873 case 0x6f: /* rev DH-G1 */ 874 return "Athlon 64 or Sempron"; 875 default: 876 break; 877 } 878 return "Unknown AMD64 CPU"; 879 880 #if 0 881 case 16: 882 return "Family 10h"; 883 case 17: 884 return "Family 11h"; 885 case 18: 886 return "Family 12h"; 887 case 19: 888 return "Family 14h"; 889 case 20: 890 return "Family 15h"; 891 #endif 892 893 default: 894 break; 895 } 896 897 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 898 return family_str; 899 } 900 901 static void 902 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 903 { 904 const struct x86_cache_info *cai; 905 u_int descs[4]; 906 int iterations, i, j; 907 uint8_t desc; 908 uint32_t brand[12]; 909 910 memset(ci, 0, sizeof(*ci)); 911 ci->ci_dev = cpuname; 912 913 ci->ci_cpu_type = x86_identify(); 914 if (ci->ci_cpu_type >= 0) { 915 /* Old pre-cpuid instruction cpu */ 916 ci->ci_cpuid_level = -1; 917 return; 918 } 919 920 x86_cpuid(0, descs); 921 ci->ci_cpuid_level = descs[0]; 922 ci->ci_vendor[0] = descs[1]; 923 ci->ci_vendor[2] = descs[2]; 924 ci->ci_vendor[1] = descs[3]; 925 ci->ci_vendor[3] = 0; 926 927 x86_cpuid(0x80000000, brand); 928 if (brand[0] >= 0x80000004) { 929 x86_cpuid(0x80000002, brand); 930 x86_cpuid(0x80000003, brand + 4); 931 x86_cpuid(0x80000004, brand + 8); 932 for (i = 0; i < 48; i++) 933 if (((char *) brand)[i] != ' ') 934 break; 935 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 936 } 937 938 if (ci->ci_cpuid_level < 1) 939 return; 940 941 x86_cpuid(1, descs); 942 ci->ci_signature = descs[0]; 943 944 /* Extract full family/model values */ 945 ci->ci_family = CPUID2FAMILY(ci->ci_signature); 946 ci->ci_model = CPUID2MODEL(ci->ci_signature); 947 if (ci->ci_family == 15) 948 ci->ci_family += CPUID2EXTFAMILY(ci->ci_signature); 949 if (ci->ci_family == 6 || ci->ci_family == 15) 950 ci->ci_model += CPUID2EXTMODEL(ci->ci_signature) << 4; 951 952 /* Brand is low order 8 bits of ebx */ 953 ci->ci_brand_id = descs[1] & 0xff; 954 ci->ci_initapicid = (descs[1] >> 24) & 0xff; 955 956 ci->ci_feat_val[1] = descs[2]; 957 ci->ci_feat_val[0] = descs[3]; 958 959 if (ci->ci_cpuid_level < 2) 960 return; 961 962 /* 963 * Parse the cache info from `cpuid', if we have it. 964 * XXX This is kinda ugly, but hey, so is the architecture... 965 */ 966 967 x86_cpuid(2, descs); 968 969 iterations = descs[0] & 0xff; 970 while (iterations-- > 0) { 971 for (i = 0; i < 4; i++) { 972 if (descs[i] & 0x80000000) 973 continue; 974 for (j = 0; j < 4; j++) { 975 if (i == 0 && j == 0) 976 continue; 977 desc = (descs[i] >> (j * 8)) & 0xff; 978 if (desc == 0) 979 continue; 980 cai = cache_info_lookup(intel_cpuid_cache_info, 981 desc); 982 if (cai != NULL) 983 ci->ci_cinfo[cai->cai_index] = *cai; 984 } 985 } 986 x86_cpuid(2, descs); 987 } 988 989 if (ci->ci_cpuid_level < 3) 990 return; 991 992 /* 993 * If the processor serial number misfeature is present and supported, 994 * extract it here. 995 */ 996 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 997 ci->ci_cpu_serial[0] = ci->ci_signature; 998 x86_cpuid(3, descs); 999 ci->ci_cpu_serial[2] = descs[2]; 1000 ci->ci_cpu_serial[1] = descs[3]; 1001 } 1002 } 1003 1004 static void 1005 cpu_probe_features(struct cpu_info *ci) 1006 { 1007 const struct cpu_cpuid_nameclass *cpup = NULL; 1008 unsigned int i; 1009 1010 if (ci->ci_cpuid_level < 1) 1011 return; 1012 1013 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1014 if (!strncmp((char *)ci->ci_vendor, 1015 i386_cpuid_cpus[i].cpu_id, 12)) { 1016 cpup = &i386_cpuid_cpus[i]; 1017 break; 1018 } 1019 } 1020 1021 if (cpup == NULL) 1022 return; 1023 1024 i = ci->ci_family - CPU_MINFAMILY; 1025 1026 if (i >= __arraycount(cpup->cpu_family)) 1027 i = __arraycount(cpup->cpu_family) - 1; 1028 1029 if (cpup->cpu_family[i].cpu_probe == NULL) 1030 return; 1031 1032 (*cpup->cpu_family[i].cpu_probe)(ci); 1033 } 1034 1035 static void 1036 intel_family_new_probe(struct cpu_info *ci) 1037 { 1038 uint32_t descs[4]; 1039 1040 x86_cpuid(0x80000000, descs); 1041 1042 /* 1043 * Determine extended feature flags. 1044 */ 1045 if (descs[0] >= 0x80000001) { 1046 x86_cpuid(0x80000001, descs); 1047 ci->ci_feat_val[2] |= descs[3]; 1048 ci->ci_feat_val[3] |= descs[2]; 1049 } 1050 } 1051 1052 static void 1053 amd_family6_probe(struct cpu_info *ci) 1054 { 1055 uint32_t descs[4]; 1056 char *p; 1057 size_t i; 1058 1059 x86_cpuid(0x80000000, descs); 1060 1061 /* 1062 * Determine the extended feature flags. 1063 */ 1064 if (descs[0] >= 0x80000001) { 1065 x86_cpuid(0x80000001, descs); 1066 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 1067 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 1068 } 1069 1070 if (*cpu_brand_string == '\0') 1071 return; 1072 1073 for (i = 1; i < __arraycount(amd_brand); i++) 1074 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 1075 ci->ci_brand_id = i; 1076 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 1077 break; 1078 } 1079 } 1080 1081 static void 1082 amd_family5_setup(struct cpu_info *ci) 1083 { 1084 1085 switch (ci->ci_model) { 1086 case 0: /* AMD-K5 Model 0 */ 1087 /* 1088 * According to the AMD Processor Recognition App Note, 1089 * the AMD-K5 Model 0 uses the wrong bit to indicate 1090 * support for global PTEs, instead using bit 9 (APIC) 1091 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 1092 */ 1093 if (ci->ci_feat_val[0] & CPUID_APIC) 1094 ci->ci_feat_val[0] = 1095 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 1096 /* 1097 * XXX But pmap_pg_g is already initialized -- need to kick 1098 * XXX the pmap somehow. How does the MP branch do this? 1099 */ 1100 break; 1101 } 1102 } 1103 1104 static void 1105 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1106 { 1107 u_int descs[4]; 1108 1109 x86_cpuid(0x80860007, descs); 1110 *frequency = descs[0]; 1111 *voltage = descs[1]; 1112 *percentage = descs[2]; 1113 } 1114 1115 static void 1116 transmeta_cpu_info(struct cpu_info *ci) 1117 { 1118 u_int descs[4], nreg; 1119 u_int frequency, voltage, percentage; 1120 1121 x86_cpuid(0x80860000, descs); 1122 nreg = descs[0]; 1123 if (nreg >= 0x80860001) { 1124 x86_cpuid(0x80860001, descs); 1125 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1126 (descs[1] >> 24) & 0xff, 1127 (descs[1] >> 16) & 0xff, 1128 (descs[1] >> 8) & 0xff, 1129 descs[1] & 0xff); 1130 } 1131 if (nreg >= 0x80860002) { 1132 x86_cpuid(0x80860002, descs); 1133 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1134 (descs[1] >> 24) & 0xff, 1135 (descs[1] >> 16) & 0xff, 1136 (descs[1] >> 8) & 0xff, 1137 descs[1] & 0xff, 1138 descs[2]); 1139 } 1140 if (nreg >= 0x80860006) { 1141 union { 1142 char text[65]; 1143 u_int descs[4][4]; 1144 } info; 1145 int i; 1146 1147 for (i=0; i<4; i++) { 1148 x86_cpuid(0x80860003 + i, info.descs[i]); 1149 } 1150 info.text[64] = '\0'; 1151 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1152 } 1153 1154 if (nreg >= 0x80860007) { 1155 tmx86_get_longrun_status(&frequency, 1156 &voltage, &percentage); 1157 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1158 frequency, voltage, percentage); 1159 } 1160 } 1161 1162 void 1163 identifycpu(int fd, const char *cpuname) 1164 { 1165 const char *name = "", *modifier, *vendorname, *brand = ""; 1166 int class = CPUCLASS_386; 1167 unsigned int i; 1168 int modif, family; 1169 const struct cpu_cpuid_nameclass *cpup = NULL; 1170 const struct cpu_cpuid_family *cpufam; 1171 const char *feature_str[5]; 1172 struct cpu_info *ci, cistore; 1173 size_t sz; 1174 char buf[512]; 1175 char *bp; 1176 struct cpu_ucode_version ucode; 1177 union { 1178 struct cpu_ucode_version_amd amd; 1179 struct cpu_ucode_version_intel1 intel1; 1180 } ucvers; 1181 1182 ci = &cistore; 1183 cpu_probe_base_features(ci, cpuname); 1184 cpu_probe_features(ci); 1185 1186 if (ci->ci_cpu_type >= 0) { 1187 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1188 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1189 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1190 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1191 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1192 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1193 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1194 modifier = ""; 1195 } else { 1196 modif = (ci->ci_signature >> 12) & 0x3; 1197 family = ci->ci_family; 1198 if (family < CPU_MINFAMILY) 1199 errx(1, "identifycpu: strange family value"); 1200 if (family > CPU_MAXFAMILY) 1201 family = CPU_MAXFAMILY; 1202 1203 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1204 if (!strncmp((char *)ci->ci_vendor, 1205 i386_cpuid_cpus[i].cpu_id, 12)) { 1206 cpup = &i386_cpuid_cpus[i]; 1207 break; 1208 } 1209 } 1210 1211 if (cpup == NULL) { 1212 cpu_vendor = CPUVENDOR_UNKNOWN; 1213 if (ci->ci_vendor[0] != '\0') 1214 vendorname = (char *)&ci->ci_vendor[0]; 1215 else 1216 vendorname = "Unknown"; 1217 class = family - 3; 1218 modifier = ""; 1219 name = ""; 1220 ci->ci_info = NULL; 1221 } else { 1222 cpu_vendor = cpup->cpu_vendor; 1223 vendorname = cpup->cpu_vendorname; 1224 modifier = modifiers[modif]; 1225 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 1226 name = cpufam->cpu_models[ci->ci_model]; 1227 if (name == NULL || *name == '\0') 1228 name = cpufam->cpu_model_default; 1229 class = cpufam->cpu_class; 1230 ci->ci_info = cpufam->cpu_info; 1231 1232 if (cpu_vendor == CPUVENDOR_INTEL) { 1233 if (ci->ci_family == 6 && ci->ci_model >= 5) { 1234 const char *tmp; 1235 tmp = intel_family6_name(ci); 1236 if (tmp != NULL) 1237 name = tmp; 1238 } 1239 if (ci->ci_family == 15 && 1240 ci->ci_brand_id < 1241 __arraycount(i386_intel_brand) && 1242 i386_intel_brand[ci->ci_brand_id]) 1243 name = 1244 i386_intel_brand[ci->ci_brand_id]; 1245 } 1246 1247 if (cpu_vendor == CPUVENDOR_AMD) { 1248 if (ci->ci_family == 6 && ci->ci_model >= 6) { 1249 if (ci->ci_brand_id == 1) 1250 /* 1251 * It's Duron. We override the 1252 * name, since it might have 1253 * been misidentified as Athlon. 1254 */ 1255 name = 1256 amd_brand[ci->ci_brand_id]; 1257 else 1258 brand = amd_brand_name; 1259 } 1260 if (CPUID2FAMILY(ci->ci_signature) == 0xf) { 1261 /* Identify AMD64 CPU names. */ 1262 const char *tmp; 1263 tmp = amd_amd64_name(ci); 1264 if (tmp != NULL) 1265 name = tmp; 1266 } 1267 } 1268 1269 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 1270 vendorname = "VIA"; 1271 } 1272 } 1273 1274 ci->ci_cpu_class = class; 1275 1276 sz = sizeof(ci->ci_tsc_freq); 1277 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 1278 sz = sizeof(use_pae); 1279 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 1280 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 1281 1282 snprintf(cpu_model, sizeof(cpu_model), "%s%s%s%s%s%s%s (%s-class)", 1283 vendorname, 1284 *modifier ? " " : "", modifier, 1285 *name ? " " : "", name, 1286 *brand ? " " : "", brand, 1287 classnames[class]); 1288 aprint_normal("%s: %s", cpuname, cpu_model); 1289 1290 if (ci->ci_tsc_freq != 0) 1291 aprint_normal(", %ju.%02ju MHz", 1292 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 1293 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 1294 if (ci->ci_signature != 0) 1295 aprint_normal(", id 0x%x", ci->ci_signature); 1296 aprint_normal("\n"); 1297 1298 if (ci->ci_info) 1299 (*ci->ci_info)(ci); 1300 1301 /* 1302 * display CPU feature flags 1303 */ 1304 1305 #define MAX_FEATURE_LEN 60 /* XXX Need to find a better way to set this */ 1306 1307 feature_str[0] = CPUID_FLAGS1; 1308 feature_str[1] = CPUID2_FLAGS1; 1309 feature_str[2] = CPUID_EXT_FLAGS; 1310 feature_str[3] = NULL; 1311 feature_str[4] = NULL; 1312 1313 switch (cpu_vendor) { 1314 case CPUVENDOR_AMD: 1315 feature_str[3] = CPUID_AMD_FLAGS4; 1316 break; 1317 case CPUVENDOR_INTEL: 1318 feature_str[2] = CPUID_INTEL_EXT_FLAGS; 1319 feature_str[3] = CPUID_INTEL_FLAGS4; 1320 break; 1321 case CPUVENDOR_IDT: 1322 feature_str[4] = CPUID_FLAGS_PADLOCK; 1323 break; 1324 default: 1325 break; 1326 } 1327 1328 for (i = 0; i <= 4; i++) { 1329 if (ci->ci_feat_val[i] && feature_str[i] != NULL) { 1330 snprintb_m(buf, sizeof(buf), feature_str[i], 1331 ci->ci_feat_val[i], MAX_FEATURE_LEN); 1332 bp = buf; 1333 while (*bp != '\0') { 1334 aprint_verbose("%s: %sfeatures%c %s\n", 1335 cpuname, (i == 4)?"padlock ":"", 1336 (i == 4 || i == 0)?' ':'1' + i, bp); 1337 bp += strlen(bp) + 1; 1338 } 1339 } 1340 } 1341 1342 if (*cpu_brand_string != '\0') 1343 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 1344 1345 x86_print_cacheinfo(ci); 1346 1347 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 1348 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 1349 cpuname, 1350 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 1351 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 1352 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 1353 } 1354 1355 if (ci->ci_cpu_class == CPUCLASS_386) { 1356 errx(1, "NetBSD requires an 80486 or later processor"); 1357 } 1358 1359 if (ci->ci_cpu_type == CPU_486DLC) { 1360 #ifndef CYRIX_CACHE_WORKS 1361 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 1362 #else 1363 #ifndef CYRIX_CACHE_REALLY_WORKS 1364 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 1365 #else 1366 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 1367 #endif 1368 #endif 1369 } 1370 1371 /* 1372 * Everything past this point requires a Pentium or later. 1373 */ 1374 if (ci->ci_cpuid_level < 0) 1375 return; 1376 1377 identifycpu_cpuids(ci); 1378 1379 #ifdef INTEL_CORETEMP 1380 if (cpu_vendor == CPUVENDOR_INTEL && ci->ci_cpuid_level >= 0x06) 1381 coretemp_register(ci); 1382 #endif 1383 1384 if (cpu_vendor == CPUVENDOR_AMD) { 1385 uint32_t data[4]; 1386 1387 x86_cpuid(0x80000000, data); 1388 if (data[0] >= 0x80000007) 1389 powernow_probe(ci); 1390 1391 if ((data[0] >= 0x8000000a) 1392 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 1393 1394 x86_cpuid(0x8000000a, data); 1395 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 1396 data[0] & 0xf); 1397 aprint_verbose("%s: SVM NASID %d\n", cpuname, data[1]); 1398 snprintb_m(buf, sizeof(buf), CPUID_AMD_SVM_FLAGS, 1399 data[3], MAX_FEATURE_LEN); 1400 bp = buf; 1401 while (*bp != '\0') { 1402 aprint_verbose("%s: SVM features %s\n", 1403 cpuname, bp); 1404 bp += strlen(bp) + 1; 1405 } 1406 } 1407 } 1408 1409 #ifdef INTEL_ONDEMAND_CLOCKMOD 1410 clockmod_init(); 1411 #endif 1412 1413 aprint_normal_dev(ci->ci_dev, "family %02x model %02x stepping %02x\n", 1414 ci->ci_family, ci->ci_model, CPUID2STEPPING(ci->ci_signature)); 1415 1416 if (cpu_vendor == CPUVENDOR_AMD) 1417 ucode.loader_version = CPU_UCODE_LOADER_AMD; 1418 else if (cpu_vendor == CPUVENDOR_INTEL) 1419 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 1420 else 1421 return; 1422 1423 ucode.data = &ucvers; 1424 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 1425 #ifdef __i386__ 1426 struct cpu_ucode_version_64 ucode_64; 1427 if (errno != ENOTTY) 1428 return; 1429 /* Try the 64 bit ioctl */ 1430 memset(&ucode_64, 0, sizeof ucode_64); 1431 ucode_64.data = &ucvers; 1432 ucode_64.loader_version = ucode.loader_version; 1433 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 1434 return; 1435 #endif 1436 } 1437 1438 if (cpu_vendor == CPUVENDOR_AMD) 1439 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 1440 else if (cpu_vendor == CPUVENDOR_INTEL) 1441 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 1442 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 1443 } 1444 1445 static const char * 1446 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 1447 const char *sep) 1448 { 1449 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1450 char human_num[HUMAN_BUFSIZE]; 1451 1452 if (cai->cai_totalsize == 0) 1453 return sep; 1454 1455 if (sep == NULL) 1456 aprint_verbose_dev(ci->ci_dev, ""); 1457 else 1458 aprint_verbose("%s", sep); 1459 if (name != NULL) 1460 aprint_verbose("%s ", name); 1461 1462 if (cai->cai_string != NULL) { 1463 aprint_verbose("%s ", cai->cai_string); 1464 } else { 1465 (void)humanize_number(human_num, sizeof(human_num), 1466 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 1467 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 1468 } 1469 switch (cai->cai_associativity) { 1470 case 0: 1471 aprint_verbose("disabled"); 1472 break; 1473 case 1: 1474 aprint_verbose("direct-mapped"); 1475 break; 1476 case 0xff: 1477 aprint_verbose("fully associative"); 1478 break; 1479 default: 1480 aprint_verbose("%d-way", cai->cai_associativity); 1481 break; 1482 } 1483 return ", "; 1484 } 1485 1486 static const char * 1487 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 1488 const char *sep) 1489 { 1490 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1491 char human_num[HUMAN_BUFSIZE]; 1492 1493 if (cai->cai_totalsize == 0) 1494 return sep; 1495 1496 if (sep == NULL) 1497 aprint_verbose_dev(ci->ci_dev, ""); 1498 else 1499 aprint_verbose("%s", sep); 1500 if (name != NULL) 1501 aprint_verbose("%s ", name); 1502 1503 if (cai->cai_string != NULL) { 1504 aprint_verbose("%s", cai->cai_string); 1505 } else { 1506 (void)humanize_number(human_num, sizeof(human_num), 1507 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 1508 aprint_verbose("%d %s entries ", cai->cai_totalsize, 1509 human_num); 1510 switch (cai->cai_associativity) { 1511 case 0: 1512 aprint_verbose("disabled"); 1513 break; 1514 case 1: 1515 aprint_verbose("direct-mapped"); 1516 break; 1517 case 0xff: 1518 aprint_verbose("fully associative"); 1519 break; 1520 default: 1521 aprint_verbose("%d-way", cai->cai_associativity); 1522 break; 1523 } 1524 } 1525 return ", "; 1526 } 1527 1528 static const struct x86_cache_info * 1529 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 1530 { 1531 int i; 1532 1533 for (i = 0; cai[i].cai_desc != 0; i++) { 1534 if (cai[i].cai_desc == desc) 1535 return (&cai[i]); 1536 } 1537 1538 return (NULL); 1539 } 1540 1541 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 1542 AMD_L2CACHE_INFO; 1543 1544 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 1545 AMD_L3CACHE_INFO; 1546 1547 static void 1548 amd_cpu_cacheinfo(struct cpu_info *ci) 1549 { 1550 const struct x86_cache_info *cp; 1551 struct x86_cache_info *cai; 1552 u_int descs[4]; 1553 u_int lfunc; 1554 1555 /* 1556 * K5 model 0 has none of this info. 1557 */ 1558 if (ci->ci_family == 5 && ci->ci_model == 0) 1559 return; 1560 1561 /* 1562 * Determine the largest extended function value. 1563 */ 1564 x86_cpuid(0x80000000, descs); 1565 lfunc = descs[0]; 1566 1567 /* 1568 * Determine L1 cache/TLB info. 1569 */ 1570 if (lfunc < 0x80000005) { 1571 /* No L1 cache info available. */ 1572 return; 1573 } 1574 1575 x86_cpuid(0x80000005, descs); 1576 1577 /* 1578 * K6-III and higher have large page TLBs. 1579 */ 1580 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1581 cai = &ci->ci_cinfo[CAI_ITLB2]; 1582 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1583 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1584 cai->cai_linesize = largepagesize; 1585 1586 cai = &ci->ci_cinfo[CAI_DTLB2]; 1587 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1588 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1589 cai->cai_linesize = largepagesize; 1590 } 1591 1592 cai = &ci->ci_cinfo[CAI_ITLB]; 1593 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1594 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1595 cai->cai_linesize = (4 * 1024); 1596 1597 cai = &ci->ci_cinfo[CAI_DTLB]; 1598 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1599 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1600 cai->cai_linesize = (4 * 1024); 1601 1602 cai = &ci->ci_cinfo[CAI_DCACHE]; 1603 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1604 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1605 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1606 1607 cai = &ci->ci_cinfo[CAI_ICACHE]; 1608 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1609 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1610 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1611 1612 /* 1613 * Determine L2 cache/TLB info. 1614 */ 1615 if (lfunc < 0x80000006) { 1616 /* No L2 cache info available. */ 1617 return; 1618 } 1619 1620 x86_cpuid(0x80000006, descs); 1621 1622 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1623 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1624 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1625 cai->cai_linesize = (4 * 1024); 1626 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1627 cai->cai_associativity); 1628 if (cp != NULL) 1629 cai->cai_associativity = cp->cai_associativity; 1630 else 1631 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1632 1633 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1634 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1635 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1636 cai->cai_linesize = largepagesize; 1637 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1638 cai->cai_associativity); 1639 if (cp != NULL) 1640 cai->cai_associativity = cp->cai_associativity; 1641 else 1642 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1643 1644 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1645 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1646 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1647 cai->cai_linesize = (4 * 1024); 1648 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1649 cai->cai_associativity); 1650 if (cp != NULL) 1651 cai->cai_associativity = cp->cai_associativity; 1652 else 1653 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1654 1655 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1656 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1657 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1658 cai->cai_linesize = largepagesize; 1659 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1660 cai->cai_associativity); 1661 if (cp != NULL) 1662 cai->cai_associativity = cp->cai_associativity; 1663 else 1664 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1665 1666 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1667 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1668 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1669 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1670 1671 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1672 cai->cai_associativity); 1673 if (cp != NULL) 1674 cai->cai_associativity = cp->cai_associativity; 1675 else 1676 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1677 1678 /* 1679 * Determine L3 cache info on AMD Family 10h and newer processors 1680 */ 1681 if (ci->ci_family >= 0x10) { 1682 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1683 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1684 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1685 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1686 1687 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1688 cai->cai_associativity); 1689 if (cp != NULL) 1690 cai->cai_associativity = cp->cai_associativity; 1691 else 1692 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1693 } 1694 1695 /* 1696 * Determine 1GB TLB info. 1697 */ 1698 if (lfunc < 0x80000019) { 1699 /* No 1GB TLB info available. */ 1700 return; 1701 } 1702 1703 x86_cpuid(0x80000019, descs); 1704 1705 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1706 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1707 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1708 cai->cai_linesize = (1024 * 1024 * 1024); 1709 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1710 cai->cai_associativity); 1711 if (cp != NULL) 1712 cai->cai_associativity = cp->cai_associativity; 1713 else 1714 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1715 1716 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1717 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1718 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1719 cai->cai_linesize = (1024 * 1024 * 1024); 1720 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1721 cai->cai_associativity); 1722 if (cp != NULL) 1723 cai->cai_associativity = cp->cai_associativity; 1724 else 1725 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1726 1727 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1728 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1729 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1730 cai->cai_linesize = (1024 * 1024 * 1024); 1731 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1732 cai->cai_associativity); 1733 if (cp != NULL) 1734 cai->cai_associativity = cp->cai_associativity; 1735 else 1736 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1737 1738 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1739 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1740 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1741 cai->cai_linesize = (1024 * 1024 * 1024); 1742 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1743 cai->cai_associativity); 1744 if (cp != NULL) 1745 cai->cai_associativity = cp->cai_associativity; 1746 else 1747 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1748 } 1749 1750 static void 1751 via_cpu_cacheinfo(struct cpu_info *ci) 1752 { 1753 struct x86_cache_info *cai; 1754 int stepping; 1755 u_int descs[4]; 1756 u_int lfunc; 1757 1758 stepping = CPUID2STEPPING(ci->ci_signature); 1759 1760 /* 1761 * Determine the largest extended function value. 1762 */ 1763 x86_cpuid(0x80000000, descs); 1764 lfunc = descs[0]; 1765 1766 /* 1767 * Determine L1 cache/TLB info. 1768 */ 1769 if (lfunc < 0x80000005) { 1770 /* No L1 cache info available. */ 1771 return; 1772 } 1773 1774 x86_cpuid(0x80000005, descs); 1775 1776 cai = &ci->ci_cinfo[CAI_ITLB]; 1777 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1778 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1779 cai->cai_linesize = (4 * 1024); 1780 1781 cai = &ci->ci_cinfo[CAI_DTLB]; 1782 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1783 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1784 cai->cai_linesize = (4 * 1024); 1785 1786 cai = &ci->ci_cinfo[CAI_DCACHE]; 1787 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1788 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1789 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1790 if (ci->ci_model == 9 && stepping == 8) { 1791 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1792 cai->cai_associativity = 2; 1793 } 1794 1795 cai = &ci->ci_cinfo[CAI_ICACHE]; 1796 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1797 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1798 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1799 if (ci->ci_model == 9 && stepping == 8) { 1800 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1801 cai->cai_associativity = 2; 1802 } 1803 1804 /* 1805 * Determine L2 cache/TLB info. 1806 */ 1807 if (lfunc < 0x80000006) { 1808 /* No L2 cache info available. */ 1809 return; 1810 } 1811 1812 x86_cpuid(0x80000006, descs); 1813 1814 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1815 if (ci->ci_model >= 9) { 1816 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1817 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1818 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1819 } else { 1820 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1821 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1822 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1823 } 1824 } 1825 1826 static void 1827 x86_print_cacheinfo(struct cpu_info *ci) 1828 { 1829 const char *sep; 1830 1831 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 1832 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 1833 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 1834 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 1835 if (sep != NULL) 1836 aprint_verbose("\n"); 1837 } 1838 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 1839 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 1840 if (sep != NULL) 1841 aprint_verbose("\n"); 1842 } 1843 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 1844 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 1845 if (sep != NULL) 1846 aprint_verbose("\n"); 1847 } 1848 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 1849 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 1850 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 1851 if (sep != NULL) 1852 aprint_verbose("\n"); 1853 } 1854 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 1855 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 1856 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 1857 if (sep != NULL) 1858 aprint_verbose("\n"); 1859 } 1860 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 1861 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 1862 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 1863 if (sep != NULL) 1864 aprint_verbose("\n"); 1865 } 1866 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 1867 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 1868 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 1869 if (sep != NULL) 1870 aprint_verbose("\n"); 1871 } 1872 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 1873 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", NULL); 1874 if (sep != NULL) 1875 aprint_verbose("\n"); 1876 } 1877 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 1878 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", NULL); 1879 if (sep != NULL) 1880 aprint_verbose("\n"); 1881 } 1882 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 1883 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", NULL); 1884 if (sep != NULL) 1885 aprint_verbose("\n"); 1886 } 1887 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 1888 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", NULL); 1889 if (sep != NULL) 1890 aprint_verbose("\n"); 1891 } 1892 } 1893 1894 static void 1895 powernow_probe(struct cpu_info *ci) 1896 { 1897 uint32_t regs[4]; 1898 char buf[256]; 1899 1900 x86_cpuid(0x80000007, regs); 1901 1902 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 1903 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 1904 buf); 1905 } 1906 1907 int 1908 ucodeupdate_check(int fd, struct cpu_ucode *uc) 1909 { 1910 struct cpu_info ci; 1911 int loader_version, res; 1912 struct cpu_ucode_version versreq; 1913 1914 cpu_probe_base_features(&ci, "unknown"); 1915 1916 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 1917 loader_version = CPU_UCODE_LOADER_AMD; 1918 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 1919 loader_version = CPU_UCODE_LOADER_INTEL1; 1920 else 1921 return -1; 1922 1923 /* check whether the kernel understands this loader version */ 1924 versreq.loader_version = loader_version; 1925 versreq.data = 0; 1926 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 1927 if (res) 1928 return -1; 1929 1930 switch (loader_version) { 1931 case CPU_UCODE_LOADER_AMD: 1932 if (uc->cpu_nr != -1) { 1933 /* printf? */ 1934 return -1; 1935 } 1936 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 1937 break; 1938 case CPU_UCODE_LOADER_INTEL1: 1939 if (uc->cpu_nr == -1) 1940 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 1941 else 1942 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 1943 break; 1944 default: /* can't happen */ 1945 return -1; 1946 } 1947 uc->loader_version = loader_version; 1948 return 0; 1949 } 1950
Indexes created Fri Sep 26 08:10:20 GMT 2025