i386.c revision 1.39
1 /* $NetBSD: i386.c,v 1.39 2013/03/06 11:52:53 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.39 2013/03/06 11:52:53 yamt Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cacheinfo.h> 85 #include <x86/cpu_ucode.h> 86 87 #include "../cpuctl.h" 88 #include "cpuctl_i386.h" 89 90 /* Size of buffer for printing humanized numbers */ 91 #define HUMAN_BUFSIZE sizeof("999KB") 92 93 struct cpu_info { 94 const char *ci_dev; 95 int32_t ci_cpu_type; /* for cpu's without cpuid */ 96 int32_t ci_cpuid_level; /* highest cpuid supported */ 97 uint32_t ci_signature; /* X86 cpuid type */ 98 uint32_t ci_family; /* from ci_signature */ 99 uint32_t ci_model; /* from ci_signature */ 100 uint32_t ci_feat_val[8]; /* X86 CPUID feature bits 101 * [0] basic features %edx 102 * [1] basic features %ecx 103 * [2] extended features %edx 104 * [3] extended features %ecx 105 * [4] VIA padlock features 106 * [5] XCR0 bits (d:0 %eax) 107 * [6] xsave flags (d:1 %eax) 108 */ 109 uint32_t ci_cpu_class; /* CPU class */ 110 uint32_t ci_brand_id; /* Intel brand id */ 111 uint32_t ci_vendor[4]; /* vendor string */ 112 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 113 uint64_t ci_tsc_freq; /* cpu cycles/second */ 114 uint8_t ci_packageid; 115 uint8_t ci_coreid; 116 uint8_t ci_smtid; 117 uint32_t ci_initapicid; 118 119 uint32_t ci_cur_xsave; 120 uint32_t ci_max_xsave; 121 122 struct x86_cache_info ci_cinfo[CAI_COUNT]; 123 void (*ci_info)(struct cpu_info *); 124 }; 125 126 struct cpu_nocpuid_nameclass { 127 int cpu_vendor; 128 const char *cpu_vendorname; 129 const char *cpu_name; 130 int cpu_class; 131 void (*cpu_setup)(struct cpu_info *); 132 void (*cpu_cacheinfo)(struct cpu_info *); 133 void (*cpu_info)(struct cpu_info *); 134 }; 135 136 struct cpu_cpuid_nameclass { 137 const char *cpu_id; 138 int cpu_vendor; 139 const char *cpu_vendorname; 140 struct cpu_cpuid_family { 141 int cpu_class; 142 const char *cpu_models[256]; 143 const char *cpu_model_default; 144 void (*cpu_setup)(struct cpu_info *); 145 void (*cpu_probe)(struct cpu_info *); 146 void (*cpu_info)(struct cpu_info *); 147 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 148 }; 149 150 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 151 152 /* 153 * Map Brand ID from cpuid instruction to brand name. 154 * Source: Intel Processor Identification and the CPUID Instruction, AP-485 155 */ 156 static const char * const i386_intel_brand[] = { 157 "", /* Unsupported */ 158 "Celeron", /* Intel (R) Celeron (TM) processor */ 159 "Pentium III", /* Intel (R) Pentium (R) III processor */ 160 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 161 "Pentium III", /* Intel (R) Pentium (R) III processor */ 162 "", /* Reserved */ 163 "Mobile Pentium III", /* Mobile Intel (R) Pentium (R) III processor-M */ 164 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 165 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 166 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 167 "Celeron", /* Intel (R) Celeron (TM) processor */ 168 "Xeon", /* Intel (R) Xeon (TM) processor */ 169 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 170 "", /* Reserved */ 171 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 172 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 173 }; 174 175 /* 176 * AMD processors don't have Brand IDs, so we need these names for probe. 177 */ 178 static const char * const amd_brand[] = { 179 "", 180 "Duron", /* AMD Duron(tm) */ 181 "MP", /* AMD Athlon(tm) MP */ 182 "XP", /* AMD Athlon(tm) XP */ 183 "4" /* AMD Athlon(tm) 4 */ 184 }; 185 186 static int cpu_vendor; 187 static char cpu_brand_string[49]; 188 static char amd_brand_name[48]; 189 static int use_pae, largepagesize; 190 191 static void via_cpu_probe(struct cpu_info *); 192 static void amd_family6_probe(struct cpu_info *); 193 static void intel_family_new_probe(struct cpu_info *); 194 static const char *intel_family6_name(struct cpu_info *); 195 static const char *amd_amd64_name(struct cpu_info *); 196 static void amd_family5_setup(struct cpu_info *); 197 static void transmeta_cpu_info(struct cpu_info *); 198 static const char *print_cache_config(struct cpu_info *, int, const char *, 199 const char *); 200 static const char *print_tlb_config(struct cpu_info *, int, const char *, 201 const char *); 202 static void amd_cpu_cacheinfo(struct cpu_info *); 203 static void via_cpu_cacheinfo(struct cpu_info *); 204 static void x86_print_cacheinfo(struct cpu_info *); 205 static const struct x86_cache_info *cache_info_lookup( 206 const struct x86_cache_info *, uint8_t); 207 static void cyrix6x86_cpu_setup(struct cpu_info *); 208 static void winchip_cpu_setup(struct cpu_info *); 209 static void amd_family5_setup(struct cpu_info *); 210 static void powernow_probe(struct cpu_info *); 211 212 /* 213 * Note: these are just the ones that may not have a cpuid instruction. 214 * We deal with the rest in a different way. 215 */ 216 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 217 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 218 NULL, NULL, NULL }, /* CPU_386SX */ 219 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 220 NULL, NULL, NULL }, /* CPU_386 */ 221 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 222 NULL, NULL, NULL }, /* CPU_486SX */ 223 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 224 NULL, NULL, NULL }, /* CPU_486 */ 225 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 226 NULL, NULL, NULL }, /* CPU_486DLC */ 227 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 228 NULL, NULL, NULL }, /* CPU_6x86 */ 229 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 230 NULL, NULL, NULL }, /* CPU_NX586 */ 231 }; 232 233 const char *classnames[] = { 234 "386", 235 "486", 236 "586", 237 "686" 238 }; 239 240 const char *modifiers[] = { 241 "", 242 "OverDrive", 243 "Dual", 244 "" 245 }; 246 247 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 248 { 249 "GenuineIntel", 250 CPUVENDOR_INTEL, 251 "Intel", 252 /* Family 4 */ 253 { { 254 CPUCLASS_486, 255 { 256 "486DX", "486DX", "486SX", "486DX2", "486SL", 257 "486SX2", 0, "486DX2 W/B Enhanced", 258 "486DX4", 0, 0, 0, 0, 0, 0, 0, 259 }, 260 "486", /* Default */ 261 NULL, 262 NULL, 263 NULL, 264 }, 265 /* Family 5 */ 266 { 267 CPUCLASS_586, 268 { 269 "Pentium (P5 A-step)", "Pentium (P5)", 270 "Pentium (P54C)", "Pentium (P24T)", 271 "Pentium/MMX", "Pentium", 0, 272 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 273 0, 0, 0, 0, 0, 0, 0, 274 }, 275 "Pentium", /* Default */ 276 NULL, 277 NULL, 278 NULL, 279 }, 280 /* Family 6 */ 281 { 282 CPUCLASS_686, 283 { 284 /* Updated from intel_x86_325486.pdf Aug 2012 */ 285 [0x00] = "Pentium Pro (A-step)", 286 [0x01] = "Pentium Pro", 287 [0x03] = "Pentium II (Klamath)", 288 [0x04] = "Pentium Pro", 289 [0x05] = "Pentium II/Celeron (Deschutes)", 290 [0x06] = "Celeron (Mendocino)", 291 [0x07] = "Pentium III (Katmai)", 292 [0x08] = "Pentium III (Coppermine)", 293 [0x09] = "Pentium M (Banias)", 294 [0x0a] = "Pentium III Xeon (Cascades)", 295 [0x0b] = "Pentium III (Tualatin)", 296 [0x0d] = "Pentium M (Dothan)", 297 [0x0e] = "Pentium Core Duo", // "M (Yonah)", 298 [0x0f] = "Core 2", 299 [0x15] = "EP80579 Integrated Processor", 300 [0x16] = "Celeron (45nm)", 301 [0x17] = "Core 2 Extreme", 302 [0x1a] = "Core i7 (Nehalem)", 303 [0x1c] = "Atom Family", 304 [0x1d] = "XeonMP 74xx (Nehalem)", 305 [0x1e] = "Core i7 and i5", 306 [0x1f] = "Core i7 and i5", 307 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 308 [0x26] = "Atom Family", 309 [0x27] = "Atom Family", 310 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, i3 2xxx", 311 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 312 [0x2e] = "Xeon 75xx & 65xx", 313 [0x2d] = "Xeon E5 Sandy bridy family", 314 [0x2f] = "Xeon E7 family", 315 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, Ivy bridge", 316 [0x3c] = "Next Intel Core", 317 [0x3e] = "Next gen Xeon E5, Ivy bridge", 318 [0x45] = "Next Intel Core", 319 }, 320 "Pentium Pro, II or III", /* Default */ 321 NULL, 322 intel_family_new_probe, 323 NULL, 324 }, 325 /* Family > 6 */ 326 { 327 CPUCLASS_686, 328 { 329 0, 0, 0, 0, 0, 0, 0, 0, 330 0, 0, 0, 0, 0, 0, 0, 0, 331 }, 332 "Pentium 4", /* Default */ 333 NULL, 334 intel_family_new_probe, 335 NULL, 336 } } 337 }, 338 { 339 "AuthenticAMD", 340 CPUVENDOR_AMD, 341 "AMD", 342 /* Family 4 */ 343 { { 344 CPUCLASS_486, 345 { 346 0, 0, 0, "Am486DX2 W/T", 347 0, 0, 0, "Am486DX2 W/B", 348 "Am486DX4 W/T or Am5x86 W/T 150", 349 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 350 0, 0, "Am5x86 W/T 133/160", 351 "Am5x86 W/B 133/160", 352 }, 353 "Am486 or Am5x86", /* Default */ 354 NULL, 355 NULL, 356 NULL, 357 }, 358 /* Family 5 */ 359 { 360 CPUCLASS_586, 361 { 362 "K5", "K5", "K5", "K5", 0, 0, "K6", 363 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 364 "K6-2+/III+", 0, 0, 365 }, 366 "K5 or K6", /* Default */ 367 amd_family5_setup, 368 NULL, 369 amd_cpu_cacheinfo, 370 }, 371 /* Family 6 */ 372 { 373 CPUCLASS_686, 374 { 375 0, "Athlon Model 1", "Athlon Model 2", 376 "Duron", "Athlon Model 4 (Thunderbird)", 377 0, "Athlon", "Duron", "Athlon", 0, 378 "Athlon", 0, 0, 0, 0, 0, 379 }, 380 "K7 (Athlon)", /* Default */ 381 NULL, 382 amd_family6_probe, 383 amd_cpu_cacheinfo, 384 }, 385 /* Family > 6 */ 386 { 387 CPUCLASS_686, 388 { 389 0, 0, 0, 0, 0, 0, 0, 0, 390 0, 0, 0, 0, 0, 0, 0, 0, 391 }, 392 "Unknown K8 (Athlon)", /* Default */ 393 NULL, 394 amd_family6_probe, 395 amd_cpu_cacheinfo, 396 } } 397 }, 398 { 399 "CyrixInstead", 400 CPUVENDOR_CYRIX, 401 "Cyrix", 402 /* Family 4 */ 403 { { 404 CPUCLASS_486, 405 { 406 0, 0, 0, 407 "MediaGX", 408 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 409 }, 410 "486", /* Default */ 411 cyrix6x86_cpu_setup, /* XXX ?? */ 412 NULL, 413 NULL, 414 }, 415 /* Family 5 */ 416 { 417 CPUCLASS_586, 418 { 419 0, 0, "6x86", 0, 420 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 421 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 422 }, 423 "6x86", /* Default */ 424 cyrix6x86_cpu_setup, 425 NULL, 426 NULL, 427 }, 428 /* Family 6 */ 429 { 430 CPUCLASS_686, 431 { 432 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 433 0, 0, 0, 0, 0, 0, 0, 0, 434 }, 435 "6x86MX", /* Default */ 436 cyrix6x86_cpu_setup, 437 NULL, 438 NULL, 439 }, 440 /* Family > 6 */ 441 { 442 CPUCLASS_686, 443 { 444 0, 0, 0, 0, 0, 0, 0, 0, 445 0, 0, 0, 0, 0, 0, 0, 0, 446 }, 447 "Unknown 6x86MX", /* Default */ 448 NULL, 449 NULL, 450 NULL, 451 } } 452 }, 453 { /* MediaGX is now owned by National Semiconductor */ 454 "Geode by NSC", 455 CPUVENDOR_CYRIX, /* XXX */ 456 "National Semiconductor", 457 /* Family 4, NSC never had any of these */ 458 { { 459 CPUCLASS_486, 460 { 461 0, 0, 0, 0, 0, 0, 0, 0, 462 0, 0, 0, 0, 0, 0, 0, 0, 463 }, 464 "486 compatible", /* Default */ 465 NULL, 466 NULL, 467 NULL, 468 }, 469 /* Family 5: Geode family, formerly MediaGX */ 470 { 471 CPUCLASS_586, 472 { 473 0, 0, 0, 0, 474 "Geode GX1", 475 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 476 }, 477 "Geode", /* Default */ 478 cyrix6x86_cpu_setup, 479 NULL, 480 amd_cpu_cacheinfo, 481 }, 482 /* Family 6, not yet available from NSC */ 483 { 484 CPUCLASS_686, 485 { 486 0, 0, 0, 0, 0, 0, 0, 0, 487 0, 0, 0, 0, 0, 0, 0, 0, 488 }, 489 "Pentium Pro compatible", /* Default */ 490 NULL, 491 NULL, 492 NULL, 493 }, 494 /* Family > 6, not yet available from NSC */ 495 { 496 CPUCLASS_686, 497 { 498 0, 0, 0, 0, 0, 0, 0, 0, 499 0, 0, 0, 0, 0, 0, 0, 0, 500 }, 501 "Pentium Pro compatible", /* Default */ 502 NULL, 503 NULL, 504 NULL, 505 } } 506 }, 507 { 508 "CentaurHauls", 509 CPUVENDOR_IDT, 510 "IDT", 511 /* Family 4, IDT never had any of these */ 512 { { 513 CPUCLASS_486, 514 { 515 0, 0, 0, 0, 0, 0, 0, 0, 516 0, 0, 0, 0, 0, 0, 0, 0, 517 }, 518 "486 compatible", /* Default */ 519 NULL, 520 NULL, 521 NULL, 522 }, 523 /* Family 5 */ 524 { 525 CPUCLASS_586, 526 { 527 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 528 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 529 }, 530 "WinChip", /* Default */ 531 winchip_cpu_setup, 532 NULL, 533 NULL, 534 }, 535 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 536 { 537 CPUCLASS_686, 538 { 539 0, 0, 0, 0, 0, 0, "C3 Samuel", 540 "C3 Samuel 2/Ezra", "C3 Ezra-T", 541 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 542 0, "VIA Nano", 543 }, 544 "Unknown VIA/IDT", /* Default */ 545 NULL, 546 via_cpu_probe, 547 via_cpu_cacheinfo, 548 }, 549 /* Family > 6, not yet available from VIA */ 550 { 551 CPUCLASS_686, 552 { 553 0, 0, 0, 0, 0, 0, 0, 0, 554 0, 0, 0, 0, 0, 0, 0, 0, 555 }, 556 "Pentium Pro compatible", /* Default */ 557 NULL, 558 NULL, 559 NULL, 560 } } 561 }, 562 { 563 "GenuineTMx86", 564 CPUVENDOR_TRANSMETA, 565 "Transmeta", 566 /* Family 4, Transmeta never had any of these */ 567 { { 568 CPUCLASS_486, 569 { 570 0, 0, 0, 0, 0, 0, 0, 0, 571 0, 0, 0, 0, 0, 0, 0, 0, 572 }, 573 "486 compatible", /* Default */ 574 NULL, 575 NULL, 576 NULL, 577 }, 578 /* Family 5 */ 579 { 580 CPUCLASS_586, 581 { 582 0, 0, 0, 0, 0, 0, 0, 0, 583 0, 0, 0, 0, 0, 0, 0, 0, 584 }, 585 "Crusoe", /* Default */ 586 NULL, 587 NULL, 588 transmeta_cpu_info, 589 }, 590 /* Family 6, not yet available from Transmeta */ 591 { 592 CPUCLASS_686, 593 { 594 0, 0, 0, 0, 0, 0, 0, 0, 595 0, 0, 0, 0, 0, 0, 0, 0, 596 }, 597 "Pentium Pro compatible", /* Default */ 598 NULL, 599 NULL, 600 NULL, 601 }, 602 /* Family > 6, not yet available from Transmeta */ 603 { 604 CPUCLASS_686, 605 { 606 0, 0, 0, 0, 0, 0, 0, 0, 607 0, 0, 0, 0, 0, 0, 0, 0, 608 }, 609 "Pentium Pro compatible", /* Default */ 610 NULL, 611 NULL, 612 NULL, 613 } } 614 } 615 }; 616 617 /* 618 * disable the TSC such that we don't use the TSC in microtime(9) 619 * because some CPUs got the implementation wrong. 620 */ 621 static void 622 disable_tsc(struct cpu_info *ci) 623 { 624 if (ci->ci_feat_val[0] & CPUID_TSC) { 625 ci->ci_feat_val[0] &= ~CPUID_TSC; 626 aprint_error("WARNING: broken TSC disabled\n"); 627 } 628 } 629 630 static void 631 cyrix6x86_cpu_setup(struct cpu_info *ci) 632 { 633 634 /* 635 * Do not disable the TSC on the Geode GX, it's reported to 636 * work fine. 637 */ 638 if (ci->ci_signature != 0x552) 639 disable_tsc(ci); 640 } 641 642 void 643 winchip_cpu_setup(struct cpu_info *ci) 644 { 645 switch (ci->ci_model) { 646 case 4: /* WinChip C6 */ 647 disable_tsc(ci); 648 } 649 } 650 651 652 static void 653 identifycpu_cpuids(struct cpu_info *ci) 654 { 655 const char *cpuname = ci->ci_dev; 656 u_int lp_max = 1; /* logical processors per package */ 657 u_int smt_max; /* smt per core */ 658 u_int core_max = 1; /* core per package */ 659 u_int smt_bits, core_bits; 660 uint32_t descs[4]; 661 uint32_t highest_basic_info; 662 663 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 664 ci->ci_packageid = ci->ci_initapicid; 665 ci->ci_coreid = 0; 666 ci->ci_smtid = 0; 667 if (cpu_vendor != CPUVENDOR_INTEL) { 668 return; 669 } 670 671 /* 672 * 253668.pdf 7.10.2 673 */ 674 675 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 676 x86_cpuid(1, descs); 677 lp_max = (descs[1] >> 16) & 0xff; 678 } 679 x86_cpuid(0, descs); 680 highest_basic_info = descs[0]; 681 if (highest_basic_info >= 4) { 682 x86_cpuid2(4, 0, descs); 683 core_max = (descs[0] >> 26) + 1; 684 } 685 assert(lp_max >= core_max); 686 smt_max = lp_max / core_max; 687 smt_bits = ilog2(smt_max - 1) + 1; 688 core_bits = ilog2(core_max - 1) + 1; 689 if (smt_bits + core_bits) { 690 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 691 } 692 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 693 ci->ci_packageid); 694 if (core_bits) { 695 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 696 697 ci->ci_coreid = 698 __SHIFTOUT(ci->ci_initapicid, core_mask); 699 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 700 } 701 if (smt_bits) { 702 u_int smt_mask = __BITS((int)0, (int)(smt_bits - 1)); 703 704 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, smt_mask); 705 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 706 } 707 } 708 709 static void 710 via_cpu_probe(struct cpu_info *ci) 711 { 712 u_int stepping = CPUID2STEPPING(ci->ci_signature); 713 u_int descs[4]; 714 u_int lfunc; 715 716 /* 717 * Determine the largest extended function value. 718 */ 719 x86_cpuid(0x80000000, descs); 720 lfunc = descs[0]; 721 722 /* 723 * Determine the extended feature flags. 724 */ 725 if (lfunc >= 0x80000001) { 726 x86_cpuid(0x80000001, descs); 727 ci->ci_feat_val[2] |= descs[3]; 728 } 729 730 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 731 return; 732 733 /* Nehemiah or Esther */ 734 x86_cpuid(0xc0000000, descs); 735 lfunc = descs[0]; 736 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 737 return; 738 739 x86_cpuid(0xc0000001, descs); 740 lfunc = descs[3]; 741 ci->ci_feat_val[4] = lfunc; 742 } 743 744 static const char * 745 intel_family6_name(struct cpu_info *ci) 746 { 747 const char *ret = NULL; 748 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 749 750 if (ci->ci_model == 5) { 751 switch (l2cache) { 752 case 0: 753 case 128 * 1024: 754 ret = "Celeron (Covington)"; 755 break; 756 case 256 * 1024: 757 ret = "Mobile Pentium II (Dixon)"; 758 break; 759 case 512 * 1024: 760 ret = "Pentium II"; 761 break; 762 case 1 * 1024 * 1024: 763 case 2 * 1024 * 1024: 764 ret = "Pentium II Xeon"; 765 break; 766 } 767 } else if (ci->ci_model == 6) { 768 switch (l2cache) { 769 case 256 * 1024: 770 case 512 * 1024: 771 ret = "Mobile Pentium II"; 772 break; 773 } 774 } else if (ci->ci_model == 7) { 775 switch (l2cache) { 776 case 512 * 1024: 777 ret = "Pentium III"; 778 break; 779 case 1 * 1024 * 1024: 780 case 2 * 1024 * 1024: 781 ret = "Pentium III Xeon"; 782 break; 783 } 784 } else if (ci->ci_model >= 8) { 785 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 786 switch (ci->ci_brand_id) { 787 case 0x3: 788 if (ci->ci_signature == 0x6B1) 789 ret = "Celeron"; 790 break; 791 case 0x8: 792 if (ci->ci_signature >= 0xF13) 793 ret = "genuine processor"; 794 break; 795 case 0xB: 796 if (ci->ci_signature >= 0xF13) 797 ret = "Xeon MP"; 798 break; 799 case 0xE: 800 if (ci->ci_signature < 0xF13) 801 ret = "Xeon"; 802 break; 803 } 804 if (ret == NULL) 805 ret = i386_intel_brand[ci->ci_brand_id]; 806 } 807 } 808 809 return ret; 810 } 811 812 /* 813 * Identify AMD64 CPU names from cpuid. 814 * 815 * Based on: 816 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 817 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 818 * "Revision Guide for AMD NPT Family 0Fh Processors" 819 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 820 * and other miscellaneous reports. 821 * 822 * This is all rather pointless, these are cross 'brand' since the raw 823 * silicon is shared. 824 */ 825 static const char * 826 amd_amd64_name(struct cpu_info *ci) 827 { 828 static char family_str[32]; 829 830 /* Only called if family >= 15 */ 831 832 switch (ci->ci_family) { 833 case 15: 834 switch (ci->ci_model) { 835 case 0x21: /* rev JH-E1/E6 */ 836 case 0x41: /* rev JH-F2 */ 837 return "Dual-Core Opteron"; 838 case 0x23: /* rev JH-E6 (Toledo) */ 839 return "Dual-Core Opteron or Athlon 64 X2"; 840 case 0x43: /* rev JH-F2 (Windsor) */ 841 return "Athlon 64 FX or Athlon 64 X2"; 842 case 0x24: /* rev SH-E5 (Lancaster?) */ 843 return "Mobile Athlon 64 or Turion 64"; 844 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 845 return "Opteron or Athlon 64 FX"; 846 case 0x15: /* rev SH-D0 */ 847 case 0x25: /* rev SH-E4 */ 848 return "Opteron"; 849 case 0x27: /* rev DH-E4, SH-E4 */ 850 return "Athlon 64 or Athlon 64 FX or Opteron"; 851 case 0x48: /* rev BH-F2 */ 852 return "Turion 64 X2"; 853 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 854 case 0x07: /* rev SH-CG (ClawHammer) */ 855 case 0x0b: /* rev CH-CG */ 856 case 0x14: /* rev SH-D0 */ 857 case 0x17: /* rev SH-D0 */ 858 case 0x1b: /* rev CH-D0 */ 859 return "Athlon 64"; 860 case 0x2b: /* rev BH-E4 (Manchester) */ 861 case 0x4b: /* rev BH-F2 (Windsor) */ 862 return "Athlon 64 X2"; 863 case 0x6b: /* rev BH-G1 (Brisbane) */ 864 return "Athlon X2 or Athlon 64 X2"; 865 case 0x08: /* rev CH-CG */ 866 case 0x0c: /* rev DH-CG (Newcastle) */ 867 case 0x0e: /* rev DH-CG (Newcastle?) */ 868 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 869 case 0x18: /* rev CH-D0 */ 870 case 0x1c: /* rev DH-D0 (Winchester) */ 871 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 872 case 0x2c: /* rev DH-E3/E6 */ 873 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 874 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 875 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 876 case 0x6f: /* rev DH-G1 */ 877 return "Athlon 64 or Sempron"; 878 default: 879 break; 880 } 881 return "Unknown AMD64 CPU"; 882 883 #if 0 884 case 16: 885 return "Family 10h"; 886 case 17: 887 return "Family 11h"; 888 case 18: 889 return "Family 12h"; 890 case 19: 891 return "Family 14h"; 892 case 20: 893 return "Family 15h"; 894 #endif 895 896 default: 897 break; 898 } 899 900 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 901 return family_str; 902 } 903 904 static void 905 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 906 { 907 const struct x86_cache_info *cai; 908 u_int descs[4]; 909 int iterations, i, j; 910 uint8_t desc; 911 uint32_t brand[12]; 912 913 memset(ci, 0, sizeof(*ci)); 914 ci->ci_dev = cpuname; 915 916 ci->ci_cpu_type = x86_identify(); 917 if (ci->ci_cpu_type >= 0) { 918 /* Old pre-cpuid instruction cpu */ 919 ci->ci_cpuid_level = -1; 920 return; 921 } 922 923 x86_cpuid(0, descs); 924 ci->ci_cpuid_level = descs[0]; 925 ci->ci_vendor[0] = descs[1]; 926 ci->ci_vendor[2] = descs[2]; 927 ci->ci_vendor[1] = descs[3]; 928 ci->ci_vendor[3] = 0; 929 930 x86_cpuid(0x80000000, brand); 931 if (brand[0] >= 0x80000004) { 932 x86_cpuid(0x80000002, brand); 933 x86_cpuid(0x80000003, brand + 4); 934 x86_cpuid(0x80000004, brand + 8); 935 for (i = 0; i < 48; i++) 936 if (((char *) brand)[i] != ' ') 937 break; 938 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 939 } 940 941 if (ci->ci_cpuid_level < 1) 942 return; 943 944 x86_cpuid(1, descs); 945 ci->ci_signature = descs[0]; 946 947 /* Extract full family/model values */ 948 ci->ci_family = CPUID2FAMILY(ci->ci_signature); 949 ci->ci_model = CPUID2MODEL(ci->ci_signature); 950 if (ci->ci_family == 15) 951 ci->ci_family += CPUID2EXTFAMILY(ci->ci_signature); 952 if (ci->ci_family == 6 || ci->ci_family == 15) 953 ci->ci_model += CPUID2EXTMODEL(ci->ci_signature) << 4; 954 955 /* Brand is low order 8 bits of ebx */ 956 ci->ci_brand_id = descs[1] & 0xff; 957 ci->ci_initapicid = (descs[1] >> 24) & 0xff; 958 959 ci->ci_feat_val[1] = descs[2]; 960 ci->ci_feat_val[0] = descs[3]; 961 962 if (ci->ci_cpuid_level < 2) 963 return; 964 965 /* 966 * Parse the cache info from `cpuid', if we have it. 967 * XXX This is kinda ugly, but hey, so is the architecture... 968 */ 969 970 x86_cpuid(2, descs); 971 972 iterations = descs[0] & 0xff; 973 while (iterations-- > 0) { 974 for (i = 0; i < 4; i++) { 975 if (descs[i] & 0x80000000) 976 continue; 977 for (j = 0; j < 4; j++) { 978 if (i == 0 && j == 0) 979 continue; 980 desc = (descs[i] >> (j * 8)) & 0xff; 981 if (desc == 0) 982 continue; 983 cai = cache_info_lookup(intel_cpuid_cache_info, 984 desc); 985 if (cai != NULL) 986 ci->ci_cinfo[cai->cai_index] = *cai; 987 } 988 } 989 x86_cpuid(2, descs); 990 } 991 992 if (ci->ci_cpuid_level < 3) 993 return; 994 995 /* 996 * If the processor serial number misfeature is present and supported, 997 * extract it here. 998 */ 999 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1000 ci->ci_cpu_serial[0] = ci->ci_signature; 1001 x86_cpuid(3, descs); 1002 ci->ci_cpu_serial[2] = descs[2]; 1003 ci->ci_cpu_serial[1] = descs[3]; 1004 } 1005 1006 if (ci->ci_cpuid_level < 0xd) 1007 return; 1008 1009 /* Get support XRC0 bits */ 1010 x86_cpuid2(0xd, 0, descs); 1011 ci->ci_feat_val[5] = descs[0]; /* Actually 64 bits */ 1012 ci->ci_cur_xsave = descs[1]; 1013 ci->ci_max_xsave = descs[2]; 1014 1015 /* Additional flags (eg xsaveopt support) */ 1016 x86_cpuid2(0xd, 1, descs); 1017 ci->ci_feat_val[6] = descs[0]; /* Actually 64 bits */ 1018 } 1019 1020 static void 1021 cpu_probe_features(struct cpu_info *ci) 1022 { 1023 const struct cpu_cpuid_nameclass *cpup = NULL; 1024 unsigned int i; 1025 1026 if (ci->ci_cpuid_level < 1) 1027 return; 1028 1029 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1030 if (!strncmp((char *)ci->ci_vendor, 1031 i386_cpuid_cpus[i].cpu_id, 12)) { 1032 cpup = &i386_cpuid_cpus[i]; 1033 break; 1034 } 1035 } 1036 1037 if (cpup == NULL) 1038 return; 1039 1040 i = ci->ci_family - CPU_MINFAMILY; 1041 1042 if (i >= __arraycount(cpup->cpu_family)) 1043 i = __arraycount(cpup->cpu_family) - 1; 1044 1045 if (cpup->cpu_family[i].cpu_probe == NULL) 1046 return; 1047 1048 (*cpup->cpu_family[i].cpu_probe)(ci); 1049 } 1050 1051 static void 1052 intel_family_new_probe(struct cpu_info *ci) 1053 { 1054 uint32_t descs[4]; 1055 1056 x86_cpuid(0x80000000, descs); 1057 1058 /* 1059 * Determine extended feature flags. 1060 */ 1061 if (descs[0] >= 0x80000001) { 1062 x86_cpuid(0x80000001, descs); 1063 ci->ci_feat_val[2] |= descs[3]; 1064 ci->ci_feat_val[3] |= descs[2]; 1065 } 1066 } 1067 1068 static void 1069 amd_family6_probe(struct cpu_info *ci) 1070 { 1071 uint32_t descs[4]; 1072 char *p; 1073 size_t i; 1074 1075 x86_cpuid(0x80000000, descs); 1076 1077 /* 1078 * Determine the extended feature flags. 1079 */ 1080 if (descs[0] >= 0x80000001) { 1081 x86_cpuid(0x80000001, descs); 1082 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 1083 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 1084 } 1085 1086 if (*cpu_brand_string == '\0') 1087 return; 1088 1089 for (i = 1; i < __arraycount(amd_brand); i++) 1090 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 1091 ci->ci_brand_id = i; 1092 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 1093 break; 1094 } 1095 } 1096 1097 static void 1098 amd_family5_setup(struct cpu_info *ci) 1099 { 1100 1101 switch (ci->ci_model) { 1102 case 0: /* AMD-K5 Model 0 */ 1103 /* 1104 * According to the AMD Processor Recognition App Note, 1105 * the AMD-K5 Model 0 uses the wrong bit to indicate 1106 * support for global PTEs, instead using bit 9 (APIC) 1107 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 1108 */ 1109 if (ci->ci_feat_val[0] & CPUID_APIC) 1110 ci->ci_feat_val[0] = 1111 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 1112 /* 1113 * XXX But pmap_pg_g is already initialized -- need to kick 1114 * XXX the pmap somehow. How does the MP branch do this? 1115 */ 1116 break; 1117 } 1118 } 1119 1120 static void 1121 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1122 { 1123 u_int descs[4]; 1124 1125 x86_cpuid(0x80860007, descs); 1126 *frequency = descs[0]; 1127 *voltage = descs[1]; 1128 *percentage = descs[2]; 1129 } 1130 1131 static void 1132 transmeta_cpu_info(struct cpu_info *ci) 1133 { 1134 u_int descs[4], nreg; 1135 u_int frequency, voltage, percentage; 1136 1137 x86_cpuid(0x80860000, descs); 1138 nreg = descs[0]; 1139 if (nreg >= 0x80860001) { 1140 x86_cpuid(0x80860001, descs); 1141 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1142 (descs[1] >> 24) & 0xff, 1143 (descs[1] >> 16) & 0xff, 1144 (descs[1] >> 8) & 0xff, 1145 descs[1] & 0xff); 1146 } 1147 if (nreg >= 0x80860002) { 1148 x86_cpuid(0x80860002, descs); 1149 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1150 (descs[1] >> 24) & 0xff, 1151 (descs[1] >> 16) & 0xff, 1152 (descs[1] >> 8) & 0xff, 1153 descs[1] & 0xff, 1154 descs[2]); 1155 } 1156 if (nreg >= 0x80860006) { 1157 union { 1158 char text[65]; 1159 u_int descs[4][4]; 1160 } info; 1161 int i; 1162 1163 for (i=0; i<4; i++) { 1164 x86_cpuid(0x80860003 + i, info.descs[i]); 1165 } 1166 info.text[64] = '\0'; 1167 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1168 } 1169 1170 if (nreg >= 0x80860007) { 1171 tmx86_get_longrun_status(&frequency, 1172 &voltage, &percentage); 1173 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1174 frequency, voltage, percentage); 1175 } 1176 } 1177 1178 static void 1179 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1180 { 1181 char buf[32 * 16]; 1182 char *bp; 1183 1184 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1185 1186 if (val == 0 || fmt == NULL) 1187 return; 1188 1189 snprintb_m(buf, sizeof(buf), fmt, val, 1190 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1191 bp = buf; 1192 while (*bp != '\0') { 1193 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1194 bp += strlen(bp) + 1; 1195 } 1196 } 1197 1198 void 1199 identifycpu(int fd, const char *cpuname) 1200 { 1201 const char *name = "", *modifier, *vendorname, *brand = ""; 1202 int class = CPUCLASS_386; 1203 unsigned int i; 1204 int modif, family; 1205 const struct cpu_cpuid_nameclass *cpup = NULL; 1206 const struct cpu_cpuid_family *cpufam; 1207 struct cpu_info *ci, cistore; 1208 size_t sz; 1209 struct cpu_ucode_version ucode; 1210 union { 1211 struct cpu_ucode_version_amd amd; 1212 struct cpu_ucode_version_intel1 intel1; 1213 } ucvers; 1214 1215 ci = &cistore; 1216 cpu_probe_base_features(ci, cpuname); 1217 cpu_probe_features(ci); 1218 1219 if (ci->ci_cpu_type >= 0) { 1220 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1221 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1222 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1223 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1224 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1225 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1226 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1227 modifier = ""; 1228 } else { 1229 modif = (ci->ci_signature >> 12) & 0x3; 1230 family = ci->ci_family; 1231 if (family < CPU_MINFAMILY) 1232 errx(1, "identifycpu: strange family value"); 1233 if (family > CPU_MAXFAMILY) 1234 family = CPU_MAXFAMILY; 1235 1236 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1237 if (!strncmp((char *)ci->ci_vendor, 1238 i386_cpuid_cpus[i].cpu_id, 12)) { 1239 cpup = &i386_cpuid_cpus[i]; 1240 break; 1241 } 1242 } 1243 1244 if (cpup == NULL) { 1245 cpu_vendor = CPUVENDOR_UNKNOWN; 1246 if (ci->ci_vendor[0] != '\0') 1247 vendorname = (char *)&ci->ci_vendor[0]; 1248 else 1249 vendorname = "Unknown"; 1250 class = family - 3; 1251 modifier = ""; 1252 name = ""; 1253 ci->ci_info = NULL; 1254 } else { 1255 cpu_vendor = cpup->cpu_vendor; 1256 vendorname = cpup->cpu_vendorname; 1257 modifier = modifiers[modif]; 1258 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 1259 name = cpufam->cpu_models[ci->ci_model]; 1260 if (name == NULL || *name == '\0') 1261 name = cpufam->cpu_model_default; 1262 class = cpufam->cpu_class; 1263 ci->ci_info = cpufam->cpu_info; 1264 1265 if (cpu_vendor == CPUVENDOR_INTEL) { 1266 if (ci->ci_family == 6 && ci->ci_model >= 5) { 1267 const char *tmp; 1268 tmp = intel_family6_name(ci); 1269 if (tmp != NULL) 1270 name = tmp; 1271 } 1272 if (ci->ci_family == 15 && 1273 ci->ci_brand_id < 1274 __arraycount(i386_intel_brand) && 1275 i386_intel_brand[ci->ci_brand_id]) 1276 name = 1277 i386_intel_brand[ci->ci_brand_id]; 1278 } 1279 1280 if (cpu_vendor == CPUVENDOR_AMD) { 1281 if (ci->ci_family == 6 && ci->ci_model >= 6) { 1282 if (ci->ci_brand_id == 1) 1283 /* 1284 * It's Duron. We override the 1285 * name, since it might have 1286 * been misidentified as Athlon. 1287 */ 1288 name = 1289 amd_brand[ci->ci_brand_id]; 1290 else 1291 brand = amd_brand_name; 1292 } 1293 if (CPUID2FAMILY(ci->ci_signature) == 0xf) { 1294 /* Identify AMD64 CPU names. */ 1295 const char *tmp; 1296 tmp = amd_amd64_name(ci); 1297 if (tmp != NULL) 1298 name = tmp; 1299 } 1300 } 1301 1302 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 1303 vendorname = "VIA"; 1304 } 1305 } 1306 1307 ci->ci_cpu_class = class; 1308 1309 sz = sizeof(ci->ci_tsc_freq); 1310 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 1311 sz = sizeof(use_pae); 1312 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 1313 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 1314 1315 /* 1316 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 1317 * we try to determine from the family/model values. 1318 */ 1319 if (*cpu_brand_string != '\0') 1320 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 1321 1322 aprint_normal("%s: %s", cpuname, vendorname); 1323 if (*modifier) 1324 aprint_normal(" %s", modifier); 1325 if (*name) 1326 aprint_normal(" %s", name); 1327 if (*brand) 1328 aprint_normal(" %s", brand); 1329 aprint_normal(" (%s-class)", classnames[class]); 1330 1331 if (ci->ci_tsc_freq != 0) 1332 aprint_normal(", %ju.%02ju MHz\n", 1333 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 1334 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 1335 1336 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 1337 ci->ci_family, ci->ci_model, CPUID2STEPPING(ci->ci_signature)); 1338 if (ci->ci_signature != 0) 1339 aprint_normal(" (id %#x)", ci->ci_signature); 1340 aprint_normal("\n"); 1341 1342 if (ci->ci_info) 1343 (*ci->ci_info)(ci); 1344 1345 /* 1346 * display CPU feature flags 1347 */ 1348 1349 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 1350 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 1351 1352 /* These next two are actually common definitions! */ 1353 print_bits(cpuname, "features2", 1354 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 1355 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 1356 print_bits(cpuname, "features3", 1357 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 1358 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 1359 1360 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 1361 ci->ci_feat_val[4]); 1362 1363 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[5]); 1364 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 1365 ci->ci_feat_val[6]); 1366 1367 if (ci->ci_max_xsave != 0) { 1368 aprint_normal("%s: xsave area size: current %d, maximum %d", 1369 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 1370 aprint_normal(", xgetbv %sabled\n", 1371 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 1372 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 1373 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 1374 x86_xgetbv()); 1375 } 1376 1377 x86_print_cacheinfo(ci); 1378 1379 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 1380 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 1381 cpuname, 1382 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 1383 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 1384 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 1385 } 1386 1387 if (ci->ci_cpu_class == CPUCLASS_386) { 1388 errx(1, "NetBSD requires an 80486 or later processor"); 1389 } 1390 1391 if (ci->ci_cpu_type == CPU_486DLC) { 1392 #ifndef CYRIX_CACHE_WORKS 1393 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 1394 #else 1395 #ifndef CYRIX_CACHE_REALLY_WORKS 1396 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 1397 #else 1398 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 1399 #endif 1400 #endif 1401 } 1402 1403 /* 1404 * Everything past this point requires a Pentium or later. 1405 */ 1406 if (ci->ci_cpuid_level < 0) 1407 return; 1408 1409 identifycpu_cpuids(ci); 1410 1411 #ifdef INTEL_CORETEMP 1412 if (cpu_vendor == CPUVENDOR_INTEL && ci->ci_cpuid_level >= 0x06) 1413 coretemp_register(ci); 1414 #endif 1415 1416 if (cpu_vendor == CPUVENDOR_AMD) { 1417 uint32_t data[4]; 1418 1419 x86_cpuid(0x80000000, data); 1420 if (data[0] >= 0x80000007) 1421 powernow_probe(ci); 1422 1423 if ((data[0] >= 0x8000000a) 1424 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 1425 x86_cpuid(0x8000000a, data); 1426 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 1427 data[0] & 0xf); 1428 aprint_verbose("%s: SVM NASID %d\n", cpuname, data[1]); 1429 print_bits(cpuname, "SVM features", CPUID_AMD_SVM_FLAGS, 1430 data[3]); 1431 } 1432 } else if (cpu_vendor == CPUVENDOR_INTEL) { 1433 uint32_t data[4]; 1434 uint32_t highest_basic_info; 1435 uint32_t bi_index; 1436 1437 x86_cpuid(0x00000000, data); 1438 highest_basic_info = data[0]; 1439 aprint_verbose("%s: highest basic info %08x\n", cpuname, 1440 highest_basic_info); 1441 for (bi_index = 1; bi_index <= highest_basic_info; bi_index++) { 1442 x86_cpuid(bi_index, data); 1443 switch (bi_index) { 1444 case 6: 1445 print_bits(cpuname, "DSPM-eax", 1446 CPUID_DSPM_FLAGS, data[0]); 1447 print_bits(cpuname, "DSPM-ecx", 1448 CPUID_DSPM_FLAGS1, data[2]); 1449 break; 1450 case 7: 1451 aprint_verbose("%s: SEF highest subleaf %08x\n", 1452 cpuname, data[0]); 1453 print_bits(cpuname, "SEF-main", CPUID_SEF_FLAGS, 1454 data[1]); 1455 break; 1456 #if 0 1457 default: 1458 aprint_verbose("%s: basic %08x-eax %08x\n", 1459 cpuname, bi_index, data[0]); 1460 aprint_verbose("%s: basic %08x-ebx %08x\n", 1461 cpuname, bi_index, data[1]); 1462 aprint_verbose("%s: basic %08x-ecx %08x\n", 1463 cpuname, bi_index, data[2]); 1464 aprint_verbose("%s: basic %08x-edx %08x\n", 1465 cpuname, bi_index, data[3]); 1466 break; 1467 #endif 1468 } 1469 } 1470 } 1471 1472 #ifdef INTEL_ONDEMAND_CLOCKMOD 1473 clockmod_init(); 1474 #endif 1475 1476 if (cpu_vendor == CPUVENDOR_AMD) 1477 ucode.loader_version = CPU_UCODE_LOADER_AMD; 1478 else if (cpu_vendor == CPUVENDOR_INTEL) 1479 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 1480 else 1481 return; 1482 1483 ucode.data = &ucvers; 1484 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 1485 #ifdef __i386__ 1486 struct cpu_ucode_version_64 ucode_64; 1487 if (errno != ENOTTY) 1488 return; 1489 /* Try the 64 bit ioctl */ 1490 memset(&ucode_64, 0, sizeof ucode_64); 1491 ucode_64.data = &ucvers; 1492 ucode_64.loader_version = ucode.loader_version; 1493 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 1494 return; 1495 #endif 1496 } 1497 1498 if (cpu_vendor == CPUVENDOR_AMD) 1499 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 1500 else if (cpu_vendor == CPUVENDOR_INTEL) 1501 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 1502 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 1503 } 1504 1505 static const char * 1506 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 1507 const char *sep) 1508 { 1509 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1510 char human_num[HUMAN_BUFSIZE]; 1511 1512 if (cai->cai_totalsize == 0) 1513 return sep; 1514 1515 if (sep == NULL) 1516 aprint_verbose_dev(ci->ci_dev, ""); 1517 else 1518 aprint_verbose("%s", sep); 1519 if (name != NULL) 1520 aprint_verbose("%s ", name); 1521 1522 if (cai->cai_string != NULL) { 1523 aprint_verbose("%s ", cai->cai_string); 1524 } else { 1525 (void)humanize_number(human_num, sizeof(human_num), 1526 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 1527 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 1528 } 1529 switch (cai->cai_associativity) { 1530 case 0: 1531 aprint_verbose("disabled"); 1532 break; 1533 case 1: 1534 aprint_verbose("direct-mapped"); 1535 break; 1536 case 0xff: 1537 aprint_verbose("fully associative"); 1538 break; 1539 default: 1540 aprint_verbose("%d-way", cai->cai_associativity); 1541 break; 1542 } 1543 return ", "; 1544 } 1545 1546 static const char * 1547 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 1548 const char *sep) 1549 { 1550 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1551 char human_num[HUMAN_BUFSIZE]; 1552 1553 if (cai->cai_totalsize == 0) 1554 return sep; 1555 1556 if (sep == NULL) 1557 aprint_verbose_dev(ci->ci_dev, ""); 1558 else 1559 aprint_verbose("%s", sep); 1560 if (name != NULL) 1561 aprint_verbose("%s ", name); 1562 1563 if (cai->cai_string != NULL) { 1564 aprint_verbose("%s", cai->cai_string); 1565 } else { 1566 (void)humanize_number(human_num, sizeof(human_num), 1567 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 1568 aprint_verbose("%d %s entries ", cai->cai_totalsize, 1569 human_num); 1570 switch (cai->cai_associativity) { 1571 case 0: 1572 aprint_verbose("disabled"); 1573 break; 1574 case 1: 1575 aprint_verbose("direct-mapped"); 1576 break; 1577 case 0xff: 1578 aprint_verbose("fully associative"); 1579 break; 1580 default: 1581 aprint_verbose("%d-way", cai->cai_associativity); 1582 break; 1583 } 1584 } 1585 return ", "; 1586 } 1587 1588 static const struct x86_cache_info * 1589 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 1590 { 1591 int i; 1592 1593 for (i = 0; cai[i].cai_desc != 0; i++) { 1594 if (cai[i].cai_desc == desc) 1595 return (&cai[i]); 1596 } 1597 1598 return (NULL); 1599 } 1600 1601 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 1602 AMD_L2CACHE_INFO; 1603 1604 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 1605 AMD_L3CACHE_INFO; 1606 1607 static void 1608 amd_cpu_cacheinfo(struct cpu_info *ci) 1609 { 1610 const struct x86_cache_info *cp; 1611 struct x86_cache_info *cai; 1612 u_int descs[4]; 1613 u_int lfunc; 1614 1615 /* 1616 * K5 model 0 has none of this info. 1617 */ 1618 if (ci->ci_family == 5 && ci->ci_model == 0) 1619 return; 1620 1621 /* 1622 * Determine the largest extended function value. 1623 */ 1624 x86_cpuid(0x80000000, descs); 1625 lfunc = descs[0]; 1626 1627 /* 1628 * Determine L1 cache/TLB info. 1629 */ 1630 if (lfunc < 0x80000005) { 1631 /* No L1 cache info available. */ 1632 return; 1633 } 1634 1635 x86_cpuid(0x80000005, descs); 1636 1637 /* 1638 * K6-III and higher have large page TLBs. 1639 */ 1640 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1641 cai = &ci->ci_cinfo[CAI_ITLB2]; 1642 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1643 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1644 cai->cai_linesize = largepagesize; 1645 1646 cai = &ci->ci_cinfo[CAI_DTLB2]; 1647 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1648 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1649 cai->cai_linesize = largepagesize; 1650 } 1651 1652 cai = &ci->ci_cinfo[CAI_ITLB]; 1653 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1654 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1655 cai->cai_linesize = (4 * 1024); 1656 1657 cai = &ci->ci_cinfo[CAI_DTLB]; 1658 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1659 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1660 cai->cai_linesize = (4 * 1024); 1661 1662 cai = &ci->ci_cinfo[CAI_DCACHE]; 1663 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1664 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1665 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1666 1667 cai = &ci->ci_cinfo[CAI_ICACHE]; 1668 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1669 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1670 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1671 1672 /* 1673 * Determine L2 cache/TLB info. 1674 */ 1675 if (lfunc < 0x80000006) { 1676 /* No L2 cache info available. */ 1677 return; 1678 } 1679 1680 x86_cpuid(0x80000006, descs); 1681 1682 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1683 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1684 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1685 cai->cai_linesize = (4 * 1024); 1686 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1687 cai->cai_associativity); 1688 if (cp != NULL) 1689 cai->cai_associativity = cp->cai_associativity; 1690 else 1691 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1692 1693 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1694 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1695 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1696 cai->cai_linesize = largepagesize; 1697 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1698 cai->cai_associativity); 1699 if (cp != NULL) 1700 cai->cai_associativity = cp->cai_associativity; 1701 else 1702 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1703 1704 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1705 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1706 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1707 cai->cai_linesize = (4 * 1024); 1708 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1709 cai->cai_associativity); 1710 if (cp != NULL) 1711 cai->cai_associativity = cp->cai_associativity; 1712 else 1713 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1714 1715 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1716 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1717 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1718 cai->cai_linesize = largepagesize; 1719 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1720 cai->cai_associativity); 1721 if (cp != NULL) 1722 cai->cai_associativity = cp->cai_associativity; 1723 else 1724 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1725 1726 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1727 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1728 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1729 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1730 1731 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1732 cai->cai_associativity); 1733 if (cp != NULL) 1734 cai->cai_associativity = cp->cai_associativity; 1735 else 1736 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1737 1738 /* 1739 * Determine L3 cache info on AMD Family 10h and newer processors 1740 */ 1741 if (ci->ci_family >= 0x10) { 1742 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1743 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1744 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1745 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1746 1747 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1748 cai->cai_associativity); 1749 if (cp != NULL) 1750 cai->cai_associativity = cp->cai_associativity; 1751 else 1752 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1753 } 1754 1755 /* 1756 * Determine 1GB TLB info. 1757 */ 1758 if (lfunc < 0x80000019) { 1759 /* No 1GB TLB info available. */ 1760 return; 1761 } 1762 1763 x86_cpuid(0x80000019, descs); 1764 1765 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1766 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1767 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1768 cai->cai_linesize = (1024 * 1024 * 1024); 1769 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1770 cai->cai_associativity); 1771 if (cp != NULL) 1772 cai->cai_associativity = cp->cai_associativity; 1773 else 1774 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1775 1776 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1777 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1778 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1779 cai->cai_linesize = (1024 * 1024 * 1024); 1780 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1781 cai->cai_associativity); 1782 if (cp != NULL) 1783 cai->cai_associativity = cp->cai_associativity; 1784 else 1785 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1786 1787 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1788 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1789 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1790 cai->cai_linesize = (1024 * 1024 * 1024); 1791 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1792 cai->cai_associativity); 1793 if (cp != NULL) 1794 cai->cai_associativity = cp->cai_associativity; 1795 else 1796 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1797 1798 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1799 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1800 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1801 cai->cai_linesize = (1024 * 1024 * 1024); 1802 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1803 cai->cai_associativity); 1804 if (cp != NULL) 1805 cai->cai_associativity = cp->cai_associativity; 1806 else 1807 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1808 } 1809 1810 static void 1811 via_cpu_cacheinfo(struct cpu_info *ci) 1812 { 1813 struct x86_cache_info *cai; 1814 int stepping; 1815 u_int descs[4]; 1816 u_int lfunc; 1817 1818 stepping = CPUID2STEPPING(ci->ci_signature); 1819 1820 /* 1821 * Determine the largest extended function value. 1822 */ 1823 x86_cpuid(0x80000000, descs); 1824 lfunc = descs[0]; 1825 1826 /* 1827 * Determine L1 cache/TLB info. 1828 */ 1829 if (lfunc < 0x80000005) { 1830 /* No L1 cache info available. */ 1831 return; 1832 } 1833 1834 x86_cpuid(0x80000005, descs); 1835 1836 cai = &ci->ci_cinfo[CAI_ITLB]; 1837 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1838 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1839 cai->cai_linesize = (4 * 1024); 1840 1841 cai = &ci->ci_cinfo[CAI_DTLB]; 1842 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1843 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1844 cai->cai_linesize = (4 * 1024); 1845 1846 cai = &ci->ci_cinfo[CAI_DCACHE]; 1847 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1848 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1849 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1850 if (ci->ci_model == 9 && stepping == 8) { 1851 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1852 cai->cai_associativity = 2; 1853 } 1854 1855 cai = &ci->ci_cinfo[CAI_ICACHE]; 1856 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1857 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1858 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1859 if (ci->ci_model == 9 && stepping == 8) { 1860 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1861 cai->cai_associativity = 2; 1862 } 1863 1864 /* 1865 * Determine L2 cache/TLB info. 1866 */ 1867 if (lfunc < 0x80000006) { 1868 /* No L2 cache info available. */ 1869 return; 1870 } 1871 1872 x86_cpuid(0x80000006, descs); 1873 1874 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1875 if (ci->ci_model >= 9) { 1876 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1877 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1878 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1879 } else { 1880 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1881 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1882 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1883 } 1884 } 1885 1886 static void 1887 x86_print_cacheinfo(struct cpu_info *ci) 1888 { 1889 const char *sep; 1890 1891 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 1892 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 1893 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 1894 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 1895 if (sep != NULL) 1896 aprint_verbose("\n"); 1897 } 1898 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 1899 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 1900 if (sep != NULL) 1901 aprint_verbose("\n"); 1902 } 1903 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 1904 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 1905 if (sep != NULL) 1906 aprint_verbose("\n"); 1907 } 1908 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 1909 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 1910 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 1911 if (sep != NULL) 1912 aprint_verbose("\n"); 1913 } 1914 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 1915 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 1916 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 1917 if (sep != NULL) 1918 aprint_verbose("\n"); 1919 } 1920 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 1921 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 1922 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 1923 if (sep != NULL) 1924 aprint_verbose("\n"); 1925 } 1926 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 1927 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 1928 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 1929 if (sep != NULL) 1930 aprint_verbose("\n"); 1931 } 1932 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 1933 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", NULL); 1934 if (sep != NULL) 1935 aprint_verbose("\n"); 1936 } 1937 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 1938 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", NULL); 1939 if (sep != NULL) 1940 aprint_verbose("\n"); 1941 } 1942 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 1943 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", NULL); 1944 if (sep != NULL) 1945 aprint_verbose("\n"); 1946 } 1947 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 1948 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", NULL); 1949 if (sep != NULL) 1950 aprint_verbose("\n"); 1951 } 1952 } 1953 1954 static void 1955 powernow_probe(struct cpu_info *ci) 1956 { 1957 uint32_t regs[4]; 1958 char buf[256]; 1959 1960 x86_cpuid(0x80000007, regs); 1961 1962 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 1963 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 1964 buf); 1965 } 1966 1967 int 1968 ucodeupdate_check(int fd, struct cpu_ucode *uc) 1969 { 1970 struct cpu_info ci; 1971 int loader_version, res; 1972 struct cpu_ucode_version versreq; 1973 1974 cpu_probe_base_features(&ci, "unknown"); 1975 1976 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 1977 loader_version = CPU_UCODE_LOADER_AMD; 1978 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 1979 loader_version = CPU_UCODE_LOADER_INTEL1; 1980 else 1981 return -1; 1982 1983 /* check whether the kernel understands this loader version */ 1984 versreq.loader_version = loader_version; 1985 versreq.data = 0; 1986 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 1987 if (res) 1988 return -1; 1989 1990 switch (loader_version) { 1991 case CPU_UCODE_LOADER_AMD: 1992 if (uc->cpu_nr != -1) { 1993 /* printf? */ 1994 return -1; 1995 } 1996 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 1997 break; 1998 case CPU_UCODE_LOADER_INTEL1: 1999 if (uc->cpu_nr == -1) 2000 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2001 else 2002 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2003 break; 2004 default: /* can't happen */ 2005 return -1; 2006 } 2007 uc->loader_version = loader_version; 2008 return 0; 2009 } 2010
Indexes created Sun Sep 28 16:09:52 GMT 2025