i386.c revision 1.43
1 /* $NetBSD: i386.c,v 1.43 2013/10/04 17:12:48 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c)2008 YAMAMOTO Takashi, 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 #ifndef lint 60 __RCSID("$NetBSD: i386.c,v 1.43 2013/10/04 17:12:48 msaitoh Exp $"); 61 #endif /* not lint */ 62 63 #include <sys/types.h> 64 #include <sys/param.h> 65 #include <sys/bitops.h> 66 #include <sys/sysctl.h> 67 #include <sys/ioctl.h> 68 #include <sys/cpuio.h> 69 70 #include <errno.h> 71 #include <string.h> 72 #include <stdio.h> 73 #include <stdlib.h> 74 #include <err.h> 75 #include <assert.h> 76 #include <math.h> 77 #include <util.h> 78 79 #include <machine/specialreg.h> 80 #include <machine/cpu.h> 81 82 #include <x86/cpuvar.h> 83 #include <x86/cputypes.h> 84 #include <x86/cacheinfo.h> 85 #include <x86/cpu_ucode.h> 86 87 #include "../cpuctl.h" 88 #include "cpuctl_i386.h" 89 90 /* Size of buffer for printing humanized numbers */ 91 #define HUMAN_BUFSIZE sizeof("999KB") 92 93 struct cpu_info { 94 const char *ci_dev; 95 int32_t ci_cpu_type; /* for cpu's without cpuid */ 96 int32_t ci_cpuid_level; /* highest cpuid supported */ 97 uint32_t ci_signature; /* X86 cpuid type */ 98 uint32_t ci_family; /* from ci_signature */ 99 uint32_t ci_model; /* from ci_signature */ 100 uint32_t ci_feat_val[8]; /* X86 CPUID feature bits 101 * [0] basic features %edx 102 * [1] basic features %ecx 103 * [2] extended features %edx 104 * [3] extended features %ecx 105 * [4] VIA padlock features 106 * [5] XCR0 bits (d:0 %eax) 107 * [6] xsave flags (d:1 %eax) 108 */ 109 uint32_t ci_cpu_class; /* CPU class */ 110 uint32_t ci_brand_id; /* Intel brand id */ 111 uint32_t ci_vendor[4]; /* vendor string */ 112 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 113 uint64_t ci_tsc_freq; /* cpu cycles/second */ 114 uint8_t ci_packageid; 115 uint8_t ci_coreid; 116 uint8_t ci_smtid; 117 uint32_t ci_initapicid; 118 119 uint32_t ci_cur_xsave; 120 uint32_t ci_max_xsave; 121 122 struct x86_cache_info ci_cinfo[CAI_COUNT]; 123 void (*ci_info)(struct cpu_info *); 124 }; 125 126 struct cpu_nocpuid_nameclass { 127 int cpu_vendor; 128 const char *cpu_vendorname; 129 const char *cpu_name; 130 int cpu_class; 131 void (*cpu_setup)(struct cpu_info *); 132 void (*cpu_cacheinfo)(struct cpu_info *); 133 void (*cpu_info)(struct cpu_info *); 134 }; 135 136 struct cpu_cpuid_nameclass { 137 const char *cpu_id; 138 int cpu_vendor; 139 const char *cpu_vendorname; 140 struct cpu_cpuid_family { 141 int cpu_class; 142 const char *cpu_models[256]; 143 const char *cpu_model_default; 144 void (*cpu_setup)(struct cpu_info *); 145 void (*cpu_probe)(struct cpu_info *); 146 void (*cpu_info)(struct cpu_info *); 147 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 148 }; 149 150 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO; 151 152 /* 153 * Map Brand ID from cpuid instruction to brand name. 154 * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32 155 * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32 156 * Architectures Software Developer's Manual, Volume 2A". 157 */ 158 static const char * const i386_intel_brand[] = { 159 "", /* Unsupported */ 160 "Celeron", /* Intel (R) Celeron (TM) processor */ 161 "Pentium III", /* Intel (R) Pentium (R) III processor */ 162 "Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */ 163 "Pentium III", /* Intel (R) Pentium (R) III processor */ 164 "", /* 0x05: Reserved */ 165 "Mobile Pentium III", /* Mobile Intel (R) Pentium (R) III processor-M */ 166 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 167 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 168 "Pentium 4", /* Intel (R) Pentium (R) 4 processor */ 169 "Celeron", /* Intel (R) Celeron (TM) processor */ 170 "Xeon", /* Intel (R) Xeon (TM) processor */ 171 "Xeon MP", /* Intel (R) Xeon (TM) processor MP */ 172 "", /* 0x0d: Reserved */ 173 "Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */ 174 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 175 "", /* 0x10: Reserved */ 176 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 177 "Celeron M", /* Intel (R) Celeron (R) M processor */ 178 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 179 "Celeron", /* Intel (R) Celeron (R) processor */ 180 "Mobile Genuine", /* Moblie Genuine Intel (R) processor */ 181 "Pentium M", /* Intel (R) Pentium (R) M processor */ 182 "Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */ 183 }; 184 185 /* 186 * AMD processors don't have Brand IDs, so we need these names for probe. 187 */ 188 static const char * const amd_brand[] = { 189 "", 190 "Duron", /* AMD Duron(tm) */ 191 "MP", /* AMD Athlon(tm) MP */ 192 "XP", /* AMD Athlon(tm) XP */ 193 "4" /* AMD Athlon(tm) 4 */ 194 }; 195 196 static int cpu_vendor; 197 static char cpu_brand_string[49]; 198 static char amd_brand_name[48]; 199 static int use_pae, largepagesize; 200 201 static void via_cpu_probe(struct cpu_info *); 202 static void amd_family6_probe(struct cpu_info *); 203 static void intel_family_new_probe(struct cpu_info *); 204 static const char *intel_family6_name(struct cpu_info *); 205 static const char *amd_amd64_name(struct cpu_info *); 206 static void amd_family5_setup(struct cpu_info *); 207 static void transmeta_cpu_info(struct cpu_info *); 208 static const char *print_cache_config(struct cpu_info *, int, const char *, 209 const char *); 210 static const char *print_tlb_config(struct cpu_info *, int, const char *, 211 const char *); 212 static void amd_cpu_cacheinfo(struct cpu_info *); 213 static void via_cpu_cacheinfo(struct cpu_info *); 214 static void x86_print_cacheinfo(struct cpu_info *); 215 static const struct x86_cache_info *cache_info_lookup( 216 const struct x86_cache_info *, uint8_t); 217 static void cyrix6x86_cpu_setup(struct cpu_info *); 218 static void winchip_cpu_setup(struct cpu_info *); 219 static void amd_family5_setup(struct cpu_info *); 220 static void powernow_probe(struct cpu_info *); 221 222 /* 223 * Note: these are just the ones that may not have a cpuid instruction. 224 * We deal with the rest in a different way. 225 */ 226 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 227 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 228 NULL, NULL, NULL }, /* CPU_386SX */ 229 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 230 NULL, NULL, NULL }, /* CPU_386 */ 231 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 232 NULL, NULL, NULL }, /* CPU_486SX */ 233 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 234 NULL, NULL, NULL }, /* CPU_486 */ 235 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 236 NULL, NULL, NULL }, /* CPU_486DLC */ 237 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 238 NULL, NULL, NULL }, /* CPU_6x86 */ 239 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 240 NULL, NULL, NULL }, /* CPU_NX586 */ 241 }; 242 243 const char *classnames[] = { 244 "386", 245 "486", 246 "586", 247 "686" 248 }; 249 250 const char *modifiers[] = { 251 "", 252 "OverDrive", 253 "Dual", 254 "" 255 }; 256 257 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 258 { 259 /* 260 * For Intel processors, check Chapter 35Model-specific 261 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures 262 * Software Developer's Manual, Volume 3C". 263 */ 264 "GenuineIntel", 265 CPUVENDOR_INTEL, 266 "Intel", 267 /* Family 4 */ 268 { { 269 CPUCLASS_486, 270 { 271 "486DX", "486DX", "486SX", "486DX2", "486SL", 272 "486SX2", 0, "486DX2 W/B Enhanced", 273 "486DX4", 0, 0, 0, 0, 0, 0, 0, 274 }, 275 "486", /* Default */ 276 NULL, 277 NULL, 278 NULL, 279 }, 280 /* Family 5 */ 281 { 282 CPUCLASS_586, 283 { 284 "Pentium (P5 A-step)", "Pentium (P5)", 285 "Pentium (P54C)", "Pentium (P24T)", 286 "Pentium/MMX", "Pentium", 0, 287 "Pentium (P54C)", "Pentium/MMX (Tillamook)", 288 0, 0, 0, 0, 0, 0, 0, 289 }, 290 "Pentium", /* Default */ 291 NULL, 292 NULL, 293 NULL, 294 }, 295 /* Family 6 */ 296 { 297 CPUCLASS_686, 298 { 299 [0x00] = "Pentium Pro (A-step)", 300 [0x01] = "Pentium Pro", 301 [0x03] = "Pentium II (Klamath)", 302 [0x04] = "Pentium Pro", 303 [0x05] = "Pentium II/Celeron (Deschutes)", 304 [0x06] = "Celeron (Mendocino)", 305 [0x07] = "Pentium III (Katmai)", 306 [0x08] = "Pentium III (Coppermine)", 307 [0x09] = "Pentium M (Banias)", 308 [0x0a] = "Pentium III Xeon (Cascades)", 309 [0x0b] = "Pentium III (Tualatin)", 310 [0x0d] = "Pentium M (Dothan)", 311 [0x0e] = "Pentium Core Duo, Core solo", 312 [0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, " 313 "Core 2 Quad 6xxx, " 314 "Core 2 Extreme 6xxx, " 315 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx " 316 "and Pentium DC", 317 [0x15] = "EP80579 Integrated Processor", 318 [0x16] = "Celeron (45nm)", 319 [0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, " 320 "Core 2 Quad 8xxx and 9xxx", 321 [0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx " 322 "(Nehalem)", 323 [0x1c] = "Atom Family", 324 [0x1d] = "XeonMP 74xx (Nehalem)", 325 [0x1e] = "Core i7 and i5", 326 [0x1f] = "Core i7 and i5", 327 [0x25] = "Xeon 36xx & 56xx, i7, i5 and i3", 328 [0x26] = "Atom Family", 329 [0x27] = "Atom Family", 330 [0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, " 331 "i3 2xxx", 332 [0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3", 333 [0x2d] = "Xeon E5 Sandy bridy family", 334 [0x2e] = "Xeon 75xx & 65xx", 335 [0x2f] = "Xeon E7 family", 336 [0x35] = "Atom Family", 337 [0x36] = "Atom S1000", 338 [0x37] = "Atom C2000, E3000", 339 [0x3a] = "Xeon E3-1200v2 and 3rd gen core, " 340 "Ivy bridge", 341 [0x3c] = "4th gen Core, Xeon E3-12xx v3 " 342 "(Haswell)", 343 [0x3d] = "Next gen Core", 344 [0x3e] = "Next gen Xeon E5/E7, Ivy bridge", 345 [0x3f] = "Future gen Xeon", 346 [0x45] = "4th gen Core, Xeon E3-12xx v3 " 347 "(Haswell)", 348 [0x46] = "4th gen Core, Xeon E3-12xx v3 " 349 "(Haswell)", 350 [0x4d] = "Atom C2000, E3000", 351 }, 352 "Pentium Pro, II or III", /* Default */ 353 NULL, 354 intel_family_new_probe, 355 NULL, 356 }, 357 /* Family > 6 */ 358 { 359 CPUCLASS_686, 360 { 361 0, 0, 0, 0, 0, 0, 0, 0, 362 0, 0, 0, 0, 0, 0, 0, 0, 363 }, 364 "Pentium 4", /* Default */ 365 NULL, 366 intel_family_new_probe, 367 NULL, 368 } } 369 }, 370 { 371 "AuthenticAMD", 372 CPUVENDOR_AMD, 373 "AMD", 374 /* Family 4 */ 375 { { 376 CPUCLASS_486, 377 { 378 0, 0, 0, "Am486DX2 W/T", 379 0, 0, 0, "Am486DX2 W/B", 380 "Am486DX4 W/T or Am5x86 W/T 150", 381 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 382 0, 0, "Am5x86 W/T 133/160", 383 "Am5x86 W/B 133/160", 384 }, 385 "Am486 or Am5x86", /* Default */ 386 NULL, 387 NULL, 388 NULL, 389 }, 390 /* Family 5 */ 391 { 392 CPUCLASS_586, 393 { 394 "K5", "K5", "K5", "K5", 0, 0, "K6", 395 "K6", "K6-2", "K6-III", "Geode LX", 0, 0, 396 "K6-2+/III+", 0, 0, 397 }, 398 "K5 or K6", /* Default */ 399 amd_family5_setup, 400 NULL, 401 amd_cpu_cacheinfo, 402 }, 403 /* Family 6 */ 404 { 405 CPUCLASS_686, 406 { 407 0, "Athlon Model 1", "Athlon Model 2", 408 "Duron", "Athlon Model 4 (Thunderbird)", 409 0, "Athlon", "Duron", "Athlon", 0, 410 "Athlon", 0, 0, 0, 0, 0, 411 }, 412 "K7 (Athlon)", /* Default */ 413 NULL, 414 amd_family6_probe, 415 amd_cpu_cacheinfo, 416 }, 417 /* Family > 6 */ 418 { 419 CPUCLASS_686, 420 { 421 0, 0, 0, 0, 0, 0, 0, 0, 422 0, 0, 0, 0, 0, 0, 0, 0, 423 }, 424 "Unknown K8 (Athlon)", /* Default */ 425 NULL, 426 amd_family6_probe, 427 amd_cpu_cacheinfo, 428 } } 429 }, 430 { 431 "CyrixInstead", 432 CPUVENDOR_CYRIX, 433 "Cyrix", 434 /* Family 4 */ 435 { { 436 CPUCLASS_486, 437 { 438 0, 0, 0, 439 "MediaGX", 440 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 441 }, 442 "486", /* Default */ 443 cyrix6x86_cpu_setup, /* XXX ?? */ 444 NULL, 445 NULL, 446 }, 447 /* Family 5 */ 448 { 449 CPUCLASS_586, 450 { 451 0, 0, "6x86", 0, 452 "MMX-enhanced MediaGX (GXm)", /* or Geode? */ 453 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 454 }, 455 "6x86", /* Default */ 456 cyrix6x86_cpu_setup, 457 NULL, 458 NULL, 459 }, 460 /* Family 6 */ 461 { 462 CPUCLASS_686, 463 { 464 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 465 0, 0, 0, 0, 0, 0, 0, 0, 466 }, 467 "6x86MX", /* Default */ 468 cyrix6x86_cpu_setup, 469 NULL, 470 NULL, 471 }, 472 /* Family > 6 */ 473 { 474 CPUCLASS_686, 475 { 476 0, 0, 0, 0, 0, 0, 0, 0, 477 0, 0, 0, 0, 0, 0, 0, 0, 478 }, 479 "Unknown 6x86MX", /* Default */ 480 NULL, 481 NULL, 482 NULL, 483 } } 484 }, 485 { /* MediaGX is now owned by National Semiconductor */ 486 "Geode by NSC", 487 CPUVENDOR_CYRIX, /* XXX */ 488 "National Semiconductor", 489 /* Family 4, NSC never had any of these */ 490 { { 491 CPUCLASS_486, 492 { 493 0, 0, 0, 0, 0, 0, 0, 0, 494 0, 0, 0, 0, 0, 0, 0, 0, 495 }, 496 "486 compatible", /* Default */ 497 NULL, 498 NULL, 499 NULL, 500 }, 501 /* Family 5: Geode family, formerly MediaGX */ 502 { 503 CPUCLASS_586, 504 { 505 0, 0, 0, 0, 506 "Geode GX1", 507 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 508 }, 509 "Geode", /* Default */ 510 cyrix6x86_cpu_setup, 511 NULL, 512 amd_cpu_cacheinfo, 513 }, 514 /* Family 6, not yet available from NSC */ 515 { 516 CPUCLASS_686, 517 { 518 0, 0, 0, 0, 0, 0, 0, 0, 519 0, 0, 0, 0, 0, 0, 0, 0, 520 }, 521 "Pentium Pro compatible", /* Default */ 522 NULL, 523 NULL, 524 NULL, 525 }, 526 /* Family > 6, not yet available from NSC */ 527 { 528 CPUCLASS_686, 529 { 530 0, 0, 0, 0, 0, 0, 0, 0, 531 0, 0, 0, 0, 0, 0, 0, 0, 532 }, 533 "Pentium Pro compatible", /* Default */ 534 NULL, 535 NULL, 536 NULL, 537 } } 538 }, 539 { 540 "CentaurHauls", 541 CPUVENDOR_IDT, 542 "IDT", 543 /* Family 4, IDT never had any of these */ 544 { { 545 CPUCLASS_486, 546 { 547 0, 0, 0, 0, 0, 0, 0, 0, 548 0, 0, 0, 0, 0, 0, 0, 0, 549 }, 550 "486 compatible", /* Default */ 551 NULL, 552 NULL, 553 NULL, 554 }, 555 /* Family 5 */ 556 { 557 CPUCLASS_586, 558 { 559 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 560 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 561 }, 562 "WinChip", /* Default */ 563 winchip_cpu_setup, 564 NULL, 565 NULL, 566 }, 567 /* Family 6, VIA acquired IDT Centaur design subsidiary */ 568 { 569 CPUCLASS_686, 570 { 571 0, 0, 0, 0, 0, 0, "C3 Samuel", 572 "C3 Samuel 2/Ezra", "C3 Ezra-T", 573 "C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther", 574 0, "VIA Nano", 575 }, 576 "Unknown VIA/IDT", /* Default */ 577 NULL, 578 via_cpu_probe, 579 via_cpu_cacheinfo, 580 }, 581 /* Family > 6, not yet available from VIA */ 582 { 583 CPUCLASS_686, 584 { 585 0, 0, 0, 0, 0, 0, 0, 0, 586 0, 0, 0, 0, 0, 0, 0, 0, 587 }, 588 "Pentium Pro compatible", /* Default */ 589 NULL, 590 NULL, 591 NULL, 592 } } 593 }, 594 { 595 "GenuineTMx86", 596 CPUVENDOR_TRANSMETA, 597 "Transmeta", 598 /* Family 4, Transmeta never had any of these */ 599 { { 600 CPUCLASS_486, 601 { 602 0, 0, 0, 0, 0, 0, 0, 0, 603 0, 0, 0, 0, 0, 0, 0, 0, 604 }, 605 "486 compatible", /* Default */ 606 NULL, 607 NULL, 608 NULL, 609 }, 610 /* Family 5 */ 611 { 612 CPUCLASS_586, 613 { 614 0, 0, 0, 0, 0, 0, 0, 0, 615 0, 0, 0, 0, 0, 0, 0, 0, 616 }, 617 "Crusoe", /* Default */ 618 NULL, 619 NULL, 620 transmeta_cpu_info, 621 }, 622 /* Family 6, not yet available from Transmeta */ 623 { 624 CPUCLASS_686, 625 { 626 0, 0, 0, 0, 0, 0, 0, 0, 627 0, 0, 0, 0, 0, 0, 0, 0, 628 }, 629 "Pentium Pro compatible", /* Default */ 630 NULL, 631 NULL, 632 NULL, 633 }, 634 /* Family > 6, not yet available from Transmeta */ 635 { 636 CPUCLASS_686, 637 { 638 0, 0, 0, 0, 0, 0, 0, 0, 639 0, 0, 0, 0, 0, 0, 0, 0, 640 }, 641 "Pentium Pro compatible", /* Default */ 642 NULL, 643 NULL, 644 NULL, 645 } } 646 } 647 }; 648 649 /* 650 * disable the TSC such that we don't use the TSC in microtime(9) 651 * because some CPUs got the implementation wrong. 652 */ 653 static void 654 disable_tsc(struct cpu_info *ci) 655 { 656 if (ci->ci_feat_val[0] & CPUID_TSC) { 657 ci->ci_feat_val[0] &= ~CPUID_TSC; 658 aprint_error("WARNING: broken TSC disabled\n"); 659 } 660 } 661 662 static void 663 cyrix6x86_cpu_setup(struct cpu_info *ci) 664 { 665 666 /* 667 * Do not disable the TSC on the Geode GX, it's reported to 668 * work fine. 669 */ 670 if (ci->ci_signature != 0x552) 671 disable_tsc(ci); 672 } 673 674 void 675 winchip_cpu_setup(struct cpu_info *ci) 676 { 677 switch (ci->ci_model) { 678 case 4: /* WinChip C6 */ 679 disable_tsc(ci); 680 } 681 } 682 683 684 static void 685 identifycpu_cpuids(struct cpu_info *ci) 686 { 687 const char *cpuname = ci->ci_dev; 688 u_int lp_max = 1; /* logical processors per package */ 689 u_int smt_max; /* smt per core */ 690 u_int core_max = 1; /* core per package */ 691 u_int smt_bits, core_bits; 692 uint32_t descs[4]; 693 uint32_t highest_basic_info; 694 695 aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid); 696 ci->ci_packageid = ci->ci_initapicid; 697 ci->ci_coreid = 0; 698 ci->ci_smtid = 0; 699 if (cpu_vendor != CPUVENDOR_INTEL) { 700 return; 701 } 702 703 /* 704 * 253668.pdf 7.10.2 705 */ 706 707 if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) { 708 x86_cpuid(1, descs); 709 lp_max = (descs[1] >> 16) & 0xff; 710 } 711 x86_cpuid(0, descs); 712 highest_basic_info = descs[0]; 713 if (highest_basic_info >= 4) { 714 x86_cpuid2(4, 0, descs); 715 core_max = (descs[0] >> 26) + 1; 716 } 717 assert(lp_max >= core_max); 718 smt_max = lp_max / core_max; 719 smt_bits = ilog2(smt_max - 1) + 1; 720 core_bits = ilog2(core_max - 1) + 1; 721 if (smt_bits + core_bits) { 722 ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits); 723 } 724 aprint_verbose("%s: Cluster/Package ID %u\n", cpuname, 725 ci->ci_packageid); 726 if (core_bits) { 727 u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1); 728 729 ci->ci_coreid = 730 __SHIFTOUT(ci->ci_initapicid, core_mask); 731 aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid); 732 } 733 if (smt_bits) { 734 u_int smt_mask = __BITS((int)0, (int)(smt_bits - 1)); 735 736 ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid, smt_mask); 737 aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid); 738 } 739 } 740 741 static void 742 via_cpu_probe(struct cpu_info *ci) 743 { 744 u_int stepping = CPUID2STEPPING(ci->ci_signature); 745 u_int descs[4]; 746 u_int lfunc; 747 748 /* 749 * Determine the largest extended function value. 750 */ 751 x86_cpuid(0x80000000, descs); 752 lfunc = descs[0]; 753 754 /* 755 * Determine the extended feature flags. 756 */ 757 if (lfunc >= 0x80000001) { 758 x86_cpuid(0x80000001, descs); 759 ci->ci_feat_val[2] |= descs[3]; 760 } 761 762 if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3)) 763 return; 764 765 /* Nehemiah or Esther */ 766 x86_cpuid(0xc0000000, descs); 767 lfunc = descs[0]; 768 if (lfunc < 0xc0000001) /* no ACE, no RNG */ 769 return; 770 771 x86_cpuid(0xc0000001, descs); 772 lfunc = descs[3]; 773 ci->ci_feat_val[4] = lfunc; 774 } 775 776 static const char * 777 intel_family6_name(struct cpu_info *ci) 778 { 779 const char *ret = NULL; 780 u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize; 781 782 if (ci->ci_model == 5) { 783 switch (l2cache) { 784 case 0: 785 case 128 * 1024: 786 ret = "Celeron (Covington)"; 787 break; 788 case 256 * 1024: 789 ret = "Mobile Pentium II (Dixon)"; 790 break; 791 case 512 * 1024: 792 ret = "Pentium II"; 793 break; 794 case 1 * 1024 * 1024: 795 case 2 * 1024 * 1024: 796 ret = "Pentium II Xeon"; 797 break; 798 } 799 } else if (ci->ci_model == 6) { 800 switch (l2cache) { 801 case 256 * 1024: 802 case 512 * 1024: 803 ret = "Mobile Pentium II"; 804 break; 805 } 806 } else if (ci->ci_model == 7) { 807 switch (l2cache) { 808 case 512 * 1024: 809 ret = "Pentium III"; 810 break; 811 case 1 * 1024 * 1024: 812 case 2 * 1024 * 1024: 813 ret = "Pentium III Xeon"; 814 break; 815 } 816 } else if (ci->ci_model >= 8) { 817 if (ci->ci_brand_id && ci->ci_brand_id < 0x10) { 818 switch (ci->ci_brand_id) { 819 case 0x3: 820 if (ci->ci_signature == 0x6B1) 821 ret = "Celeron"; 822 break; 823 case 0x8: 824 if (ci->ci_signature >= 0xF13) 825 ret = "genuine processor"; 826 break; 827 case 0xB: 828 if (ci->ci_signature >= 0xF13) 829 ret = "Xeon MP"; 830 break; 831 case 0xE: 832 if (ci->ci_signature < 0xF13) 833 ret = "Xeon"; 834 break; 835 } 836 if (ret == NULL) 837 ret = i386_intel_brand[ci->ci_brand_id]; 838 } 839 } 840 841 return ret; 842 } 843 844 /* 845 * Identify AMD64 CPU names from cpuid. 846 * 847 * Based on: 848 * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors" 849 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf 850 * "Revision Guide for AMD NPT Family 0Fh Processors" 851 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf 852 * and other miscellaneous reports. 853 * 854 * This is all rather pointless, these are cross 'brand' since the raw 855 * silicon is shared. 856 */ 857 static const char * 858 amd_amd64_name(struct cpu_info *ci) 859 { 860 static char family_str[32]; 861 862 /* Only called if family >= 15 */ 863 864 switch (ci->ci_family) { 865 case 15: 866 switch (ci->ci_model) { 867 case 0x21: /* rev JH-E1/E6 */ 868 case 0x41: /* rev JH-F2 */ 869 return "Dual-Core Opteron"; 870 case 0x23: /* rev JH-E6 (Toledo) */ 871 return "Dual-Core Opteron or Athlon 64 X2"; 872 case 0x43: /* rev JH-F2 (Windsor) */ 873 return "Athlon 64 FX or Athlon 64 X2"; 874 case 0x24: /* rev SH-E5 (Lancaster?) */ 875 return "Mobile Athlon 64 or Turion 64"; 876 case 0x05: /* rev SH-B0/B3/C0/CG (SledgeHammer?) */ 877 return "Opteron or Athlon 64 FX"; 878 case 0x15: /* rev SH-D0 */ 879 case 0x25: /* rev SH-E4 */ 880 return "Opteron"; 881 case 0x27: /* rev DH-E4, SH-E4 */ 882 return "Athlon 64 or Athlon 64 FX or Opteron"; 883 case 0x48: /* rev BH-F2 */ 884 return "Turion 64 X2"; 885 case 0x04: /* rev SH-B0/C0/CG (ClawHammer) */ 886 case 0x07: /* rev SH-CG (ClawHammer) */ 887 case 0x0b: /* rev CH-CG */ 888 case 0x14: /* rev SH-D0 */ 889 case 0x17: /* rev SH-D0 */ 890 case 0x1b: /* rev CH-D0 */ 891 return "Athlon 64"; 892 case 0x2b: /* rev BH-E4 (Manchester) */ 893 case 0x4b: /* rev BH-F2 (Windsor) */ 894 return "Athlon 64 X2"; 895 case 0x6b: /* rev BH-G1 (Brisbane) */ 896 return "Athlon X2 or Athlon 64 X2"; 897 case 0x08: /* rev CH-CG */ 898 case 0x0c: /* rev DH-CG (Newcastle) */ 899 case 0x0e: /* rev DH-CG (Newcastle?) */ 900 case 0x0f: /* rev DH-CG (Newcastle/Paris) */ 901 case 0x18: /* rev CH-D0 */ 902 case 0x1c: /* rev DH-D0 (Winchester) */ 903 case 0x1f: /* rev DH-D0 (Winchester/Victoria) */ 904 case 0x2c: /* rev DH-E3/E6 */ 905 case 0x2f: /* rev DH-E3/E6 (Venice/Palermo) */ 906 case 0x4f: /* rev DH-F2 (Orleans/Manila) */ 907 case 0x5f: /* rev DH-F2 (Orleans/Manila) */ 908 case 0x6f: /* rev DH-G1 */ 909 return "Athlon 64 or Sempron"; 910 default: 911 break; 912 } 913 return "Unknown AMD64 CPU"; 914 915 #if 0 916 case 16: 917 return "Family 10h"; 918 case 17: 919 return "Family 11h"; 920 case 18: 921 return "Family 12h"; 922 case 19: 923 return "Family 14h"; 924 case 20: 925 return "Family 15h"; 926 #endif 927 928 default: 929 break; 930 } 931 932 snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family); 933 return family_str; 934 } 935 936 static void 937 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname) 938 { 939 const struct x86_cache_info *cai; 940 u_int descs[4]; 941 int iterations, i, j; 942 uint8_t desc; 943 uint32_t brand[12]; 944 945 memset(ci, 0, sizeof(*ci)); 946 ci->ci_dev = cpuname; 947 948 ci->ci_cpu_type = x86_identify(); 949 if (ci->ci_cpu_type >= 0) { 950 /* Old pre-cpuid instruction cpu */ 951 ci->ci_cpuid_level = -1; 952 return; 953 } 954 955 x86_cpuid(0, descs); 956 ci->ci_cpuid_level = descs[0]; 957 ci->ci_vendor[0] = descs[1]; 958 ci->ci_vendor[2] = descs[2]; 959 ci->ci_vendor[1] = descs[3]; 960 ci->ci_vendor[3] = 0; 961 962 x86_cpuid(0x80000000, brand); 963 if (brand[0] >= 0x80000004) { 964 x86_cpuid(0x80000002, brand); 965 x86_cpuid(0x80000003, brand + 4); 966 x86_cpuid(0x80000004, brand + 8); 967 for (i = 0; i < 48; i++) 968 if (((char *) brand)[i] != ' ') 969 break; 970 memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i); 971 } 972 973 if (ci->ci_cpuid_level < 1) 974 return; 975 976 x86_cpuid(1, descs); 977 ci->ci_signature = descs[0]; 978 979 /* Extract full family/model values */ 980 ci->ci_family = CPUID2FAMILY(ci->ci_signature); 981 ci->ci_model = CPUID2MODEL(ci->ci_signature); 982 if (ci->ci_family == 15) 983 ci->ci_family += CPUID2EXTFAMILY(ci->ci_signature); 984 if (ci->ci_family == 6 || ci->ci_family == 15) 985 ci->ci_model += CPUID2EXTMODEL(ci->ci_signature) << 4; 986 987 /* Brand is low order 8 bits of ebx */ 988 ci->ci_brand_id = descs[1] & 0xff; 989 ci->ci_initapicid = (descs[1] >> 24) & 0xff; 990 991 ci->ci_feat_val[1] = descs[2]; 992 ci->ci_feat_val[0] = descs[3]; 993 994 if (ci->ci_cpuid_level < 2) 995 return; 996 997 /* 998 * Parse the cache info from `cpuid', if we have it. 999 * XXX This is kinda ugly, but hey, so is the architecture... 1000 */ 1001 1002 x86_cpuid(2, descs); 1003 1004 iterations = descs[0] & 0xff; 1005 while (iterations-- > 0) { 1006 for (i = 0; i < 4; i++) { 1007 if (descs[i] & 0x80000000) 1008 continue; 1009 for (j = 0; j < 4; j++) { 1010 if (i == 0 && j == 0) 1011 continue; 1012 desc = (descs[i] >> (j * 8)) & 0xff; 1013 if (desc == 0) 1014 continue; 1015 cai = cache_info_lookup(intel_cpuid_cache_info, 1016 desc); 1017 if (cai != NULL) 1018 ci->ci_cinfo[cai->cai_index] = *cai; 1019 } 1020 } 1021 x86_cpuid(2, descs); 1022 } 1023 1024 if (ci->ci_cpuid_level < 3) 1025 return; 1026 1027 /* 1028 * If the processor serial number misfeature is present and supported, 1029 * extract it here. 1030 */ 1031 if ((ci->ci_feat_val[0] & CPUID_PN) != 0) { 1032 ci->ci_cpu_serial[0] = ci->ci_signature; 1033 x86_cpuid(3, descs); 1034 ci->ci_cpu_serial[2] = descs[2]; 1035 ci->ci_cpu_serial[1] = descs[3]; 1036 } 1037 1038 if (ci->ci_cpuid_level < 0xd) 1039 return; 1040 1041 /* Get support XCR0 bits */ 1042 x86_cpuid2(0xd, 0, descs); 1043 ci->ci_feat_val[5] = descs[0]; /* Actually 64 bits */ 1044 ci->ci_cur_xsave = descs[1]; 1045 ci->ci_max_xsave = descs[2]; 1046 1047 /* Additional flags (eg xsaveopt support) */ 1048 x86_cpuid2(0xd, 1, descs); 1049 ci->ci_feat_val[6] = descs[0]; /* Actually 64 bits */ 1050 } 1051 1052 static void 1053 cpu_probe_features(struct cpu_info *ci) 1054 { 1055 const struct cpu_cpuid_nameclass *cpup = NULL; 1056 unsigned int i; 1057 1058 if (ci->ci_cpuid_level < 1) 1059 return; 1060 1061 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1062 if (!strncmp((char *)ci->ci_vendor, 1063 i386_cpuid_cpus[i].cpu_id, 12)) { 1064 cpup = &i386_cpuid_cpus[i]; 1065 break; 1066 } 1067 } 1068 1069 if (cpup == NULL) 1070 return; 1071 1072 i = ci->ci_family - CPU_MINFAMILY; 1073 1074 if (i >= __arraycount(cpup->cpu_family)) 1075 i = __arraycount(cpup->cpu_family) - 1; 1076 1077 if (cpup->cpu_family[i].cpu_probe == NULL) 1078 return; 1079 1080 (*cpup->cpu_family[i].cpu_probe)(ci); 1081 } 1082 1083 static void 1084 intel_family_new_probe(struct cpu_info *ci) 1085 { 1086 uint32_t descs[4]; 1087 1088 x86_cpuid(0x80000000, descs); 1089 1090 /* 1091 * Determine extended feature flags. 1092 */ 1093 if (descs[0] >= 0x80000001) { 1094 x86_cpuid(0x80000001, descs); 1095 ci->ci_feat_val[2] |= descs[3]; 1096 ci->ci_feat_val[3] |= descs[2]; 1097 } 1098 } 1099 1100 static void 1101 amd_family6_probe(struct cpu_info *ci) 1102 { 1103 uint32_t descs[4]; 1104 char *p; 1105 size_t i; 1106 1107 x86_cpuid(0x80000000, descs); 1108 1109 /* 1110 * Determine the extended feature flags. 1111 */ 1112 if (descs[0] >= 0x80000001) { 1113 x86_cpuid(0x80000001, descs); 1114 ci->ci_feat_val[2] |= descs[3]; /* %edx */ 1115 ci->ci_feat_val[3] = descs[2]; /* %ecx */ 1116 } 1117 1118 if (*cpu_brand_string == '\0') 1119 return; 1120 1121 for (i = 1; i < __arraycount(amd_brand); i++) 1122 if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) { 1123 ci->ci_brand_id = i; 1124 strlcpy(amd_brand_name, p, sizeof(amd_brand_name)); 1125 break; 1126 } 1127 } 1128 1129 static void 1130 amd_family5_setup(struct cpu_info *ci) 1131 { 1132 1133 switch (ci->ci_model) { 1134 case 0: /* AMD-K5 Model 0 */ 1135 /* 1136 * According to the AMD Processor Recognition App Note, 1137 * the AMD-K5 Model 0 uses the wrong bit to indicate 1138 * support for global PTEs, instead using bit 9 (APIC) 1139 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 1140 */ 1141 if (ci->ci_feat_val[0] & CPUID_APIC) 1142 ci->ci_feat_val[0] = 1143 (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE; 1144 /* 1145 * XXX But pmap_pg_g is already initialized -- need to kick 1146 * XXX the pmap somehow. How does the MP branch do this? 1147 */ 1148 break; 1149 } 1150 } 1151 1152 static void 1153 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage) 1154 { 1155 u_int descs[4]; 1156 1157 x86_cpuid(0x80860007, descs); 1158 *frequency = descs[0]; 1159 *voltage = descs[1]; 1160 *percentage = descs[2]; 1161 } 1162 1163 static void 1164 transmeta_cpu_info(struct cpu_info *ci) 1165 { 1166 u_int descs[4], nreg; 1167 u_int frequency, voltage, percentage; 1168 1169 x86_cpuid(0x80860000, descs); 1170 nreg = descs[0]; 1171 if (nreg >= 0x80860001) { 1172 x86_cpuid(0x80860001, descs); 1173 aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n", 1174 (descs[1] >> 24) & 0xff, 1175 (descs[1] >> 16) & 0xff, 1176 (descs[1] >> 8) & 0xff, 1177 descs[1] & 0xff); 1178 } 1179 if (nreg >= 0x80860002) { 1180 x86_cpuid(0x80860002, descs); 1181 aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n", 1182 (descs[1] >> 24) & 0xff, 1183 (descs[1] >> 16) & 0xff, 1184 (descs[1] >> 8) & 0xff, 1185 descs[1] & 0xff, 1186 descs[2]); 1187 } 1188 if (nreg >= 0x80860006) { 1189 union { 1190 char text[65]; 1191 u_int descs[4][4]; 1192 } info; 1193 int i; 1194 1195 for (i=0; i<4; i++) { 1196 x86_cpuid(0x80860003 + i, info.descs[i]); 1197 } 1198 info.text[64] = '\0'; 1199 aprint_verbose_dev(ci->ci_dev, "%s\n", info.text); 1200 } 1201 1202 if (nreg >= 0x80860007) { 1203 tmx86_get_longrun_status(&frequency, 1204 &voltage, &percentage); 1205 aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n", 1206 frequency, voltage, percentage); 1207 } 1208 } 1209 1210 static void 1211 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val) 1212 { 1213 char buf[32 * 16]; 1214 char *bp; 1215 1216 #define MAX_LINE_LEN 79 /* get from command arg or 'stty cols' ? */ 1217 1218 if (val == 0 || fmt == NULL) 1219 return; 1220 1221 snprintb_m(buf, sizeof(buf), fmt, val, 1222 MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1); 1223 bp = buf; 1224 while (*bp != '\0') { 1225 aprint_verbose("%s: %s %s\n", cpuname, hdr, bp); 1226 bp += strlen(bp) + 1; 1227 } 1228 } 1229 1230 void 1231 identifycpu(int fd, const char *cpuname) 1232 { 1233 const char *name = "", *modifier, *vendorname, *brand = ""; 1234 int class = CPUCLASS_386; 1235 unsigned int i; 1236 int modif, family; 1237 const struct cpu_cpuid_nameclass *cpup = NULL; 1238 const struct cpu_cpuid_family *cpufam; 1239 struct cpu_info *ci, cistore; 1240 size_t sz; 1241 struct cpu_ucode_version ucode; 1242 union { 1243 struct cpu_ucode_version_amd amd; 1244 struct cpu_ucode_version_intel1 intel1; 1245 } ucvers; 1246 1247 ci = &cistore; 1248 cpu_probe_base_features(ci, cpuname); 1249 cpu_probe_features(ci); 1250 1251 if (ci->ci_cpu_type >= 0) { 1252 if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus)) 1253 errx(1, "unknown cpu type %d", ci->ci_cpu_type); 1254 name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name; 1255 cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor; 1256 vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname; 1257 class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class; 1258 ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info; 1259 modifier = ""; 1260 } else { 1261 modif = (ci->ci_signature >> 12) & 0x3; 1262 family = ci->ci_family; 1263 if (family < CPU_MINFAMILY) 1264 errx(1, "identifycpu: strange family value"); 1265 if (family > CPU_MAXFAMILY) 1266 family = CPU_MAXFAMILY; 1267 1268 for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) { 1269 if (!strncmp((char *)ci->ci_vendor, 1270 i386_cpuid_cpus[i].cpu_id, 12)) { 1271 cpup = &i386_cpuid_cpus[i]; 1272 break; 1273 } 1274 } 1275 1276 if (cpup == NULL) { 1277 cpu_vendor = CPUVENDOR_UNKNOWN; 1278 if (ci->ci_vendor[0] != '\0') 1279 vendorname = (char *)&ci->ci_vendor[0]; 1280 else 1281 vendorname = "Unknown"; 1282 class = family - 3; 1283 modifier = ""; 1284 name = ""; 1285 ci->ci_info = NULL; 1286 } else { 1287 cpu_vendor = cpup->cpu_vendor; 1288 vendorname = cpup->cpu_vendorname; 1289 modifier = modifiers[modif]; 1290 cpufam = &cpup->cpu_family[family - CPU_MINFAMILY]; 1291 name = cpufam->cpu_models[ci->ci_model]; 1292 if (name == NULL || *name == '\0') 1293 name = cpufam->cpu_model_default; 1294 class = cpufam->cpu_class; 1295 ci->ci_info = cpufam->cpu_info; 1296 1297 if (cpu_vendor == CPUVENDOR_INTEL) { 1298 if (ci->ci_family == 6 && ci->ci_model >= 5) { 1299 const char *tmp; 1300 tmp = intel_family6_name(ci); 1301 if (tmp != NULL) 1302 name = tmp; 1303 } 1304 if (ci->ci_family == 15 && 1305 ci->ci_brand_id < 1306 __arraycount(i386_intel_brand) && 1307 i386_intel_brand[ci->ci_brand_id]) 1308 name = 1309 i386_intel_brand[ci->ci_brand_id]; 1310 } 1311 1312 if (cpu_vendor == CPUVENDOR_AMD) { 1313 if (ci->ci_family == 6 && ci->ci_model >= 6) { 1314 if (ci->ci_brand_id == 1) 1315 /* 1316 * It's Duron. We override the 1317 * name, since it might have 1318 * been misidentified as Athlon. 1319 */ 1320 name = 1321 amd_brand[ci->ci_brand_id]; 1322 else 1323 brand = amd_brand_name; 1324 } 1325 if (CPUID2FAMILY(ci->ci_signature) == 0xf) { 1326 /* Identify AMD64 CPU names. */ 1327 const char *tmp; 1328 tmp = amd_amd64_name(ci); 1329 if (tmp != NULL) 1330 name = tmp; 1331 } 1332 } 1333 1334 if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6) 1335 vendorname = "VIA"; 1336 } 1337 } 1338 1339 ci->ci_cpu_class = class; 1340 1341 sz = sizeof(ci->ci_tsc_freq); 1342 (void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0); 1343 sz = sizeof(use_pae); 1344 (void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0); 1345 largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024); 1346 1347 /* 1348 * The 'cpu_brand_string' is much more useful than the 'cpu_model' 1349 * we try to determine from the family/model values. 1350 */ 1351 if (*cpu_brand_string != '\0') 1352 aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string); 1353 1354 aprint_normal("%s: %s", cpuname, vendorname); 1355 if (*modifier) 1356 aprint_normal(" %s", modifier); 1357 if (*name) 1358 aprint_normal(" %s", name); 1359 if (*brand) 1360 aprint_normal(" %s", brand); 1361 aprint_normal(" (%s-class)", classnames[class]); 1362 1363 if (ci->ci_tsc_freq != 0) 1364 aprint_normal(", %ju.%02ju MHz\n", 1365 ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000, 1366 (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100); 1367 1368 aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x", 1369 ci->ci_family, ci->ci_model, CPUID2STEPPING(ci->ci_signature)); 1370 if (ci->ci_signature != 0) 1371 aprint_normal(" (id %#x)", ci->ci_signature); 1372 aprint_normal("\n"); 1373 1374 if (ci->ci_info) 1375 (*ci->ci_info)(ci); 1376 1377 /* 1378 * display CPU feature flags 1379 */ 1380 1381 print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]); 1382 print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]); 1383 1384 /* These next two are actually common definitions! */ 1385 print_bits(cpuname, "features2", 1386 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS 1387 : CPUID_EXT_FLAGS, ci->ci_feat_val[2]); 1388 print_bits(cpuname, "features3", 1389 cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4 1390 : CPUID_AMD_FLAGS4, ci->ci_feat_val[3]); 1391 1392 print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK, 1393 ci->ci_feat_val[4]); 1394 1395 print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[5]); 1396 print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS, 1397 ci->ci_feat_val[6]); 1398 1399 if (ci->ci_max_xsave != 0) { 1400 aprint_normal("%s: xsave area size: current %d, maximum %d", 1401 cpuname, ci->ci_cur_xsave, ci->ci_max_xsave); 1402 aprint_normal(", xgetbv %sabled\n", 1403 ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis"); 1404 if (ci->ci_feat_val[1] & CPUID2_OSXSAVE) 1405 print_bits(cpuname, "enabled xsave", XCR0_FLAGS1, 1406 x86_xgetbv()); 1407 } 1408 1409 x86_print_cacheinfo(ci); 1410 1411 if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) { 1412 aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n", 1413 cpuname, 1414 ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536, 1415 ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536, 1416 ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536); 1417 } 1418 1419 if (ci->ci_cpu_class == CPUCLASS_386) { 1420 errx(1, "NetBSD requires an 80486 or later processor"); 1421 } 1422 1423 if (ci->ci_cpu_type == CPU_486DLC) { 1424 #ifndef CYRIX_CACHE_WORKS 1425 aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 1426 #else 1427 #ifndef CYRIX_CACHE_REALLY_WORKS 1428 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n"); 1429 #else 1430 aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n"); 1431 #endif 1432 #endif 1433 } 1434 1435 /* 1436 * Everything past this point requires a Pentium or later. 1437 */ 1438 if (ci->ci_cpuid_level < 0) 1439 return; 1440 1441 identifycpu_cpuids(ci); 1442 1443 #ifdef INTEL_CORETEMP 1444 if (cpu_vendor == CPUVENDOR_INTEL && ci->ci_cpuid_level >= 0x06) 1445 coretemp_register(ci); 1446 #endif 1447 1448 if (cpu_vendor == CPUVENDOR_AMD) { 1449 uint32_t data[4]; 1450 1451 x86_cpuid(0x80000000, data); 1452 if (data[0] >= 0x80000007) 1453 powernow_probe(ci); 1454 1455 if ((data[0] >= 0x8000000a) 1456 && (ci->ci_feat_val[3] & CPUID_SVM) != 0) { 1457 x86_cpuid(0x8000000a, data); 1458 aprint_verbose("%s: SVM Rev. %d\n", cpuname, 1459 data[0] & 0xf); 1460 aprint_verbose("%s: SVM NASID %d\n", cpuname, data[1]); 1461 print_bits(cpuname, "SVM features", CPUID_AMD_SVM_FLAGS, 1462 data[3]); 1463 } 1464 } else if (cpu_vendor == CPUVENDOR_INTEL) { 1465 uint32_t data[4]; 1466 uint32_t highest_basic_info; 1467 uint32_t bi_index; 1468 1469 x86_cpuid(0x00000000, data); 1470 highest_basic_info = data[0]; 1471 aprint_verbose("%s: highest basic info %08x\n", cpuname, 1472 highest_basic_info); 1473 for (bi_index = 1; bi_index <= highest_basic_info; bi_index++) { 1474 x86_cpuid(bi_index, data); 1475 switch (bi_index) { 1476 case 6: 1477 print_bits(cpuname, "DSPM-eax", 1478 CPUID_DSPM_FLAGS, data[0]); 1479 print_bits(cpuname, "DSPM-ecx", 1480 CPUID_DSPM_FLAGS1, data[2]); 1481 break; 1482 case 7: 1483 aprint_verbose("%s: SEF highest subleaf %08x\n", 1484 cpuname, data[0]); 1485 print_bits(cpuname, "SEF-main", CPUID_SEF_FLAGS, 1486 data[1]); 1487 break; 1488 #if 0 1489 default: 1490 aprint_verbose("%s: basic %08x-eax %08x\n", 1491 cpuname, bi_index, data[0]); 1492 aprint_verbose("%s: basic %08x-ebx %08x\n", 1493 cpuname, bi_index, data[1]); 1494 aprint_verbose("%s: basic %08x-ecx %08x\n", 1495 cpuname, bi_index, data[2]); 1496 aprint_verbose("%s: basic %08x-edx %08x\n", 1497 cpuname, bi_index, data[3]); 1498 break; 1499 #endif 1500 } 1501 } 1502 } 1503 1504 #ifdef INTEL_ONDEMAND_CLOCKMOD 1505 clockmod_init(); 1506 #endif 1507 1508 if (cpu_vendor == CPUVENDOR_AMD) 1509 ucode.loader_version = CPU_UCODE_LOADER_AMD; 1510 else if (cpu_vendor == CPUVENDOR_INTEL) 1511 ucode.loader_version = CPU_UCODE_LOADER_INTEL1; 1512 else 1513 return; 1514 1515 ucode.data = &ucvers; 1516 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) { 1517 #ifdef __i386__ 1518 struct cpu_ucode_version_64 ucode_64; 1519 if (errno != ENOTTY) 1520 return; 1521 /* Try the 64 bit ioctl */ 1522 memset(&ucode_64, 0, sizeof ucode_64); 1523 ucode_64.data = &ucvers; 1524 ucode_64.loader_version = ucode.loader_version; 1525 if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0) 1526 return; 1527 #endif 1528 } 1529 1530 if (cpu_vendor == CPUVENDOR_AMD) 1531 printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version); 1532 else if (cpu_vendor == CPUVENDOR_INTEL) 1533 printf("%s: microcode version 0x%x, platform ID %d\n", cpuname, 1534 ucvers.intel1.ucodeversion, ucvers.intel1.platformid); 1535 } 1536 1537 static const char * 1538 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name, 1539 const char *sep) 1540 { 1541 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1542 char human_num[HUMAN_BUFSIZE]; 1543 1544 if (cai->cai_totalsize == 0) 1545 return sep; 1546 1547 if (sep == NULL) 1548 aprint_verbose_dev(ci->ci_dev, ""); 1549 else 1550 aprint_verbose("%s", sep); 1551 if (name != NULL) 1552 aprint_verbose("%s ", name); 1553 1554 if (cai->cai_string != NULL) { 1555 aprint_verbose("%s ", cai->cai_string); 1556 } else { 1557 (void)humanize_number(human_num, sizeof(human_num), 1558 cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE); 1559 aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize); 1560 } 1561 switch (cai->cai_associativity) { 1562 case 0: 1563 aprint_verbose("disabled"); 1564 break; 1565 case 1: 1566 aprint_verbose("direct-mapped"); 1567 break; 1568 case 0xff: 1569 aprint_verbose("fully associative"); 1570 break; 1571 default: 1572 aprint_verbose("%d-way", cai->cai_associativity); 1573 break; 1574 } 1575 return ", "; 1576 } 1577 1578 static const char * 1579 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name, 1580 const char *sep) 1581 { 1582 struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag]; 1583 char human_num[HUMAN_BUFSIZE]; 1584 1585 if (cai->cai_totalsize == 0) 1586 return sep; 1587 1588 if (sep == NULL) 1589 aprint_verbose_dev(ci->ci_dev, ""); 1590 else 1591 aprint_verbose("%s", sep); 1592 if (name != NULL) 1593 aprint_verbose("%s ", name); 1594 1595 if (cai->cai_string != NULL) { 1596 aprint_verbose("%s", cai->cai_string); 1597 } else { 1598 (void)humanize_number(human_num, sizeof(human_num), 1599 cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE); 1600 aprint_verbose("%d %s entries ", cai->cai_totalsize, 1601 human_num); 1602 switch (cai->cai_associativity) { 1603 case 0: 1604 aprint_verbose("disabled"); 1605 break; 1606 case 1: 1607 aprint_verbose("direct-mapped"); 1608 break; 1609 case 0xff: 1610 aprint_verbose("fully associative"); 1611 break; 1612 default: 1613 aprint_verbose("%d-way", cai->cai_associativity); 1614 break; 1615 } 1616 } 1617 return ", "; 1618 } 1619 1620 static const struct x86_cache_info * 1621 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc) 1622 { 1623 int i; 1624 1625 for (i = 0; cai[i].cai_desc != 0; i++) { 1626 if (cai[i].cai_desc == desc) 1627 return (&cai[i]); 1628 } 1629 1630 return (NULL); 1631 } 1632 1633 static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] = 1634 AMD_L2CACHE_INFO; 1635 1636 static const struct x86_cache_info amd_cpuid_l3cache_assoc_info[] = 1637 AMD_L3CACHE_INFO; 1638 1639 static void 1640 amd_cpu_cacheinfo(struct cpu_info *ci) 1641 { 1642 const struct x86_cache_info *cp; 1643 struct x86_cache_info *cai; 1644 u_int descs[4]; 1645 u_int lfunc; 1646 1647 /* 1648 * K5 model 0 has none of this info. 1649 */ 1650 if (ci->ci_family == 5 && ci->ci_model == 0) 1651 return; 1652 1653 /* 1654 * Determine the largest extended function value. 1655 */ 1656 x86_cpuid(0x80000000, descs); 1657 lfunc = descs[0]; 1658 1659 /* 1660 * Determine L1 cache/TLB info. 1661 */ 1662 if (lfunc < 0x80000005) { 1663 /* No L1 cache info available. */ 1664 return; 1665 } 1666 1667 x86_cpuid(0x80000005, descs); 1668 1669 /* 1670 * K6-III and higher have large page TLBs. 1671 */ 1672 if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) { 1673 cai = &ci->ci_cinfo[CAI_ITLB2]; 1674 cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]); 1675 cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]); 1676 cai->cai_linesize = largepagesize; 1677 1678 cai = &ci->ci_cinfo[CAI_DTLB2]; 1679 cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]); 1680 cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]); 1681 cai->cai_linesize = largepagesize; 1682 } 1683 1684 cai = &ci->ci_cinfo[CAI_ITLB]; 1685 cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]); 1686 cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]); 1687 cai->cai_linesize = (4 * 1024); 1688 1689 cai = &ci->ci_cinfo[CAI_DTLB]; 1690 cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]); 1691 cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]); 1692 cai->cai_linesize = (4 * 1024); 1693 1694 cai = &ci->ci_cinfo[CAI_DCACHE]; 1695 cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]); 1696 cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]); 1697 cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]); 1698 1699 cai = &ci->ci_cinfo[CAI_ICACHE]; 1700 cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]); 1701 cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]); 1702 cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]); 1703 1704 /* 1705 * Determine L2 cache/TLB info. 1706 */ 1707 if (lfunc < 0x80000006) { 1708 /* No L2 cache info available. */ 1709 return; 1710 } 1711 1712 x86_cpuid(0x80000006, descs); 1713 1714 cai = &ci->ci_cinfo[CAI_L2_ITLB]; 1715 cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]); 1716 cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]); 1717 cai->cai_linesize = (4 * 1024); 1718 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1719 cai->cai_associativity); 1720 if (cp != NULL) 1721 cai->cai_associativity = cp->cai_associativity; 1722 else 1723 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1724 1725 cai = &ci->ci_cinfo[CAI_L2_ITLB2]; 1726 cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]); 1727 cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]); 1728 cai->cai_linesize = largepagesize; 1729 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1730 cai->cai_associativity); 1731 if (cp != NULL) 1732 cai->cai_associativity = cp->cai_associativity; 1733 else 1734 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1735 1736 cai = &ci->ci_cinfo[CAI_L2_DTLB]; 1737 cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]); 1738 cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]); 1739 cai->cai_linesize = (4 * 1024); 1740 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1741 cai->cai_associativity); 1742 if (cp != NULL) 1743 cai->cai_associativity = cp->cai_associativity; 1744 else 1745 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1746 1747 cai = &ci->ci_cinfo[CAI_L2_DTLB2]; 1748 cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]); 1749 cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]); 1750 cai->cai_linesize = largepagesize; 1751 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1752 cai->cai_associativity); 1753 if (cp != NULL) 1754 cai->cai_associativity = cp->cai_associativity; 1755 else 1756 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1757 1758 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1759 cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]); 1760 cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]); 1761 cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]); 1762 1763 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1764 cai->cai_associativity); 1765 if (cp != NULL) 1766 cai->cai_associativity = cp->cai_associativity; 1767 else 1768 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1769 1770 /* 1771 * Determine L3 cache info on AMD Family 10h and newer processors 1772 */ 1773 if (ci->ci_family >= 0x10) { 1774 cai = &ci->ci_cinfo[CAI_L3CACHE]; 1775 cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]); 1776 cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]); 1777 cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]); 1778 1779 cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info, 1780 cai->cai_associativity); 1781 if (cp != NULL) 1782 cai->cai_associativity = cp->cai_associativity; 1783 else 1784 cai->cai_associativity = 0; /* XXX Unkn/Rsvd */ 1785 } 1786 1787 /* 1788 * Determine 1GB TLB info. 1789 */ 1790 if (lfunc < 0x80000019) { 1791 /* No 1GB TLB info available. */ 1792 return; 1793 } 1794 1795 x86_cpuid(0x80000019, descs); 1796 1797 cai = &ci->ci_cinfo[CAI_L1_1GBITLB]; 1798 cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]); 1799 cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]); 1800 cai->cai_linesize = (1024 * 1024 * 1024); 1801 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1802 cai->cai_associativity); 1803 if (cp != NULL) 1804 cai->cai_associativity = cp->cai_associativity; 1805 else 1806 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1807 1808 cai = &ci->ci_cinfo[CAI_L1_1GBDTLB]; 1809 cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]); 1810 cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]); 1811 cai->cai_linesize = (1024 * 1024 * 1024); 1812 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1813 cai->cai_associativity); 1814 if (cp != NULL) 1815 cai->cai_associativity = cp->cai_associativity; 1816 else 1817 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1818 1819 cai = &ci->ci_cinfo[CAI_L2_1GBITLB]; 1820 cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]); 1821 cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]); 1822 cai->cai_linesize = (1024 * 1024 * 1024); 1823 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1824 cai->cai_associativity); 1825 if (cp != NULL) 1826 cai->cai_associativity = cp->cai_associativity; 1827 else 1828 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1829 1830 cai = &ci->ci_cinfo[CAI_L2_1GBDTLB]; 1831 cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]); 1832 cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]); 1833 cai->cai_linesize = (1024 * 1024 * 1024); 1834 cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info, 1835 cai->cai_associativity); 1836 if (cp != NULL) 1837 cai->cai_associativity = cp->cai_associativity; 1838 else 1839 cai->cai_associativity = 0; /* XXX Unknown/reserved */ 1840 } 1841 1842 static void 1843 via_cpu_cacheinfo(struct cpu_info *ci) 1844 { 1845 struct x86_cache_info *cai; 1846 int stepping; 1847 u_int descs[4]; 1848 u_int lfunc; 1849 1850 stepping = CPUID2STEPPING(ci->ci_signature); 1851 1852 /* 1853 * Determine the largest extended function value. 1854 */ 1855 x86_cpuid(0x80000000, descs); 1856 lfunc = descs[0]; 1857 1858 /* 1859 * Determine L1 cache/TLB info. 1860 */ 1861 if (lfunc < 0x80000005) { 1862 /* No L1 cache info available. */ 1863 return; 1864 } 1865 1866 x86_cpuid(0x80000005, descs); 1867 1868 cai = &ci->ci_cinfo[CAI_ITLB]; 1869 cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]); 1870 cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]); 1871 cai->cai_linesize = (4 * 1024); 1872 1873 cai = &ci->ci_cinfo[CAI_DTLB]; 1874 cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]); 1875 cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]); 1876 cai->cai_linesize = (4 * 1024); 1877 1878 cai = &ci->ci_cinfo[CAI_DCACHE]; 1879 cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]); 1880 cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]); 1881 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]); 1882 if (ci->ci_model == 9 && stepping == 8) { 1883 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1884 cai->cai_associativity = 2; 1885 } 1886 1887 cai = &ci->ci_cinfo[CAI_ICACHE]; 1888 cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]); 1889 cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]); 1890 cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]); 1891 if (ci->ci_model == 9 && stepping == 8) { 1892 /* Erratum: stepping 8 reports 4 when it should be 2 */ 1893 cai->cai_associativity = 2; 1894 } 1895 1896 /* 1897 * Determine L2 cache/TLB info. 1898 */ 1899 if (lfunc < 0x80000006) { 1900 /* No L2 cache info available. */ 1901 return; 1902 } 1903 1904 x86_cpuid(0x80000006, descs); 1905 1906 cai = &ci->ci_cinfo[CAI_L2CACHE]; 1907 if (ci->ci_model >= 9) { 1908 cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]); 1909 cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]); 1910 cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]); 1911 } else { 1912 cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]); 1913 cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]); 1914 cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]); 1915 } 1916 } 1917 1918 static void 1919 x86_print_cacheinfo(struct cpu_info *ci) 1920 { 1921 const char *sep; 1922 1923 if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 || 1924 ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) { 1925 sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL); 1926 sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep); 1927 if (sep != NULL) 1928 aprint_verbose("\n"); 1929 } 1930 if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) { 1931 sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL); 1932 if (sep != NULL) 1933 aprint_verbose("\n"); 1934 } 1935 if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) { 1936 sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL); 1937 if (sep != NULL) 1938 aprint_verbose("\n"); 1939 } 1940 if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) { 1941 sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL); 1942 sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep); 1943 if (sep != NULL) 1944 aprint_verbose("\n"); 1945 } 1946 if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) { 1947 sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL); 1948 sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep); 1949 if (sep != NULL) 1950 aprint_verbose("\n"); 1951 } 1952 if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) { 1953 sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL); 1954 sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep); 1955 if (sep != NULL) 1956 aprint_verbose("\n"); 1957 } 1958 if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) { 1959 sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL); 1960 sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep); 1961 if (sep != NULL) 1962 aprint_verbose("\n"); 1963 } 1964 if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) { 1965 sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL); 1966 sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep); 1967 if (sep != NULL) 1968 aprint_verbose("\n"); 1969 } 1970 if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) { 1971 sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", 1972 NULL); 1973 if (sep != NULL) 1974 aprint_verbose("\n"); 1975 } 1976 if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) { 1977 sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", 1978 NULL); 1979 if (sep != NULL) 1980 aprint_verbose("\n"); 1981 } 1982 if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) { 1983 sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", 1984 NULL); 1985 if (sep != NULL) 1986 aprint_verbose("\n"); 1987 } 1988 if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) { 1989 sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", 1990 NULL); 1991 if (sep != NULL) 1992 aprint_verbose("\n"); 1993 } 1994 } 1995 1996 static void 1997 powernow_probe(struct cpu_info *ci) 1998 { 1999 uint32_t regs[4]; 2000 char buf[256]; 2001 2002 x86_cpuid(0x80000007, regs); 2003 2004 snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]); 2005 aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n", 2006 buf); 2007 } 2008 2009 int 2010 ucodeupdate_check(int fd, struct cpu_ucode *uc) 2011 { 2012 struct cpu_info ci; 2013 int loader_version, res; 2014 struct cpu_ucode_version versreq; 2015 2016 cpu_probe_base_features(&ci, "unknown"); 2017 2018 if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD")) 2019 loader_version = CPU_UCODE_LOADER_AMD; 2020 else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel")) 2021 loader_version = CPU_UCODE_LOADER_INTEL1; 2022 else 2023 return -1; 2024 2025 /* check whether the kernel understands this loader version */ 2026 versreq.loader_version = loader_version; 2027 versreq.data = 0; 2028 res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq); 2029 if (res) 2030 return -1; 2031 2032 switch (loader_version) { 2033 case CPU_UCODE_LOADER_AMD: 2034 if (uc->cpu_nr != -1) { 2035 /* printf? */ 2036 return -1; 2037 } 2038 uc->cpu_nr = CPU_UCODE_ALL_CPUS; 2039 break; 2040 case CPU_UCODE_LOADER_INTEL1: 2041 if (uc->cpu_nr == -1) 2042 uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */ 2043 else 2044 uc->cpu_nr = CPU_UCODE_CURRENT_CPU; 2045 break; 2046 default: /* can't happen */ 2047 return -1; 2048 } 2049 uc->loader_version = loader_version; 2050 return 0; 2051 } 2052
Indexes created Mon Oct 27 02:09:54 GMT 2025